ASoC: OMAP4: Add support for McPDM24.0.9

McPDM driver is the interface between Phoenix audio codec
and the ABE for audio paths. It can also interface directly
with the OMAP4430 processor.

Signed-off-by: Jorge Eduardo Candelaria <x0107209@ti.com>

5 files changed, 585 insertions, 0 deletions

diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h
index e8f84a087439..40e53f29ce24 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/mach/irqs.h
@@ -512,6 +512,8 @@
 #define INT_44XX_PARTHASH_IRQ	(79 + IRQ_GIC_START)
 #define INT_44XX_MMC3_IRQ	(94 + IRQ_GIC_START)
 
+/* MCPDM 4430 IRQ request line */
+#define INT_44XX_MCPDM_IRQ	(112 + IRQ_GIC_START)
 
 /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
  * 16 MPUIO lines */
diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig
index 5a3ccc6c5738..e905302d1f13 100644
--- a/sound/soc/omap/Kconfig
+++ b/sound/soc/omap/Kconfig
@@ -6,6 +6,9 @@ config SND_OMAP_SOC_MCBSP
 	tristate
 	select OMAP_MCBSP
 
+config SND_OMAP_SOC_MCPDM
+	tristate
+
 config SND_OMAP_SOC_N810
 	tristate "SoC Audio support for Nokia N810"
 	depends on SND_OMAP_SOC && MACH_NOKIA_N810 && I2C
diff --git a/sound/soc/omap/Makefile b/sound/soc/omap/Makefile
index 2ddf7e0e897e..1ad3cab0d5ab 100644
--- a/sound/soc/omap/Makefile
+++ b/sound/soc/omap/Makefile
@@ -1,9 +1,11 @@
 # OMAP Platform Support
 snd-soc-omap-objs := omap-pcm.o
 snd-soc-omap-mcbsp-objs := omap-mcbsp.o
+snd-soc-omap-mcpdm-objs := omap-mcpdm.o
 
 obj-$(CONFIG_SND_OMAP_SOC) += snd-soc-omap.o
 obj-$(CONFIG_SND_OMAP_SOC_MCBSP) += snd-soc-omap-mcbsp.o
+obj-$(CONFIG_SND_OMAP_SOC_MCPDM) += snd-soc-omap-mcpdm.o
 
 # OMAP Machine Support
 snd-soc-n810-objs := n810.o
diff --git a/sound/soc/omap/mcpdm.c b/sound/soc/omap/mcpdm.c
new file mode 100755
index 000000000000..50079f142566
--- /dev/null
+++ b/sound/soc/omap/mcpdm.c
@@ -0,0 +1,426 @@
+/*
+ * mcpdm.c  --  McPDM interface driver
+ *
+ * Author: Jorge Eduardo Candelaria <x0107209@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/wait.h>
+#include <linux/interrupt.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include "mcpdm.h"
+
+struct omap_mcpdm *mcpdm;
+
+void omap_mcpdm_write(u16 reg, u32 val)
+{
+	__raw_writel(val, mcpdm->io_base + reg);
+}
+
+int omap_mcpdm_read(u16 reg)
+{
+	return __raw_readl(mcpdm->io_base + reg);
+}
+
+void omap_mcpdm_reg_dump(void)
+{
+	dev_dbg(mcpdm->dev, "***********************\n");
+	dev_dbg(mcpdm->dev, "IRQSTATUS_RAW:  0x%04x\n",
+			omap_mcpdm_read(MCPDM_IRQSTATUS_RAW));
+	dev_dbg(mcpdm->dev, "IRQSTATUS:  0x%04x\n",
+			omap_mcpdm_read(MCPDM_IRQSTATUS));
+	dev_dbg(mcpdm->dev, "IRQENABLE_SET:  0x%04x\n",
+			omap_mcpdm_read(MCPDM_IRQENABLE_SET));
+	dev_dbg(mcpdm->dev, "IRQENABLE_CLR:  0x%04x\n",
+			omap_mcpdm_read(MCPDM_IRQENABLE_CLR));
+	dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
+			omap_mcpdm_read(MCPDM_IRQWAKE_EN));
+	dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
+			omap_mcpdm_read(MCPDM_DMAENABLE_SET));
+	dev_dbg(mcpdm->dev, "DMAENABLE_CLR:  0x%04x\n",
+			omap_mcpdm_read(MCPDM_DMAENABLE_CLR));
+	dev_dbg(mcpdm->dev, "DMAWAKEEN:  0x%04x\n",
+			omap_mcpdm_read(MCPDM_DMAWAKEEN));
+	dev_dbg(mcpdm->dev, "CTRL:  0x%04x\n",
+			omap_mcpdm_read(MCPDM_CTRL));
+	dev_dbg(mcpdm->dev, "DN_DATA:  0x%04x\n",
+			omap_mcpdm_read(MCPDM_DN_DATA));
+	dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
+			omap_mcpdm_read(MCPDM_UP_DATA));
+	dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
+			omap_mcpdm_read(MCPDM_FIFO_CTRL_DN));
+	dev_dbg(mcpdm->dev, "FIFO_CTRL_UP:  0x%04x\n",
+			omap_mcpdm_read(MCPDM_FIFO_CTRL_UP));
+	dev_dbg(mcpdm->dev, "DN_OFFSET:  0x%04x\n",
+			omap_mcpdm_read(MCPDM_DN_OFFSET));
+	dev_dbg(mcpdm->dev, "***********************\n");
+}
+EXPORT_SYMBOL(omap_mcpdm_reg_dump);
+
+void omap_mcpdm_start(int links)
+{
+	int ctrl = omap_mcpdm_read(MCPDM_CTRL);
+
+	if (links & MCPDM_UPLINK)
+		ctrl &= ~SW_UP_RST;
+
+	if (links & MCPDM_DOWNLINK)
+		ctrl &= ~SW_DN_RST;
+
+	omap_mcpdm_write(MCPDM_CTRL, ctrl);
+}
+EXPORT_SYMBOL(omap_mcpdm_start);
+
+void omap_mcpdm_stop(int links)
+{
+	int ctrl = omap_mcpdm_read(MCPDM_CTRL);
+
+	if (links & MCPDM_UPLINK)
+		ctrl |= SW_UP_RST;
+
+	if (links & MCPDM_DOWNLINK)
+		ctrl |= SW_DN_RST;
+
+	omap_mcpdm_write(MCPDM_CTRL, ctrl);
+}
+EXPORT_SYMBOL(omap_mcpdm_stop);
+
+int omap_mcpdm_get_channels(int links, int channels)
+{
+	int count;
+
+	if (links & MCPDM_UPLINK)
+		channels &= PDM_UP_MASK | PDM_STATUS_MASK;
+
+	if (links & MCPDM_DOWNLINK)
+		channels &= PDM_DN_MASK | PDM_CMD_MASK;
+
+	/* Brian Kernighan's method for counting set bits */
+	for (count = 0; channels; count++)
+		channels &= channels - 1;
+
+	return count;
+}
+
+int omap_mcpdm_set_uplink(struct omap_mcpdm_link *uplink)
+{
+	int irq_mask = 0;
+	int ctrl;
+
+	if (!uplink)
+		return -EINVAL;
+
+	mcpdm->uplink = uplink;
+
+	/* Enable irq request generation */
+	irq_mask |= uplink->irq_mask & UPLINK_IRQ_MASK;
+	omap_mcpdm_write(MCPDM_IRQENABLE_SET, irq_mask);
+
+	/* Configure uplink threshold */
+	if (uplink->threshold > UP_THRES_MAX)
+		uplink->threshold = UP_THRES_MAX;
+
+	omap_mcpdm_write(MCPDM_FIFO_CTRL_UP, uplink->threshold);
+
+	/* Configure DMA controller */
+	omap_mcpdm_write(MCPDM_DMAENABLE_SET, DMA_UP_ENABLE);
+
+	/* Set pdm out format */
+	ctrl = omap_mcpdm_read(MCPDM_CTRL);
+	ctrl |= uplink->format & PDMOUTFORMAT;
+
+	/* Enable uplink channels */
+	ctrl |= uplink->channels & (PDM_UP_MASK | PDM_STATUS_MASK);
+	omap_mcpdm_write(MCPDM_CTRL, ctrl);
+
+	/* Calculate number of uplink channels */
+	mcpdm->up_channels = omap_mcpdm_get_channels(MCPDM_UPLINK,
+					uplink->channels);
+
+	return 0;
+}
+EXPORT_SYMBOL(omap_mcpdm_set_uplink);
+
+int omap_mcpdm_set_downlink(struct omap_mcpdm_link *downlink)
+{
+	int irq_mask = 0;
+	int ctrl;
+
+	if (!downlink)
+		return -EINVAL;
+
+	mcpdm->downlink = downlink;
+
+	/* Enable irq request generation */
+	irq_mask |= downlink->irq_mask & DOWNLINK_IRQ_MASK;
+	omap_mcpdm_write(MCPDM_IRQENABLE_SET, irq_mask);
+
+	/* Configure uplink threshold */
+	if (downlink->threshold > DN_THRES_MAX)
+		downlink->threshold = DN_THRES_MAX;
+
+	omap_mcpdm_write(MCPDM_FIFO_CTRL_DN, downlink->threshold);
+
+	/* Configure DMA controller */
+	omap_mcpdm_write(MCPDM_DMAENABLE_SET, DMA_DN_ENABLE);
+
+	/* Set pdm out format */
+	ctrl = omap_mcpdm_read(MCPDM_CTRL);
+	ctrl |= downlink->format & PDMOUTFORMAT;
+
+	/* Enable uplink channels */
+	ctrl |= downlink->channels & (PDM_DN_MASK | PDM_CMD_MASK);
+	omap_mcpdm_write(MCPDM_CTRL, ctrl);
+
+	/* Calculate number of downlink channels  */
+	mcpdm->dn_channels = omap_mcpdm_get_channels(MCPDM_DOWNLINK,
+			downlink->channels);
+
+	return 0;
+}
+EXPORT_SYMBOL(omap_mcpdm_set_downlink);
+
+static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
+{
+	struct omap_mcpdm *mcpdm_irq = dev_id;
+	int irq_status;
+
+	irq_status = omap_mcpdm_read(MCPDM_IRQSTATUS);
+	switch (irq_status) {
+	case DN_IRQ_FULL:
+	case DN_IRQ_EMTPY:
+		dev_dbg(mcpdm_irq->dev, "DN FIFO error %x\n", irq_status);
+		omap_mcpdm_stop(MCPDM_DOWNLINK);
+		omap_mcpdm_set_downlink(mcpdm_irq->downlink);
+		omap_mcpdm_start(MCPDM_DOWNLINK);
+		break;
+	case DN_IRQ:
+		dev_dbg(mcpdm_irq->dev, "DN write request\n");
+		break;
+	case UP_IRQ_FULL:
+	case UP_IRQ_EMPTY:
+		dev_dbg(mcpdm_irq->dev, "UP FIFO error %x\n", irq_status);
+		omap_mcpdm_stop(MCPDM_UPLINK);
+		omap_mcpdm_set_uplink(mcpdm_irq->uplink);
+		omap_mcpdm_start(MCPDM_UPLINK);
+		break;
+	case UP_IRQ:
+		dev_dbg(mcpdm_irq->dev, "UP write request\n");
+		break;
+	}
+
+	omap_mcpdm_write(MCPDM_IRQSTATUS, irq_status);
+
+	return IRQ_HANDLED;
+}
+
+int omap_mcpdm_request(void)
+{
+	int ret;
+
+	clk_enable(mcpdm->clk);
+
+	spin_lock(&mcpdm->lock);
+
+	if (!mcpdm->free) {
+		dev_err(mcpdm->dev, "McPDM interface is in use\n");
+		spin_unlock(&mcpdm->lock);
+		return -EBUSY;
+	}
+	mcpdm->free = 0;
+
+	spin_unlock(&mcpdm->lock);
+
+	/* Disable lines while request is ongoing */
+	omap_mcpdm_write(MCPDM_CTRL, 0x00);
+
+	ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
+				0, "McPDM", (void *)mcpdm);
+	if (ret) {
+		dev_err(mcpdm->dev, "Request for McPDM IRQ failed\n");
+		return ret;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(omap_mcpdm_request);
+
+void omap_mcpdm_free(void)
+{
+	clk_disable(mcpdm->clk);
+
+	spin_lock(&mcpdm->lock);
+	if (mcpdm->free) {
+		dev_err(mcpdm->dev, "McPDM interface is already free\n");
+		spin_unlock(&mcpdm->lock);
+	}
+	mcpdm->free = 1;
+	spin_unlock(&mcpdm->lock);
+
+	free_irq(mcpdm->irq, (void *)mcpdm);
+}
+EXPORT_SYMBOL(omap_mcpdm_free);
+
+int omap_mcpdm_set_offset(int offset1, int offset2)
+{
+	int offset;
+
+	if ((offset1 > DN_OFST_MAX) || (offset2 > DN_OFST_MAX))
+		return -EINVAL;
+
+	offset = (offset1 << DN_OFST_RX1) | (offset2 << DN_OFST_RX2);
+
+	/* Enable/disable offset cancellation for downlink channel 1 */
+	if (offset1)
+		offset |= DN_OFST_RX1_EN;
+	else
+		offset &= ~DN_OFST_RX1_EN;
+
+	/* Enable/disable offset cancellation for downlink channel 2 */
+	if (offset2)
+		offset |= DN_OFST_RX2_EN;
+	else
+		offset &= ~DN_OFST_RX2_EN;
+
+	omap_mcpdm_write(MCPDM_DN_OFFSET, offset);
+
+	return 0;
+}
+EXPORT_SYMBOL(omap_mcpdm_set_offset);
+
+static int __devinit omap_mcpdm_probe(struct platform_device *pdev)
+{
+	struct omap_mcpdm_platform_data *pdata = pdev->dev.platform_data;
+	int ret = 0;
+
+	if (!pdata) {
+		dev_err(&pdev->dev, "McPDM device initialized without "
+					"platform data\n");
+		ret = -EINVAL;
+		goto exit;
+	}
+	dev_dbg(&pdev->dev, "Initializing OMAP McPDM driver \n");
+
+	mcpdm = kzalloc(sizeof(struct omap_mcpdm), GFP_KERNEL);
+	if (!mcpdm) {
+		ret = -ENOMEM;
+		goto exit;
+	}
+
+	spin_lock_init(&mcpdm->lock);
+	mcpdm->free = 1;
+	mcpdm->phys_base = pdata->phys_base;
+	mcpdm->io_base = ioremap(mcpdm->phys_base, SZ_4K);
+	if (!mcpdm->io_base) {
+		ret = -ENOMEM;
+		goto err_ioremap;
+	}
+
+	mcpdm->irq = pdata->irq;
+
+	/* FIXME: Enable this ones correct clk nodes available */
+	if (!cpu_is_omap44xx()) {
+		mcpdm->clk = clk_get(&pdev->dev, "fclk");
+		if (IS_ERR(mcpdm->clk)) {
+			ret = PTR_ERR(mcpdm->clk);
+			dev_err(&pdev->dev, "unable to get fclk: %d\n", ret);
+			goto err_clk;
+		}
+	}
+
+	mcpdm->pdata = pdata;
+	mcpdm->dev = &pdev->dev;
+	platform_set_drvdata(pdev, mcpdm);
+
+
+	return 0;
+
+err_clk:
+	iounmap(mcpdm->io_base);
+err_ioremap:
+	kfree(mcpdm);
+exit:
+	return ret;
+}
+
+static int __devexit omap_mcpdm_remove(struct platform_device *pdev)
+{
+	struct omap_mcpdm *mcpdm_ptr = platform_get_drvdata(pdev);
+
+	platform_set_drvdata(pdev, NULL);
+
+	if (mcpdm_ptr) {
+		clk_disable(mcpdm_ptr->clk);
+		clk_put(mcpdm_ptr->clk);
+
+		iounmap(mcpdm_ptr->io_base);
+
+		mcpdm_ptr->clk = NULL;
+		mcpdm_ptr->free = 0;
+		mcpdm_ptr->dev = NULL;
+	}
+
+	printk(KERN_INFO "McPDM driver removed \n");
+
+	return 0;
+}
+
+static struct platform_driver omap_mcpdm_driver = {
+	.probe = omap_mcpdm_probe,
+	.remove = omap_mcpdm_remove,
+	.driver = {
+		.name = "omap-mcpdm",
+	},
+};
+
+static struct platform_device *omap_mcpdm_device;
+
+static struct omap_mcpdm_platform_data mcpdm_pdata = {
+	.phys_base = OMAP44XX_MCPDM_BASE,
+	.irq = INT_44XX_MCPDM_IRQ,
+};
+
+int __init omap_mcpdm_init(void)
+{
+	int ret;
+	struct platform_device *device;
+
+	device = platform_device_alloc("omap-mcpdm", -1);
+	device->dev.platform_data = &mcpdm_pdata;
+
+	omap_mcpdm_device = device;
+	(void) platform_device_add(omap_mcpdm_device);
+
+	ret = platform_driver_register(&omap_mcpdm_driver);
+	if (ret)
+		goto error;
+	return 0;
+
+error:
+	printk(KERN_ERR "OMAP McPDM initialization error\n");
+	return ret;
+}
+arch_initcall(omap_mcpdm_init);
diff --git a/sound/soc/omap/mcpdm.h b/sound/soc/omap/mcpdm.h
new file mode 100755
index 000000000000..9fd2dfbf2593
--- /dev/null
+++ b/sound/soc/omap/mcpdm.h
@@ -0,0 +1,152 @@
+/*
+ * mcpdm.h -- Defines for McPDM driver
+ *
+ * Author: Jorge Eduardo Candelaria <x0107209@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#define OMAP44XX_MCPDM_BASE	0x40132000
+
+/* McPDM registers */
+
+#define MCPDM_REVISION		0x00
+#define MCPDM_SYSCONFIG		0x10
+#define MCPDM_IRQSTATUS_RAW	0x24
+#define MCPDM_IRQSTATUS		0x28
+#define MCPDM_IRQENABLE_SET	0x2C
+#define MCPDM_IRQENABLE_CLR	0x30
+#define MCPDM_IRQWAKE_EN	0x34
+#define MCPDM_DMAENABLE_SET	0x38
+#define MCPDM_DMAENABLE_CLR	0x3C
+#define MCPDM_DMAWAKEEN		0x40
+#define MCPDM_CTRL		0x44
+#define MCPDM_DN_DATA		0x48
+#define MCPDM_UP_DATA		0x4C
+#define MCPDM_FIFO_CTRL_DN	0x50
+#define MCPDM_FIFO_CTRL_UP	0x54
+#define MCPDM_DN_OFFSET		0x58
+
+/*
+ * MCPDM_IRQ bit fields
+ * IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR
+ */
+
+#define DN_IRQ			(1 << 0)
+#define DN_IRQ_EMTPY		(1 << 1)
+#define DN_IRQ_ALMST_EMPTY	(1 << 2)
+#define DN_IRQ_FULL		(1 << 3)
+
+#define UP_IRQ			(1 << 8)
+#define UP_IRQ_EMPTY		(1 << 9)
+#define UP_IRQ_ALMST_FULL	(1 << 10)
+#define UP_IRQ_FULL		(1 << 11)
+
+#define DOWNLINK_IRQ_MASK	0x00F
+#define UPLINK_IRQ_MASK		0xF00
+
+/*
+ * MCPDM_DMAENABLE bit fields
+ */
+
+#define DMA_DN_ENABLE		0x1
+#define DMA_UP_ENABLE		0x2
+
+/*
+ * MCPDM_CTRL bit fields
+ */
+
+#define PDM_UP1_EN		0x0001
+#define PDM_UP2_EN		0x0002
+#define PDM_UP3_EN		0x0004
+#define PDM_DN1_EN		0x0008
+#define PDM_DN2_EN		0x0010
+#define PDM_DN3_EN		0x0020
+#define PDM_DN4_EN		0x0040
+#define PDM_DN5_EN		0x0080
+#define PDMOUTFORMAT		0x0100
+#define CMD_INT			0x0200
+#define STATUS_INT		0x0400
+#define SW_UP_RST		0x0800
+#define SW_DN_RST		0x1000
+#define PDM_UP_MASK		0x007
+#define PDM_DN_MASK		0x0F8
+#define PDM_CMD_MASK		0x200
+#define PDM_STATUS_MASK		0x400
+
+
+#define PDMOUTFORMAT_LJUST	(0 << 8)
+#define PDMOUTFORMAT_RJUST	(1 << 8)
+
+/*
+ * MCPDM_FIFO_CTRL bit fields
+ */
+
+#define UP_THRES_MAX		0xF
+#define DN_THRES_MAX		0xF
+
+/*
+ * MCPDM_DN_OFFSET bit fields
+ */
+
+#define DN_OFST_RX1_EN		0x0001
+#define DN_OFST_RX2_EN		0x0100
+
+#define DN_OFST_RX1		1
+#define DN_OFST_RX2		9
+#define DN_OFST_MAX		0x1F
+
+#define MCPDM_UPLINK		1
+#define MCPDM_DOWNLINK		2
+
+struct omap_mcpdm_link {
+	int irq_mask;
+	int threshold;
+	int format;
+	int channels;
+};
+
+struct omap_mcpdm_platform_data {
+	unsigned long phys_base;
+	u16 irq;
+};
+
+struct omap_mcpdm {
+	struct device *dev;
+	unsigned long phys_base;
+	void __iomem *io_base;
+	u8 free;
+	int irq;
+
+	spinlock_t lock;
+	struct omap_mcpdm_platform_data *pdata;
+	struct clk *clk;
+	struct omap_mcpdm_link *downlink;
+	struct omap_mcpdm_link *uplink;
+	struct completion irq_completion;
+
+	int dn_channels;
+	int up_channels;
+};
+
+void omap_mcpdm_reg_dump(void);
+void omap_mcpdm_start(int links);
+void omap_mcpdm_stop(int links);
+int omap_mcpdm_set_uplink(struct omap_mcpdm_link *uplink);
+int omap_mcpdm_set_downlink(struct omap_mcpdm_link *downlink);
+int omap_mcpdm_request(void);
+void omap_mcpdm_free(void);
+int omap_mcpdm_set_offset(int offset1, int offset2);