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authorKrish Sadhukhan <krish.sadhukhan@oracle.com>2020-09-17 21:20:38 +0000
committerBorislav Petkov <bp@suse.de>2020-09-19 20:46:59 +0200
commite1ebb2b49048c4767cfa0d8466f9c701e549fa5e (patch)
tree2b9bf9e48ea3daa5d2fca77dd780a4b8d23b9631
parent75d1cc0e05af579301ce4e49cf6399be4b4e6e76 (diff)
KVM: SVM: Don't flush cache if hardware enforces cache coherency across encryption domainsx86_cpu_for_v5.10
In some hardware implementations, coherency between the encrypted and unencrypted mappings of the same physical page in a VM is enforced. In such a system, it is not required for software to flush the VM's page from all CPU caches in the system prior to changing the value of the C-bit for the page. So check that bit before flushing the cache. Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Link: https://lkml.kernel.org/r/20200917212038.5090-4-krish.sadhukhan@oracle.com
-rw-r--r--arch/x86/kvm/svm/sev.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c
index 402dc4234e39..567792fbbc9f 100644
--- a/arch/x86/kvm/svm/sev.c
+++ b/arch/x86/kvm/svm/sev.c
@@ -384,7 +384,8 @@ static void sev_clflush_pages(struct page *pages[], unsigned long npages)
uint8_t *page_virtual;
unsigned long i;
- if (npages == 0 || pages == NULL)
+ if (this_cpu_has(X86_FEATURE_SME_COHERENT) || npages == 0 ||
+ pages == NULL)
return;
for (i = 0; i < npages; i++) {