diff options
author | Mateusz Jończyk <mat.jonczyk@o2.pl> | 2025-03-22 16:45:41 +0100 |
---|---|---|
committer | Ingo Molnar <mingo@kernel.org> | 2025-03-25 08:17:49 +0100 |
commit | 99bb1bd810eaf37e15ef757a30a815e774a2445b (patch) | |
tree | 2796624e30e42079a302afb73236a3073da51f0b | |
parent | 2487b6b9bf2874cfca7efb59c95650c5b1d88d43 (diff) |
x86/Kconfig: Correct X86_X2APIC help text
Currently, it is not true that the kernel will panic with CONFIG_X86_X2APIC=n
on systems that require it; it will try to disable the APIC and run without
it to at least give the user a clear warning message. See the second
variant of check_x2apic() in arch/x86/kernel/apic/apic.c .
Also massage some other parts of the help text.
Fixes: 9232c49ff31c ("x86/Kconfig: Enable X86_X2APIC by default and improve help text")
Signed-off-by: Mateusz Jończyk <mat.jonczyk@o2.pl>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20250322154541.40325-1-mat.jonczyk@o2.pl
-rw-r--r-- | arch/x86/Kconfig | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index e72cb7779038..ef48584c8889 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -471,14 +471,15 @@ config X86_X2APIC in 2019, but it can be disabled by the BIOS. It is also frequently emulated in virtual machines, even when the host CPU does not support it. Support in the CPU can be checked by executing - cat /proc/cpuinfo | grep x2apic + grep x2apic /proc/cpuinfo - If this configuration option is disabled, the kernel will not boot on - some platforms that have x2APIC enabled. + If this configuration option is disabled, the kernel will boot with + very reduced functionality and performance on some platforms that + have x2APIC enabled. On the other hand, on hardware that does not + support x2APIC, a kernel with this option enabled will just fallback + to older APIC implementations. - Say N if you know that your platform does not have x2APIC. - - Otherwise, say Y. + If in doubt, say Y. config X86_POSTED_MSI bool "Enable MSI and MSI-x delivery by posted interrupts" |