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-rw-r--r--drivers/net/ipa/ipa_data-sc7180.c11
-rw-r--r--drivers/net/ipa/ipa_data-sdm845.c9
-rw-r--r--drivers/net/ipa/ipa_data.h36
-rw-r--r--drivers/net/ipa/ipa_endpoint.c14
-rw-r--r--drivers/net/ipa/ipa_endpoint.h1
-rw-r--r--drivers/net/ipa/ipa_main.c77
-rw-r--r--drivers/net/ipa/ipa_reg.h46
7 files changed, 97 insertions, 97 deletions
diff --git a/drivers/net/ipa/ipa_data-sc7180.c b/drivers/net/ipa/ipa_data-sc7180.c
index 216f790b22b6..621ad15c9e67 100644
--- a/drivers/net/ipa/ipa_data-sc7180.c
+++ b/drivers/net/ipa/ipa_data-sc7180.c
@@ -14,6 +14,7 @@ static const struct ipa_qsb_data ipa_qsb_data[] = {
[IPA_QSB_MASTER_DDR] = {
.max_writes = 8,
.max_reads = 12,
+ /* no outstanding read byte (beat) limit */
},
};
@@ -30,11 +31,13 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
.tlv_count = 20,
},
.endpoint = {
- .seq_type = IPA_SEQ_DMA_ONLY,
.config = {
.resource_group = 0,
.dma_mode = true,
.dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
+ .tx = {
+ .seq_type = IPA_SEQ_DMA,
+ },
},
},
},
@@ -49,7 +52,6 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
.tlv_count = 6,
},
.endpoint = {
- .seq_type = IPA_SEQ_INVALID,
.config = {
.resource_group = 0,
.aggregation = true,
@@ -72,14 +74,14 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
},
.endpoint = {
.filter_support = true,
- .seq_type =
- IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP,
.config = {
.resource_group = 0,
.checksum = true,
.qmap = true,
.status_enable = true,
.tx = {
+ .seq_type = IPA_SEQ_1_PASS_SKIP_LAST_UC,
+ .seq_rep_type = IPA_SEQ_REP_DMA_PARSER,
.status_endpoint =
IPA_ENDPOINT_MODEM_AP_RX,
},
@@ -97,7 +99,6 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
.tlv_count = 6,
},
.endpoint = {
- .seq_type = IPA_SEQ_INVALID,
.config = {
.resource_group = 0,
.checksum = true,
diff --git a/drivers/net/ipa/ipa_data-sdm845.c b/drivers/net/ipa/ipa_data-sdm845.c
index d9659fd22322..6b5173f47444 100644
--- a/drivers/net/ipa/ipa_data-sdm845.c
+++ b/drivers/net/ipa/ipa_data-sdm845.c
@@ -36,11 +36,13 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
.tlv_count = 20,
},
.endpoint = {
- .seq_type = IPA_SEQ_DMA_ONLY,
.config = {
.resource_group = 1,
.dma_mode = true,
.dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
+ .tx = {
+ .seq_type = IPA_SEQ_DMA,
+ },
},
},
},
@@ -55,7 +57,6 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
.tlv_count = 8,
},
.endpoint = {
- .seq_type = IPA_SEQ_INVALID,
.config = {
.resource_group = 1,
.aggregation = true,
@@ -78,14 +79,13 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
},
.endpoint = {
.filter_support = true,
- .seq_type =
- IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
.config = {
.resource_group = 1,
.checksum = true,
.qmap = true,
.status_enable = true,
.tx = {
+ .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
.status_endpoint =
IPA_ENDPOINT_MODEM_AP_RX,
},
@@ -103,7 +103,6 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
.tlv_count = 8,
},
.endpoint = {
- .seq_type = IPA_SEQ_INVALID,
.config = {
.resource_group = 1,
.checksum = true,
diff --git a/drivers/net/ipa/ipa_data.h b/drivers/net/ipa/ipa_data.h
index d50cd5ae7714..7816583fc14a 100644
--- a/drivers/net/ipa/ipa_data.h
+++ b/drivers/net/ipa/ipa_data.h
@@ -18,8 +18,9 @@
* Boot-time configuration data is used to define the configuration of the
* IPA and GSI resources to use for a given platform. This data is supplied
* via the Device Tree match table, associated with a particular compatible
- * string. The data defines information about resources, endpoints, and
- * channels.
+ * string. The data defines information about how resources, endpoints and
+ * channels, memory, clocking and so on are allocated and used for the
+ * platform.
*
* Resources are data structures used internally by the IPA hardware. The
* configuration data defines the number (or limits of the number) of various
@@ -59,10 +60,12 @@ enum ipa_qsb_master_id {
* struct ipa_qsb_data - Qualcomm System Bus configuration data
* @max_writes: Maximum outstanding write requests for this master
* @max_reads: Maximum outstanding read requests for this master
+ * @max_reads_beats: Max outstanding read bytes in 8-byte "beats" (if non-zero)
*/
struct ipa_qsb_data {
u8 max_writes;
u8 max_reads;
+ u8 max_reads_beats; /* Not present for IPA v3.5.1 */
};
/**
@@ -73,10 +76,10 @@ struct ipa_qsb_data {
*
* A GSI channel is a unidirectional means of transferring data to or
* from (and through) the IPA. A GSI channel has a ring buffer made
- * up of "transfer elements" (TREs) that specify individual data transfers
- * or IPA immediate commands. TREs are filled by the AP, and control
- * is passed to IPA hardware by writing the last written element
- * into a doorbell register.
+ * up of "transfer ring elements" (TREs) that specify individual data
+ * transfers or IPA immediate commands. TREs are filled by the AP,
+ * and control is passed to IPA hardware by writing the last written
+ * element into a doorbell register.
*
* When data transfer commands have completed the GSI generates an
* event (a structure of data) and optionally signals the AP with
@@ -95,12 +98,16 @@ struct gsi_channel_data {
/**
* struct ipa_endpoint_tx_data - configuration data for TX endpoints
+ * @seq_type: primary packet processing sequencer type
+ * @seq_rep_type: sequencer type for replication processing
* @status_endpoint: endpoint to which status elements are sent
*
* The @status_endpoint is only valid if the endpoint's @status_enable
* flag is set.
*/
struct ipa_endpoint_tx_data {
+ enum ipa_seq_type seq_type;
+ enum ipa_seq_rep_type seq_rep_type;
enum ipa_endpoint_name status_endpoint;
};
@@ -152,7 +159,6 @@ struct ipa_endpoint_config_data {
/**
* struct ipa_endpoint_data - IPA endpoint configuration data
* @filter_support: whether endpoint supports filtering
- * @seq_type: hardware sequencer type used for endpoint
* @config: hardware configuration (see above)
*
* Not all endpoints support the IPA filtering capability. A filter table
@@ -162,14 +168,10 @@ struct ipa_endpoint_config_data {
* in the system, and indicate whether they support filtering.
*
* The remaining endpoint configuration data applies only to AP endpoints.
- * The IPA hardware is implemented by sequencers, and the AP must program
- * the type(s) of these sequencers at initialization time. The remaining
- * endpoint configuration data is defined above.
*/
struct ipa_endpoint_data {
bool filter_support;
- /* The next two are specified only for AP endpoints */
- enum ipa_seq_type seq_type;
+ /* Everything else is specified only for AP endpoints */
struct ipa_endpoint_config_data config;
};
@@ -263,7 +265,7 @@ struct ipa_resource_data {
* @imem_addr: physical address of IPA region within IMEM
* @imem_size: size in bytes of IPA IMEM region
* @smem_id: item identifier for IPA region within SMEM memory
- * @imem_size: size in bytes of the IPA SMEM region
+ * @smem_size: size in bytes of the IPA SMEM region
*/
struct ipa_mem_data {
u32 local_count;
@@ -306,14 +308,14 @@ struct ipa_clock_data {
* @endpoint_count: number of entries in the endpoint_data array
* @endpoint_data: IPA endpoint/GSI channel data
* @resource_data: IPA resource configuration data
- * @mem_count: number of entries in the mem_data array
- * @mem_data: IPA-local shared memory region data
+ * @mem_data: IPA memory region data
+ * @clock_data: IPA clock and interconnect data
*/
struct ipa_data {
enum ipa_version version;
- u32 qsb_count; /* # entries in qsb_data[] */
+ u32 qsb_count; /* number of entries in qsb_data[] */
const struct ipa_qsb_data *qsb_data;
- u32 endpoint_count; /* # entries in endpoint_data[] */
+ u32 endpoint_count; /* number of entries in endpoint_data[] */
const struct ipa_gsi_endpoint_data *endpoint_data;
const struct ipa_resource_data *resource_data;
const struct ipa_mem_data *mem_data;
diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c
index 7209ee3c3124..88310d358557 100644
--- a/drivers/net/ipa/ipa_endpoint.c
+++ b/drivers/net/ipa/ipa_endpoint.c
@@ -884,18 +884,17 @@ static void ipa_endpoint_init_rsrc_grp(struct ipa_endpoint *endpoint)
static void ipa_endpoint_init_seq(struct ipa_endpoint *endpoint)
{
u32 offset = IPA_REG_ENDP_INIT_SEQ_N_OFFSET(endpoint->endpoint_id);
- u32 seq_type = endpoint->seq_type;
u32 val = 0;
if (!endpoint->toward_ipa)
return; /* Register not valid for RX endpoints */
- /* Sequencer type is made up of four nibbles */
- val |= u32_encode_bits(seq_type & 0xf, HPS_SEQ_TYPE_FMASK);
- val |= u32_encode_bits((seq_type >> 4) & 0xf, DPS_SEQ_TYPE_FMASK);
- /* The second two apply to replicated packets */
- val |= u32_encode_bits((seq_type >> 8) & 0xf, HPS_REP_SEQ_TYPE_FMASK);
- val |= u32_encode_bits((seq_type >> 12) & 0xf, DPS_REP_SEQ_TYPE_FMASK);
+ /* Low-order byte configures primary packet processing */
+ val |= u32_encode_bits(endpoint->data->tx.seq_type, SEQ_TYPE_FMASK);
+
+ /* Second byte configures replicated packet processing */
+ val |= u32_encode_bits(endpoint->data->tx.seq_rep_type,
+ SEQ_REP_TYPE_FMASK);
iowrite32(val, endpoint->ipa->reg_virt + offset);
}
@@ -1766,7 +1765,6 @@ static void ipa_endpoint_init_one(struct ipa *ipa, enum ipa_endpoint_name name,
endpoint->ipa = ipa;
endpoint->ee_id = data->ee_id;
- endpoint->seq_type = data->endpoint.seq_type;
endpoint->channel_id = data->channel_id;
endpoint->endpoint_id = data->endpoint_id;
endpoint->toward_ipa = data->toward_ipa;
diff --git a/drivers/net/ipa/ipa_endpoint.h b/drivers/net/ipa/ipa_endpoint.h
index 881ecc27bd6e..c6c55ea35394 100644
--- a/drivers/net/ipa/ipa_endpoint.h
+++ b/drivers/net/ipa/ipa_endpoint.h
@@ -46,7 +46,6 @@ enum ipa_endpoint_name {
*/
struct ipa_endpoint {
struct ipa *ipa;
- enum ipa_seq_type seq_type;
enum gsi_ee_id ee_id;
u32 channel_id;
u32 endpoint_id;
diff --git a/drivers/net/ipa/ipa_main.c b/drivers/net/ipa/ipa_main.c
index d354e3e65ec5..64b92dfdd3f5 100644
--- a/drivers/net/ipa/ipa_main.c
+++ b/drivers/net/ipa/ipa_main.c
@@ -249,52 +249,40 @@ static void ipa_hardware_config_comp(struct ipa *ipa)
iowrite32(val, ipa->reg_virt + IPA_REG_COMP_CFG_OFFSET);
}
-/* Configure DDR and PCIe max read/write QSB values */
-static void ipa_hardware_config_qsb(struct ipa *ipa)
+/* Configure DDR and (possibly) PCIe max read/write QSB values */
+static void
+ipa_hardware_config_qsb(struct ipa *ipa, const struct ipa_data *data)
{
- enum ipa_version version = ipa->version;
- u32 max0;
- u32 max1;
+ const struct ipa_qsb_data *data0;
+ const struct ipa_qsb_data *data1;
u32 val;
- /* QMB_0 represents DDR; QMB_1 represents PCIe */
- val = u32_encode_bits(8, GEN_QMB_0_MAX_WRITES_FMASK);
- switch (version) {
- case IPA_VERSION_4_2:
- max1 = 0; /* PCIe not present */
- break;
- case IPA_VERSION_4_5:
- max1 = 8;
- break;
- default:
- max1 = 4;
- break;
- }
- val |= u32_encode_bits(max1, GEN_QMB_1_MAX_WRITES_FMASK);
+ /* assert(data->qsb_count > 0); */
+ /* assert(data->qsb_count < 3); */
+
+ /* QMB 0 represents DDR; QMB 1 (if present) represents PCIe */
+ data0 = &data->qsb_data[IPA_QSB_MASTER_DDR];
+ if (data->qsb_count > 1)
+ data1 = &data->qsb_data[IPA_QSB_MASTER_PCIE];
+
+ /* Max outstanding write accesses for QSB masters */
+ val = u32_encode_bits(data0->max_writes, GEN_QMB_0_MAX_WRITES_FMASK);
+ if (data->qsb_count > 1)
+ val |= u32_encode_bits(data1->max_writes,
+ GEN_QMB_1_MAX_WRITES_FMASK);
iowrite32(val, ipa->reg_virt + IPA_REG_QSB_MAX_WRITES_OFFSET);
- max1 = 12;
- switch (version) {
- case IPA_VERSION_3_5_1:
- max0 = 8;
- break;
- case IPA_VERSION_4_0:
- case IPA_VERSION_4_1:
- max0 = 12;
- break;
- case IPA_VERSION_4_2:
- max0 = 12;
- max1 = 0; /* PCIe not present */
- break;
- case IPA_VERSION_4_5:
- max0 = 0; /* No limit (hardware maximum) */
- break;
- }
- val = u32_encode_bits(max0, GEN_QMB_0_MAX_READS_FMASK);
- val |= u32_encode_bits(max1, GEN_QMB_1_MAX_READS_FMASK);
- if (version != IPA_VERSION_3_5_1) {
- /* GEN_QMB_0_MAX_READS_BEATS is 0 */
- /* GEN_QMB_1_MAX_READS_BEATS is 0 */
+ /* Max outstanding read accesses for QSB masters */
+ val = u32_encode_bits(data0->max_reads, GEN_QMB_0_MAX_READS_FMASK);
+ if (ipa->version >= IPA_VERSION_4_0)
+ val |= u32_encode_bits(data0->max_reads_beats,
+ GEN_QMB_0_MAX_READS_BEATS_FMASK);
+ if (data->qsb_count > 1) {
+ val |= u32_encode_bits(data1->max_reads,
+ GEN_QMB_1_MAX_READS_FMASK);
+ if (ipa->version >= IPA_VERSION_4_0)
+ val |= u32_encode_bits(data1->max_reads_beats,
+ GEN_QMB_1_MAX_READS_BEATS_FMASK);
}
iowrite32(val, ipa->reg_virt + IPA_REG_QSB_MAX_READS_OFFSET);
}
@@ -385,8 +373,9 @@ static void ipa_hardware_dcd_deconfig(struct ipa *ipa)
/**
* ipa_hardware_config() - Primitive hardware initialization
* @ipa: IPA pointer
+ * @data: IPA configuration data
*/
-static void ipa_hardware_config(struct ipa *ipa)
+static void ipa_hardware_config(struct ipa *ipa, const struct ipa_data *data)
{
enum ipa_version version = ipa->version;
u32 granularity;
@@ -414,7 +403,7 @@ static void ipa_hardware_config(struct ipa *ipa)
ipa_hardware_config_comp(ipa);
/* Configure system bus limits */
- ipa_hardware_config_qsb(ipa);
+ ipa_hardware_config_qsb(ipa, data);
if (version < IPA_VERSION_4_5) {
/* Configure aggregation timer granularity */
@@ -610,7 +599,7 @@ static int ipa_config(struct ipa *ipa, const struct ipa_data *data)
*/
ipa_clock_get(ipa);
- ipa_hardware_config(ipa);
+ ipa_hardware_config(ipa, data);
ret = ipa_endpoint_config(ipa);
if (ret)
diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h
index 732e691e9aa6..36fe746575f6 100644
--- a/drivers/net/ipa/ipa_reg.h
+++ b/drivers/net/ipa/ipa_reg.h
@@ -580,28 +580,40 @@ static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp)
/* Valid only for TX (IPA consumer) endpoints */
#define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(txep) \
(0x0000083c + 0x0070 * (txep))
-#define HPS_SEQ_TYPE_FMASK GENMASK(3, 0)
-#define DPS_SEQ_TYPE_FMASK GENMASK(7, 4)
-#define HPS_REP_SEQ_TYPE_FMASK GENMASK(11, 8)
-#define DPS_REP_SEQ_TYPE_FMASK GENMASK(15, 12)
+#define SEQ_TYPE_FMASK GENMASK(7, 0)
+#define SEQ_REP_TYPE_FMASK GENMASK(15, 8)
/**
- * enum ipa_seq_type - HPS and DPS sequencer type fields in ENDP_INIT_SEQ_N
- * @IPA_SEQ_DMA_ONLY: only DMA is performed
- * @IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP:
- * second packet processing pass + no decipher + microcontroller
- * @IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP:
- * packet processing + no decipher + no uCP + HPS REP DMA parser
- * @IPA_SEQ_INVALID: invalid sequencer type
+ * enum ipa_seq_type - HPS and DPS sequencer type
*
- * The values defined here are broken into 4-bit nibbles that are written
- * into fields of the ENDP_INIT_SEQ registers.
+ * The low-order byte of the sequencer type register defines the number of
+ * passes a packet takes through the IPA pipeline. The last pass through can
+ * optionally skip the microprocessor. Deciphering is optional for all types;
+ * if enabled, an additional mask (two bits) is added to the type value.
+ *
+ * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are
+ * supported (or meaningful).
*/
+#define IPA_SEQ_DECIPHER 0x11
enum ipa_seq_type {
- IPA_SEQ_DMA_ONLY = 0x0000,
- IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP = 0x0004,
- IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP = 0x0806,
- IPA_SEQ_INVALID = 0xffff,
+ IPA_SEQ_DMA = 0x00,
+ IPA_SEQ_1_PASS = 0x02,
+ IPA_SEQ_2_PASS_SKIP_LAST_UC = 0x04,
+ IPA_SEQ_1_PASS_SKIP_LAST_UC = 0x06,
+ IPA_SEQ_2_PASS = 0x0a,
+ IPA_SEQ_3_PASS_SKIP_LAST_UC = 0x0c,
+};
+
+/**
+ * enum ipa_seq_rep_type - replicated packet sequencer type
+ *
+ * This goes in the second byte of the endpoint sequencer type register.
+ *
+ * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are
+ * supported (or meaningful).
+ */
+enum ipa_seq_rep_type {
+ IPA_SEQ_REP_DMA_PARSER = 0x08,
};
#define IPA_REG_ENDP_STATUS_N_OFFSET(ep) \
generated by cgit v1.2.3 (git 2.46.0) at 2025-07-17 10:35:47 +0000