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-rw-r--r--arch/x86/kernel/cpu/cacheinfo.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index cd48d34ac04b..f4817cd50cfb 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -91,6 +91,8 @@ static const enum cache_type cache_type_map[] = {
* AMD CPUs with TOPOEXT can just use CPUID(0x8000001d)
*/
+#define AMD_CPUID4_FULLY_ASSOCIATIVE 0xffff
+
union l1_cache {
struct {
unsigned line_size :8;
@@ -122,6 +124,7 @@ union l3_cache {
unsigned int val;
};
+/* L2/L3 associativity mapping */
static const unsigned short assocs[] = {
[1] = 1,
[2] = 2,
@@ -133,7 +136,7 @@ static const unsigned short assocs[] = {
[0xc] = 64,
[0xd] = 96,
[0xe] = 128,
- [0xf] = 0xffff /* Fully associative */
+ [0xf] = AMD_CPUID4_FULLY_ASSOCIATIVE
};
static const unsigned char levels[] = { 1, 1, 2, 3 };
@@ -163,7 +166,7 @@ static void legacy_amd_cpuid4(int index, union _cpuid4_leaf_eax *eax,
if (!l1->val)
return;
- assoc = assocs[l1->assoc];
+ assoc = (l1->assoc == 0xff) ? AMD_CPUID4_FULLY_ASSOCIATIVE : l1->assoc;
line_size = l1->line_size;
lines_per_tag = l1->lines_per_tag;
size_in_kb = l1->size_in_kb;
@@ -201,7 +204,7 @@ static void legacy_amd_cpuid4(int index, union _cpuid4_leaf_eax *eax,
eax->split.num_threads_sharing = 0;
eax->split.num_cores_on_die = topology_num_cores_per_package();
- if (assoc == 0xffff)
+ if (assoc == AMD_CPUID4_FULLY_ASSOCIATIVE)
eax->split.is_fully_associative = 1;
ebx->split.coherency_line_size = line_size - 1;