diff options
649 files changed, 6919 insertions, 5413 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index f8903abcdb88..13ebb1f71e49 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -171,7 +171,8 @@ amdgpu-y += \ # add SMUIO block amdgpu-y += \ smuio_v9_0.o \ - smuio_v11_0.o + smuio_v11_0.o \ + smuio_v11_0_6.o # add amdkfd interfaces amdgpu-y += amdgpu_amdkfd.o diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index f4ff8ddb52d4..86452f4f3c82 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -287,7 +287,7 @@ enum amdgpu_kiq_irq { #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ -#define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ +#define MAX_KIQ_REG_TRY 1000 int amdgpu_device_ip_set_clockgating_state(void *dev, enum amd_ip_block_type block_type, @@ -579,7 +579,8 @@ enum amd_reset_method { AMD_RESET_METHOD_MODE0, AMD_RESET_METHOD_MODE1, AMD_RESET_METHOD_MODE2, - AMD_RESET_METHOD_BACO + AMD_RESET_METHOD_BACO, + AMD_RESET_METHOD_PCI, }; /* @@ -891,6 +892,7 @@ struct amdgpu_device { /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ struct work_struct hotplug_work; struct amdgpu_irq_src crtc_irq; + struct amdgpu_irq_src vline0_irq; struct amdgpu_irq_src vupdate_irq; struct amdgpu_irq_src pageflip_irq; struct amdgpu_irq_src hpd_irq; @@ -1227,6 +1229,7 @@ bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); int amdgpu_device_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job* job); void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); +int amdgpu_device_pci_reset(struct amdgpu_device *adev); bool amdgpu_device_need_post(struct amdgpu_device *adev); void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 594a0108e90f..3e240b952e79 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -98,8 +98,7 @@ static int amdgpu_cs_bo_handles_chunk(struct amdgpu_cs_parser *p, return 0; error_free: - if (info) - kvfree(info); + kvfree(info); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 51bea409e513..7052dc35d278 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -929,6 +929,18 @@ void amdgpu_device_pci_config_reset(struct amdgpu_device *adev) pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); } +/** + * amdgpu_device_pci_reset - reset the GPU using generic PCI means + * + * @adev: amdgpu_device pointer + * + * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.). + */ +int amdgpu_device_pci_reset(struct amdgpu_device *adev) +{ + return pci_reset_function(adev->pdev); +} + /* * GPU doorbell aperture helpers function. */ @@ -1433,10 +1445,8 @@ static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, amdgpu_device_resume(dev, true); dev->switch_power_state = DRM_SWITCH_POWER_ON; - drm_kms_helper_poll_enable(dev); } else { pr_info("switched off\n"); - drm_kms_helper_poll_disable(dev); dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; amdgpu_device_suspend(dev, true); amdgpu_device_cache_pci_state(pdev); @@ -3724,7 +3734,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) r = amdgpu_device_ip_suspend_phase1(adev); - amdgpu_amdkfd_suspend(adev, !fbcon); + amdgpu_amdkfd_suspend(adev, adev->in_runpm); /* evict vram memory */ amdgpu_bo_evict_vram(adev); @@ -3808,7 +3818,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon) } } } - r = amdgpu_amdkfd_resume(adev, !fbcon); + r = amdgpu_amdkfd_resume(adev, adev->in_runpm); if (r) return r; @@ -4211,6 +4221,7 @@ bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev) case CHIP_NAVI12: case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: + case CHIP_DIMGREY_CAVEFISH: break; default: goto disabled; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 8fde2318a03c..03c529630c21 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -132,8 +132,12 @@ uint amdgpu_pg_mask = 0xffffffff; uint amdgpu_sdma_phase_quantum = 32; char *amdgpu_disable_cu = NULL; char *amdgpu_virtual_display = NULL; -/* OverDrive(bit 14) disabled by default*/ -uint amdgpu_pp_feature_mask = 0xffffbfff; + +/* + * OverDrive(bit 14) disabled by default + * GFX DCS(bit 19) disabled by default + */ +uint amdgpu_pp_feature_mask = 0xfff7bfff; uint amdgpu_force_long_training; int amdgpu_job_hang_limit; int amdgpu_lbpw = -1; @@ -789,9 +793,9 @@ module_param_named(tmz, amdgpu_tmz, int, 0444); /** * DOC: reset_method (int) - * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) + * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco, 5 = pci) */ -MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); +MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco, 5 = pci)"); module_param_named(reset_method, amdgpu_reset_method, int, 0444); /** @@ -1344,11 +1348,12 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev) adev->in_runpm = true; if (amdgpu_device_supports_atpx(drm_dev)) drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; - drm_kms_helper_poll_disable(drm_dev); ret = amdgpu_device_suspend(drm_dev, false); - if (ret) + if (ret) { + adev->in_runpm = false; return ret; + } if (amdgpu_device_supports_atpx(drm_dev)) { /* Only need to handle PCI state in the driver for ATPX @@ -1401,7 +1406,6 @@ static int amdgpu_pmops_runtime_resume(struct device *dev) amdgpu_device_baco_exit(drm_dev); } ret = amdgpu_device_resume(drm_dev, false); - drm_kms_helper_poll_enable(drm_dev); if (amdgpu_device_supports_atpx(drm_dev)) drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; adev->in_runpm = false; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index cd2c676a2797..8e0a6c62322e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -193,15 +193,16 @@ static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev) } bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev, - int pipe, int queue) + struct amdgpu_ring *ring) { - bool multipipe_policy = amdgpu_gfx_is_multipipe_capable(adev); - int cond; - /* Policy: alternate between normal and high priority */ - cond = multipipe_policy ? pipe : queue; - - return ((cond % 2) != 0); + /* Policy: use 1st queue as high priority compute queue if we + * have more than one compute queue. + */ + if (adev->gfx.num_compute_rings > 1 && + ring == &adev->gfx.compute_ring[0]) + return true; + return false; } void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index 6b5a8f4642cc..72dbcd2bc6a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -380,7 +380,7 @@ void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec, int pipe, int queue); bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev, - int pipe, int queue); + struct amdgpu_ring *ring); int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me, int pipe, int queue); void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 024d0a563a65..7645223ea0ef 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -195,6 +195,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync) ring->funcs->emit_mem_sync(ring); + if (ring->funcs->emit_wave_limit && + ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH) + ring->funcs->emit_wave_limit(ring, true); + if (ring->funcs->insert_start) ring->funcs->insert_start(ring); @@ -295,6 +299,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, ring->current_ctx = fence_ctx; if (vm && ring->funcs->emit_switch_buffer) amdgpu_ring_emit_switch_buffer(ring); + + if (ring->funcs->emit_wave_limit && + ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH) + ring->funcs->emit_wave_limit(ring, false); + amdgpu_ring_commit(ring); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h index 4ba0024aedf1..7c11bce4514b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h @@ -88,6 +88,7 @@ struct amdgpu_nbio_funcs { int (*ras_late_init)(struct amdgpu_device *adev); void (*enable_aspm)(struct amdgpu_device *adev, bool enable); + void (*program_aspm)(struct amdgpu_device *adev); }; struct amdgpu_nbio { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 1a612f51ecd9..b644c78475fd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -166,7 +166,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int max_dw, struct amdgpu_irq_src *irq_src, unsigned int irq_type, unsigned int hw_prio) { - int r, i; + int r; int sched_hw_submission = amdgpu_sched_hw_submission; u32 *num_sched; u32 hw_ip; @@ -258,8 +258,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, } ring->max_dw = max_dw; - ring->priority = DRM_SCHED_PRIORITY_NORMAL; - mutex_init(&ring->priority_mutex); + ring->hw_prio = hw_prio; if (!ring->no_scheduler) { hw_ip = ring->funcs->type; @@ -268,9 +267,6 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, &ring->sched; } - for (i = DRM_SCHED_PRIORITY_MIN; i < DRM_SCHED_PRIORITY_COUNT; ++i) - atomic_set(&ring->num_jobs[i], 0); - return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 7112137689db..56acec1075ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -197,6 +197,7 @@ struct amdgpu_ring_funcs { void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid); int (*preempt_ib)(struct amdgpu_ring *ring); void (*emit_mem_sync)(struct amdgpu_ring *ring); + void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable); }; struct amdgpu_ring { @@ -242,11 +243,7 @@ struct amdgpu_ring { struct dma_fence *vmid_wait; bool has_compute_vm_bug; bool no_scheduler; - - atomic_t num_jobs[DRM_SCHED_PRIORITY_COUNT]; - struct mutex priority_mutex; - /* protected by priority_mutex */ - int priority; + int hw_prio; #if defined(CONFIG_DEBUG_FS) struct dentry *ent; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c index 541ef6be390f..659b385b27b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c @@ -324,7 +324,7 @@ static void amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device *adev, struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev) { - struct amdgpu_hive_info *hive = NULL, *tmp = NULL; + struct amdgpu_hive_info *hive = NULL; int ret; if (!adev->gmc.xgmi.hive_id) @@ -337,11 +337,9 @@ struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev) mutex_lock(&xgmi_mutex); - if (!list_empty(&xgmi_hive_list)) { - list_for_each_entry_safe(hive, tmp, &xgmi_hive_list, node) { - if (hive->hive_id == adev->gmc.xgmi.hive_id) - goto pro_end; - } + list_for_each_entry(hive, &xgmi_hive_list, node) { + if (hive->hive_id == adev->gmc.xgmi.hive_id) + goto pro_end; } hive = kzalloc(sizeof(*hive), GFP_KERNEL); diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 13737b317f7c..4d6832cc7fb0 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -1251,13 +1251,22 @@ static void kv_restore_regs_for_reset(struct amdgpu_device *adev, WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute); } -static int cik_gpu_pci_config_reset(struct amdgpu_device *adev) +/** + * cik_asic_pci_config_reset - soft reset GPU + * + * @adev: amdgpu_device pointer + * + * Use PCI Config method to reset the GPU. + * + * Returns 0 for success. + */ +static int cik_asic_pci_config_reset(struct amdgpu_device *adev) { struct kv_reset_save_regs kv_save = { 0 }; u32 i; int r = -EINVAL; - dev_info(adev->dev, "GPU pci config reset\n"); + amdgpu_atombios_scratch_regs_engine_hung(adev, true); if (adev->flags & AMD_IS_APU) kv_save_regs_for_reset(adev, &kv_save); @@ -1285,26 +1294,6 @@ static int cik_gpu_pci_config_reset(struct amdgpu_device *adev) if (adev->flags & AMD_IS_APU) kv_restore_regs_for_reset(adev, &kv_save); - return r; -} - -/** - * cik_asic_pci_config_reset - soft reset GPU - * - * @adev: amdgpu_device pointer - * - * Use PCI Config method to reset the GPU. - * - * Returns 0 for success. - */ -static int cik_asic_pci_config_reset(struct amdgpu_device *adev) -{ - int r; - - amdgpu_atombios_scratch_regs_engine_hung(adev, true); - - r = cik_gpu_pci_config_reset(adev); - amdgpu_atombios_scratch_regs_engine_hung(adev, false); return r; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 024460b9775d..45d1172b7bff 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -70,6 +70,11 @@ #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L +#define mmCGTS_TCC_DISABLE_gc_10_3 0x5006 +#define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1 +#define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007 +#define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1 + #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 @@ -98,10 +103,6 @@ #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 -#define mmCGTS_TCC_DISABLE_Vangogh 0x5006 -#define mmCGTS_TCC_DISABLE_Vangogh_BASE_IDX 1 -#define mmCGTS_USER_TCC_DISABLE_Vangogh 0x5007 -#define mmCGTS_USER_TCC_DISABLE_Vangogh_BASE_IDX 1 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 @@ -4491,8 +4492,7 @@ static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) + ring->pipe; - hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe, - ring->queue) ? + hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; /* type-2 packets are deprecated on MEC, use type-3 instead */ r = amdgpu_ring_init(adev, ring, 1024, @@ -4939,15 +4939,12 @@ static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) /* TCCs are global (not instanced). */ uint32_t tcc_disable; - switch (adev->asic_type) { - case CHIP_VANGOGH: - tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_Vangogh) | - RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_Vangogh); - break; - default: + if (adev->asic_type >= CHIP_SIENNA_CICHLID) { + tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) | + RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3); + } else { tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | - RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); - break; + RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); } adev->gfx.config.tcc_disabled_mask = @@ -6544,8 +6541,7 @@ static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct struct amdgpu_device *adev = ring->adev; if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { - if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe, - ring->queue)) { + if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; mqd->cp_hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 37639214cbbb..84d2eaa38101 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -29,6 +29,7 @@ #include "amdgpu.h" #include "amdgpu_gfx.h" +#include "amdgpu_ring.h" #include "vi.h" #include "vi_structs.h" #include "vid.h" @@ -1923,8 +1924,7 @@ static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) + ring->pipe; - hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe, - ring->queue) ? + hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_RING_PRIO_DEFAULT; /* type-2 packets are deprecated on MEC, use type-3 instead */ r = amdgpu_ring_init(adev, ring, 1024, @@ -4442,8 +4442,7 @@ static void gfx_v8_0_mqd_set_priority(struct amdgpu_ring *ring, struct vi_mqd *m struct amdgpu_device *adev = ring->adev; if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { - if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe, - ring->queue)) { + if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; mqd->cp_hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; @@ -6847,6 +6846,66 @@ static void gfx_v8_0_emit_mem_sync_compute(struct amdgpu_ring *ring) amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ } + +/* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ +#define mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT 0x0000007f +static void gfx_v8_0_emit_wave_limit_cs(struct amdgpu_ring *ring, + uint32_t pipe, bool enable) +{ + uint32_t val; + uint32_t wcl_cs_reg; + + val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT; + + switch (pipe) { + case 0: + wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS0; + break; + case 1: + wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS1; + break; + case 2: + wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS2; + break; + case 3: + wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS3; + break; + default: + DRM_DEBUG("invalid pipe %d\n", pipe); + return; + } + + amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); + +} + +#define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT 0x07ffffff +static void gfx_v8_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable) +{ + struct amdgpu_device *adev = ring->adev; + uint32_t val; + int i; + + /* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit + * number of gfx waves. Setting 5 bit will make sure gfx only gets + * around 25% of gpu resources. + */ + val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT; + amdgpu_ring_emit_wreg(ring, mmSPI_WCL_PIPE_PERCENT_GFX, val); + + /* Restrict waves for normal/low priority compute queues as well + * to get best QoS for high priority compute jobs. + * + * amdgpu controls only 1st ME(0-3 CS pipes). + */ + for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { + if (i != ring->pipe) + gfx_v8_0_emit_wave_limit_cs(ring, i, enable); + + } + +} + static const struct amd_ip_funcs gfx_v8_0_ip_funcs = { .name = "gfx_v8_0", .early_init = gfx_v8_0_early_init, @@ -6930,7 +6989,9 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { 7 + /* gfx_v8_0_ring_emit_pipeline_sync */ VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v8_0_ring_emit_vm_flush */ 7 + 7 + 7 + /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */ - 7, /* gfx_v8_0_emit_mem_sync_compute */ + 7 + /* gfx_v8_0_emit_mem_sync_compute */ + 5 + /* gfx_v8_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */ + 15, /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */ .emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */ .emit_ib = gfx_v8_0_ring_emit_ib_compute, .emit_fence = gfx_v8_0_ring_emit_fence_compute, @@ -6944,6 +7005,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { .pad_ib = amdgpu_ring_generic_pad_ib, .emit_wreg = gfx_v8_0_ring_emit_wreg, .emit_mem_sync = gfx_v8_0_emit_mem_sync_compute, + .emit_wave_limit = gfx_v8_0_emit_wave_limit, }; static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index a896e3d0fcf8..65db88bb6cbc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -52,6 +52,7 @@ #include "asic_reg/pwr/pwr_10_0_offset.h" #include "asic_reg/pwr/pwr_10_0_sh_mask.h" +#include "asic_reg/gc/gc_9_0_default.h" #define GFX9_NUM_GFX_RINGS 1 #define GFX9_MEC_HPD_SIZE 4096 @@ -2227,8 +2228,7 @@ static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) + ring->pipe; - hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe, - ring->queue) ? + hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; /* type-2 packets are deprecated on MEC, use type-3 instead */ return amdgpu_ring_init(adev, ring, 1024, @@ -3390,9 +3390,7 @@ static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *m struct amdgpu_device *adev = ring->adev; if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { - if (amdgpu_gfx_is_high_priority_compute_queue(adev, - ring->pipe, - ring->queue)) { + if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; mqd->cp_hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; @@ -6670,6 +6668,65 @@ static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring) amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ } +static void gfx_v9_0_emit_wave_limit_cs(struct amdgpu_ring *ring, + uint32_t pipe, bool enable) +{ + struct amdgpu_device *adev = ring->adev; + uint32_t val; + uint32_t wcl_cs_reg; + + /* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ + val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS0_DEFAULT; + + switch (pipe) { + case 0: + wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS0); + break; + case 1: + wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS1); + break; + case 2: + wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS2); + break; + case 3: + wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS3); + break; + default: + DRM_DEBUG("invalid pipe %d\n", pipe); + return; + } + + amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); + +} +static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable) +{ + struct amdgpu_device *adev = ring->adev; + uint32_t val; + int i; + + + /* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit + * number of gfx waves. Setting 5 bit will make sure gfx only gets + * around 25% of gpu resources. + */ + val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT; + amdgpu_ring_emit_wreg(ring, + SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX), + val); + + /* Restrict waves for normal/low priority compute queues as well + * to get best QoS for high priority compute jobs. + * + * amdgpu controls only 1st ME(0-3 CS pipes). + */ + for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { + if (i != ring->pipe) + gfx_v9_0_emit_wave_limit_cs(ring, i, enable); + + } +} + static const struct amd_ip_funcs gfx_v9_0_ip_funcs = { .name = "gfx_v9_0", .early_init = gfx_v9_0_early_init, @@ -6759,7 +6816,9 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 2 + /* gfx_v9_0_ring_emit_vm_flush */ 8 + 8 + 8 + /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */ - 7, /* gfx_v9_0_emit_mem_sync */ + 7 + /* gfx_v9_0_emit_mem_sync */ + 5 + /* gfx_v9_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */ + 15, /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */ .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ .emit_ib = gfx_v9_0_ring_emit_ib_compute, .emit_fence = gfx_v9_0_ring_emit_fence, @@ -6775,6 +6834,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, .emit_mem_sync = gfx_v9_0_emit_mem_sync, + .emit_wave_limit = gfx_v9_0_emit_wave_limit, }; static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index aedef9017c4c..3686e777c76c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -239,46 +239,44 @@ static const char *mmhub_client_ids_vega20[][2] = { }; static const char *mmhub_client_ids_arcturus[][2] = { + [0][0] = "DBGU1", + [1][0] = "XDP", [2][0] = "MP1", - [3][0] = "MP0", - [10][0] = "UTCL2", - [13][0] = "OSS", [14][0] = "HDP", - [15][0] = "SDMA0", - [32+15][0] = "SDMA1", - [64+15][0] = "SDMA2", - [96+15][0] = "SDMA3", - [128+15][0] = "SDMA4", - [160+11][0] = "JPEG", - [160+12][0] = "VCN", - [160+13][0] = "VCNU", - [160+15][0] = "SDMA5", - [192+10][0] = "UTCL2", - [192+11][0] = "JPEG1", - [192+12][0] = "VCN1", - [192+13][0] = "VCN1U", - [192+15][0] = "SDMA6", - [224+15][0] = "SDMA7", + [171][0] = "JPEG", + [172][0] = "VCN", + [173][0] = "VCNU", + [203][0] = "JPEG1", + [204][0] = "VCN1", + [205][0] = "VCN1U", + [256][0] = "SDMA0", + [257][0] = "SDMA1", + [258][0] = "SDMA2", + [259][0] = "SDMA3", + [260][0] = "SDMA4", + [261][0] = "SDMA5", + [262][0] = "SDMA6", + [263][0] = "SDMA7", + [384][0] = "OSS", [0][1] = "DBGU1", [1][1] = "XDP", [2][1] = "MP1", - [3][1] = "MP0", - [13][1] = "OSS", [14][1] = "HDP", - [15][1] = "SDMA0", - [32+15][1] = "SDMA1", - [64+15][1] = "SDMA2", - [96+15][1] = "SDMA3", - [128+15][1] = "SDMA4", - [160+11][1] = "JPEG", - [160+12][1] = "VCN", - [160+13][1] = "VCNU", - [160+15][1] = "SDMA5", - [192+11][1] = "JPEG1", - [192+12][1] = "VCN1", - [192+13][1] = "VCN1U", - [192+15][1] = "SDMA6", - [224+15][1] = "SDMA7", + [171][1] = "JPEG", + [172][1] = "VCN", + [173][1] = "VCNU", + [203][1] = "JPEG1", + [204][1] = "VCN1", + [205][1] = "VCN1U", + [256][1] = "SDMA0", + [257][1] = "SDMA1", + [258][1] = "SDMA2", + [259][1] = "SDMA3", + [260][1] = "SDMA4", + [261][1] = "SDMA5", + [262][1] = "SDMA6", + [263][1] = "SDMA7", + [384][1] = "OSS", }; static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c index b860f1c7b5b1..05ddec7ba7e2 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c @@ -34,6 +34,14 @@ #define smnCPM_CONTROL 0x11180460 #define smnPCIE_CNTL2 0x11180070 #define smnPCIE_LC_CNTL 0x11140280 +#define smnPCIE_LC_CNTL3 0x111402d4 +#define smnPCIE_LC_CNTL6 0x111402ec +#define smnPCIE_LC_CNTL7 0x111402f0 +#define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x1014008c +#define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x10123538 +#define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x10140324 +#define smnPSWUSP0_PCIE_LC_CNTL2 0x111402c4 +#define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c #define mmBIF_SDMA2_DOORBELL_RANGE 0x01d6 #define mmBIF_SDMA2_DOORBELL_RANGE_BASE_IDX 2 @@ -350,6 +358,111 @@ static void nbio_v2_3_enable_aspm(struct amdgpu_device *adev, WREG32_PCIE(smnPCIE_LC_CNTL, data); } +static void nbio_v2_3_program_ltr(struct amdgpu_device *adev) +{ + uint32_t def, data; + + WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, 0x75EB); + + def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP2); + data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK; + if (def != data) + WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP2, data); + + def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL); + data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK; + if (def != data) + WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data); + + def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); + data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; + if (def != data) + WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); +} + +static void nbio_v2_3_program_aspm(struct amdgpu_device *adev) +{ + uint32_t def, data; + + def = data = RREG32_PCIE(smnPCIE_LC_CNTL); + data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; + data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; + data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; + if (def != data) + WREG32_PCIE(smnPCIE_LC_CNTL, data); + + def = data = RREG32_PCIE(smnPCIE_LC_CNTL7); + data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK; + if (def != data) + WREG32_PCIE(smnPCIE_LC_CNTL7, data); + + def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK); + data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK; + if (def != data) + WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data); + + def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); + data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; + if (def != data) + WREG32_PCIE(smnPCIE_LC_CNTL3, data); + + def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3); + data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK; + data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK; + if (def != data) + WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3, data); + + def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5); + data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK; + if (def != data) + WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5, data); + + def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); + data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; + if (def != data) + WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); + + WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001); + + def = data = RREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2); + data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | + PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK; + data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK; + if (def != data) + WREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2, data); + + def = data = RREG32_PCIE(smnPCIE_LC_CNTL6); + data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK | + PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK; + if (def != data) + WREG32_PCIE(smnPCIE_LC_CNTL6, data); + + nbio_v2_3_program_ltr(adev); + + def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3); + data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; + data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT; + if (def != data) + WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3, data); + + def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5); + data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT; + if (def != data) + WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5, data); + + def = data = RREG32_PCIE(smnPCIE_LC_CNTL); + data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; + data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; + data |= 0x1 << PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT; + if (def != data) + WREG32_PCIE(smnPCIE_LC_CNTL, data); + + def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); + data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; + if (def != data) + WREG32_PCIE(smnPCIE_LC_CNTL3, data); +} + const struct amdgpu_nbio_funcs nbio_v2_3_funcs = { .get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset, .get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset, @@ -370,4 +483,5 @@ const struct amdgpu_nbio_funcs nbio_v2_3_funcs = { .init_registers = nbio_v2_3_init_registers, .remap_hdp_registers = nbio_v2_3_remap_hdp_registers, .enable_aspm = nbio_v2_3_enable_aspm, + .program_aspm = nbio_v2_3_program_aspm, }; diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 66279f0c6808..160fa5f59805 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -38,7 +38,6 @@ #include "gc/gc_10_1_0_offset.h" #include "gc/gc_10_1_0_sh_mask.h" -#include "smuio/smuio_11_0_0_offset.h" #include "mp/mp_11_0_offset.h" #include "soc15.h" @@ -61,6 +60,8 @@ #include "dce_virtual.h" #include "mes_v10_1.h" #include "mxgpu_nv.h" +#include "smuio_v11_0.h" +#include "smuio_v11_0_6.h" static const struct amd_ip_funcs nv_common_ip_funcs; @@ -202,6 +203,7 @@ static bool nv_read_bios_from_rom(struct amdgpu_device *adev, { u32 *dw_ptr; u32 i, length_dw; + u32 rom_index_offset, rom_data_offset; if (bios == NULL) return false; @@ -214,11 +216,16 @@ static bool nv_read_bios_from_rom(struct amdgpu_device *adev, dw_ptr = (u32 *)bios; length_dw = ALIGN(length_bytes, 4) / 4; + rom_index_offset = + adev->smuio.funcs->get_rom_index_offset(adev); + rom_data_offset = + adev->smuio.funcs->get_rom_data_offset(adev); + /* set rom index to 0 */ - WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); + WREG32(rom_index_offset, 0); /* read out the rom data */ for (i = 0; i < length_dw; i++) - dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); + dw_ptr[i] = RREG32(rom_data_offset); return true; } @@ -384,7 +391,8 @@ nv_asic_reset_method(struct amdgpu_device *adev) if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || - amdgpu_reset_method == AMD_RESET_METHOD_BACO) + amdgpu_reset_method == AMD_RESET_METHOD_BACO || + amdgpu_reset_method == AMD_RESET_METHOD_PCI) return amdgpu_reset_method; if (amdgpu_reset_method != -1) @@ -416,6 +424,10 @@ static int nv_asic_reset(struct amdgpu_device *adev) return 0; switch (nv_asic_reset_method(adev)) { + case AMD_RESET_METHOD_PCI: + dev_info(adev->dev, "PCI reset\n"); + ret = amdgpu_device_pci_reset(adev); + break; case AMD_RESET_METHOD_BACO: dev_info(adev->dev, "BACO reset\n"); @@ -468,11 +480,14 @@ static void nv_pcie_gen3_enable(struct amdgpu_device *adev) static void nv_program_aspm(struct amdgpu_device *adev) { - - if (amdgpu_aspm == 0) + if (amdgpu_aspm != 1) return; - /* todo */ + if ((adev->asic_type >= CHIP_SIENNA_CICHLID) && + !(adev->flags & AMD_IS_APU) && + (adev->nbio.funcs->program_aspm)) + adev->nbio.funcs->program_aspm(adev); + } static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, @@ -561,6 +576,11 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) } adev->hdp.funcs = &hdp_v5_0_funcs; + if (adev->asic_type >= CHIP_SIENNA_CICHLID) + adev->smuio.funcs = &smuio_v11_0_6_funcs; + else + adev->smuio.funcs = &smuio_v11_0_funcs; + if (adev->asic_type == CHIP_SIENNA_CICHLID) adev->gmc.xgmi.supported = true; @@ -798,10 +818,10 @@ static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, * The ASPM function is not fully enabled and verified on * Navi yet. Temporarily skip this until ASPM enabled. */ -#if 0 - if (adev->nbio.funcs->enable_aspm) + if ((adev->asic_type >= CHIP_SIENNA_CICHLID) && + !(adev->flags & AMD_IS_APU) && + (adev->nbio.funcs->enable_aspm)) adev->nbio.funcs->enable_aspm(adev, !enter); -#endif return 0; } @@ -1129,6 +1149,8 @@ static int nv_common_set_clockgating_state(void *handle, state == AMD_CG_STATE_GATE); adev->hdp.funcs->update_clock_gating(adev, state == AMD_CG_STATE_GATE); + adev->smuio.funcs->update_rom_clock_gating(adev, + state == AMD_CG_STATE_GATE); break; default: break; @@ -1154,6 +1176,8 @@ static void nv_common_get_clockgating_state(void *handle, u32 *flags) adev->hdp.funcs->get_clock_gating_state(adev, flags); + adev->smuio.funcs->get_clock_gating_state(adev, flags); + return; } diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 3cf0589bfea5..6b5cf7882a12 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -1270,7 +1270,7 @@ static int si_gpu_pci_config_reset(struct amdgpu_device *adev) u32 i; int r = -EINVAL; - dev_info(adev->dev, "GPU pci config reset\n"); + amdgpu_atombios_scratch_regs_engine_hung(adev, true); /* set mclk/sclk to bypass */ si_set_clk_bypass_mode(adev); @@ -1294,20 +1294,6 @@ static int si_gpu_pci_config_reset(struct amdgpu_device *adev) } udelay(1); } - - return r; -} - -static int si_asic_reset(struct amdgpu_device *adev) -{ - int r; - - dev_info(adev->dev, "PCI CONFIG reset\n"); - - amdgpu_atombios_scratch_regs_engine_hung(adev, true); - - r = si_gpu_pci_config_reset(adev); - amdgpu_atombios_scratch_regs_engine_hung(adev, false); return r; @@ -1321,14 +1307,34 @@ static bool si_asic_supports_baco(struct amdgpu_device *adev) static enum amd_reset_method si_asic_reset_method(struct amdgpu_device *adev) { - if (amdgpu_reset_method != AMD_RESET_METHOD_LEGACY && - amdgpu_reset_method != -1) + if (amdgpu_reset_method == AMD_RESET_METHOD_PCI) + return amdgpu_reset_method; + else if (amdgpu_reset_method != AMD_RESET_METHOD_LEGACY && + amdgpu_reset_method != -1) dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", - amdgpu_reset_method); + amdgpu_reset_method); return AMD_RESET_METHOD_LEGACY; } +static int si_asic_reset(struct amdgpu_device *adev) +{ + int r; + + switch (si_asic_reset_method(adev)) { + case AMD_RESET_METHOD_PCI: + dev_info(adev->dev, "PCI reset\n"); + r = amdgpu_device_pci_reset(adev); + break; + default: + dev_info(adev->dev, "PCI CONFIG reset\n"); + r = si_gpu_pci_config_reset(adev); + break; + } + + return r; +} + static u32 si_get_config_memsize(struct amdgpu_device *adev) { return RREG32(mmCONFIG_MEMSIZE); diff --git a/drivers/gpu/drm/amd/amdgpu/smuio_v11_0_6.c b/drivers/gpu/drm/amd/amdgpu/smuio_v11_0_6.c new file mode 100644 index 000000000000..3a18dbb55c32 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/smuio_v11_0_6.c @@ -0,0 +1,77 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "amdgpu.h" +#include "smuio_v11_0_6.h" +#include "smuio/smuio_11_0_6_offset.h" +#include "smuio/smuio_11_0_6_sh_mask.h" + +static u32 smuio_v11_0_6_get_rom_index_offset(struct amdgpu_device *adev) +{ + return SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX); +} + +static u32 smuio_v11_0_6_get_rom_data_offset(struct amdgpu_device *adev) +{ + return SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA); +} + +static void smuio_v11_0_6_update_rom_clock_gating(struct amdgpu_device *adev, bool enable) +{ + u32 def, data; + + /* enable/disable ROM CG is not supported on APU */ + if (adev->flags & AMD_IS_APU) + return; + + def = data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0); + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) + data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | + CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); + else + data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | + CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK; + + if (def != data) + WREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0, data); +} + +static void smuio_v11_0_6_get_clock_gating_state(struct amdgpu_device *adev, u32 *flags) +{ + u32 data; + + /* CGTT_ROM_CLK_CTRL0 is not available for APU */ + if (adev->flags & AMD_IS_APU) + return; + + data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0); + if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK)) + *flags |= AMD_CG_SUPPORT_ROM_MGCG; +} + +const struct amdgpu_smuio_funcs smuio_v11_0_6_funcs = { + .get_rom_index_offset = smuio_v11_0_6_get_rom_index_offset, + .get_rom_data_offset = smuio_v11_0_6_get_rom_data_offset, + .update_rom_clock_gating = smuio_v11_0_6_update_rom_clock_gating, + .get_clock_gating_state = smuio_v11_0_6_get_clock_gating_state, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/smuio_v11_0_6.h b/drivers/gpu/drm/amd/amdgpu/smuio_v11_0_6.h new file mode 100644 index 000000000000..3c3f4ab0bc9b --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/smuio_v11_0_6.h @@ -0,0 +1,30 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __SMUIO_V11_0_6_H__ +#define __SMUIO_V11_0_6_H__ + +#include "soc15_common.h" + +extern const struct amdgpu_smuio_funcs smuio_v11_0_6_funcs; + +#endif /* __SMUIO_V11_0_6_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 2396be16c28e..1221aa6b40a9 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -233,6 +233,8 @@ static u32 soc15_get_xclk(struct amdgpu_device *adev) { u32 reference_clock = adev->clock.spll.reference_freq; + if (adev->asic_type == CHIP_RENOIR) + return 10000; if (adev->asic_type == CHIP_RAVEN) return reference_clock / 4; @@ -479,7 +481,8 @@ soc15_asic_reset_method(struct amdgpu_device *adev) if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || - amdgpu_reset_method == AMD_RESET_METHOD_BACO) + amdgpu_reset_method == AMD_RESET_METHOD_BACO || + amdgpu_reset_method == AMD_RESET_METHOD_PCI) return amdgpu_reset_method; if (amdgpu_reset_method != -1) @@ -524,15 +527,18 @@ static int soc15_asic_reset(struct amdgpu_device *adev) return 0; switch (soc15_asic_reset_method(adev)) { - case AMD_RESET_METHOD_BACO: - dev_info(adev->dev, "BACO reset\n"); - return soc15_asic_baco_reset(adev); - case AMD_RESET_METHOD_MODE2: - dev_info(adev->dev, "MODE2 reset\n"); - return amdgpu_dpm_mode2_reset(adev); - default: - dev_info(adev->dev, "MODE1 reset\n"); - return soc15_asic_mode1_reset(adev); + case AMD_RESET_METHOD_PCI: + dev_info(adev->dev, "PCI reset\n"); + return amdgpu_device_pci_reset(adev); + case AMD_RESET_METHOD_BACO: + dev_info(adev->dev, "BACO reset\n"); + return soc15_asic_baco_reset(adev); + case AMD_RESET_METHOD_MODE2: + dev_info(adev->dev, "MODE2 reset\n"); + return amdgpu_dpm_mode2_reset(adev); + default: + dev_info(adev->dev, "MODE1 reset\n"); + return soc15_asic_mode1_reset(adev); } } diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index d56b474b3a21..eafb76aebd00 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -642,11 +642,21 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num, return -EINVAL; } -static int vi_gpu_pci_config_reset(struct amdgpu_device *adev) +/** + * vi_asic_pci_config_reset - soft reset GPU + * + * @adev: amdgpu_device pointer + * + * Use PCI Config method to reset the GPU. + * + * Returns 0 for success. + */ +static int vi_asic_pci_config_reset(struct amdgpu_device *adev) { u32 i; + int r = -EINVAL; - dev_info(adev->dev, "GPU pci config reset\n"); + amdgpu_atombios_scratch_regs_engine_hung(adev, true); /* disable BM */ pci_clear_master(adev->pdev); @@ -661,29 +671,11 @@ static int vi_gpu_pci_config_reset(struct amdgpu_device *adev) /* enable BM */ pci_set_master(adev->pdev); adev->has_hw_reset = true; - return 0; + r = 0; + break; } udelay(1); } - return -EINVAL; -} - -/** - * vi_asic_pci_config_reset - soft reset GPU - * - * @adev: amdgpu_device pointer - * - * Use PCI Config method to reset the GPU. - * - * Returns 0 for success. - */ -static int vi_asic_pci_config_reset(struct amdgpu_device *adev) -{ - int r; - - amdgpu_atombios_scratch_regs_engine_hung(adev, true); - - r = vi_gpu_pci_config_reset(adev); amdgpu_atombios_scratch_regs_engine_hung(adev, false); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 16262e5d93f5..7351dd195274 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -243,11 +243,11 @@ get_sh_mem_bases_nybble_64(struct kfd_process_device *pdd) static inline void dqm_lock(struct device_queue_manager *dqm) { mutex_lock(&dqm->lock_hidden); - dqm->saved_flags = memalloc_nofs_save(); + dqm->saved_flags = memalloc_noreclaim_save(); } static inline void dqm_unlock(struct device_queue_manager *dqm) { - memalloc_nofs_restore(dqm->saved_flags); + memalloc_noreclaim_restore(dqm->saved_flags); mutex_unlock(&dqm->lock_hidden); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index a3fc23873819..0be72789ccbc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -497,8 +497,6 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr, dev->node_props.num_sdma_queues_per_engine); sysfs_show_32bit_prop(buffer, offs, "num_cp_queues", dev->node_props.num_cp_queues); - sysfs_show_64bit_prop(buffer, offs, "unique_id", - dev->node_props.unique_id); if (dev->gpu) { log_max_watch_addr = @@ -529,6 +527,9 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr, dev->node_props.capability); sysfs_show_32bit_prop(buffer, offs, "sdma_fw_version", dev->gpu->sdma_fw_version); + sysfs_show_64bit_prop(buffer, offs, "unique_id", + amdgpu_amdkfd_get_unique_id(dev->gpu->kgd)); + } return sysfs_show_32bit_prop(buffer, offs, "max_engine_clk_ccompute", @@ -1340,7 +1341,6 @@ int kfd_topology_add_device(struct kfd_dev *gpu) dev->gpu->dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) ? amdgpu_amdkfd_get_num_gws(dev->gpu->kgd) : 0; dev->node_props.num_cp_queues = get_cp_queues_num(dev->gpu->dqm); - dev->node_props.unique_id = amdgpu_amdkfd_get_unique_id(dev->gpu->kgd); kfd_fill_mem_clk_max_info(dev); kfd_fill_iolink_non_crat_info(dev); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index 326d9b26b7aa..416fd910e12e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -57,7 +57,6 @@ struct kfd_node_properties { uint64_t hive_id; - uint64_t unique_id; uint32_t cpu_cores_count; uint32_t simd_count; uint32_t mem_banks_count; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 67fd9f4ef93e..94cd5ddd67ef 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1128,7 +1128,7 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) #ifdef CONFIG_DRM_AMD_DC_HDCP if (adev->dm.hdcp_workqueue) { - hdcp_destroy(adev->dm.hdcp_workqueue); + hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); adev->dm.hdcp_workqueue = NULL; } @@ -5374,9 +5374,7 @@ static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable) struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); struct amdgpu_device *adev = drm_to_adev(crtc->dev); struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); -#if defined(CONFIG_DRM_AMD_DC_DCN) struct amdgpu_display_manager *dm = &adev->dm; -#endif int rc = 0; if (enable) { @@ -5396,7 +5394,6 @@ static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable) if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) return -EBUSY; -#if defined(CONFIG_DRM_AMD_DC_DCN) if (amdgpu_in_reset(adev)) return 0; @@ -5416,7 +5413,6 @@ static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable) mutex_unlock(&dm->dc_lock); -#endif return 0; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index b297ddc24d3a..0cdbfcd475ec 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -376,7 +376,7 @@ static void event_cpirq(struct work_struct *work) } -void hdcp_destroy(struct hdcp_workqueue *hdcp_work) +void hdcp_destroy(struct kobject *kobj, struct hdcp_workqueue *hdcp_work) { int i = 0; @@ -385,6 +385,7 @@ void hdcp_destroy(struct hdcp_workqueue *hdcp_work) cancel_delayed_work_sync(&hdcp_work[i].watchdog_timer_dwork); } + sysfs_remove_bin_file(kobj, &hdcp_work[0].attr); kfree(hdcp_work->srm); kfree(hdcp_work->srm_temp); kfree(hdcp_work); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h index 5159b3a5e5b0..09294ff122fe 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h @@ -69,7 +69,7 @@ void hdcp_update_display(struct hdcp_workqueue *hdcp_work, void hdcp_reset_display(struct hdcp_workqueue *work, unsigned int link_index); void hdcp_handle_cpirq(struct hdcp_workqueue *work, unsigned int link_index); -void hdcp_destroy(struct hdcp_workqueue *work); +void hdcp_destroy(struct kobject *kobj, struct hdcp_workqueue *work); struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, struct cp_psp *cp_psp, struct dc *dc); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 3244a6ea7a65..5159399f8239 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -526,11 +526,11 @@ bool dm_helpers_submit_i2c( bool dm_helpers_dp_write_dsc_enable( struct dc_context *ctx, const struct dc_stream_state *stream, - bool enable -) + bool enable) { uint8_t enable_dsc = enable ? 1 : 0; struct amdgpu_dm_connector *aconnector; + uint8_t ret; if (!stream) return false; @@ -541,13 +541,13 @@ bool dm_helpers_dp_write_dsc_enable( if (!aconnector->dsc_aux) return false; - return (drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1) >= 0); + ret = drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1); } if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT) return dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); - return false; + return (ret > 0); } bool dm_helpers_is_dp_sink_present(struct dc_link *link) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c index 26ed70e5538a..e0000c180ed1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c @@ -662,6 +662,20 @@ static int amdgpu_dm_set_crtc_irq_state(struct amdgpu_device *adev, __func__); } +static int amdgpu_dm_set_vline0_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned int crtc_id, + enum amdgpu_interrupt_state state) +{ + return dm_irq_state( + adev, + source, + crtc_id, + state, + IRQ_TYPE_VLINE0, + __func__); +} + static int amdgpu_dm_set_vupdate_irq_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned int crtc_id, @@ -681,6 +695,11 @@ static const struct amdgpu_irq_src_funcs dm_crtc_irq_funcs = { .process = amdgpu_dm_irq_handler, }; +static const struct amdgpu_irq_src_funcs dm_vline0_irq_funcs = { + .set = amdgpu_dm_set_vline0_irq_state, + .process = amdgpu_dm_irq_handler, +}; + static const struct amdgpu_irq_src_funcs dm_vupdate_irq_funcs = { .set = amdgpu_dm_set_vupdate_irq_state, .process = amdgpu_dm_irq_handler, @@ -702,6 +721,9 @@ void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev) adev->crtc_irq.num_types = adev->mode_info.num_crtc; adev->crtc_irq.funcs = &dm_crtc_irq_funcs; + adev->vline0_irq.num_types = adev->mode_info.num_crtc; + adev->vline0_irq.funcs = &dm_vline0_irq_funcs; + adev->vupdate_irq.num_types = adev->mode_info.num_crtc; adev->vupdate_irq.funcs = &dm_vupdate_irq_funcs; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 8d5378f53243..c9aede2f783d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -205,27 +205,9 @@ static bool create_links( link = link_create(&link_init_params); if (link) { - bool should_destory_link = false; - - if (link->connector_signal == SIGNAL_TYPE_EDP) { - if (dc->config.edp_not_connected) { - if (!IS_DIAG_DC(dc->ctx->dce_environment)) - should_destory_link = true; - } else { - enum dc_connection_type type; - dc_link_detect_sink(link, &type); - if (type == dc_connection_none) - should_destory_link = true; - } - } - - if (dc->config.force_enum_edp || !should_destory_link) { dc->links[dc->link_count] = link; link->dc = dc; ++dc->link_count; - } else { - link_destroy(&link); - } } } @@ -1016,8 +998,30 @@ destruct_dc: return NULL; } +static void detect_edp_presence(struct dc *dc) +{ + struct dc_link *edp_link = get_edp_link(dc); + bool edp_sink_present = true; + + if (!edp_link) + return; + + if (dc->config.edp_not_connected) { + edp_sink_present = false; + } else { + enum dc_connection_type type; + dc_link_detect_sink(edp_link, &type); + if (type == dc_connection_none) + edp_sink_present = false; + } + + edp_link->edp_sink_present = edp_sink_present; +} + void dc_hardware_init(struct dc *dc) { + + detect_edp_presence(dc); if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW) dc->hwss.init_hw(dc); } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 8506739a22f7..fa5059f71727 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -3688,8 +3688,8 @@ uint32_t dc_link_bandwidth_kbps( * but the difference is minimal and is in a safe direction, * which all works well around potential ambiguity of DP 1.4a spec. */ - link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000, - link_bw_kbps, 32); + long long fec_link_bw_kbps = link_bw_kbps * 970LL; + link_bw_kbps = (uint32_t)(div64_s64(fec_link_bw_kbps, 1000LL)); } return link_bw_kbps; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 739a39eeb941..4eee3a55fa30 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -42,7 +42,7 @@ #include "inc/hw/dmcu.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.2.121" +#define DC_VER "3.2.122" #define MAX_SURFACES 3 #define MAX_PLANES 6 diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h index e99273bff46d..ec55b77727d5 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h @@ -51,7 +51,6 @@ struct dc_dsc_policy { int min_slice_height; // Must not be less than 8 uint32_t max_target_bpp; uint32_t min_target_bpp; - uint32_t preferred_bpp_x16; bool enable_dsc_when_not_needed; }; @@ -63,8 +62,8 @@ bool dc_dsc_parse_dsc_dpcd(const struct dc *dc, bool dc_dsc_compute_bandwidth_range( const struct display_stream_compressor *dsc, uint32_t dsc_min_slice_height_override, - uint32_t min_bpp_x16, - uint32_t max_bpp_x16, + uint32_t min_bpp, + uint32_t max_bpp, const struct dsc_dec_dpcd_caps *dsc_sink_caps, const struct dc_crtc_timing *timing, struct dc_dsc_bw_range *range); @@ -79,7 +78,7 @@ bool dc_dsc_compute_config( struct dc_dsc_config *dsc_cfg); void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, - uint32_t max_target_bpp_limit_override_x16, + uint32_t max_target_bpp_limit_override, struct dc_dsc_policy *policy); void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit); diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 09e8be5f7a1e..b41e6367b15e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -769,7 +769,6 @@ struct dc_crtc_timing { #endif struct dc_crtc_timing_flags flags; - uint32_t dsc_fixed_bits_per_pixel_x16; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */ struct dc_dsc_config dsc_cfg; }; diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h index d5d8f0ad9233..e189f16bc026 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_link.h +++ b/drivers/gpu/drm/amd/display/dc/dc_link.h @@ -103,6 +103,8 @@ struct dc_link { bool lttpr_non_transparent_mode; bool is_internal_display; + bool edp_sink_present; + /* caps is the same as reported_link_cap. link_traing use * reported_link_cap. Will clean up. TODO */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 17ec63253fc3..dec58b3c42e4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -240,7 +240,7 @@ static bool calc_fb_divider_checking_tolerance( pll_settings->calculated_pix_clk_100hz = actual_calculated_clock_100hz; pll_settings->vco_freq = - actual_calculated_clock_100hz * post_divider / 10; + div_u64((u64)actual_calculated_clock_100hz * post_divider, 10); return true; } return false; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c index 0cf130dc4e52..453aaa5757bd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c @@ -57,6 +57,7 @@ static void dmub_abm_enable_fractional_pwm(struct dc_context *dc) union dmub_rb_cmd cmd; uint32_t fractional_pwm = (dc->dc->config.disable_fractional_pwm == false) ? 1 : 0; + memset(&cmd, 0, sizeof(cmd)); cmd.abm_set_pwm_frac.header.type = DMUB_CMD__ABM; cmd.abm_set_pwm_frac.header.sub_type = DMUB_CMD__ABM_SET_PWM_FRAC; cmd.abm_set_pwm_frac.abm_set_pwm_frac_data.fractional_pwm = fractional_pwm; @@ -135,6 +136,7 @@ static bool dmub_abm_set_level(struct abm *abm, uint32_t level) union dmub_rb_cmd cmd; struct dc_context *dc = abm->ctx; + memset(&cmd, 0, sizeof(cmd)); cmd.abm_set_level.header.type = DMUB_CMD__ABM; cmd.abm_set_level.header.sub_type = DMUB_CMD__ABM_SET_LEVEL; cmd.abm_set_level.abm_set_level_data.level = level; @@ -160,6 +162,7 @@ static bool dmub_abm_init_config(struct abm *abm, // Copy iramtable into cw7 memcpy(dc->dmub_srv->dmub->scratch_mem_fb.cpu_addr, (void *)src, bytes); + memset(&cmd, 0, sizeof(cmd)); // Fw will copy from cw7 to fw_state cmd.abm_init_config.header.type = DMUB_CMD__ABM; cmd.abm_init_config.header.sub_type = DMUB_CMD__ABM_INIT_CONFIG; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c index d399270fd17e..c97ee5abc0ef 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c @@ -33,8 +33,9 @@ void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv, union dmub_hw_lock_flags *hw_locks, struct dmub_hw_lock_inst_flags *inst_flags) { - union dmub_rb_cmd cmd = { 0 }; + union dmub_rb_cmd cmd; + memset(&cmd, 0, sizeof(cmd)); cmd.lock_hw.header.type = DMUB_CMD__HW_LOCK; cmd.lock_hw.header.sub_type = 0; cmd.lock_hw.header.payload_bytes = sizeof(struct dmub_cmd_lock_hw_data); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index 4228caa74119..69e34bef274c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -101,6 +101,7 @@ static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state * if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED) return false; + memset(&cmd, 0, sizeof(cmd)); cmd.psr_set_version.header.type = DMUB_CMD__PSR; cmd.psr_set_version.header.sub_type = DMUB_CMD__PSR_SET_VERSION; switch (stream->link->psr_settings.psr_version) { @@ -131,7 +132,7 @@ static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait) uint32_t retry_count; enum dc_psr_state state = PSR_STATE0; - + memset(&cmd, 0, sizeof(cmd)); cmd.psr_enable.header.type = DMUB_CMD__PSR; if (enable) @@ -184,6 +185,7 @@ static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level) if (state == PSR_STATE0) return; + memset(&cmd, 0, sizeof(cmd)); cmd.psr_set_level.header.type = DMUB_CMD__PSR; cmd.psr_set_level.header.sub_type = DMUB_CMD__PSR_SET_LEVEL; cmd.psr_set_level.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_level_data); @@ -233,6 +235,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, psr_context->sdpTransmitLineNumDeadline); + memset(&cmd, 0, sizeof(cmd)); cmd.psr_copy_settings.header.type = DMUB_CMD__PSR; cmd.psr_copy_settings.header.sub_type = DMUB_CMD__PSR_COPY_SETTINGS; cmd.psr_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_psr_copy_settings_data); @@ -285,6 +288,7 @@ static void dmub_psr_force_static(struct dmub_psr *dmub) union dmub_rb_cmd cmd; struct dc_context *dc = dmub->ctx; + memset(&cmd, 0, sizeof(cmd)); cmd.psr_force_static.header.type = DMUB_CMD__PSR; cmd.psr_force_static.header.sub_type = DMUB_CMD__PSR_FORCE_STATIC; cmd.psr_enable.header.payload_bytes = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c index 7f4766e45dff..e8b6065fffad 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c @@ -47,7 +47,7 @@ unsigned int snprintf_count(char *pBuf, unsigned int bufSize, char *fmt, ...) { - unsigned int ret_vsnprintf; + int ret_vsnprintf; unsigned int chars_printed; va_list args; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c index 81db0179f7ea..59024653430c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c @@ -956,6 +956,21 @@ void dcn10_link_encoder_enable_tmds_output( } } +void dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa( + struct link_encoder *enc, + enum clock_source_id clock_source, + enum dc_color_depth color_depth, + enum signal_type signal, + uint32_t pixel_clock) +{ + struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); + + dcn10_link_encoder_enable_tmds_output( + enc, clock_source, color_depth, signal, pixel_clock); + + REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); +} + /* enables DP PHY output */ void dcn10_link_encoder_enable_dp_output( struct link_encoder *enc, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h index d4caad670855..3e1a582e4b88 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h @@ -42,6 +42,7 @@ #define LE_DCN_COMMON_REG_LIST(id) \ SRI(DIG_BE_CNTL, DIG, id), \ SRI(DIG_BE_EN_CNTL, DIG, id), \ + SRI(DIG_CLOCK_PATTERN, DIG, id), \ SRI(TMDS_CTL_BITS, DIG, id), \ SRI(DP_CONFIG, DP, id), \ SRI(DP_DPHY_CNTL, DP, id), \ @@ -83,6 +84,7 @@ struct dcn10_link_enc_hpd_registers { struct dcn10_link_enc_registers { uint32_t DIG_BE_CNTL; uint32_t DIG_BE_EN_CNTL; + uint32_t DIG_CLOCK_PATTERN; uint32_t DP_CONFIG; uint32_t DP_DPHY_CNTL; uint32_t DP_DPHY_INTERNAL_CTRL; @@ -168,6 +170,7 @@ struct dcn10_link_enc_registers { LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\ LE_SF(DIG0_DIG_BE_CNTL, DIG_MODE, mask_sh),\ LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\ + LE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\ LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\ LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\ @@ -218,6 +221,7 @@ struct dcn10_link_enc_registers { type DIG_HPD_SELECT;\ type DIG_MODE;\ type DIG_FE_SOURCE_SELECT;\ + type DIG_CLOCK_PATTERN;\ type DPHY_BYPASS;\ type DPHY_ATEST_SEL_LANE0;\ type DPHY_ATEST_SEL_LANE1;\ @@ -536,6 +540,13 @@ void dcn10_link_encoder_enable_tmds_output( enum signal_type signal, uint32_t pixel_clock); +void dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa( + struct link_encoder *enc, + enum clock_source_id clock_source, + enum dc_color_depth color_depth, + enum signal_type signal, + uint32_t pixel_clock); + /* enables DP PHY output */ void dcn10_link_encoder_enable_dp_output( struct link_encoder *enc, diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c index 15c2ff264ff6..fa013496e26b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c @@ -363,7 +363,7 @@ static const struct link_encoder_funcs dcn20_link_enc_funcs = { dcn10_link_encoder_validate_output_with_stream, .hw_init = enc2_hw_init, .setup = dcn10_link_encoder_setup, - .enable_tmds_output = dcn10_link_encoder_enable_tmds_output, + .enable_tmds_output = dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa, .enable_dp_output = dcn20_link_encoder_enable_dp_output, .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output, .disable_output = dcn10_link_encoder_disable_output, diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index 064f158ce671..2c2dbfcd8957 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -297,8 +297,8 @@ static struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = { }, }, .num_states = 5, - .sr_exit_time_us = 11.6, - .sr_enter_plus_exit_time_us = 13.9, + .sr_exit_time_us = 8.6, + .sr_enter_plus_exit_time_us = 10.9, .urgent_latency_us = 4.0, .urgent_latency_pixel_data_only_us = 4.0, .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, @@ -2097,6 +2097,7 @@ int dcn20_populate_dml_pipes_from_context( pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2; pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst; pipes[pipe_cnt].dout.dp_lanes = 4; + pipes[pipe_cnt].dout.is_virtual = 0; pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min; pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max; switch (get_num_odm_splits(&res_ctx->pipe_ctx[i])) { @@ -2150,6 +2151,7 @@ int dcn20_populate_dml_pipes_from_context( break; default: /* In case there is no signal, set dp with 4 lanes to allow max config */ + pipes[pipe_cnt].dout.is_virtual = 1; pipes[pipe_cnt].dout.output_type = dm_dp; pipes[pipe_cnt].dout.dp_lanes = 4; } @@ -3245,7 +3247,7 @@ restore_dml_state: bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate) { - bool voltage_supported = false; + bool voltage_supported; DC_FP_START(); voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate); DC_FP_END(); @@ -3506,7 +3508,8 @@ void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000; // FCLK:UCLK ratio is 1.08 - min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32); + min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080, + 1000000); calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? min_dcfclk : min_fclk_required_by_uclk; diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c index 96ee0b82f458..d3b643089603 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c @@ -123,7 +123,7 @@ void dcn21_optimize_pwr_state( * PHY will hang on the next mode set attempt. * if enable PLL follow by disable PLL (without executing lane enable/disable), * RDPCS_PHY_DP_MPLLB_STATE remains 1, - * which indicate that PLL disable attempt actually didn’t go through. + * which indicate that PLL disable attempt actually didn't go through. * As a workaround, insert PHY lane enable/disable before PLL disable. */ void dcn21_PLAT_58856_wa(struct dc_state *context, struct pipe_ctx *pipe_ctx) @@ -143,6 +143,7 @@ static bool dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst, uint32_t optio struct dc_context *dc = abm->ctx; uint32_t ramping_boundary = 0xFFFF; + memset(&cmd, 0, sizeof(cmd)); cmd.abm_set_pipe.header.type = DMUB_CMD__ABM; cmd.abm_set_pipe.header.sub_type = DMUB_CMD__ABM_SET_PIPE; cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = otg_inst; @@ -212,6 +213,7 @@ bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx, if (abm && panel_cntl) dmub_abm_set_pipe(abm, otg_inst, SET_ABM_PIPE_NORMAL, panel_cntl->inst); + memset(&cmd, 0, sizeof(cmd)); cmd.abm_set_backlight.header.type = DMUB_CMD__ABM; cmd.abm_set_backlight.header.sub_type = DMUB_CMD__ABM_SET_BACKLIGHT; cmd.abm_set_backlight.abm_set_backlight_data.frame_ramp = frame_ramp; diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c index 674376428916..072f8c880924 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c @@ -1329,8 +1329,8 @@ validate_out: return out; } -bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context, - bool fast_validate) +static noinline bool dcn21_validate_bandwidth_fp(struct dc *dc, + struct dc_state *context, bool fast_validate) { bool out = false; @@ -1383,6 +1383,22 @@ validate_out: return out; } + +/* + * Some of the functions further below use the FPU, so we need to wrap this + * with DC_FP_START()/DC_FP_END(). Use the same approach as for + * dcn20_validate_bandwidth in dcn20_resource.c. + */ +bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context, + bool fast_validate) +{ + bool voltage_supported; + DC_FP_START(); + voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate); + DC_FP_END(); + return voltage_supported; +} + static void dcn21_destroy_resource_pool(struct resource_pool **pool) { struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool); diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c index f33e3de08176..0f3f510fd83b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c @@ -4168,10 +4168,11 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { locals->DIOSupport[i] = true; for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { - if (locals->OutputBppPerState[i][k] == BPP_INVALID - || (mode_lib->vba.OutputFormat[k] == dm_420 + if (!mode_lib->vba.skip_dio_check[k] + && (locals->OutputBppPerState[i][k] == BPP_INVALID + || (mode_lib->vba.OutputFormat[k] == dm_420 && mode_lib->vba.Interlace[k] == true - && mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true)) { + && mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true))) { locals->DIOSupport[i] = false; } } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c index 47e8e71113ee..210c96cd5b03 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c @@ -4289,10 +4289,11 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { locals->DIOSupport[i] = true; for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { - if (locals->OutputBppPerState[i][k] == BPP_INVALID - || (mode_lib->vba.OutputFormat[k] == dm_420 + if (!mode_lib->vba.skip_dio_check[k] + && (locals->OutputBppPerState[i][k] == BPP_INVALID + || (mode_lib->vba.OutputFormat[k] == dm_420 && mode_lib->vba.Interlace[k] == true - && mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true)) { + && mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true))) { locals->DIOSupport[i] = false; } } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c index 0bcec113ecac..398210d1af34 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c @@ -4257,10 +4257,11 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { locals->DIOSupport[i] = true; for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { - if (locals->OutputBppPerState[i][k] == BPP_INVALID - || (mode_lib->vba.OutputFormat[k] == dm_420 + if (!mode_lib->vba.skip_dio_check[k] + && (locals->OutputBppPerState[i][k] == BPP_INVALID + || (mode_lib->vba.OutputFormat[k] == dm_420 && mode_lib->vba.Interlace[k] == true - && mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true)) { + && mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true))) { locals->DIOSupport[i] = false; } } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c index 8fdb34aa70ff..bc07082c1357 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c @@ -4263,7 +4263,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l for (i = 0; i < v->soc.num_states; i++) { v->DIOSupport[i] = true; for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) { - if (v->BlendingAndTiming[k] == k && (v->Output[k] == dm_dp || v->Output[k] == dm_edp || v->Output[k] == dm_hdmi) + if (!v->skip_dio_check[k] && v->BlendingAndTiming[k] == k && (v->Output[k] == dm_dp || v->Output[k] == dm_edp || v->Output[k] == dm_hdmi) && (v->OutputBppPerState[i][k] == 0 || (v->OutputFormat[k] == dm_420 && v->Interlace[k] == true && v->ProgressiveToInterlaceUnitInOPP == true))) { v->DIOSupport[i] = false; diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h index dd0c3b1780d7..0c5128187e08 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h @@ -297,6 +297,7 @@ struct _vcs_dpi_display_output_params_st { int num_active_wb; int output_bpc; int output_type; + int is_virtual; int output_format; int dsc_slices; int max_audio_sample_rate; diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c index c9fbb33f05a3..bc0485a59018 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c @@ -451,6 +451,8 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib) dout->output_bpp; mode_lib->vba.Output[mode_lib->vba.NumberOfActivePlanes] = (enum output_encoder_class) (dout->output_type); + mode_lib->vba.skip_dio_check[mode_lib->vba.NumberOfActivePlanes] = + dout->is_virtual; if (!dout->dsc_enable) mode_lib->vba.ForcedOutputLinkBPP[mode_lib->vba.NumberOfActivePlanes] = dout->output_bpp; diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h index 3529fedc4c52..025aa5bd8ea0 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -340,6 +340,7 @@ struct vba_vars_st { unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX]; enum output_format_class OutputFormat[DC__NUM_DPP__MAX]; enum output_encoder_class Output[DC__NUM_DPP__MAX]; + bool skip_dio_check[DC__NUM_DPP__MAX]; unsigned int BlendingAndTiming[DC__NUM_DPP__MAX]; bool SynchronizedVBlank; unsigned int NumberOfCursors[DC__NUM_DPP__MAX]; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index 82a805088204..c62d0eddc9c6 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -369,11 +369,6 @@ static bool decide_dsc_target_bpp_x16( /* enough bandwidth without dsc */ *target_bpp_x16 = 0; should_use_dsc = false; - } else if (policy->preferred_bpp_x16 > 0 && - policy->preferred_bpp_x16 <= range.max_target_bpp_x16 && - policy->preferred_bpp_x16 >= range.min_target_bpp_x16) { - *target_bpp_x16 = policy->preferred_bpp_x16; - should_use_dsc = true; } else if (target_bandwidth_kbps >= range.max_kbps) { /* use max target bpp allowed */ *target_bpp_x16 = range.max_target_bpp_x16; @@ -550,7 +545,7 @@ static bool setup_dsc_config( int target_bandwidth_kbps, const struct dc_crtc_timing *timing, int min_slice_height_override, - int max_dsc_target_bpp_limit_override_x16, + int max_dsc_target_bpp_limit_override, struct dc_dsc_config *dsc_cfg) { struct dsc_enc_caps dsc_common_caps; @@ -569,7 +564,7 @@ static bool setup_dsc_config( memset(dsc_cfg, 0, sizeof(struct dc_dsc_config)); - dc_dsc_get_policy_for_timing(timing, max_dsc_target_bpp_limit_override_x16, &policy); + dc_dsc_get_policy_for_timing(timing, max_dsc_target_bpp_limit_override, &policy); pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right; pic_height = timing->v_addressable + timing->v_border_top + timing->v_border_bottom; @@ -870,8 +865,8 @@ bool dc_dsc_parse_dsc_dpcd(const struct dc *dc, const uint8_t *dpcd_dsc_basic_da bool dc_dsc_compute_bandwidth_range( const struct display_stream_compressor *dsc, uint32_t dsc_min_slice_height_override, - uint32_t min_bpp_x16, - uint32_t max_bpp_x16, + uint32_t min_bpp, + uint32_t max_bpp, const struct dsc_dec_dpcd_caps *dsc_sink_caps, const struct dc_crtc_timing *timing, struct dc_dsc_bw_range *range) @@ -888,10 +883,10 @@ bool dc_dsc_compute_bandwidth_range( if (is_dsc_possible) is_dsc_possible = setup_dsc_config(dsc_sink_caps, &dsc_enc_caps, 0, timing, - dsc_min_slice_height_override, max_bpp_x16, &config); + dsc_min_slice_height_override, max_bpp, &config); if (is_dsc_possible) - get_dsc_bandwidth_range(min_bpp_x16, max_bpp_x16, &dsc_common_caps, timing, range); + get_dsc_bandwidth_range(min_bpp, max_bpp, &dsc_common_caps, timing, range); return is_dsc_possible; } @@ -900,7 +895,7 @@ bool dc_dsc_compute_config( const struct display_stream_compressor *dsc, const struct dsc_dec_dpcd_caps *dsc_sink_caps, uint32_t dsc_min_slice_height_override, - uint32_t max_target_bpp_limit_override_x16, + uint32_t max_target_bpp_limit_override, uint32_t target_bandwidth_kbps, const struct dc_crtc_timing *timing, struct dc_dsc_config *dsc_cfg) @@ -913,11 +908,11 @@ bool dc_dsc_compute_config( &dsc_enc_caps, target_bandwidth_kbps, timing, dsc_min_slice_height_override, - max_target_bpp_limit_override_x16, dsc_cfg); + max_target_bpp_limit_override, dsc_cfg); return is_dsc_possible; } -void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, uint32_t max_target_bpp_limit_override_x16, struct dc_dsc_policy *policy) +void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, uint32_t max_target_bpp_limit_override, struct dc_dsc_policy *policy) { uint32_t bpc = 0; @@ -972,15 +967,13 @@ void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, uint32_t return; } - policy->preferred_bpp_x16 = timing->dsc_fixed_bits_per_pixel_x16; - /* internal upper limit, default 16 bpp */ if (policy->max_target_bpp > dsc_policy_max_target_bpp_limit) policy->max_target_bpp = dsc_policy_max_target_bpp_limit; /* apply override */ - if (max_target_bpp_limit_override_x16 && policy->max_target_bpp > max_target_bpp_limit_override_x16 / 16) - policy->max_target_bpp = max_target_bpp_limit_override_x16 / 16; + if (max_target_bpp_limit_override && policy->max_target_bpp > max_target_bpp_limit_override) + policy->max_target_bpp = max_target_bpp_limit_override; /* enable DSC when not needed, default false */ if (dsc_policy_enable_dsc_when_not_needed) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h index ffd37696b6b9..316301fc1e30 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h @@ -309,9 +309,9 @@ static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_cl static inline bool should_update_pstate_support(bool safe_to_lower, bool calc_support, bool cur_support) { if (cur_support != calc_support) { - if (calc_support == true && safe_to_lower) + if (calc_support && safe_to_lower) return true; - else if (calc_support == false && !safe_to_lower) + else if (!calc_support && !safe_to_lower) return true; } diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c index f956b3bde680..34f43cb650f8 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c @@ -58,6 +58,18 @@ enum dc_irq_source to_dal_irq_source_dcn10( return DC_IRQ_SOURCE_VBLANK5; case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: return DC_IRQ_SOURCE_VBLANK6; + case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC1_VLINE0; + case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC2_VLINE0; + case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC3_VLINE0; + case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC4_VLINE0; + case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC5_VLINE0; + case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC6_VLINE0; case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT: return DC_IRQ_SOURCE_VUPDATE1; case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT: @@ -167,6 +179,11 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = { .ack = NULL }; +static const struct irq_source_info_funcs vline0_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { .set = NULL, .ack = NULL @@ -241,6 +258,14 @@ static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { .funcs = &vblank_irq_info_funcs\ } +#define vline0_int_entry(reg_num)\ + [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\ + IRQ_REG_ENTRY(OTG, reg_num,\ + OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\ + OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\ + .funcs = &vline0_irq_info_funcs\ + } + #define dummy_irq_entry() \ {\ .funcs = &dummy_irq_info_funcs\ @@ -349,6 +374,12 @@ irq_source_info_dcn10[DAL_IRQ_SOURCES_NUMBER] = { vblank_int_entry(3), vblank_int_entry(4), vblank_int_entry(5), + vline0_int_entry(0), + vline0_int_entry(1), + vline0_int_entry(2), + vline0_int_entry(3), + vline0_int_entry(4), + vline0_int_entry(5), }; static const struct irq_service_funcs irq_service_funcs_dcn10 = { diff --git a/drivers/gpu/drm/amd/display/dc/irq_types.h b/drivers/gpu/drm/amd/display/dc/irq_types.h index d0ccd81ad5b4..87812d81fed3 100644 --- a/drivers/gpu/drm/amd/display/dc/irq_types.h +++ b/drivers/gpu/drm/amd/display/dc/irq_types.h @@ -160,6 +160,7 @@ enum irq_type IRQ_TYPE_PFLIP = DC_IRQ_SOURCE_PFLIP1, IRQ_TYPE_VUPDATE = DC_IRQ_SOURCE_VUPDATE1, IRQ_TYPE_VBLANK = DC_IRQ_SOURCE_VBLANK1, + IRQ_TYPE_VLINE0 = DC_IRQ_SOURCE_DC1_VLINE0, }; #define DAL_VALID_IRQ_SRC_NUM(src) \ diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 5aaa35c8c172..072b4e7e624b 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -47,10 +47,10 @@ /* Firmware versioning. */ #ifdef DMUB_EXPOSE_VERSION -#define DMUB_FW_VERSION_GIT_HASH 0xca1cd48c9 +#define DMUB_FW_VERSION_GIT_HASH 0x6444c02e7 #define DMUB_FW_VERSION_MAJOR 0 #define DMUB_FW_VERSION_MINOR 0 -#define DMUB_FW_VERSION_REVISION 50 +#define DMUB_FW_VERSION_REVISION 51 #define DMUB_FW_VERSION_TEST 0 #define DMUB_FW_VERSION_VBIOS 0 #define DMUB_FW_VERSION_HOTFIX 0 @@ -491,13 +491,34 @@ struct dmub_rb_cmd_enable_disp_power_gating { struct dmub_cmd_enable_disp_power_gating_data power_gating; }; -struct dmub_cmd_dig1_transmitter_control_data { +struct dmub_dig_transmitter_control_data_v1_7 { + uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ + uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ + union { + uint8_t digmode; /**< enum atom_encode_mode_def */ + uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ + } mode_laneset; + uint8_t lanenum; /**< Number of lanes */ + union { + uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ + } symclk_units; + uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ + uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ + uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ + uint8_t reserved0; /**< For future use */ + uint8_t reserved1; /**< For future use */ + uint8_t reserved2[3]; /**< For future use */ + uint32_t reserved3[11]; /**< For future use */ +}; + +union dmub_cmd_dig1_transmitter_control_data { struct dig_transmitter_control_parameters_v1_6 dig; + struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; }; struct dmub_rb_cmd_dig1_transmitter_control { struct dmub_cmd_header header; - struct dmub_cmd_dig1_transmitter_control_data transmitter_control; + union dmub_cmd_dig1_transmitter_control_data transmitter_control; }; struct dmub_rb_cmd_dpphy_init { diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c index b26ed64eaf98..904ce9b88088 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c @@ -548,6 +548,8 @@ enum mod_hdcp_status mod_hdcp_hdcp2_validate_ake_cert(struct mod_hdcp *hdcp) TA_HDCP2_MSG_AUTHENTICATION_STATUS__RECEIVERID_REVOKED) { hdcp->connection.is_hdcp2_revoked = 1; status = MOD_HDCP_STATUS_HDCP2_AKE_CERT_REVOKED; + } else { + status = MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE; } } mutex_unlock(&psp->hdcp_context.mutex); diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 9676016a37ce..43ed6291b2b8 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -213,6 +213,7 @@ enum PP_FEATURE_MASK { PP_ACG_MASK = 0x10000, PP_STUTTER_MODE = 0x20000, PP_AVFS_MASK = 0x40000, + PP_GFX_DCS_MASK = 0x80000, }; enum DC_FEATURE_MASK { diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_6_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_6_offset.h new file mode 100644 index 000000000000..55facadea54b --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_6_offset.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _smuio_11_0_6_OFFSET_HEADER +#define _smuio_11_0_6_OFFSET_HEADER + + + +// addressBlock: smuio_smuio_SmuSmuioDec +// base address: 0x5a000 +#define mmCGTT_ROM_CLK_CTRL0 0x00e4 +#define mmCGTT_ROM_CLK_CTRL0_BASE_IDX 0 +#define mmROM_INDEX 0x00e5 +#define mmROM_INDEX_BASE_IDX 0 +#define mmROM_DATA 0x00e6 +#define mmROM_DATA_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_6_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_6_sh_mask.h new file mode 100644 index 000000000000..7d6a2fac2839 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_6_sh_mask.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _smuio_11_0_6_SH_MASK_HEADER +#define _smuio_11_0_6_SH_MASK_HEADER + + +//CGTT_ROM_CLK_CTRL0 +#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL +#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L +//ROM_INDEX +#define ROM_INDEX__ROM_INDEX__SHIFT 0x0 +#define ROM_INDEX__ROM_INDEX_MASK 0x01FFFFFFL +//ROM_DATA +#define ROM_DATA__ROM_DATA__SHIFT 0x0 +#define ROM_DATA__ROM_DATA_MASK 0xFFFFFFFFL + +#endif diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index cf475ac01b27..5fa65f191a37 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -3059,7 +3059,8 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev, char *buf) { struct amdgpu_device *adev = dev_get_drvdata(dev); - uint32_t limit = 0; + int limit_type = to_sensor_dev_attr(attr)->index; + uint32_t limit = limit_type << 24; ssize_t size; int r; @@ -3073,7 +3074,7 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev, } if (is_support_sw_smu(adev)) { - smu_get_power_limit(&adev->smu, &limit, true); + smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_MAX); size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) { adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true); @@ -3093,7 +3094,8 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, char *buf) { struct amdgpu_device *adev = dev_get_drvdata(dev); - uint32_t limit = 0; + int limit_type = to_sensor_dev_attr(attr)->index; + uint32_t limit = limit_type << 24; ssize_t size; int r; @@ -3107,7 +3109,7 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, } if (is_support_sw_smu(adev)) { - smu_get_power_limit(&adev->smu, &limit, false); + smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_CURRENT); size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) { adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false); @@ -3122,6 +3124,15 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, return size; } +static ssize_t amdgpu_hwmon_show_power_label(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int limit_type = to_sensor_dev_attr(attr)->index; + + return snprintf(buf, PAGE_SIZE, "%s\n", + limit_type == SMU_FAST_PPT_LIMIT ? "fastPPT" : "slowPPT"); +} static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, struct device_attribute *attr, @@ -3129,6 +3140,7 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, size_t count) { struct amdgpu_device *adev = dev_get_drvdata(dev); + int limit_type = to_sensor_dev_attr(attr)->index; int err; u32 value; @@ -3143,7 +3155,7 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, return err; value = value / 1000000; /* convert to Watt */ - + value |= limit_type << 24; err = pm_runtime_get_sync(adev_to_drm(adev)->dev); if (err < 0) { @@ -3355,6 +3367,12 @@ static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0); static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0); static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0); +static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0); +static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1); +static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1); +static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1); +static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1); +static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1); static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0); static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0); static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0); @@ -3393,6 +3411,12 @@ static struct attribute *hwmon_attributes[] = { &sensor_dev_attr_power1_cap_max.dev_attr.attr, &sensor_dev_attr_power1_cap_min.dev_attr.attr, &sensor_dev_attr_power1_cap.dev_attr.attr, + &sensor_dev_attr_power1_label.dev_attr.attr, + &sensor_dev_attr_power2_average.dev_attr.attr, + &sensor_dev_attr_power2_cap_max.dev_attr.attr, + &sensor_dev_attr_power2_cap_min.dev_attr.attr, + &sensor_dev_attr_power2_cap.dev_attr.attr, + &sensor_dev_attr_power2_label.dev_attr.attr, &sensor_dev_attr_freq1_input.dev_attr.attr, &sensor_dev_attr_freq1_label.dev_attr.attr, &sensor_dev_attr_freq2_input.dev_attr.attr, @@ -3485,8 +3509,9 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, effective_mode &= ~S_IWUSR; } - if (((adev->flags & AMD_IS_APU) || - adev->family == AMDGPU_FAMILY_SI) && /* not implemented yet */ + if (((adev->family == AMDGPU_FAMILY_SI) || + ((adev->flags & AMD_IS_APU) && + (adev->asic_type != CHIP_VANGOGH))) && /* not implemented yet */ (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr || attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr|| attr == &sensor_dev_attr_power1_cap.dev_attr.attr)) @@ -3549,6 +3574,16 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, attr == &sensor_dev_attr_temp3_label.dev_attr.attr)) return 0; + /* only Vangogh has fast PPT limit and power labels */ + if (!(adev->asic_type == CHIP_VANGOGH) && + (attr == &sensor_dev_attr_power2_average.dev_attr.attr || + attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr || + attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr || + attr == &sensor_dev_attr_power2_cap.dev_attr.attr || + attr == &sensor_dev_attr_power2_label.dev_attr.attr || + attr == &sensor_dev_attr_power1_label.dev_attr.attr)) + return 0; + return effective_mode; } diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h index 44279c2afccb..10b0624ade65 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h @@ -161,6 +161,19 @@ enum smu_power_src_type SMU_POWER_SOURCE_COUNT, }; +enum smu_ppt_limit_type +{ + SMU_DEFAULT_PPT_LIMIT = 0, + SMU_FAST_PPT_LIMIT, +}; + +enum smu_ppt_limit_level +{ + SMU_PPT_LIMIT_MIN = -1, + SMU_PPT_LIMIT_CURRENT, + SMU_PPT_LIMIT_MAX, +}; + enum smu_memory_pool_size { SMU_MEMORY_POOL_SIZE_ZERO = 0, @@ -702,6 +715,12 @@ struct pptable_funcs { int (*get_power_limit)(struct smu_context *smu); /** + * @get_ppt_limit: Get the device's ppt limits. + */ + int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit, + enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level); + + /** * @set_df_cstate: Set data fabric cstate. */ int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state); @@ -1218,7 +1237,7 @@ int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed); int smu_get_power_limit(struct smu_context *smu, uint32_t *limit, - bool max_setting); + enum smu_ppt_limit_level limit_level); int smu_set_power_limit(struct smu_context *smu, uint32_t limit); int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h index 68c87d4b1ce3..aa4822202587 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h @@ -210,6 +210,10 @@ __SMU_DUMMY_MAP(DisallowGpo), \ __SMU_DUMMY_MAP(Enable2ndUSB20Port), \ __SMU_DUMMY_MAP(RequestActiveWgp), \ + __SMU_DUMMY_MAP(SetFastPPTLimit), \ + __SMU_DUMMY_MAP(SetSlowPPTLimit), \ + __SMU_DUMMY_MAP(GetFastPPTLimit), \ + __SMU_DUMMY_MAP(GetSlowPPTLimit), \ #undef __SMU_DUMMY_MAP #define __SMU_DUMMY_MAP(type) SMU_MSG_##type diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h index c7d57e9555cc..d4cddd2390a2 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h @@ -129,6 +129,15 @@ struct smu_11_0_power_context { enum smu_11_0_power_state power_state; }; +struct smu_11_5_power_context { + uint32_t power_source; + uint8_t in_power_limit_boost_mode; + enum smu_11_0_power_state power_state; + + uint32_t current_fast_ppt_limit; + uint32_t max_fast_ppt_limit; +}; + enum smu_v11_0_baco_seq { BACO_SEQ_BACO = 0, BACO_SEQ_MSR, @@ -272,10 +281,6 @@ int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu); int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu); -void smu_v11_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics); - -void smu_v11_0_init_gpu_metrics_v2_0(struct gpu_metrics_v2_0 *gpu_metrics); - int smu_v11_0_gfx_ulv_control(struct smu_context *smu, bool enablement); diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h index 55d7892e4e0e..fe130a497d6c 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h @@ -104,7 +104,11 @@ #define PPSMC_MSG_DramLogSetDramBufferSize 0x46 #define PPSMC_MSG_RequestActiveWgp 0x47 #define PPSMC_MSG_QueryActiveWgp 0x48 -#define PPSMC_Message_Count 0x49 +#define PPSMC_MSG_SetFastPPTLimit 0x49 +#define PPSMC_MSG_SetSlowPPTLimit 0x4A +#define PPSMC_MSG_GetFastPPTLimit 0x4B +#define PPSMC_MSG_GetSlowPPTLimit 0x4C +#define PPSMC_Message_Count 0x4D //Argument for PPSMC_MSG_GfxDeviceDriverReset enum { diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v12_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v12_0.h index fa2e8cb07967..02de3b6199e5 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_v12_0.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_v12_0.h @@ -60,7 +60,5 @@ int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_ int smu_v12_0_set_driver_table_location(struct smu_context *smu); -void smu_v12_0_init_gpu_metrics_v2_0(struct gpu_metrics_v2_0 *gpu_metrics); - #endif #endif diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c index 88322781e447..ed05a30d1139 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c @@ -1487,7 +1487,7 @@ static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr, } if (!smu10_data->fine_grain_enabled) { - pr_err("Fine grain not started\n"); + pr_err("pp_od_clk_voltage is not accessible if power_dpm_force_perfomance_level is not in manual mode!\n"); return -EINVAL; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index c00f3f531965..d143ef1b460b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -2044,22 +2044,40 @@ int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed) int smu_get_power_limit(struct smu_context *smu, uint32_t *limit, - bool max_setting) + enum smu_ppt_limit_level limit_level) { + uint32_t limit_type = *limit >> 24; + int ret = 0; + if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) return -EOPNOTSUPP; mutex_lock(&smu->mutex); - *limit = (max_setting ? smu->max_power_limit : smu->current_power_limit); + if (limit_type != SMU_DEFAULT_PPT_LIMIT) { + if (smu->ppt_funcs->get_ppt_limit) + ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); + } else { + switch (limit_level) { + case SMU_PPT_LIMIT_CURRENT: + *limit = smu->current_power_limit; + break; + case SMU_PPT_LIMIT_MAX: + *limit = smu->max_power_limit; + break; + default: + break; + } + } mutex_unlock(&smu->mutex); - return 0; + return ret; } int smu_set_power_limit(struct smu_context *smu, uint32_t limit) { + uint32_t limit_type = limit >> 24; int ret = 0; if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) @@ -2067,6 +2085,12 @@ int smu_set_power_limit(struct smu_context *smu, uint32_t limit) mutex_lock(&smu->mutex); + if (limit_type != SMU_DEFAULT_PPT_LIMIT) + if (smu->ppt_funcs->set_power_limit) { + ret = smu->ppt_funcs->set_power_limit(smu, limit); + goto out; + } + if (limit > smu->max_power_limit) { dev_err(smu->adev->dev, "New power limit (%d) is over the max allowed %d\n", diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c index f0cc4de9ced5..45564a776e9b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c @@ -2239,7 +2239,7 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu, if (ret) return ret; - smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 0); gpu_metrics->temperature_edge = metrics.TemperatureEdge; gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; @@ -2276,6 +2276,8 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu, gpu_metrics->pcie_link_speed = arcturus_get_current_pcie_link_speed(smu); + gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); + *table = (void *)gpu_metrics; return sizeof(struct gpu_metrics_v1_0); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index f7f78daffd27..6e641f1513d8 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -2314,7 +2314,7 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, mutex_unlock(&smu->metrics_lock); - smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 0); gpu_metrics->temperature_edge = metrics.TemperatureEdge; gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; @@ -2354,6 +2354,8 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, gpu_metrics->pcie_link_speed = smu_v11_0_get_current_pcie_link_speed(smu); + gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); + *table = (void *)gpu_metrics; return sizeof(struct gpu_metrics_v1_0); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index e3ba40d9f83f..af73e1430af5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -261,6 +261,11 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT); } + if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) && + (adev->asic_type > CHIP_SIENNA_CICHLID) && + !(adev->flags & AMD_IS_APU)) + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT); + if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) @@ -294,6 +299,12 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT); + if (smu->dc_controlled_by_gpio) + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); + + if (amdgpu_aspm == 1) + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); + return 0; } @@ -2950,7 +2961,7 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, if (ret) return ret; - smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 0); gpu_metrics->temperature_edge = metrics->TemperatureEdge; gpu_metrics->temperature_hotspot = metrics->TemperatureHotspot; @@ -2993,6 +3004,8 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, gpu_metrics->pcie_link_speed = smu_v11_0_get_current_pcie_link_speed(smu); + gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); + *table = (void *)gpu_metrics; return sizeof(struct gpu_metrics_v1_0); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c index cf6176afd4d5..90585461a56e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c @@ -474,12 +474,14 @@ int smu_v11_0_fini_smc_tables(struct smu_context *smu) int smu_v11_0_init_power(struct smu_context *smu) { struct smu_power_context *smu_power = &smu->smu_power; + size_t size = smu->adev->asic_type == CHIP_VANGOGH ? + sizeof(struct smu_11_5_power_context) : + sizeof(struct smu_11_0_power_context); - smu_power->power_context = kzalloc(sizeof(struct smu_11_0_power_context), - GFP_KERNEL); + smu_power->power_context = kzalloc(size, GFP_KERNEL); if (!smu_power->power_context) return -ENOMEM; - smu_power->power_context_size = sizeof(struct smu_11_0_power_context); + smu_power->power_context_size = size; return 0; } @@ -2021,30 +2023,6 @@ int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu) return link_speed[speed_level]; } -void smu_v11_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics) -{ - memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0)); - - gpu_metrics->common_header.structure_size = - sizeof(struct gpu_metrics_v1_0); - gpu_metrics->common_header.format_revision = 1; - gpu_metrics->common_header.content_revision = 0; - - gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); -} - -void smu_v11_0_init_gpu_metrics_v2_0(struct gpu_metrics_v2_0 *gpu_metrics) -{ - memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v2_0)); - - gpu_metrics->common_header.structure_size = - sizeof(struct gpu_metrics_v2_0); - gpu_metrics->common_header.format_revision = 2; - gpu_metrics->common_header.content_revision = 0; - - gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); -} - int smu_v11_0_gfx_ulv_control(struct smu_context *smu, bool enablement) { diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c index f0f06ef47b9e..093b01159408 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -122,6 +122,10 @@ static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(SetSoftMinCclk, PPSMC_MSG_SetSoftMinCclk, 0), MSG_MAP(SetSoftMaxCclk, PPSMC_MSG_SetSoftMaxCclk, 0), MSG_MAP(RequestActiveWgp, PPSMC_MSG_RequestActiveWgp, 0), + MSG_MAP(SetFastPPTLimit, PPSMC_MSG_SetFastPPTLimit, 0), + MSG_MAP(SetSlowPPTLimit, PPSMC_MSG_SetSlowPPTLimit, 0), + MSG_MAP(GetFastPPTLimit, PPSMC_MSG_GetFastPPTLimit, 0), + MSG_MAP(GetSlowPPTLimit, PPSMC_MSG_GetSlowPPTLimit, 0), }; static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = { @@ -1406,7 +1410,7 @@ static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, if (ret) return ret; - smu_v11_0_init_gpu_metrics_v2_0(gpu_metrics); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 0); gpu_metrics->temperature_gfx = metrics.GfxTemperature; gpu_metrics->temperature_soc = metrics.SocTemperature; @@ -1442,6 +1446,8 @@ static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, gpu_metrics->throttle_status = metrics.ThrottlerStatus; + gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); + *table = (void *)gpu_metrics; return sizeof(struct gpu_metrics_v2_0); @@ -1455,7 +1461,8 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) { - dev_warn(smu->adev->dev, "Fine grain is not enabled!\n"); + dev_warn(smu->adev->dev, + "pp_od_clk_voltage is not accessible if power_dpm_force_perfomance_level is not in manual mode!\n"); return -EINVAL; } @@ -1771,6 +1778,112 @@ static int vangogh_mode2_reset(struct smu_context *smu) return vangogh_mode_reset(smu, SMU_RESET_MODE_2); } +static int vangogh_get_power_limit(struct smu_context *smu) +{ + struct smu_11_5_power_context *power_context = + smu->smu_power.power_context; + uint32_t ppt_limit; + int ret = 0; + + if (smu->adev->pm.fw_version < 0x43f1e00) + return ret; + + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSlowPPTLimit, &ppt_limit); + if (ret) { + dev_err(smu->adev->dev, "Get slow PPT limit failed!\n"); + return ret; + } + /* convert from milliwatt to watt */ + smu->current_power_limit = ppt_limit / 1000; + smu->max_power_limit = 29; + + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit); + if (ret) { + dev_err(smu->adev->dev, "Get fast PPT limit failed!\n"); + return ret; + } + /* convert from milliwatt to watt */ + power_context->current_fast_ppt_limit = ppt_limit / 1000; + power_context->max_fast_ppt_limit = 30; + + return ret; +} + +static int vangogh_get_ppt_limit(struct smu_context *smu, + uint32_t *ppt_limit, + enum smu_ppt_limit_type type, + enum smu_ppt_limit_level level) +{ + struct smu_11_5_power_context *power_context = + smu->smu_power.power_context; + + if (!power_context) + return -EOPNOTSUPP; + + if (type == SMU_FAST_PPT_LIMIT) { + switch (level) { + case SMU_PPT_LIMIT_MAX: + *ppt_limit = power_context->max_fast_ppt_limit; + break; + case SMU_PPT_LIMIT_CURRENT: + *ppt_limit = power_context->current_fast_ppt_limit; + break; + default: + break; + } + } + + return 0; +} + +static int vangogh_set_power_limit(struct smu_context *smu, uint32_t ppt_limit) +{ + struct smu_11_5_power_context *power_context = + smu->smu_power.power_context; + uint32_t limit_type = ppt_limit >> 24; + int ret = 0; + + if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { + dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); + return -EOPNOTSUPP; + } + + switch (limit_type) { + case SMU_DEFAULT_PPT_LIMIT: + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_SetSlowPPTLimit, + ppt_limit * 1000, /* convert from watt to milliwatt */ + NULL); + if (ret) + return ret; + + smu->current_power_limit = ppt_limit; + break; + case SMU_FAST_PPT_LIMIT: + ppt_limit &= ~(SMU_FAST_PPT_LIMIT << 24); + if (ppt_limit > power_context->max_fast_ppt_limit) { + dev_err(smu->adev->dev, + "New power limit (%d) is over the max allowed %d\n", + ppt_limit, power_context->max_fast_ppt_limit); + return ret; + } + + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_SetFastPPTLimit, + ppt_limit * 1000, /* convert from watt to milliwatt */ + NULL); + if (ret) + return ret; + + power_context->current_fast_ppt_limit = ppt_limit; + break; + default: + return -EINVAL; + } + + return ret; +} + static const struct pptable_funcs vangogh_ppt_funcs = { .check_fw_status = smu_v11_0_check_fw_status, @@ -1807,6 +1920,9 @@ static const struct pptable_funcs vangogh_ppt_funcs = { .post_init = vangogh_post_smu_init, .mode2_reset = vangogh_mode2_reset, .gfx_off_control = smu_v11_0_gfx_off_control, + .get_ppt_limit = vangogh_get_ppt_limit, + .get_power_limit = vangogh_get_power_limit, + .set_power_limit = vangogh_set_power_limit, }; void vangogh_set_ppt_funcs(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c index ab15570305f7..5faa509f0dba 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c @@ -350,7 +350,8 @@ static int renoir_od_edit_dpm_table(struct smu_context *smu, struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) { - dev_warn(smu->adev->dev, "Fine grain is not enabled!\n"); + dev_warn(smu->adev->dev, + "pp_od_clk_voltage is not accessible if power_dpm_force_perfomance_level is not in manual mode!\n"); return -EINVAL; } @@ -1129,7 +1130,7 @@ static int renoir_get_smu_metrics_data(struct smu_context *smu, *value = metrics->AverageUvdActivity / 100; break; case METRICS_AVERAGE_SOCKETPOWER: - *value = metrics->CurrentSocketPower << 8; + *value = (metrics->CurrentSocketPower << 8) / 1000; break; case METRICS_TEMPERATURE_EDGE: *value = (metrics->GfxTemperature / 100) * @@ -1257,7 +1258,7 @@ static ssize_t renoir_get_gpu_metrics(struct smu_context *smu, if (ret) return ret; - smu_v12_0_init_gpu_metrics_v2_0(gpu_metrics); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 0); gpu_metrics->temperature_gfx = metrics.GfxTemperature; gpu_metrics->temperature_soc = metrics.SocTemperature; @@ -1298,6 +1299,8 @@ static ssize_t renoir_get_gpu_metrics(struct smu_context *smu, gpu_metrics->fan_pwm = metrics.FanPwm; + gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); + *table = (void *)gpu_metrics; return sizeof(struct gpu_metrics_v2_0); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c index 06abf2a7ce9e..6cc4855c8a37 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c @@ -278,15 +278,3 @@ int smu_v12_0_set_driver_table_location(struct smu_context *smu) return ret; } - -void smu_v12_0_init_gpu_metrics_v2_0(struct gpu_metrics_v2_0 *gpu_metrics) -{ - memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v2_0)); - - gpu_metrics->common_header.structure_size = - sizeof(struct gpu_metrics_v2_0); - gpu_metrics->common_header.format_revision = 2; - gpu_metrics->common_header.content_revision = 0; - - gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); -} diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index d9ecaa04d14e..bb620fdd4cd2 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -746,3 +746,31 @@ int smu_cmn_get_metrics_table(struct smu_context *smu, return ret; } + +void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev) +{ + struct metrics_table_header *header = (struct metrics_table_header *)table; + uint16_t structure_size; + +#define METRICS_VERSION(a, b) ((a << 16) | b ) + + switch (METRICS_VERSION(frev, crev)) { + case METRICS_VERSION(1, 0): + structure_size = sizeof(struct gpu_metrics_v1_0); + break; + case METRICS_VERSION(2, 0): + structure_size = sizeof(struct gpu_metrics_v2_0); + break; + default: + break; + } + +#undef METRICS_VERSION + + memset(header, 0xFF, structure_size); + + header->format_revision = frev; + header->content_revision = crev; + header->structure_size = structure_size; + +} diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h index 08ccf2d3257c..c69250185575 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h @@ -97,5 +97,7 @@ int smu_cmn_get_metrics_table(struct smu_context *smu, void *metrics_table, bool bypass_cache); +void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev); + #endif #endif diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug index be76054c01d8..72a38f28393f 100644 --- a/drivers/gpu/drm/i915/Kconfig.debug +++ b/drivers/gpu/drm/i915/Kconfig.debug @@ -19,6 +19,8 @@ config DRM_I915_WERROR config DRM_I915_DEBUG bool "Enable additional driver debugging" depends on DRM_I915 + depends on EXPERT # only for developers + depends on !COMPILE_TEST # never built by robots select DEBUG_FS select PREEMPT_COUNT select I2C_CHARDEV diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index d30374df67f0..e3e69e6cef65 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -256,6 +256,33 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) offset = 0; /* + * When using an X-tiled surface the plane starts to + * misbehave if the x offset + width exceeds the stride. + * hsw/bdw: underrun galore + * ilk/snb/ivb: wrap to the next tile row mid scanout + * i965/g4x: so far appear immune to this + * vlv/chv: TODO check + * + * Linear surfaces seem to work just fine, even on hsw/bdw + * despite them not using the linear offset anymore. + */ + if (INTEL_GEN(dev_priv) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) { + u32 alignment = intel_surf_alignment(fb, 0); + int cpp = fb->format->cpp[0]; + + while ((src_x + src_w) * cpp > plane_state->color_plane[0].stride) { + if (offset == 0) { + drm_dbg_kms(&dev_priv->drm, + "Unable to find suitable display surface offset due to X-tiling\n"); + return -EINVAL; + } + + offset = intel_plane_adjust_aligned_offset(&src_x, &src_y, plane_state, 0, + offset, offset - alignment); + } + } + + /* * Put the final coordinates back so that the src * coordinate checks will see the right values. */ diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 9843a0f202a0..7ea1e5b487b6 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1322,8 +1322,8 @@ static bool has_async_flips(struct drm_i915_private *i915) return INTEL_GEN(i915) >= 5; } -static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, - int color_plane) +unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, + int color_plane) { struct drm_i915_private *dev_priv = to_i915(fb->dev); @@ -1590,10 +1590,10 @@ static u32 intel_adjust_aligned_offset(int *x, int *y, * Adjust the tile offset by moving the difference into * the x/y offsets. */ -static u32 intel_plane_adjust_aligned_offset(int *x, int *y, - const struct intel_plane_state *state, - int color_plane, - u32 old_offset, u32 new_offset) +u32 intel_plane_adjust_aligned_offset(int *x, int *y, + const struct intel_plane_state *state, + int color_plane, + u32 old_offset, u32 new_offset) { return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane, state->hw.rotation, diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 64ffa34544a7..76f8a805b0a3 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -653,6 +653,12 @@ void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state); struct intel_encoder * intel_get_crtc_new_encoder(const struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state); +unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, + int color_plane); +u32 intel_plane_adjust_aligned_offset(int *x, int *y, + const struct intel_plane_state *state, + int color_plane, + u32 old_offset, u32 new_offset); /* modesetting */ void intel_modeset_init_hw(struct drm_i915_private *i915); diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index d5f4b40a8460..95919d325b0b 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -2218,7 +2218,11 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi, has_hdmi_sink)) return MODE_CLOCK_HIGH; - /* BXT DPLL can't generate 223-240 MHz */ + /* GLK DPLL can't generate 446-480 MHz */ + if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000) + return MODE_CLOCK_RANGE; + + /* BXT/GLK DPLL can't generate 223-240 MHz */ if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) return MODE_CLOCK_RANGE; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c index 215766cc22bf..000e1cd8e920 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c @@ -85,6 +85,47 @@ void i915_gem_suspend_late(struct drm_i915_private *i915) wbinvd_on_all_cpus(); } +int i915_gem_freeze(struct drm_i915_private *i915) +{ + /* Discard all purgeable objects, let userspace recover those as + * required after resuming. + */ + i915_gem_shrink_all(i915); + + return 0; +} + +int i915_gem_freeze_late(struct drm_i915_private *i915) +{ + struct drm_i915_gem_object *obj; + intel_wakeref_t wakeref; + + /* + * Called just before we write the hibernation image. + * + * We need to update the domain tracking to reflect that the CPU + * will be accessing all the pages to create and restore from the + * hibernation, and so upon restoration those pages will be in the + * CPU domain. + * + * To make sure the hibernation image contains the latest state, + * we update that state just before writing out the image. + * + * To try and reduce the hibernation image, we manually shrink + * the objects as well, see i915_gem_freeze() + */ + + with_intel_runtime_pm(&i915->runtime_pm, wakeref) + i915_gem_shrink(i915, -1UL, NULL, ~0); + i915_gem_drain_freed_objects(i915); + + wbinvd_on_all_cpus(); + list_for_each_entry(obj, &i915->mm.shrink_list, mm.link) + __start_cpu_write(obj); + + return 0; +} + void i915_gem_resume(struct drm_i915_private *i915) { GEM_TRACE("%s\n", dev_name(i915->drm.dev)); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.h b/drivers/gpu/drm/i915/gem/i915_gem_pm.h index 26b78dbdc225..c9a66630e92e 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.h @@ -19,4 +19,7 @@ void i915_gem_idle_work_handler(struct work_struct *work); void i915_gem_suspend(struct drm_i915_private *i915); void i915_gem_suspend_late(struct drm_i915_private *i915); +int i915_gem_freeze(struct drm_i915_private *i915); +int i915_gem_freeze_late(struct drm_i915_private *i915); + #endif /* __I915_GEM_PM_H__ */ diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c index 551935348ad8..a1e197a6e999 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c @@ -753,22 +753,18 @@ i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *i915, mutex_lock(&i915->mm.stolen_lock); ret = drm_mm_reserve_node(&i915->mm.stolen, stolen); mutex_unlock(&i915->mm.stolen_lock); - if (ret) { - obj = ERR_PTR(ret); + if (ret) goto err_free; - } obj = i915_gem_object_alloc(); if (!obj) { - obj = ERR_PTR(-ENOMEM); + ret = -ENOMEM; goto err_stolen; } ret = __i915_gem_object_create_stolen(mem, obj, stolen); - if (ret) { - obj = ERR_PTR(ret); + if (ret) goto err_object_free; - } i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE); return obj; @@ -779,7 +775,7 @@ err_stolen: i915_gem_stolen_remove_node(i915, stolen); err_free: kfree(stolen); - return obj; + return ERR_PTR(ret); } bool i915_gem_object_is_stolen(const struct drm_i915_gem_object *obj) diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c index 8551e6de50e8..de575fdb033f 100644 --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c @@ -240,7 +240,7 @@ gen7_emit_state_base_address(struct batch_chunk *batch, /* general */ *cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY; /* surface */ - *cs++ = batch_addr(batch) | surface_state_base | BASE_ADDRESS_MODIFY; + *cs++ = (batch_addr(batch) + surface_state_base) | BASE_ADDRESS_MODIFY; /* dynamic */ *cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY; /* indirect */ @@ -393,6 +393,7 @@ static void emit_batch(struct i915_vma * const vma, desc_count); /* Reset inherited context registers */ + gen7_emit_pipeline_flush(&cmds); gen7_emit_pipeline_invalidate(&cmds); batch_add(&cmds, MI_LOAD_REGISTER_IMM(2)); batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7)); diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 3fdcd5ff71dd..ec366cf9ef56 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1834,6 +1834,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) wa_write_or(wal, GEN8_L3SQCREG4, GEN8_LQSC_FLUSH_COHERENT_LINES); + + /* Disable atomics in L3 to prevent unrecoverable hangs */ + wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1, + GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0); + wa_write_clr_set(wal, GEN8_L3SQCREG4, + GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0); + wa_write_clr_set(wal, GEN9_SCRATCH1, + EVICTION_PERF_FIX_ENABLE, 0); } if (IS_HASWELL(i915)) { diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 7fb91de06557..d54ea0e4681d 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -3103,7 +3103,7 @@ void intel_gvt_update_reg_whitelist(struct intel_vgpu *vgpu) struct intel_vgpu_submission *s = &vgpu->submission; struct i915_request *requests[I915_NUM_ENGINES] = {}; bool is_ctx_pinned[I915_NUM_ENGINES] = {}; - int ret; + int ret = 0; if (gvt->is_reg_whitelist_updated) return; @@ -3157,6 +3157,7 @@ void intel_gvt_update_reg_whitelist(struct intel_vgpu *vgpu) if (IS_ERR(vaddr)) { gvt_err("failed to pin init ctx obj, ring=%d, err=%lx\n", id, PTR_ERR(vaddr)); + ret = PTR_ERR(vaddr); goto out; } diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 2febda554bca..8e9cb44e66e5 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -65,6 +65,7 @@ #include "gem/i915_gem_context.h" #include "gem/i915_gem_ioctls.h" #include "gem/i915_gem_mman.h" +#include "gem/i915_gem_pm.h" #include "gt/intel_gt.h" #include "gt/intel_gt_pm.h" #include "gt/intel_rc6.h" diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 574f3575879d..56cc9191b8d0 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1800,8 +1800,6 @@ int i915_gem_init_userptr(struct drm_i915_private *dev_priv); void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv); void i915_gem_init_early(struct drm_i915_private *dev_priv); void i915_gem_cleanup_early(struct drm_i915_private *dev_priv); -int i915_gem_freeze(struct drm_i915_private *dev_priv); -int i915_gem_freeze_late(struct drm_i915_private *dev_priv); struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 9b04dff5eb32..aa4490934469 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1145,47 +1145,6 @@ void i915_gem_cleanup_early(struct drm_i915_private *dev_priv) drm_WARN_ON(&dev_priv->drm, dev_priv->mm.shrink_count); } -int i915_gem_freeze(struct drm_i915_private *dev_priv) -{ - /* Discard all purgeable objects, let userspace recover those as - * required after resuming. - */ - i915_gem_shrink_all(dev_priv); - - return 0; -} - -int i915_gem_freeze_late(struct drm_i915_private *i915) -{ - struct drm_i915_gem_object *obj; - intel_wakeref_t wakeref; - - /* - * Called just before we write the hibernation image. - * - * We need to update the domain tracking to reflect that the CPU - * will be accessing all the pages to create and restore from the - * hibernation, and so upon restoration those pages will be in the - * CPU domain. - * - * To make sure the hibernation image contains the latest state, - * we update that state just before writing out the image. - * - * To try and reduce the hibernation image, we manually shrink - * the objects as well, see i915_gem_freeze() - */ - - with_intel_runtime_pm(&i915->runtime_pm, wakeref) - i915_gem_shrink(i915, -1UL, NULL, ~0); - i915_gem_drain_freed_objects(i915); - - wbinvd_on_all_cpus(); - list_for_each_entry(obj, &i915->mm.shrink_list, mm.link) - __start_cpu_write(obj); - - return 0; -} - int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file) { struct drm_i915_file_private *file_priv; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 598abd2f5b5f..7146cd0f3256 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8225,6 +8225,7 @@ enum { #define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6) #define GEN8_LQSC_RO_PERF_DIS (1 << 27) #define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21) +#define GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(22) /* GEN8 chicken */ #define HDC_CHICKEN0 _MMIO(0x7300) @@ -12107,6 +12108,12 @@ enum skl_power_gate { #define __GEN11_VCS2_MOCS0 0x10000 #define GEN11_MFX2_MOCS(i) _MMIO(__GEN11_VCS2_MOCS0 + (i) * 4) +#define GEN9_SCRATCH_LNCF1 _MMIO(0xb008) +#define GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(0) + +#define GEN9_SCRATCH1 _MMIO(0xb11c) +#define EVICTION_PERF_FIX_ENABLE REG_BIT(8) + #define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0) #define PMFLUSHDONE_LNICRSDROP (1 << 20) #define PMFLUSH_GAPL3UNBLOCK (1 << 21) diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c b/drivers/gpu/drm/i915/selftests/i915_gem.c index 412e21604a05..dc394fb7ccfa 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem.c @@ -8,6 +8,7 @@ #include "gem/selftests/igt_gem_utils.h" #include "gem/selftests/mock_context.h" +#include "gem/i915_gem_pm.h" #include "gt/intel_gt.h" #include "gt/intel_gt_pm.h" diff --git a/drivers/gpu/drm/msm/adreno/a5xx.xml.h b/drivers/gpu/drm/msm/adreno/a5xx.xml.h index 346cc6ff3a36..7b9fcfe95c04 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a5xx.xml.h @@ -2367,6 +2367,8 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) #define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80 +#define REG_A5XX_UCHE_MODE_CNTL 0x00000e81 + #define REG_A5XX_UCHE_SVM_CNTL 0x00000e82 #define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87 diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index a5af223eaf50..7e553d3efeb2 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -222,7 +222,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) a5xx_preempt_trigger(gpu); } -static const struct { +static const struct adreno_five_hwcg_regs { u32 offset; u32 value; } a5xx_hwcg[] = { @@ -318,16 +318,124 @@ static const struct { {REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, {REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, {REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222} +}, a50x_hwcg[] = { + {REG_A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, + {REG_A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, + {REG_A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, + {REG_A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222}, + {REG_A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777}, + {REG_A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111}, + {REG_A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_HYST_UCHE, 0x00FFFFF4}, + {REG_A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, + {REG_A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220}, + {REG_A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555}, + {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404}, + {REG_A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044}, + {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002}, + {REG_A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011}, + {REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, + {REG_A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222}, + {REG_A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, + {REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, + {REG_A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, + {REG_A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, + {REG_A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, + {REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, + {REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, + {REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, +}, a512_hwcg[] = { + {REG_A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_SP1, 0x02222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, + {REG_A5XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220}, + {REG_A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, + {REG_A5XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF}, + {REG_A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, + {REG_A5XX_RBBM_CLOCK_DELAY_SP1, 0x00000080}, + {REG_A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_TP1, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222}, + {REG_A5XX_RBBM_CLOCK_CNTL3_TP1, 0x00002222}, + {REG_A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST_TP1, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST2_TP1, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777}, + {REG_A5XX_RBBM_CLOCK_HYST3_TP1, 0x00007777}, + {REG_A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY_TP1, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111}, + {REG_A5XX_RBBM_CLOCK_DELAY3_TP1, 0x00001111}, + {REG_A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, + {REG_A5XX_RBBM_CLOCK_HYST_UCHE, 0x00444444}, + {REG_A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, + {REG_A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_RB1, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_RB1, 0x00222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220}, + {REG_A5XX_RBBM_CLOCK_CNTL_CCU1, 0x00022220}, + {REG_A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555}, + {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404}, + {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1, 0x04040404}, + {REG_A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044}, + {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002}, + {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1, 0x00000002}, + {REG_A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011}, + {REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, + {REG_A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222}, + {REG_A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, + {REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, + {REG_A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, + {REG_A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, + {REG_A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, + {REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, + {REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, + {REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, }; void a5xx_set_hwcg(struct msm_gpu *gpu, bool state) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - unsigned int i; + const struct adreno_five_hwcg_regs *regs; + unsigned int i, sz; + + if (adreno_is_a508(adreno_gpu)) { + regs = a50x_hwcg; + sz = ARRAY_SIZE(a50x_hwcg); + } else if (adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu)) { + regs = a512_hwcg; + sz = ARRAY_SIZE(a512_hwcg); + } else { + regs = a5xx_hwcg; + sz = ARRAY_SIZE(a5xx_hwcg); + } - for (i = 0; i < ARRAY_SIZE(a5xx_hwcg); i++) - gpu_write(gpu, a5xx_hwcg[i].offset, - state ? a5xx_hwcg[i].value : 0); + for (i = 0; i < sz; i++) + gpu_write(gpu, regs[i].offset, + state ? regs[i].value : 0); if (adreno_is_a540(adreno_gpu)) { gpu_write(gpu, REG_A5XX_RBBM_CLOCK_DELAY_GPMU, state ? 0x00000770 : 0); @@ -538,11 +646,13 @@ static int a5xx_hw_init(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + u32 regbit; int ret; gpu_write(gpu, REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003); - if (adreno_is_a540(adreno_gpu)) + if (adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu) || + adreno_is_a540(adreno_gpu)) gpu_write(gpu, REG_A5XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); /* Make all blocks contribute to the GPU BUSY perf counter */ @@ -604,29 +714,48 @@ static int a5xx_hw_init(struct msm_gpu *gpu) 0x00100000 + adreno_gpu->gmem - 1); gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000); - if (adreno_is_a510(adreno_gpu)) { + if (adreno_is_a508(adreno_gpu) || adreno_is_a510(adreno_gpu)) { gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x20); - gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x20); + if (adreno_is_a508(adreno_gpu)) + gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400); + else + gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x20); gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x40000030); gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x20100D0A); - gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, - (0x200 << 11 | 0x200 << 22)); } else { gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x40); if (adreno_is_a530(adreno_gpu)) gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x40); - if (adreno_is_a540(adreno_gpu)) + else gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400); gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x80000060); gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16); + } + + if (adreno_is_a508(adreno_gpu)) + gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, + (0x100 << 11 | 0x100 << 22)); + else if (adreno_is_a509(adreno_gpu) || adreno_is_a510(adreno_gpu) || + adreno_is_a512(adreno_gpu)) + gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, + (0x200 << 11 | 0x200 << 22)); + else gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, (0x400 << 11 | 0x300 << 22)); - } if (adreno_gpu->info->quirks & ADRENO_QUIRK_TWO_PASS_USE_WFI) gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8)); - gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0xc0200100); + /* + * Disable the RB sampler datapath DP2 clock gating optimization + * for 1-SP GPUs, as it is enabled by default. + */ + if (adreno_is_a508(adreno_gpu) || adreno_is_a509(adreno_gpu) || + adreno_is_a512(adreno_gpu)) + gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9)); + + /* Disable UCHE global filter as SP can invalidate/flush independently */ + gpu_write(gpu, REG_A5XX_UCHE_MODE_CNTL, BIT(29)); /* Enable USE_RETENTION_FLOPS */ gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000); @@ -653,10 +782,20 @@ static int a5xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F); /* Set the highest bank bit */ - gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, 2 << 7); - gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, 2 << 1); if (adreno_is_a540(adreno_gpu)) - gpu_write(gpu, REG_A5XX_UCHE_DBG_ECO_CNTL_2, 2); + regbit = 2; + else + regbit = 1; + + gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, regbit << 7); + gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, regbit << 1); + + if (adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu) || + adreno_is_a540(adreno_gpu)) + gpu_write(gpu, REG_A5XX_UCHE_DBG_ECO_CNTL_2, regbit); + + /* Disable All flat shading optimization (ALLFLATOPTDIS) */ + gpu_rmw(gpu, REG_A5XX_VPC_DBG_ECO_CNTL, 0, (1 << 10)); /* Protect registers from the CP */ gpu_write(gpu, REG_A5XX_CP_PROTECT_CNTL, 0x00000007); @@ -688,12 +827,14 @@ static int a5xx_hw_init(struct msm_gpu *gpu) /* VPC */ gpu_write(gpu, REG_A5XX_CP_PROTECT(14), ADRENO_PROTECT_RW(0xE68, 8)); - gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 4)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 16)); /* UCHE */ gpu_write(gpu, REG_A5XX_CP_PROTECT(16), ADRENO_PROTECT_RW(0xE80, 16)); - if (adreno_is_a530(adreno_gpu) || adreno_is_a510(adreno_gpu)) + if (adreno_is_a508(adreno_gpu) || adreno_is_a509(adreno_gpu) || + adreno_is_a510(adreno_gpu) || adreno_is_a512(adreno_gpu) || + adreno_is_a530(adreno_gpu)) gpu_write(gpu, REG_A5XX_CP_PROTECT(17), ADRENO_PROTECT_RW(0x10000, 0x8000)); @@ -735,7 +876,8 @@ static int a5xx_hw_init(struct msm_gpu *gpu) if (ret) return ret; - if (!adreno_is_a510(adreno_gpu)) + if (!(adreno_is_a508(adreno_gpu) || adreno_is_a509(adreno_gpu) || + adreno_is_a510(adreno_gpu) || adreno_is_a512(adreno_gpu))) a5xx_gpmu_ucode_init(gpu); ret = a5xx_ucode_init(gpu); @@ -1168,7 +1310,8 @@ static int a5xx_pm_resume(struct msm_gpu *gpu) if (ret) return ret; - if (adreno_is_a510(adreno_gpu)) { + /* Adreno 508, 509, 510, 512 needs manual RBBM sus/res control */ + if (!(adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu))) { /* Halt the sp_input_clk at HM level */ gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, 0x00000055); a5xx_set_hwcg(gpu, true); @@ -1210,8 +1353,8 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu) u32 mask = 0xf; int i, ret; - /* A510 has 3 XIN ports in VBIF */ - if (adreno_is_a510(adreno_gpu)) + /* A508, A510 have 3 XIN ports in VBIF */ + if (adreno_is_a508(adreno_gpu) || adreno_is_a510(adreno_gpu)) mask = 0x7; /* Clear the VBIF pipe before shutting down */ @@ -1223,10 +1366,12 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu) /* * Reset the VBIF before power collapse to avoid issue with FIFO - * entries + * entries on Adreno A510 and A530 (the others will tend to lock up) */ - gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x003C0000); - gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x00000000); + if (adreno_is_a510(adreno_gpu) || adreno_is_a530(adreno_gpu)) { + gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x003C0000); + gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x00000000); + } ret = msm_gpu_pm_suspend(gpu); if (ret) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_power.c b/drivers/gpu/drm/msm/adreno/a5xx_power.c index f176a6f3eff6..5ccc9da455a1 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_power.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_power.c @@ -298,7 +298,7 @@ int a5xx_power_init(struct msm_gpu *gpu) int ret; /* Not all A5xx chips have a GPMU */ - if (adreno_is_a510(adreno_gpu)) + if (!(adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu))) return 0; /* Set up the limits management */ @@ -330,7 +330,7 @@ void a5xx_gpmu_ucode_init(struct msm_gpu *gpu) unsigned int *data, *ptr, *cmds; unsigned int cmds_size; - if (adreno_is_a510(adreno_gpu)) + if (!(adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu))) return; if (a5xx_gpu->gpmu_bo) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index e6703ae98760..9066e98eb8ef 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -245,37 +245,66 @@ static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu) return ret; } +struct a6xx_gmu_oob_bits { + int set, ack, set_new, ack_new; + const char *name; +}; + +/* These are the interrupt / ack bits for each OOB request that are set + * in a6xx_gmu_set_oob and a6xx_clear_oob + */ +static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = { + [GMU_OOB_GPU_SET] = { + .name = "GPU_SET", + .set = 16, + .ack = 24, + .set_new = 30, + .ack_new = 31, + }, + + [GMU_OOB_PERFCOUNTER_SET] = { + .name = "PERFCOUNTER", + .set = 17, + .ack = 25, + .set_new = 28, + .ack_new = 30, + }, + + [GMU_OOB_BOOT_SLUMBER] = { + .name = "BOOT_SLUMBER", + .set = 22, + .ack = 30, + }, + + [GMU_OOB_DCVS_SET] = { + .name = "GPU_DCVS", + .set = 23, + .ack = 31, + }, +}; + /* Trigger a OOB (out of band) request to the GMU */ int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) { int ret; u32 val; int request, ack; - const char *name; - switch (state) { - case GMU_OOB_GPU_SET: - if (gmu->legacy) { - request = GMU_OOB_GPU_SET_REQUEST; - ack = GMU_OOB_GPU_SET_ACK; - } else { - request = GMU_OOB_GPU_SET_REQUEST_NEW; - ack = GMU_OOB_GPU_SET_ACK_NEW; - } - name = "GPU_SET"; - break; - case GMU_OOB_BOOT_SLUMBER: - request = GMU_OOB_BOOT_SLUMBER_REQUEST; - ack = GMU_OOB_BOOT_SLUMBER_ACK; - name = "BOOT_SLUMBER"; - break; - case GMU_OOB_DCVS_SET: - request = GMU_OOB_DCVS_REQUEST; - ack = GMU_OOB_DCVS_ACK; - name = "GPU_DCVS"; - break; - default: + if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits)) return -EINVAL; + + if (gmu->legacy) { + request = a6xx_gmu_oob_bits[state].set; + ack = a6xx_gmu_oob_bits[state].ack; + } else { + request = a6xx_gmu_oob_bits[state].set_new; + ack = a6xx_gmu_oob_bits[state].ack_new; + if (!request || !ack) { + DRM_DEV_ERROR(gmu->dev, + "Invalid non-legacy GMU request %s\n", + a6xx_gmu_oob_bits[state].name); + return -EINVAL; + } } /* Trigger the equested OOB operation */ @@ -288,7 +317,7 @@ int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) if (ret) DRM_DEV_ERROR(gmu->dev, "Timeout waiting for GMU OOB set %s: 0x%x\n", - name, + a6xx_gmu_oob_bits[state].name, gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO)); /* Clear the acknowledge interrupt */ @@ -300,27 +329,17 @@ int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) /* Clear a pending OOB state in the GMU */ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) { - if (!gmu->legacy) { - WARN_ON(state != GMU_OOB_GPU_SET); - gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, - 1 << GMU_OOB_GPU_SET_CLEAR_NEW); + int bit; + + if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits)) return; - } - switch (state) { - case GMU_OOB_GPU_SET: - gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, - 1 << GMU_OOB_GPU_SET_CLEAR); - break; - case GMU_OOB_BOOT_SLUMBER: - gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, - 1 << GMU_OOB_BOOT_SLUMBER_CLEAR); - break; - case GMU_OOB_DCVS_SET: - gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, - 1 << GMU_OOB_DCVS_CLEAR); - break; - } + if (gmu->legacy) + bit = a6xx_gmu_oob_bits[state].ack; + else + bit = a6xx_gmu_oob_bits[state].ack_new; + + gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, bit); } /* Enable CPU control of SPTP power power collapse */ diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h index c6d2bced8e5d..71dfa60070cc 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -153,44 +153,27 @@ static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value) */ enum a6xx_gmu_oob_state { + /* + * Let the GMU know that a boot or slumber operation has started. The value in + * REG_A6XX_GMU_BOOT_SLUMBER_OPTION lets the GMU know which operation we are + * doing + */ GMU_OOB_BOOT_SLUMBER = 0, + /* + * Let the GMU know to not turn off any GPU registers while the CPU is in a + * critical section + */ GMU_OOB_GPU_SET, + /* + * Set a new power level for the GPU when the CPU is doing frequency scaling + */ GMU_OOB_DCVS_SET, + /* + * Used to keep the GPU on for CPU-side reads of performance counters. + */ + GMU_OOB_PERFCOUNTER_SET, }; -/* These are the interrupt / ack bits for each OOB request that are set - * in a6xx_gmu_set_oob and a6xx_clear_oob - */ - -/* - * Let the GMU know that a boot or slumber operation has started. The value in - * REG_A6XX_GMU_BOOT_SLUMBER_OPTION lets the GMU know which operation we are - * doing - */ -#define GMU_OOB_BOOT_SLUMBER_REQUEST 22 -#define GMU_OOB_BOOT_SLUMBER_ACK 30 -#define GMU_OOB_BOOT_SLUMBER_CLEAR 30 - -/* - * Set a new power level for the GPU when the CPU is doing frequency scaling - */ -#define GMU_OOB_DCVS_REQUEST 23 -#define GMU_OOB_DCVS_ACK 31 -#define GMU_OOB_DCVS_CLEAR 31 - -/* - * Let the GMU know to not turn off any GPU registers while the CPU is in a - * critical section - */ -#define GMU_OOB_GPU_SET_REQUEST 16 -#define GMU_OOB_GPU_SET_ACK 24 -#define GMU_OOB_GPU_SET_CLEAR 24 - -#define GMU_OOB_GPU_SET_REQUEST_NEW 30 -#define GMU_OOB_GPU_SET_ACK_NEW 31 -#define GMU_OOB_GPU_SET_CLEAR_NEW 31 - - void a6xx_hfi_init(struct a6xx_gmu *gmu); int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state); void a6xx_hfi_stop(struct a6xx_gmu *gmu); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 130661898546..ba8e9d3cf0fe 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -10,6 +10,7 @@ #include <linux/bitfield.h> #include <linux/devfreq.h> +#include <linux/nvmem-consumer.h> #include <linux/soc/qcom/llcc-qcom.h> #define GPU_PAS_ID 13 @@ -1117,7 +1118,7 @@ static void a6xx_llc_slices_init(struct platform_device *pdev, a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU); a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW); - if (IS_ERR(a6xx_gpu->llc_slice) && IS_ERR(a6xx_gpu->htw_llc_slice)) + if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL); } @@ -1169,14 +1170,18 @@ static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); + static DEFINE_MUTEX(perfcounter_oob); + + mutex_lock(&perfcounter_oob); /* Force the GPU power on so we can read this register */ - a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); + a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); *value = gpu_read64(gpu, REG_A6XX_RBBM_PERFCTR_CP_0_LO, REG_A6XX_RBBM_PERFCTR_CP_0_HI); - a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); + a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); + mutex_unlock(&perfcounter_oob); return 0; } @@ -1208,6 +1213,10 @@ static void a6xx_destroy(struct msm_gpu *gpu) a6xx_gmu_remove(a6xx_gpu); adreno_gpu_cleanup(adreno_gpu); + + if (a6xx_gpu->opp_table) + dev_pm_opp_put_supported_hw(a6xx_gpu->opp_table); + kfree(a6xx_gpu); } @@ -1240,6 +1249,50 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu) } static struct msm_gem_address_space * +a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); + struct iommu_domain *iommu; + struct msm_mmu *mmu; + struct msm_gem_address_space *aspace; + u64 start, size; + + iommu = iommu_domain_alloc(&platform_bus_type); + if (!iommu) + return NULL; + + /* + * This allows GPU to set the bus attributes required to use system + * cache on behalf of the iommu page table walker. + */ + if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) + adreno_set_llc_attributes(iommu); + + mmu = msm_iommu_new(&pdev->dev, iommu); + if (IS_ERR(mmu)) { + iommu_domain_free(iommu); + return ERR_CAST(mmu); + } + + /* + * Use the aperture start or SZ_16M, whichever is greater. This will + * ensure that we align with the allocated pagetable range while still + * allowing room in the lower 32 bits for GMEM and whatnot + */ + start = max_t(u64, SZ_16M, iommu->geometry.aperture_start); + size = iommu->geometry.aperture_end - start + 1; + + aspace = msm_gem_address_space_create(mmu, "gpu", + start & GENMASK_ULL(48, 0), size); + + if (IS_ERR(aspace) && !IS_ERR(mmu)) + mmu->funcs->destroy(mmu); + + return aspace; +} + +static struct msm_gem_address_space * a6xx_create_private_address_space(struct msm_gpu *gpu) { struct msm_mmu *mmu; @@ -1264,6 +1317,78 @@ static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR); } +static u32 a618_get_speed_bin(u32 fuse) +{ + if (fuse == 0) + return 0; + else if (fuse == 169) + return 1; + else if (fuse == 174) + return 2; + + return UINT_MAX; +} + +static u32 fuse_to_supp_hw(struct device *dev, u32 revn, u32 fuse) +{ + u32 val = UINT_MAX; + + if (revn == 618) + val = a618_get_speed_bin(fuse); + + if (val == UINT_MAX) { + DRM_DEV_ERROR(dev, + "missing support for speed-bin: %u. Some OPPs may not be supported by hardware", + fuse); + return UINT_MAX; + } + + return (1 << val); +} + +static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu, + u32 revn) +{ + struct opp_table *opp_table; + struct nvmem_cell *cell; + u32 supp_hw = UINT_MAX; + void *buf; + + cell = nvmem_cell_get(dev, "speed_bin"); + /* + * -ENOENT means that the platform doesn't support speedbin which is + * fine + */ + if (PTR_ERR(cell) == -ENOENT) + return 0; + else if (IS_ERR(cell)) { + DRM_DEV_ERROR(dev, + "failed to read speed-bin. Some OPPs may not be supported by hardware"); + goto done; + } + + buf = nvmem_cell_read(cell, NULL); + if (IS_ERR(buf)) { + nvmem_cell_put(cell); + DRM_DEV_ERROR(dev, + "failed to read speed-bin. Some OPPs may not be supported by hardware"); + goto done; + } + + supp_hw = fuse_to_supp_hw(dev, revn, *((u32 *) buf)); + + kfree(buf); + nvmem_cell_put(cell); + +done: + opp_table = dev_pm_opp_set_supported_hw(dev, &supp_hw, 1); + if (IS_ERR(opp_table)) + return PTR_ERR(opp_table); + + a6xx_gpu->opp_table = opp_table; + return 0; +} + static const struct adreno_gpu_funcs funcs = { .base = { .get_param = adreno_get_param, @@ -1285,7 +1410,7 @@ static const struct adreno_gpu_funcs funcs = { .gpu_state_get = a6xx_gpu_state_get, .gpu_state_put = a6xx_gpu_state_put, #endif - .create_address_space = adreno_iommu_create_address_space, + .create_address_space = a6xx_create_address_space, .create_private_address_space = a6xx_create_private_address_space, .get_rptr = a6xx_get_rptr, }, @@ -1325,6 +1450,12 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) a6xx_llc_slices_init(pdev, a6xx_gpu); + ret = a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info->revn); + if (ret) { + a6xx_destroy(&(a6xx_gpu->base.base)); + return ERR_PTR(ret); + } + ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index e793d329e77b..ce0610c5256f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -33,6 +33,8 @@ struct a6xx_gpu { void *llc_slice; void *htw_llc_slice; bool have_mmu500; + + struct opp_table *opp_table; }; #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 12e75ba360f9..600d445fabe8 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -134,6 +134,41 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a4xx_gpu_init, }, { + .rev = ADRENO_REV(5, 0, 8, ANY_ID), + .revn = 508, + .name = "A508", + .fw = { + [ADRENO_FW_PM4] = "a530_pm4.fw", + [ADRENO_FW_PFP] = "a530_pfp.fw", + }, + .gmem = (SZ_128K + SZ_8K), + /* + * Increase inactive period to 250 to avoid bouncing + * the GDSC which appears to make it grumpy + */ + .inactive_period = 250, + .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, + .init = a5xx_gpu_init, + .zapfw = "a508_zap.mdt", + }, { + .rev = ADRENO_REV(5, 0, 9, ANY_ID), + .revn = 509, + .name = "A509", + .fw = { + [ADRENO_FW_PM4] = "a530_pm4.fw", + [ADRENO_FW_PFP] = "a530_pfp.fw", + }, + .gmem = (SZ_256K + SZ_16K), + /* + * Increase inactive period to 250 to avoid bouncing + * the GDSC which appears to make it grumpy + */ + .inactive_period = 250, + .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, + .init = a5xx_gpu_init, + /* Adreno 509 uses the same ZAP as 512 */ + .zapfw = "a512_zap.mdt", + }, { .rev = ADRENO_REV(5, 1, 0, ANY_ID), .revn = 510, .name = "A510", @@ -149,6 +184,23 @@ static const struct adreno_info gpulist[] = { .inactive_period = 250, .init = a5xx_gpu_init, }, { + .rev = ADRENO_REV(5, 1, 2, ANY_ID), + .revn = 512, + .name = "A512", + .fw = { + [ADRENO_FW_PM4] = "a530_pm4.fw", + [ADRENO_FW_PFP] = "a530_pfp.fw", + }, + .gmem = (SZ_256K + SZ_16K), + /* + * Increase inactive period to 250 to avoid bouncing + * the GDSC which appears to make it grumpy + */ + .inactive_period = 250, + .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, + .init = a5xx_gpu_init, + .zapfw = "a512_zap.mdt", + }, { .rev = ADRENO_REV(5, 3, 0, 2), .revn = 530, .name = "A530", @@ -168,7 +220,7 @@ static const struct adreno_info gpulist[] = { .init = a5xx_gpu_init, .zapfw = "a530_zap.mdt", }, { - .rev = ADRENO_REV(5, 4, 0, 2), + .rev = ADRENO_REV(5, 4, 0, ANY_ID), .revn = 540, .name = "A540", .fw = { diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index f09175698827..0f184c3dd9d9 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -186,11 +186,18 @@ int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid); } +void adreno_set_llc_attributes(struct iommu_domain *iommu) +{ + struct io_pgtable_domain_attr pgtbl_cfg; + + pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA; + iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG, &pgtbl_cfg); +} + struct msm_gem_address_space * adreno_iommu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) { - struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct iommu_domain *iommu; struct msm_mmu *mmu; struct msm_gem_address_space *aspace; @@ -200,20 +207,6 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu, if (!iommu) return NULL; - - if (adreno_is_a6xx(adreno_gpu)) { - struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); - struct io_pgtable_domain_attr pgtbl_cfg; - /* - * This allows GPU to set the bus attributes required to use system - * cache on behalf of the iommu page table walker. - */ - if (!IS_ERR(a6xx_gpu->htw_llc_slice)) { - pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA; - iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG, &pgtbl_cfg); - } - } - mmu = msm_iommu_new(&pdev->dev, iommu); if (IS_ERR(mmu)) { iommu_domain_free(iommu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index b3d9a333591b..ccac275aa7a2 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -197,11 +197,26 @@ static inline int adreno_is_a430(struct adreno_gpu *gpu) return gpu->revn == 430; } +static inline int adreno_is_a508(struct adreno_gpu *gpu) +{ + return gpu->revn == 508; +} + +static inline int adreno_is_a509(struct adreno_gpu *gpu) +{ + return gpu->revn == 509; +} + static inline int adreno_is_a510(struct adreno_gpu *gpu) { return gpu->revn == 510; } +static inline int adreno_is_a512(struct adreno_gpu *gpu) +{ + return gpu->revn == 512; +} + static inline int adreno_is_a530(struct adreno_gpu *gpu) { return gpu->revn == 530; @@ -212,11 +227,6 @@ static inline int adreno_is_a540(struct adreno_gpu *gpu) return gpu->revn == 540; } -static inline bool adreno_is_a6xx(struct adreno_gpu *gpu) -{ - return ((gpu->revn < 700 && gpu->revn > 599)); -} - static inline int adreno_is_a618(struct adreno_gpu *gpu) { return gpu->revn == 618; @@ -278,6 +288,8 @@ struct msm_gem_address_space * adreno_iommu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev); +void adreno_set_llc_attributes(struct iommu_domain *iommu); + /* * For a5xx and a6xx targets load the zap shader that is used to pull the GPU * out of secure mode diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 5a056c1191df..b2be39b9144e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -4,8 +4,10 @@ */ #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ +#include <linux/delay.h> #include "dpu_encoder_phys.h" #include "dpu_hw_interrupts.h" +#include "dpu_hw_pingpong.h" #include "dpu_core_irq.h" #include "dpu_formats.h" #include "dpu_trace.h" @@ -35,6 +37,8 @@ #define DPU_ENC_WR_PTR_START_TIMEOUT_US 20000 +#define DPU_ENC_MAX_POLL_TIMEOUT_US 2000 + static bool dpu_encoder_phys_cmd_is_master(struct dpu_encoder_phys *phys_enc) { return (phys_enc->split_role != ENC_ROLE_SLAVE) ? true : false; @@ -368,15 +372,12 @@ static void dpu_encoder_phys_cmd_tearcheck_config( tc_cfg.vsync_count = vsync_hz / (mode->vtotal * drm_mode_vrefresh(mode)); - /* enable external TE after kickoff to avoid premature autorefresh */ - tc_cfg.hw_vsync_mode = 0; - /* - * By setting sync_cfg_height to near max register value, we essentially - * disable dpu hw generated TE signal, since hw TE will arrive first. - * Only caveat is if due to error, we hit wrap-around. + * Set the sync_cfg_height to twice vtotal so that if we lose a + * TE event coming from the display TE pin we won't stall immediately */ - tc_cfg.sync_cfg_height = 0xFFF0; + tc_cfg.hw_vsync_mode = 1; + tc_cfg.sync_cfg_height = mode->vtotal * 2; tc_cfg.vsync_init_val = mode->vdisplay; tc_cfg.sync_threshold_start = DEFAULT_TEARCHECK_SYNC_THRESH_START; tc_cfg.sync_threshold_continue = DEFAULT_TEARCHECK_SYNC_THRESH_CONTINUE; @@ -580,6 +581,69 @@ static void dpu_encoder_phys_cmd_prepare_for_kickoff( atomic_read(&phys_enc->pending_kickoff_cnt)); } +static bool dpu_encoder_phys_cmd_is_ongoing_pptx( + struct dpu_encoder_phys *phys_enc) +{ + struct dpu_hw_pp_vsync_info info; + + if (!phys_enc) + return false; + + phys_enc->hw_pp->ops.get_vsync_info(phys_enc->hw_pp, &info); + if (info.wr_ptr_line_count > 0 && + info.wr_ptr_line_count < phys_enc->cached_mode.vdisplay) + return true; + + return false; +} + +static void dpu_encoder_phys_cmd_prepare_commit( + struct dpu_encoder_phys *phys_enc) +{ + struct dpu_encoder_phys_cmd *cmd_enc = + to_dpu_encoder_phys_cmd(phys_enc); + int trial = 0; + + if (!phys_enc) + return; + if (!phys_enc->hw_pp) + return; + if (!dpu_encoder_phys_cmd_is_master(phys_enc)) + return; + + /* If autorefresh is already disabled, we have nothing to do */ + if (!phys_enc->hw_pp->ops.get_autorefresh(phys_enc->hw_pp, NULL)) + return; + + /* + * If autorefresh is enabled, disable it and make sure it is safe to + * proceed with current frame commit/push. Sequence fallowed is, + * 1. Disable TE + * 2. Disable autorefresh config + * 4. Poll for frame transfer ongoing to be false + * 5. Enable TE back + */ + _dpu_encoder_phys_cmd_connect_te(phys_enc, false); + phys_enc->hw_pp->ops.setup_autorefresh(phys_enc->hw_pp, 0, false); + + do { + udelay(DPU_ENC_MAX_POLL_TIMEOUT_US); + if ((trial * DPU_ENC_MAX_POLL_TIMEOUT_US) + > (KICKOFF_TIMEOUT_MS * USEC_PER_MSEC)) { + DPU_ERROR_CMDENC(cmd_enc, + "disable autorefresh failed\n"); + break; + } + + trial++; + } while (dpu_encoder_phys_cmd_is_ongoing_pptx(phys_enc)); + + _dpu_encoder_phys_cmd_connect_te(phys_enc, true); + + DPU_DEBUG_CMDENC(to_dpu_encoder_phys_cmd(phys_enc), + "disabled autorefresh\n"); +} + static int _dpu_encoder_phys_cmd_wait_for_ctl_start( struct dpu_encoder_phys *phys_enc) { @@ -621,20 +685,15 @@ static int dpu_encoder_phys_cmd_wait_for_tx_complete( static int dpu_encoder_phys_cmd_wait_for_commit_done( struct dpu_encoder_phys *phys_enc) { - int rc = 0; struct dpu_encoder_phys_cmd *cmd_enc; cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); /* only required for master controller */ - if (dpu_encoder_phys_cmd_is_master(phys_enc)) - rc = _dpu_encoder_phys_cmd_wait_for_ctl_start(phys_enc); - - /* required for both controllers */ - if (!rc && cmd_enc->serialize_wait4pp) - dpu_encoder_phys_cmd_prepare_for_kickoff(phys_enc); + if (!dpu_encoder_phys_cmd_is_master(phys_enc)) + return 0; - return rc; + return _dpu_encoder_phys_cmd_wait_for_ctl_start(phys_enc); } static int dpu_encoder_phys_cmd_wait_for_vblank( @@ -681,6 +740,7 @@ static void dpu_encoder_phys_cmd_trigger_start( static void dpu_encoder_phys_cmd_init_ops( struct dpu_encoder_phys_ops *ops) { + ops->prepare_commit = dpu_encoder_phys_cmd_prepare_commit; ops->is_master = dpu_encoder_phys_cmd_is_master; ops->mode_set = dpu_encoder_phys_cmd_mode_set; ops->mode_fixup = dpu_encoder_phys_cmd_mode_fixup; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 90393fe9e59c..189f3533525c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -12,14 +12,17 @@ #define VIG_MASK \ (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\ - BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_QOS_8LVL) |\ + BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) |\ BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT)) #define VIG_SDM845_MASK \ - (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3)) + (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3)) #define VIG_SC7180_MASK \ - (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED4)) + (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4)) + +#define VIG_SM8250_MASK \ + (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3LITE)) #define DMA_SDM845_MASK \ (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ @@ -185,7 +188,7 @@ static const struct dpu_caps sm8150_dpu_caps = { static const struct dpu_caps sm8250_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, - .qseed_type = DPU_SSPP_SCALER_QSEED3, /* TODO: qseed3 lite */ + .qseed_type = DPU_SSPP_SCALER_QSEED3LITE, .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_40, .has_src_split = true, @@ -444,6 +447,34 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = { sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), }; +static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 = + _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE); +static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 = + _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE); +static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 = + _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE); +static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 = + _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE); + +static const struct dpu_sspp_cfg sm8250_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK, + sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SM8250_MASK, + sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SM8250_MASK, + sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SM8250_MASK, + sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), +}; + /************************************************************* * MIXER sub blocks config *************************************************************/ @@ -532,23 +563,28 @@ static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = { .len = 0x90, .version = 0x40000}, }; -#define DSPP_BLK(_name, _id, _base, _sblk) \ +#define DSPP_BLK(_name, _id, _base, _mask, _sblk) \ {\ .name = _name, .id = _id, \ .base = _base, .len = 0x1800, \ - .features = DSPP_SC7180_MASK, \ + .features = _mask, \ .sblk = _sblk \ } static const struct dpu_dspp_cfg sc7180_dspp[] = { - DSPP_BLK("dspp_0", DSPP_0, 0x54000, &sc7180_dspp_sblk), + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, + &sc7180_dspp_sblk), }; static const struct dpu_dspp_cfg sm8150_dspp[] = { - DSPP_BLK("dspp_0", DSPP_0, 0x54000, &sm8150_dspp_sblk), - DSPP_BLK("dspp_1", DSPP_1, 0x56000, &sm8150_dspp_sblk), - DSPP_BLK("dspp_2", DSPP_2, 0x58000, &sm8150_dspp_sblk), - DSPP_BLK("dspp_3", DSPP_3, 0x5a000, &sm8150_dspp_sblk), + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), + DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), + DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), + DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), }; /************************************************************* @@ -624,33 +660,33 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { /************************************************************* * INTF sub blocks config *************************************************************/ -#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _features) \ +#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features) \ {\ .name = _name, .id = _id, \ .base = _base, .len = 0x280, \ .features = _features, \ .type = _type, \ .controller_id = _ctrl_id, \ - .prog_fetch_lines_worst_case = 24 \ + .prog_fetch_lines_worst_case = _progfetch \ } static const struct dpu_intf_cfg sdm845_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, INTF_SDM845_MASK), - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, INTF_SDM845_MASK), - INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, INTF_SDM845_MASK), - INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, INTF_SDM845_MASK), + INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK), + INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK), + INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK), + INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK), }; static const struct dpu_intf_cfg sc7180_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, INTF_SC7180_MASK), - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, INTF_SC7180_MASK), + INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK), + INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK), }; static const struct dpu_intf_cfg sm8150_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, INTF_SC7180_MASK), - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, INTF_SC7180_MASK), - INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, INTF_SC7180_MASK), - INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, INTF_SC7180_MASK), + INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK), + INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK), + INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK), + INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK), }; /************************************************************* @@ -969,9 +1005,8 @@ static void sm8250_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .mdp = sm8250_mdp, .ctl_count = ARRAY_SIZE(sm8150_ctl), .ctl = sm8150_ctl, - /* TODO: sspp qseed version differs from 845 */ - .sspp_count = ARRAY_SIZE(sdm845_sspp), - .sspp = sdm845_sspp, + .sspp_count = ARRAY_SIZE(sm8250_sspp), + .sspp = sm8250_sspp, .mixer_count = ARRAY_SIZE(sm8150_lm), .mixer = sm8150_lm, .dspp_count = ARRAY_SIZE(sm8150_dspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index eaef99db2d2f..ea4647d21a20 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -95,6 +95,7 @@ enum { * @DPU_SSPP_SRC Src and fetch part of the pipes, * @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support * @DPU_SSPP_SCALER_QSEED3, QSEED3 alogorithm support + * @DPU_SSPP_SCALER_QSEED3LITE, QSEED3 Lite alogorithm support * @DPU_SSPP_SCALER_QSEED4, QSEED4 algorithm support * @DPU_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes * @DPU_SSPP_CSC, Support of Color space converion @@ -114,6 +115,7 @@ enum { DPU_SSPP_SRC = 0x1, DPU_SSPP_SCALER_QSEED2, DPU_SSPP_SCALER_QSEED3, + DPU_SSPP_SCALER_QSEED3LITE, DPU_SSPP_SCALER_QSEED4, DPU_SSPP_SCALER_RGB, DPU_SSPP_CSC, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c index bea4ab5c58c5..245a7a62b5c6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c @@ -23,6 +23,7 @@ #define PP_WR_PTR_IRQ 0x024 #define PP_OUT_LINE_COUNT 0x028 #define PP_LINE_COUNT 0x02C +#define PP_AUTOREFRESH_CONFIG 0x030 #define PP_FBC_MODE 0x034 #define PP_FBC_BUDGET_CTL 0x038 @@ -120,6 +121,29 @@ static int dpu_hw_pp_setup_te_config(struct dpu_hw_pingpong *pp, return 0; } +static void dpu_hw_pp_setup_autorefresh_config(struct dpu_hw_pingpong *pp, + u32 frame_count, bool enable) +{ + DPU_REG_WRITE(&pp->hw, PP_AUTOREFRESH_CONFIG, + enable ? (BIT(31) | frame_count) : 0); +} + +/* + * dpu_hw_pp_get_autorefresh_config - Get autorefresh config from HW + * @pp: DPU pingpong structure + * @frame_count: Used to return the current frame count from hw + * + * Returns: True if autorefresh enabled, false if disabled. + */ +static bool dpu_hw_pp_get_autorefresh_config(struct dpu_hw_pingpong *pp, + u32 *frame_count) +{ + u32 val = DPU_REG_READ(&pp->hw, PP_AUTOREFRESH_CONFIG); + if (frame_count != NULL) + *frame_count = val & 0xffff; + return !!((val & BIT(31)) >> 31); +} + static int dpu_hw_pp_poll_timeout_wr_ptr(struct dpu_hw_pingpong *pp, u32 timeout_us) { @@ -228,6 +252,8 @@ static void _setup_pingpong_ops(struct dpu_hw_pingpong *c, c->ops.enable_tearcheck = dpu_hw_pp_enable_te; c->ops.connect_external_te = dpu_hw_pp_connect_external_te; c->ops.get_vsync_info = dpu_hw_pp_get_vsync_info; + c->ops.setup_autorefresh = dpu_hw_pp_setup_autorefresh_config; + c->ops.get_autorefresh = dpu_hw_pp_get_autorefresh_config; c->ops.poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr; c->ops.get_line_count = dpu_hw_pp_get_line_count; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h index 6902b9b95c8e..845b9ce80e31 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h @@ -63,6 +63,8 @@ struct dpu_hw_dither_cfg { * @setup_tearcheck : program tear check values * @enable_tearcheck : enables tear check * @get_vsync_info : retries timing info of the panel + * @setup_autorefresh : configure and enable the autorefresh config + * @get_autorefresh : retrieve autorefresh config from hardware * @setup_dither : function to program the dither hw block * @get_line_count: obtain current vertical line counter */ @@ -95,6 +97,18 @@ struct dpu_hw_pingpong_ops { struct dpu_hw_pp_vsync_info *info); /** + * configure and enable the autorefresh config + */ + void (*setup_autorefresh)(struct dpu_hw_pingpong *pp, + u32 frame_count, bool enable); + + /** + * retrieve autorefresh config from hardware + */ + bool (*get_autorefresh)(struct dpu_hw_pingpong *pp, + u32 *frame_count); + + /** * poll until write pointer transmission starts * @Return: 0 on success, -ETIMEDOUT on timeout */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 2c2ca5335aa8..34d81aa16041 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -673,6 +673,7 @@ static void _setup_layer_ops(struct dpu_hw_pipe *c, c->ops.setup_multirect = dpu_hw_sspp_setup_multirect; if (test_bit(DPU_SSPP_SCALER_QSEED3, &features) || + test_bit(DPU_SSPP_SCALER_QSEED3LITE, &features) || test_bit(DPU_SSPP_SCALER_QSEED4, &features)) { c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler3; c->ops.get_scaler_ver = _dpu_hw_sspp_get_scaler3_ver; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 85b018a9b03c..fdfd4b46e2c6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -28,6 +28,7 @@ struct dpu_hw_pipe; #define DPU_SSPP_SCALER ((1UL << DPU_SSPP_SCALER_RGB) | \ (1UL << DPU_SSPP_SCALER_QSEED2) | \ (1UL << DPU_SSPP_SCALER_QSEED3) | \ + (1UL << DPU_SSPP_SCALER_QSEED3LITE) | \ (1UL << DPU_SSPP_SCALER_QSEED4)) /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c index 84e9875994a8..f94584c982cd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c @@ -59,6 +59,19 @@ static u32 dpu_hw_util_log_mask = DPU_DBG_MASK_NONE; #define QSEED3_SEP_LUT_SIZE \ (QSEED3_LUT_SIZE * QSEED3_SEPARABLE_LUTS * sizeof(u32)) +/* DPU_SCALER_QSEED3LITE */ +#define QSEED3LITE_COEF_LUT_Y_SEP_BIT 4 +#define QSEED3LITE_COEF_LUT_UV_SEP_BIT 5 +#define QSEED3LITE_COEF_LUT_CTRL 0x4C +#define QSEED3LITE_COEF_LUT_SWAP_BIT 0 +#define QSEED3LITE_DIR_FILTER_WEIGHT 0x60 +#define QSEED3LITE_FILTERS 2 +#define QSEED3LITE_SEPARABLE_LUTS 10 +#define QSEED3LITE_LUT_SIZE 33 +#define QSEED3LITE_SEP_LUT_SIZE \ + (QSEED3LITE_LUT_SIZE * QSEED3LITE_SEPARABLE_LUTS * sizeof(u32)) + + void dpu_reg_write(struct dpu_hw_blk_reg_map *c, u32 reg_off, u32 val, @@ -156,6 +169,57 @@ static void _dpu_hw_setup_scaler3_lut(struct dpu_hw_blk_reg_map *c, } +static void _dpu_hw_setup_scaler3lite_lut(struct dpu_hw_blk_reg_map *c, + struct dpu_hw_scaler3_cfg *scaler3_cfg, u32 offset) +{ + int j, filter; + int config_lut = 0x0; + unsigned long lut_flags; + u32 lut_addr, lut_offset; + u32 *lut[QSEED3LITE_FILTERS] = {NULL, NULL}; + static const uint32_t off_tbl[QSEED3_FILTERS] = { 0x000, 0x200 }; + + DPU_REG_WRITE(c, QSEED3LITE_DIR_FILTER_WEIGHT + offset, scaler3_cfg->dir_weight); + + if (!scaler3_cfg->sep_lut) + return; + + lut_flags = (unsigned long) scaler3_cfg->lut_flag; + if (test_bit(QSEED3_COEF_LUT_Y_SEP_BIT, &lut_flags) && + (scaler3_cfg->y_rgb_sep_lut_idx < QSEED3LITE_SEPARABLE_LUTS) && + (scaler3_cfg->sep_len == QSEED3LITE_SEP_LUT_SIZE)) { + lut[0] = scaler3_cfg->sep_lut + + scaler3_cfg->y_rgb_sep_lut_idx * QSEED3LITE_LUT_SIZE; + config_lut = 1; + } + if (test_bit(QSEED3_COEF_LUT_UV_SEP_BIT, &lut_flags) && + (scaler3_cfg->uv_sep_lut_idx < QSEED3LITE_SEPARABLE_LUTS) && + (scaler3_cfg->sep_len == QSEED3LITE_SEP_LUT_SIZE)) { + lut[1] = scaler3_cfg->sep_lut + + scaler3_cfg->uv_sep_lut_idx * QSEED3LITE_LUT_SIZE; + config_lut = 1; + } + + if (config_lut) { + for (filter = 0; filter < QSEED3LITE_FILTERS; filter++) { + if (!lut[filter]) + continue; + lut_offset = 0; + lut_addr = QSEED3_COEF_LUT + offset + off_tbl[filter]; + for (j = 0; j < QSEED3LITE_LUT_SIZE; j++) { + DPU_REG_WRITE(c, + lut_addr, + (lut[filter])[lut_offset++]); + lut_addr += 4; + } + } + } + + if (test_bit(QSEED3_COEF_LUT_SWAP_BIT, &lut_flags)) + DPU_REG_WRITE(c, QSEED3_COEF_LUT_CTRL + offset, BIT(0)); + +} + static void _dpu_hw_setup_scaler3_de(struct dpu_hw_blk_reg_map *c, struct dpu_hw_scaler3_de_cfg *de_cfg, u32 offset) { @@ -242,9 +306,12 @@ void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c, op_mode |= BIT(8); } - if (scaler3_cfg->lut_flag) - _dpu_hw_setup_scaler3_lut(c, scaler3_cfg, - scaler_offset); + if (scaler3_cfg->lut_flag) { + if (scaler_version < 0x2004) + _dpu_hw_setup_scaler3_lut(c, scaler3_cfg, scaler_offset); + else + _dpu_hw_setup_scaler3lite_lut(c, scaler3_cfg, scaler_offset); + } if (scaler_version == 0x1002) { phase_init = diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h index 234eb7d65753..ff3cffde84cd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h @@ -97,6 +97,7 @@ struct dpu_hw_scaler3_de_cfg { * @ cir_lut: pointer to circular filter LUT * @ sep_lut: pointer to separable filter LUT * @ de: detail enhancer configuration + * @ dir_weight: Directional weight */ struct dpu_hw_scaler3_cfg { u32 enable; @@ -137,6 +138,8 @@ struct dpu_hw_scaler3_cfg { * Detail enhancer settings */ struct dpu_hw_scaler3_de_cfg de; + + u32 dir_weight; }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c index cf867f3f7c36..b757054e1c23 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c @@ -30,7 +30,7 @@ #define VBIF_XIN_HALT_CTRL0 0x0200 #define VBIF_XIN_HALT_CTRL1 0x0204 #define VBIF_XINL_QOS_RP_REMAP_000 0x0550 -#define VBIF_XINL_QOS_LVL_REMAP_000 0x0590 +#define VBIF_XINL_QOS_LVL_REMAP_000(v) (v < DPU_HW_VER_400 ? 0x570 : 0x0590) static void dpu_hw_clear_errors(struct dpu_hw_vbif *vbif, u32 *pnd_errors, u32 *src_errors) @@ -156,18 +156,19 @@ static void dpu_hw_set_qos_remap(struct dpu_hw_vbif *vbif, u32 xin_id, u32 level, u32 remap_level) { struct dpu_hw_blk_reg_map *c; - u32 reg_val, reg_val_lvl, mask, reg_high, reg_shift; + u32 reg_lvl, reg_val, reg_val_lvl, mask, reg_high, reg_shift; if (!vbif) return; c = &vbif->hw; + reg_lvl = VBIF_XINL_QOS_LVL_REMAP_000(c->hwversion); reg_high = ((xin_id & 0x8) >> 3) * 4 + (level * 8); reg_shift = (xin_id & 0x7) * 4; reg_val = DPU_REG_READ(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high); - reg_val_lvl = DPU_REG_READ(c, VBIF_XINL_QOS_LVL_REMAP_000 + reg_high); + reg_val_lvl = DPU_REG_READ(c, reg_lvl + reg_high); mask = 0x7 << reg_shift; @@ -178,7 +179,7 @@ static void dpu_hw_set_qos_remap(struct dpu_hw_vbif *vbif, reg_val_lvl |= (remap_level << reg_shift) & mask; DPU_REG_WRITE(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high, reg_val); - DPU_REG_WRITE(c, VBIF_XINL_QOS_LVL_REMAP_000 + reg_high, reg_val_lvl); + DPU_REG_WRITE(c, reg_lvl + reg_high, reg_val_lvl); } static void dpu_hw_set_write_gather_en(struct dpu_hw_vbif *vbif, u32 xin_id) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 374b0e8471e6..5a8e3e1fc48c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -749,7 +749,7 @@ static void _dpu_kms_set_encoder_mode(struct msm_kms *kms, case DRM_MODE_ENCODER_TMDS: info.num_of_h_tiles = 1; break; - }; + } rc = dpu_encoder_setup(encoder->dev, encoder, &info); if (rc) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index bc0231a50132..f898a8f67b7f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -1465,6 +1465,7 @@ static int _dpu_plane_init_debugfs(struct drm_plane *plane) pdpu->debugfs_root, &pdpu->debugfs_src); if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) || + cfg->features & BIT(DPU_SSPP_SCALER_QSEED3LITE) || cfg->features & BIT(DPU_SSPP_SCALER_QSEED2) || cfg->features & BIT(DPU_SSPP_SCALER_QSEED4)) { dpu_debugfs_setup_regset32(&pdpu->debugfs_scaler, diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c index df10c1ac7591..94ce62a26daf 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c @@ -177,7 +177,7 @@ static const struct mdp5_cfg_hw msm8x74v2_config = { [3] = INTF_HDMI, }, }, - .max_clk = 200000000, + .max_clk = 320000000, }; static const struct mdp5_cfg_hw apq8084_config = { diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c index 0c8f9f88301f..f5d71b274079 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c @@ -1180,7 +1180,7 @@ static void mdp5_crtc_pp_done_irq(struct mdp_irq *irq, uint32_t irqstatus) struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, pp_done); - complete(&mdp5_crtc->pp_completion); + complete_all(&mdp5_crtc->pp_completion); } static void mdp5_crtc_wait_for_pp_done(struct drm_crtc *crtc) diff --git a/drivers/gpu/drm/msm/dp/dp_aux.c b/drivers/gpu/drm/msm/dp/dp_aux.c index 19b35ae3e927..1c6e1d2b947c 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.c +++ b/drivers/gpu/drm/msm/dp/dp_aux.c @@ -336,7 +336,6 @@ static ssize_t dp_aux_transfer(struct drm_dp_aux *dp_aux, ssize_t ret; int const aux_cmd_native_max = 16; int const aux_cmd_i2c_max = 128; - int const retry_count = 5; struct dp_aux_private *aux = container_of(dp_aux, struct dp_aux_private, dp_aux); @@ -378,12 +377,6 @@ static ssize_t dp_aux_transfer(struct drm_dp_aux *dp_aux, ret = dp_aux_cmd_fifo_tx(aux, msg); if (ret < 0) { - if (aux->native) { - aux->retry_cnt++; - if (!(aux->retry_cnt % retry_count)) - dp_catalog_aux_update_cfg(aux->catalog); - dp_catalog_aux_reset(aux->catalog); - } usleep_range(400, 500); /* at least 400us to next try */ goto unlock_exit; } diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index 44f0c57798d0..b1a9b1b98f5f 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -190,6 +190,18 @@ int dp_catalog_aux_clear_hw_interrupts(struct dp_catalog *dp_catalog) return 0; } +/** + * dp_catalog_aux_reset() - reset AUX controller + * + * @aux: DP catalog structure + * + * return: void + * + * This function reset AUX controller + * + * NOTE: reset AUX controller will also clear any pending HPD related interrupts + * + */ void dp_catalog_aux_reset(struct dp_catalog *dp_catalog) { u32 aux_ctrl; @@ -483,6 +495,18 @@ int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog, return 0; } +/** + * dp_catalog_ctrl_reset() - reset DP controller + * + * @dp_catalog: DP catalog structure + * + * return: void + * + * This function reset the DP controller + * + * NOTE: reset DP controller will also clear any pending HPD related interrupts + * + */ void dp_catalog_ctrl_reset(struct dp_catalog *dp_catalog) { u32 sw_reset; diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 36b39c381b3f..1390f3547fde 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -631,7 +631,7 @@ static void _dp_ctrl_calc_tu(struct dp_tu_calc_input *in, tu = kzalloc(sizeof(*tu), GFP_KERNEL); if (!tu) - return + return; dp_panel_update_tu_timings(in, tu); @@ -1158,7 +1158,7 @@ static int dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl) default: ret = -EINVAL; break; - }; + } if (!ret) DRM_DEBUG_DP("new rate=0x%x\n", ctrl->link->link_params.rate); @@ -1296,7 +1296,6 @@ static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl, * transitioned to PUSH_IDLE. In order to start transmitting * a link training pattern, we have to first do soft reset. */ - dp_catalog_ctrl_reset(ctrl->catalog); ret = dp_ctrl_link_train(ctrl, cr, training_step); @@ -1365,7 +1364,7 @@ static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl) return ret; } -int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip) +int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip, bool reset) { struct dp_ctrl_private *ctrl; struct dp_io *dp_io; @@ -1382,6 +1381,9 @@ int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip) ctrl->dp_ctrl.orientation = flip; + if (reset) + dp_catalog_ctrl_reset(ctrl->catalog); + dp_catalog_ctrl_phy_reset(ctrl->catalog); phy_init(phy); dp_catalog_ctrl_enable_irq(ctrl->catalog, true); @@ -1496,7 +1498,6 @@ static int dp_ctrl_link_maintenance(struct dp_ctrl_private *ctrl) int training_step = DP_TRAINING_NONE; dp_ctrl_push_idle(&ctrl->dp_ctrl); - dp_catalog_ctrl_reset(ctrl->catalog); ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; @@ -1785,14 +1786,14 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl) * Set up transfer unit values and set controller state to send * video. */ + reinit_completion(&ctrl->video_comp); + dp_ctrl_configure_source_params(ctrl); dp_catalog_ctrl_config_msa(ctrl->catalog, ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate, dp_ctrl_use_fixed_nvid(ctrl)); - reinit_completion(&ctrl->video_comp); - dp_ctrl_setup_tr_unit(ctrl); dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h index f60ba93c8678..a836bd358447 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -19,7 +19,7 @@ struct dp_ctrl { u32 pixel_rate; }; -int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip); +int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip, bool reset); void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl); int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl); int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 3bc7ed21de28..5a39da6e1eaf 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -350,7 +350,7 @@ end: return rc; } -static void dp_display_host_init(struct dp_display_private *dp) +static void dp_display_host_init(struct dp_display_private *dp, int reset) { bool flip = false; @@ -365,7 +365,7 @@ static void dp_display_host_init(struct dp_display_private *dp) dp_display_set_encoder_mode(dp); dp_power_init(dp->power, flip); - dp_ctrl_host_init(dp->ctrl, flip); + dp_ctrl_host_init(dp->ctrl, flip, reset); dp_aux_init(dp->aux); dp->core_initialized = true; } @@ -403,7 +403,7 @@ static int dp_display_usbpd_configure_cb(struct device *dev) goto end; } - dp_display_host_init(dp); + dp_display_host_init(dp, false); /* * set sink to normal operation mode -- D0 @@ -651,8 +651,8 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data) dp_add_event(dp, EV_DISCONNECT_PENDING_TIMEOUT, 0, DP_TIMEOUT_5_SECOND); /* signal the disconnect event early to ensure proper teardown */ - dp_display_handle_plugged_change(g_dp_display, false); reinit_completion(&dp->audio_comp); + dp_display_handle_plugged_change(g_dp_display, false); dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK | DP_DP_IRQ_HPD_INT_MASK, true); @@ -700,6 +700,13 @@ static int dp_irq_hpd_handle(struct dp_display_private *dp, u32 data) return 0; } + if (state == ST_CONNECT_PENDING || state == ST_DISCONNECT_PENDING) { + /* wait until ST_CONNECTED */ + dp_add_event(dp, EV_IRQ_HPD_INT, 0, 1); /* delay = 1 */ + mutex_unlock(&dp->event_mutex); + return 0; + } + ret = dp_display_usbpd_attention_cb(&dp->pdev->dev); if (ret == -ECONNRESET) { /* cable unplugged */ dp->core_initialized = false; @@ -890,6 +897,9 @@ static int dp_display_disable(struct dp_display_private *dp, u32 data) /* wait only if audio was enabled */ if (dp_display->audio_enabled) { + /* signal the disconnect event */ + reinit_completion(&dp->audio_comp); + dp_display_handle_plugged_change(dp_display, false); if (!wait_for_completion_timeout(&dp->audio_comp, HZ * 5)) DRM_ERROR("audio comp timeout\n"); @@ -1002,7 +1012,7 @@ int dp_display_get_test_bpp(struct msm_dp *dp) static void dp_display_config_hpd(struct dp_display_private *dp) { - dp_display_host_init(dp); + dp_display_host_init(dp, true); dp_catalog_ctrl_hpd_config(dp->catalog); /* Enable interrupt first time @@ -1256,7 +1266,7 @@ static int dp_pm_resume(struct device *dev) dp->hpd_state = ST_DISCONNECTED; /* turn on dp ctrl/phy */ - dp_display_host_init(dp); + dp_display_host_init(dp, true); dp_catalog_ctrl_hpd_config(dp->catalog); @@ -1439,7 +1449,7 @@ int msm_dp_display_enable(struct msm_dp *dp, struct drm_encoder *encoder) state = dp_display->hpd_state; if (state == ST_DISPLAY_OFF) - dp_display_host_init(dp_display); + dp_display_host_init(dp_display, true); dp_display_enable(dp_display, 0); diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index d1780bcac8cc..9cc816663668 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -409,7 +409,6 @@ int dp_panel_timing_cfg(struct dp_panel *dp_panel) int dp_panel_init_panel_info(struct dp_panel *dp_panel) { - int rc = 0; struct drm_display_mode *drm_mode; drm_mode = &dp_panel->dp_mode.drm_mode; @@ -436,7 +435,7 @@ int dp_panel_init_panel_info(struct dp_panel *dp_panel) min_t(u32, dp_panel->dp_mode.bpp, 30)); DRM_DEBUG_DP("updated bpp = %d\n", dp_panel->dp_mode.bpp); - return rc; + return 0; } struct dp_panel *dp_panel_get(struct dp_panel_in *in) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c index 1afb7c579dbb..eca86bf448f7 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c @@ -139,7 +139,7 @@ const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = { .disable = dsi_20nm_phy_disable, .init = msm_dsi_phy_init_common, }, - .io_start = { 0xfd998300, 0xfd9a0300 }, + .io_start = { 0xfd998500, 0xfd9a0500 }, .num_dsi_phy = 2, }; diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c index e4e9bf04b736..de3b802ccd3d 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c @@ -172,9 +172,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_10nm *pll) multiplier = 1 << config->frac_bits; dec_multiple = div_u64(pll_freq * multiplier, divider); - div_u64_rem(dec_multiple, multiplier, &frac); - - dec = div_u64(dec_multiple, multiplier); + dec = div_u64_rem(dec_multiple, multiplier, &frac); if (pll_freq <= 1900000000UL) regs->pll_prop_gain_rate = 8; @@ -306,7 +304,8 @@ static void dsi_pll_commit(struct dsi_pll_10nm *pll) reg->frac_div_start_mid); pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1, reg->frac_div_start_high); - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40); + pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1, + reg->pll_lockdet_rate); pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY, 0x06); pll_write(base + REG_DSI_10nm_PHY_PLL_CMODE, 0x10); pll_write(base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS, @@ -345,6 +344,7 @@ static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll) { + struct device *dev = &pll->pdev->dev; int rc; u32 status = 0; u32 const delay_us = 100; @@ -357,8 +357,8 @@ static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll) delay_us, timeout_us); if (rc) - pr_err("DSI PLL(%d) lock failed, status=0x%08x\n", - pll->id, status); + DRM_DEV_ERROR(dev, "DSI PLL(%d) lock failed, status=0x%08x\n", + pll->id, status); return rc; } @@ -405,6 +405,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw) { struct msm_dsi_pll *pll = hw_clk_to_pll(hw); struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); + struct device *dev = &pll_10nm->pdev->dev; int rc; dsi_pll_enable_pll_bias(pll_10nm); @@ -413,7 +414,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw) rc = dsi_pll_10nm_vco_set_rate(hw,pll_10nm->vco_current_rate, 0); if (rc) { - pr_err("vco_set_rate failed, rc=%d\n", rc); + DRM_DEV_ERROR(dev, "vco_set_rate failed, rc=%d\n", rc); return rc; } @@ -430,7 +431,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw) /* Check for PLL lock */ rc = dsi_pll_10nm_lock_status(pll_10nm); if (rc) { - pr_err("PLL(%d) lock failed\n", pll_10nm->id); + DRM_DEV_ERROR(dev, "PLL(%d) lock failed\n", pll_10nm->id); goto error; } @@ -483,6 +484,7 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw, { struct msm_dsi_pll *pll = hw_clk_to_pll(hw); struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); + struct dsi_pll_config *config = &pll_10nm->pll_configuration; void __iomem *base = pll_10nm->mmio; u64 ref_clk = pll_10nm->vco_ref_clk_rate; u64 vco_rate = 0x0; @@ -503,9 +505,8 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw, /* * TODO: * 1. Assumes prescaler is disabled - * 2. Multiplier is 2^18. it should be 2^(num_of_frac_bits) */ - multiplier = 1 << 18; + multiplier = 1 << config->frac_bits; pll_freq = dec * (ref_clk * 2); tmp64 = (ref_clk * 2 * frac); pll_freq += div_u64(tmp64, multiplier); diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 108c405e03dd..94525ac76d4e 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -788,9 +788,10 @@ static int msm_ioctl_gem_info_iova(struct drm_device *dev, struct drm_file *file, struct drm_gem_object *obj, uint64_t *iova) { + struct msm_drm_private *priv = dev->dev_private; struct msm_file_private *ctx = file->driver_priv; - if (!ctx->aspace) + if (!priv->gpu) return -EINVAL; /* diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index a588b0388d27..f091c1e164fa 100644 --- a/drivers/gpu/drm/msm/msm_gem.c +++ b/drivers/gpu/drm/msm/msm_gem.c @@ -987,8 +987,7 @@ void msm_gem_free_object(struct drm_gem_object *obj) /* Don't drop the pages for imported dmabuf, as they are not * ours, just free the array we allocated: */ - if (msm_obj->pages) - kvfree(msm_obj->pages); + kvfree(msm_obj->pages); put_iova_vmas(obj); diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c index d04c349d8112..5480852bdeda 100644 --- a/drivers/gpu/drm/msm/msm_gem_submit.c +++ b/drivers/gpu/drm/msm/msm_gem_submit.c @@ -198,6 +198,8 @@ static int submit_lookup_cmds(struct msm_gem_submit *submit, submit->cmd[i].idx = submit_cmd.submit_idx; submit->cmd[i].nr_relocs = submit_cmd.nr_relocs; + userptr = u64_to_user_ptr(submit_cmd.relocs); + sz = array_size(submit_cmd.nr_relocs, sizeof(struct drm_msm_gem_submit_reloc)); /* check for overflow: */ diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h index d8151a89e163..4735251a394d 100644 --- a/drivers/gpu/drm/msm/msm_kms.h +++ b/drivers/gpu/drm/msm/msm_kms.h @@ -157,6 +157,7 @@ struct msm_kms { * from the crtc's pending_timer close to end of the frame: */ struct mutex commit_lock[MAX_CRTCS]; + struct lock_class_key commit_lock_keys[MAX_CRTCS]; unsigned pending_crtc_mask; struct msm_pending_timer pending_timers[MAX_CRTCS]; }; @@ -166,8 +167,11 @@ static inline int msm_kms_init(struct msm_kms *kms, { unsigned i, ret; - for (i = 0; i < ARRAY_SIZE(kms->commit_lock); i++) - mutex_init(&kms->commit_lock[i]); + for (i = 0; i < ARRAY_SIZE(kms->commit_lock); i++) { + lockdep_register_key(&kms->commit_lock_keys[i]); + __mutex_init(&kms->commit_lock[i], "&kms->commit_lock[i]", + &kms->commit_lock_keys[i]); + } kms->funcs = funcs; diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl0080.h b/drivers/gpu/drm/nouveau/include/nvif/cl0080.h index 57d4f457a7d4..0b86c44878e0 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl0080.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl0080.h @@ -60,37 +60,33 @@ struct nv_device_time_v0 { #define NV_DEVICE_INFO_UNIT (0xffffffffULL << 32) #define NV_DEVICE_INFO(n) ((n) | (0x00000000ULL << 32)) -#define NV_DEVICE_FIFO(n) ((n) | (0x00000001ULL << 32)) +#define NV_DEVICE_HOST(n) ((n) | (0x00000001ULL << 32)) -/* This will be returned for unsupported queries. */ +/* This will be returned in the mthd field for unsupported queries. */ #define NV_DEVICE_INFO_INVALID ~0ULL -/* These return a mask of available engines of particular type. */ -#define NV_DEVICE_INFO_ENGINE_SW NV_DEVICE_INFO(0x00000000) -#define NV_DEVICE_INFO_ENGINE_GR NV_DEVICE_INFO(0x00000001) -#define NV_DEVICE_INFO_ENGINE_MPEG NV_DEVICE_INFO(0x00000002) -#define NV_DEVICE_INFO_ENGINE_ME NV_DEVICE_INFO(0x00000003) -#define NV_DEVICE_INFO_ENGINE_CIPHER NV_DEVICE_INFO(0x00000004) -#define NV_DEVICE_INFO_ENGINE_BSP NV_DEVICE_INFO(0x00000005) -#define NV_DEVICE_INFO_ENGINE_VP NV_DEVICE_INFO(0x00000006) -#define NV_DEVICE_INFO_ENGINE_CE NV_DEVICE_INFO(0x00000007) -#define NV_DEVICE_INFO_ENGINE_SEC NV_DEVICE_INFO(0x00000008) -#define NV_DEVICE_INFO_ENGINE_MSVLD NV_DEVICE_INFO(0x00000009) -#define NV_DEVICE_INFO_ENGINE_MSPDEC NV_DEVICE_INFO(0x0000000a) -#define NV_DEVICE_INFO_ENGINE_MSPPP NV_DEVICE_INFO(0x0000000b) -#define NV_DEVICE_INFO_ENGINE_MSENC NV_DEVICE_INFO(0x0000000c) -#define NV_DEVICE_INFO_ENGINE_VIC NV_DEVICE_INFO(0x0000000d) -#define NV_DEVICE_INFO_ENGINE_SEC2 NV_DEVICE_INFO(0x0000000e) -#define NV_DEVICE_INFO_ENGINE_NVDEC NV_DEVICE_INFO(0x0000000f) -#define NV_DEVICE_INFO_ENGINE_NVENC NV_DEVICE_INFO(0x00000010) - +/* Returns the number of available runlists. */ +#define NV_DEVICE_HOST_RUNLISTS NV_DEVICE_HOST(0x00000000) /* Returns the number of available channels. */ -#define NV_DEVICE_FIFO_CHANNELS NV_DEVICE_FIFO(0x00000000) - -/* Returns a mask of available runlists. */ -#define NV_DEVICE_FIFO_RUNLISTS NV_DEVICE_FIFO(0x00000001) +#define NV_DEVICE_HOST_CHANNELS NV_DEVICE_HOST(0x00000001) -/* These return a mask of engines available on a particular runlist. */ -#define NV_DEVICE_FIFO_RUNLIST_ENGINES(n) ((n) + NV_DEVICE_FIFO(0x00000010)) -#define NV_DEVICE_FIFO_RUNLIST_ENGINES__SIZE 64 +/* Returns a mask of available engine types on runlist(data). */ +#define NV_DEVICE_HOST_RUNLIST_ENGINES NV_DEVICE_HOST(0x00000100) +#define NV_DEVICE_HOST_RUNLIST_ENGINES_SW 0x00000001 +#define NV_DEVICE_HOST_RUNLIST_ENGINES_GR 0x00000002 +#define NV_DEVICE_HOST_RUNLIST_ENGINES_MPEG 0x00000004 +#define NV_DEVICE_HOST_RUNLIST_ENGINES_ME 0x00000008 +#define NV_DEVICE_HOST_RUNLIST_ENGINES_CIPHER 0x00000010 +#define NV_DEVICE_HOST_RUNLIST_ENGINES_BSP 0x00000020 +#define NV_DEVICE_HOST_RUNLIST_ENGINES_VP 0x00000040 +#define NV_DEVICE_HOST_RUNLIST_ENGINES_CE 0x00000080 +#define NV_DEVICE_HOST_RUNLIST_ENGINES_SEC 0x00000100 +#define NV_DEVICE_HOST_RUNLIST_ENGINES_MSVLD 0x00000200 +#define NV_DEVICE_HOST_RUNLIST_ENGINES_MSPDEC 0x00000400 +#define NV_DEVICE_HOST_RUNLIST_ENGINES_MSPPP 0x00000800 +#define NV_DEVICE_HOST_RUNLIST_ENGINES_MSENC 0x00001000 +#define NV_DEVICE_HOST_RUNLIST_ENGINES_VIC 0x00002000 +#define NV_DEVICE_HOST_RUNLIST_ENGINES_SEC2 0x00004000 +#define NV_DEVICE_HOST_RUNLIST_ENGINES_NVDEC 0x00008000 +#define NV_DEVICE_HOST_RUNLIST_ENGINES_NVENC 0x00010000 #endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/fifo.h b/drivers/gpu/drm/nouveau/include/nvif/fifo.h index e9468c9f9abf..d351ac890ca1 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/fifo.h +++ b/drivers/gpu/drm/nouveau/include/nvif/fifo.h @@ -2,15 +2,15 @@ #define __NVIF_FIFO_H__ #include <nvif/device.h> -/* Returns mask of runlists that support a NV_DEVICE_INFO_ENGINE_* type. */ +/* Returns mask of runlists that support a NV_DEVICE_INFO_RUNLIST_ENGINES_* type. */ u64 nvif_fifo_runlist(struct nvif_device *, u64 engine); /* CE-supporting runlists (excluding GRCE, if others exist). */ static inline u64 nvif_fifo_runlist_ce(struct nvif_device *device) { - u64 runmgr = nvif_fifo_runlist(device, NV_DEVICE_INFO_ENGINE_GR); - u64 runmce = nvif_fifo_runlist(device, NV_DEVICE_INFO_ENGINE_CE); + u64 runmgr = nvif_fifo_runlist(device, NV_DEVICE_HOST_RUNLIST_ENGINES_GR); + u64 runmce = nvif_fifo_runlist(device, NV_DEVICE_HOST_RUNLIST_ENGINES_CE); if (runmce && !(runmce &= ~runmgr)) runmce = runmgr; return runmce; diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h index c920939a1467..a18b6cfda07e 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h @@ -3,79 +3,7 @@ #define __NVKM_DEVICE_H__ #include <core/oclass.h> #include <core/event.h> - -enum nvkm_devidx { - NVKM_SUBDEV_PCI, - NVKM_SUBDEV_VBIOS, - NVKM_SUBDEV_DEVINIT, - NVKM_SUBDEV_TOP, - NVKM_SUBDEV_IBUS, - NVKM_SUBDEV_GPIO, - NVKM_SUBDEV_I2C, - NVKM_SUBDEV_FUSE, - NVKM_SUBDEV_MXM, - NVKM_SUBDEV_MC, - NVKM_SUBDEV_BUS, - NVKM_SUBDEV_TIMER, - NVKM_SUBDEV_INSTMEM, - NVKM_SUBDEV_FB, - NVKM_SUBDEV_LTC, - NVKM_SUBDEV_MMU, - NVKM_SUBDEV_BAR, - NVKM_SUBDEV_FAULT, - NVKM_SUBDEV_ACR, - NVKM_SUBDEV_PMU, - NVKM_SUBDEV_VOLT, - NVKM_SUBDEV_ICCSENSE, - NVKM_SUBDEV_THERM, - NVKM_SUBDEV_CLK, - NVKM_SUBDEV_GSP, - - NVKM_ENGINE_BSP, - - NVKM_ENGINE_CE0, - NVKM_ENGINE_CE1, - NVKM_ENGINE_CE2, - NVKM_ENGINE_CE3, - NVKM_ENGINE_CE4, - NVKM_ENGINE_CE5, - NVKM_ENGINE_CE6, - NVKM_ENGINE_CE7, - NVKM_ENGINE_CE8, - NVKM_ENGINE_CE_LAST = NVKM_ENGINE_CE8, - - NVKM_ENGINE_CIPHER, - NVKM_ENGINE_DISP, - NVKM_ENGINE_DMAOBJ, - NVKM_ENGINE_FIFO, - NVKM_ENGINE_GR, - NVKM_ENGINE_IFB, - NVKM_ENGINE_ME, - NVKM_ENGINE_MPEG, - NVKM_ENGINE_MSENC, - NVKM_ENGINE_MSPDEC, - NVKM_ENGINE_MSPPP, - NVKM_ENGINE_MSVLD, - - NVKM_ENGINE_NVENC0, - NVKM_ENGINE_NVENC1, - NVKM_ENGINE_NVENC2, - NVKM_ENGINE_NVENC_LAST = NVKM_ENGINE_NVENC2, - - NVKM_ENGINE_NVDEC0, - NVKM_ENGINE_NVDEC1, - NVKM_ENGINE_NVDEC2, - NVKM_ENGINE_NVDEC_LAST = NVKM_ENGINE_NVDEC2, - - NVKM_ENGINE_PM, - NVKM_ENGINE_SEC, - NVKM_ENGINE_SEC2, - NVKM_ENGINE_SW, - NVKM_ENGINE_VIC, - NVKM_ENGINE_VP, - - NVKM_SUBDEV_NR -}; +enum nvkm_subdev_type; enum nvkm_device_type { NVKM_DEVICE_PCI, @@ -102,7 +30,6 @@ struct nvkm_device { struct nvkm_event event; - u64 disable_mask; u32 debug; const struct nvkm_device_chip *chip; @@ -130,58 +57,16 @@ struct nvkm_device { struct notifier_block nb; } acpi; - struct nvkm_acr *acr; - struct nvkm_bar *bar; - struct nvkm_bios *bios; - struct nvkm_bus *bus; - struct nvkm_clk *clk; - struct nvkm_devinit *devinit; - struct nvkm_fault *fault; - struct nvkm_fb *fb; - struct nvkm_fuse *fuse; - struct nvkm_gpio *gpio; - struct nvkm_gsp *gsp; - struct nvkm_i2c *i2c; - struct nvkm_subdev *ibus; - struct nvkm_iccsense *iccsense; - struct nvkm_instmem *imem; - struct nvkm_ltc *ltc; - struct nvkm_mc *mc; - struct nvkm_mmu *mmu; - struct nvkm_subdev *mxm; - struct nvkm_pci *pci; - struct nvkm_pmu *pmu; - struct nvkm_therm *therm; - struct nvkm_timer *timer; - struct nvkm_top *top; - struct nvkm_volt *volt; - - struct nvkm_engine *bsp; - struct nvkm_engine *ce[9]; - struct nvkm_engine *cipher; - struct nvkm_disp *disp; - struct nvkm_dma *dma; - struct nvkm_fifo *fifo; - struct nvkm_gr *gr; - struct nvkm_engine *ifb; - struct nvkm_engine *me; - struct nvkm_engine *mpeg; - struct nvkm_engine *msenc; - struct nvkm_engine *mspdec; - struct nvkm_engine *msppp; - struct nvkm_engine *msvld; - struct nvkm_nvenc *nvenc[3]; - struct nvkm_nvdec *nvdec[3]; - struct nvkm_pm *pm; - struct nvkm_engine *sec; - struct nvkm_sec2 *sec2; - struct nvkm_sw *sw; - struct nvkm_engine *vic; - struct nvkm_engine *vp; +#define NVKM_LAYOUT_ONCE(type,data,ptr) data *ptr; +#define NVKM_LAYOUT_INST(type,data,ptr,cnt) data *ptr[cnt]; +#include <core/layout.h> +#undef NVKM_LAYOUT_INST +#undef NVKM_LAYOUT_ONCE + struct list_head subdev; }; -struct nvkm_subdev *nvkm_device_subdev(struct nvkm_device *, int index); -struct nvkm_engine *nvkm_device_engine(struct nvkm_device *, int index); +struct nvkm_subdev *nvkm_device_subdev(struct nvkm_device *, int type, int inst); +struct nvkm_engine *nvkm_device_engine(struct nvkm_device *, int type, int inst); struct nvkm_device_func { struct nvkm_device_pci *(*pci)(struct nvkm_device *); @@ -202,55 +87,15 @@ struct nvkm_device_quirk { struct nvkm_device_chip { const char *name; - - int (*acr )(struct nvkm_device *, int idx, struct nvkm_acr **); - int (*bar )(struct nvkm_device *, int idx, struct nvkm_bar **); - int (*bios )(struct nvkm_device *, int idx, struct nvkm_bios **); - int (*bus )(struct nvkm_device *, int idx, struct nvkm_bus **); - int (*clk )(struct nvkm_device *, int idx, struct nvkm_clk **); - int (*devinit )(struct nvkm_device *, int idx, struct nvkm_devinit **); - int (*fault )(struct nvkm_device *, int idx, struct nvkm_fault **); - int (*fb )(struct nvkm_device *, int idx, struct nvkm_fb **); - int (*fuse )(struct nvkm_device *, int idx, struct nvkm_fuse **); - int (*gpio )(struct nvkm_device *, int idx, struct nvkm_gpio **); - int (*gsp )(struct nvkm_device *, int idx, struct nvkm_gsp **); - int (*i2c )(struct nvkm_device *, int idx, struct nvkm_i2c **); - int (*ibus )(struct nvkm_device *, int idx, struct nvkm_subdev **); - int (*iccsense)(struct nvkm_device *, int idx, struct nvkm_iccsense **); - int (*imem )(struct nvkm_device *, int idx, struct nvkm_instmem **); - int (*ltc )(struct nvkm_device *, int idx, struct nvkm_ltc **); - int (*mc )(struct nvkm_device *, int idx, struct nvkm_mc **); - int (*mmu )(struct nvkm_device *, int idx, struct nvkm_mmu **); - int (*mxm )(struct nvkm_device *, int idx, struct nvkm_subdev **); - int (*pci )(struct nvkm_device *, int idx, struct nvkm_pci **); - int (*pmu )(struct nvkm_device *, int idx, struct nvkm_pmu **); - int (*therm )(struct nvkm_device *, int idx, struct nvkm_therm **); - int (*timer )(struct nvkm_device *, int idx, struct nvkm_timer **); - int (*top )(struct nvkm_device *, int idx, struct nvkm_top **); - int (*volt )(struct nvkm_device *, int idx, struct nvkm_volt **); - - int (*bsp )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*ce[9] )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*cipher )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*disp )(struct nvkm_device *, int idx, struct nvkm_disp **); - int (*dma )(struct nvkm_device *, int idx, struct nvkm_dma **); - int (*fifo )(struct nvkm_device *, int idx, struct nvkm_fifo **); - int (*gr )(struct nvkm_device *, int idx, struct nvkm_gr **); - int (*ifb )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*me )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*mpeg )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*msenc )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*mspdec )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*msppp )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*msvld )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*nvenc[3])(struct nvkm_device *, int idx, struct nvkm_nvenc **); - int (*nvdec[3])(struct nvkm_device *, int idx, struct nvkm_nvdec **); - int (*pm )(struct nvkm_device *, int idx, struct nvkm_pm **); - int (*sec )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*sec2 )(struct nvkm_device *, int idx, struct nvkm_sec2 **); - int (*sw )(struct nvkm_device *, int idx, struct nvkm_sw **); - int (*vic )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*vp )(struct nvkm_device *, int idx, struct nvkm_engine **); +#define NVKM_LAYOUT_ONCE(type,data,ptr,...) \ + struct { \ + u32 inst; \ + int (*ctor)(struct nvkm_device *, enum nvkm_subdev_type, int inst, data **); \ + } ptr; +#define NVKM_LAYOUT_INST(A...) NVKM_LAYOUT_ONCE(A) +#include <core/layout.h> +#undef NVKM_LAYOUT_INST +#undef NVKM_LAYOUT_ONCE }; struct nvkm_device *nvkm_device_find(u64 name); diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h b/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h index c6b401a6ea23..e58923b67d74 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h @@ -6,12 +6,18 @@ struct nvkm_fifo_chan; struct nvkm_fb_tile; +extern const struct nvkm_subdev_func nvkm_engine; + struct nvkm_engine { const struct nvkm_engine_func *func; struct nvkm_subdev subdev; spinlock_t lock; - int usecount; + struct { + refcount_t refcount; + struct mutex mutex; + bool enabled; + } use; }; struct nvkm_engine_func { @@ -42,9 +48,10 @@ struct nvkm_engine_func { }; int nvkm_engine_ctor(const struct nvkm_engine_func *, struct nvkm_device *, - int index, bool enable, struct nvkm_engine *); + enum nvkm_subdev_type, int inst, bool enable, struct nvkm_engine *); int nvkm_engine_new_(const struct nvkm_engine_func *, struct nvkm_device *, - int index, bool enable, struct nvkm_engine **); + enum nvkm_subdev_type, int, bool enable, struct nvkm_engine **); + struct nvkm_engine *nvkm_engine_ref(struct nvkm_engine *); void nvkm_engine_unref(struct nvkm_engine **); void nvkm_engine_tile(struct nvkm_engine *, int region); diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/enum.h b/drivers/gpu/drm/nouveau/include/nvkm/core/enum.h index ce98efd4b209..070462be35d9 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/enum.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/enum.h @@ -8,6 +8,7 @@ struct nvkm_enum { const char *name; const void *data; u32 data2; + int inst; }; const struct nvkm_enum *nvkm_enum_find(const struct nvkm_enum *, u32 value); diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h b/drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h index 3981cb106aae..fd9a3f9a518e 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h @@ -21,11 +21,11 @@ void nvkm_falcon_v1_disable(struct nvkm_falcon *); void gp102_sec2_flcn_bind_context(struct nvkm_falcon *, struct nvkm_memory *); int gp102_sec2_flcn_enable(struct nvkm_falcon *); -#define FLCN_PRINTK(t,f,fmt,a...) do { \ - if (nvkm_subdev_name[(f)->owner->index] != (f)->name) \ - nvkm_##t((f)->owner, "%s: "fmt"\n", (f)->name, ##a); \ - else \ - nvkm_##t((f)->owner, fmt"\n", ##a); \ +#define FLCN_PRINTK(t,f,fmt,a...) do { \ + if ((f)->owner->name != (f)->name) \ + nvkm_##t((f)->owner, "%s: "fmt"\n", (f)->name, ##a); \ + else \ + nvkm_##t((f)->owner, fmt"\n", ##a); \ } while(0) #define FLCN_DBG(f,fmt,a...) FLCN_PRINTK(debug, (f), fmt, ##a) #define FLCN_ERR(f,fmt,a...) FLCN_PRINTK(error, (f), fmt, ##a) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/layout.h b/drivers/gpu/drm/nouveau/include/nvkm/core/layout.h new file mode 100644 index 000000000000..7afe1579b20f --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/layout.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: MIT */ +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_PCI , struct nvkm_pci , pci) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_VBIOS , struct nvkm_bios , bios) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_DEVINIT , struct nvkm_devinit , devinit) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_TOP , struct nvkm_top , top) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_PRIVRING, struct nvkm_subdev , privring) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_GPIO , struct nvkm_gpio , gpio) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_I2C , struct nvkm_i2c , i2c) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_FUSE , struct nvkm_fuse , fuse) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_MXM , struct nvkm_subdev , mxm) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_MC , struct nvkm_mc , mc) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_BUS , struct nvkm_bus , bus) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_TIMER , struct nvkm_timer , timer) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_INSTMEM , struct nvkm_instmem , imem) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_FB , struct nvkm_fb , fb) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_LTC , struct nvkm_ltc , ltc) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_MMU , struct nvkm_mmu , mmu) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_BAR , struct nvkm_bar , bar) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_FAULT , struct nvkm_fault , fault) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_ACR , struct nvkm_acr , acr) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_PMU , struct nvkm_pmu , pmu) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_VOLT , struct nvkm_volt , volt) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_ICCSENSE, struct nvkm_iccsense, iccsense) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_THERM , struct nvkm_therm , therm) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_CLK , struct nvkm_clk , clk) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_GSP , struct nvkm_gsp , gsp) +NVKM_LAYOUT_INST(NVKM_SUBDEV_IOCTRL , struct nvkm_subdev , ioctrl, 3) +NVKM_LAYOUT_ONCE(NVKM_SUBDEV_FLA , struct nvkm_subdev , fla) + +NVKM_LAYOUT_ONCE(NVKM_ENGINE_BSP , struct nvkm_engine , bsp) +NVKM_LAYOUT_INST(NVKM_ENGINE_CE , struct nvkm_engine , ce, 10) +NVKM_LAYOUT_ONCE(NVKM_ENGINE_CIPHER , struct nvkm_engine , cipher) +NVKM_LAYOUT_ONCE(NVKM_ENGINE_DISP , struct nvkm_disp , disp) +NVKM_LAYOUT_ONCE(NVKM_ENGINE_DMAOBJ , struct nvkm_dma , dma) +NVKM_LAYOUT_ONCE(NVKM_ENGINE_FIFO , struct nvkm_fifo , fifo) +NVKM_LAYOUT_ONCE(NVKM_ENGINE_GR , struct nvkm_gr , gr) +NVKM_LAYOUT_ONCE(NVKM_ENGINE_IFB , struct nvkm_engine , ifb) +NVKM_LAYOUT_ONCE(NVKM_ENGINE_ME , struct nvkm_engine , me) +NVKM_LAYOUT_ONCE(NVKM_ENGINE_MPEG , struct nvkm_engine , mpeg) +NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSENC , struct nvkm_engine , msenc) +NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSPDEC , struct nvkm_engine , mspdec) +NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSPPP , struct nvkm_engine , msppp) +NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSVLD , struct nvkm_engine , msvld) +NVKM_LAYOUT_INST(NVKM_ENGINE_NVDEC , struct nvkm_nvdec , nvdec, 5) +NVKM_LAYOUT_INST(NVKM_ENGINE_NVENC , struct nvkm_nvenc , nvenc, 3) +NVKM_LAYOUT_ONCE(NVKM_ENGINE_NVJPG , struct nvkm_engine , nvjpg) +NVKM_LAYOUT_ONCE(NVKM_ENGINE_OFA , struct nvkm_engine , ofa) +NVKM_LAYOUT_ONCE(NVKM_ENGINE_PM , struct nvkm_pm , pm) +NVKM_LAYOUT_ONCE(NVKM_ENGINE_SEC , struct nvkm_engine , sec) +NVKM_LAYOUT_ONCE(NVKM_ENGINE_SEC2 , struct nvkm_sec2 , sec2) +NVKM_LAYOUT_ONCE(NVKM_ENGINE_SW , struct nvkm_sw , sw) +NVKM_LAYOUT_ONCE(NVKM_ENGINE_VIC , struct nvkm_engine , vic) +NVKM_LAYOUT_ONCE(NVKM_ENGINE_VP , struct nvkm_engine , vp) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h b/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h index 76288c682e9e..1665738948fb 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h @@ -3,13 +3,25 @@ #define __NVKM_SUBDEV_H__ #include <core/device.h> +enum nvkm_subdev_type { +#define NVKM_LAYOUT_ONCE(t,s,p,...) t, +#define NVKM_LAYOUT_INST NVKM_LAYOUT_ONCE +#include <core/layout.h> +#undef NVKM_LAYOUT_INST +#undef NVKM_LAYOUT_ONCE + NVKM_SUBDEV_NR +}; + struct nvkm_subdev { const struct nvkm_subdev_func *func; struct nvkm_device *device; - enum nvkm_devidx index; - struct mutex mutex; + enum nvkm_subdev_type type; + int inst; + char name[16]; u32 debug; + struct list_head head; + void **pself; bool oneinit; }; @@ -23,11 +35,12 @@ struct nvkm_subdev_func { void (*intr)(struct nvkm_subdev *); }; -extern const char *nvkm_subdev_name[NVKM_SUBDEV_NR]; -int nvkm_subdev_new_(const struct nvkm_subdev_func *, struct nvkm_device *, - int index, struct nvkm_subdev **); +extern const char *nvkm_subdev_type[NVKM_SUBDEV_NR]; +int nvkm_subdev_new_(const struct nvkm_subdev_func *, struct nvkm_device *, enum nvkm_subdev_type, + int inst, struct nvkm_subdev **); void nvkm_subdev_ctor(const struct nvkm_subdev_func *, struct nvkm_device *, - int index, struct nvkm_subdev *); + enum nvkm_subdev_type, int inst, struct nvkm_subdev *); +void nvkm_subdev_disable(struct nvkm_device *, enum nvkm_subdev_type, int inst); void nvkm_subdev_del(struct nvkm_subdev **); int nvkm_subdev_preinit(struct nvkm_subdev *); int nvkm_subdev_init(struct nvkm_subdev *); @@ -38,10 +51,8 @@ void nvkm_subdev_intr(struct nvkm_subdev *); /* subdev logging */ #define nvkm_printk_(s,l,p,f,a...) do { \ const struct nvkm_subdev *_subdev = (s); \ - if (CONFIG_NOUVEAU_DEBUG >= (l) && _subdev->debug >= (l)) { \ - dev_##p(_subdev->device->dev, "%s: "f, \ - nvkm_subdev_name[_subdev->index], ##a); \ - } \ + if (CONFIG_NOUVEAU_DEBUG >= (l) && _subdev->debug >= (l)) \ + dev_##p(_subdev->device->dev, "%s: "f, _subdev->name, ##a); \ } while(0) #define nvkm_printk(s,l,p,f,a...) nvkm_printk_((s), NV_DBG_##l, p, f, ##a) #define nvkm_fatal(s,f,a...) nvkm_printk((s), FATAL, crit, f, ##a) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h index f938f024db81..d5530faf025e 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h @@ -2,5 +2,5 @@ #ifndef __NVKM_BSP_H__ #define __NVKM_BSP_H__ #include <engine/xtensa.h> -int g84_bsp_new(struct nvkm_device *, int, struct nvkm_engine **); +int g84_bsp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h index 86f420f4630b..cfd2da8e66fe 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h @@ -3,13 +3,13 @@ #define __NVKM_CE_H__ #include <engine/falcon.h> -int gt215_ce_new(struct nvkm_device *, int, struct nvkm_engine **); -int gf100_ce_new(struct nvkm_device *, int, struct nvkm_engine **); -int gk104_ce_new(struct nvkm_device *, int, struct nvkm_engine **); -int gm107_ce_new(struct nvkm_device *, int, struct nvkm_engine **); -int gm200_ce_new(struct nvkm_device *, int, struct nvkm_engine **); -int gp100_ce_new(struct nvkm_device *, int, struct nvkm_engine **); -int gp102_ce_new(struct nvkm_device *, int, struct nvkm_engine **); -int gv100_ce_new(struct nvkm_device *, int, struct nvkm_engine **); -int tu102_ce_new(struct nvkm_device *, int, struct nvkm_engine **); +int gt215_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); +int gf100_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); +int gk104_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); +int gm107_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); +int gm200_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); +int gp100_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); +int gp102_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); +int gv100_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); +int tu102_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h index 66c5c5e27520..9da9176bbbbf 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h @@ -2,5 +2,5 @@ #ifndef __NVKM_CIPHER_H__ #define __NVKM_CIPHER_H__ #include <core/engine.h> -int g84_cipher_new(struct nvkm_device *, int, struct nvkm_engine **); +int g84_cipher_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h index 0f6fa6631a19..d08d3337ba0d 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h @@ -17,25 +17,28 @@ struct nvkm_disp { struct nvkm_event hpd; struct nvkm_event vblank; - struct nvkm_oproxy *client; + struct { + spinlock_t lock; + struct nvkm_oproxy *object; + } client; }; -int nv04_disp_new(struct nvkm_device *, int, struct nvkm_disp **); -int nv50_disp_new(struct nvkm_device *, int, struct nvkm_disp **); -int g84_disp_new(struct nvkm_device *, int, struct nvkm_disp **); -int gt200_disp_new(struct nvkm_device *, int, struct nvkm_disp **); -int g94_disp_new(struct nvkm_device *, int, struct nvkm_disp **); -int mcp77_disp_new(struct nvkm_device *, int, struct nvkm_disp **); -int gt215_disp_new(struct nvkm_device *, int, struct nvkm_disp **); -int mcp89_disp_new(struct nvkm_device *, int, struct nvkm_disp **); -int gf119_disp_new(struct nvkm_device *, int, struct nvkm_disp **); -int gk104_disp_new(struct nvkm_device *, int, struct nvkm_disp **); -int gk110_disp_new(struct nvkm_device *, int, struct nvkm_disp **); -int gm107_disp_new(struct nvkm_device *, int, struct nvkm_disp **); -int gm200_disp_new(struct nvkm_device *, int, struct nvkm_disp **); -int gp100_disp_new(struct nvkm_device *, int, struct nvkm_disp **); -int gp102_disp_new(struct nvkm_device *, int, struct nvkm_disp **); -int gv100_disp_new(struct nvkm_device *, int, struct nvkm_disp **); -int tu102_disp_new(struct nvkm_device *, int, struct nvkm_disp **); -int ga102_disp_new(struct nvkm_device *, int, struct nvkm_disp **); +int nv04_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **); +int nv50_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **); +int g84_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **); +int gt200_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **); +int g94_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **); +int mcp77_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **); +int gt215_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **); +int mcp89_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **); +int gf119_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **); +int gk104_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **); +int gk110_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **); +int gm107_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **); +int gm200_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **); +int gp100_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **); +int gp102_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **); +int gv100_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **); +int tu102_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **); +int ga102_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h index 2e12cdb6bb93..a003da39fd13 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h @@ -23,9 +23,9 @@ struct nvkm_dma { struct nvkm_dmaobj *nvkm_dmaobj_search(struct nvkm_client *, u64 object); -int nv04_dma_new(struct nvkm_device *, int, struct nvkm_dma **); -int nv50_dma_new(struct nvkm_device *, int, struct nvkm_dma **); -int gf100_dma_new(struct nvkm_device *, int, struct nvkm_dma **); -int gf119_dma_new(struct nvkm_device *, int, struct nvkm_dma **); -int gv100_dma_new(struct nvkm_device *, int, struct nvkm_dma **); +int nv04_dma_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_dma **); +int nv50_dma_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_dma **); +int gf100_dma_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_dma **); +int gf119_dma_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_dma **); +int gv100_dma_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_dma **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h index 27c1f868552c..306125d17ece 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h @@ -64,7 +64,7 @@ int nvkm_falcon_get(struct nvkm_falcon *, const struct nvkm_subdev *); void nvkm_falcon_put(struct nvkm_falcon *, const struct nvkm_subdev *); int nvkm_falcon_new_(const struct nvkm_falcon_func *, struct nvkm_device *, - int index, bool enable, u32 addr, struct nvkm_engine **); + enum nvkm_subdev_type, int inst, bool enable, u32 addr, struct nvkm_engine **); struct nvkm_falcon_func { struct { diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h index b335f3a1e66d..54fab7cc36c1 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h @@ -7,6 +7,7 @@ struct nvkm_fault_data; #define NVKM_FIFO_CHID_NR 4096 +#define NVKM_FIFO_ENGN_NR 16 struct nvkm_fifo_engn { struct nvkm_object *object; @@ -17,7 +18,7 @@ struct nvkm_fifo_engn { struct nvkm_fifo_chan { const struct nvkm_fifo_chan_func *func; struct nvkm_fifo *fifo; - u64 engines; + u32 engm; struct nvkm_object object; struct list_head head; @@ -29,7 +30,7 @@ struct nvkm_fifo_chan { u64 addr; u32 size; - struct nvkm_fifo_engn engn[NVKM_SUBDEV_NR]; + struct nvkm_fifo_engn engn[NVKM_FIFO_ENGN_NR]; }; struct nvkm_fifo { @@ -40,6 +41,7 @@ struct nvkm_fifo { int nr; struct list_head chan; spinlock_t lock; + struct mutex mutex; struct nvkm_event uevent; /* async user trigger */ struct nvkm_event cevent; /* channel creation event */ @@ -57,22 +59,22 @@ nvkm_fifo_chan_inst(struct nvkm_fifo *, u64 inst, unsigned long *flags); struct nvkm_fifo_chan * nvkm_fifo_chan_chid(struct nvkm_fifo *, int chid, unsigned long *flags); -int nv04_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); -int nv10_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); -int nv17_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); -int nv40_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); -int nv50_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); -int g84_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); -int gf100_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); -int gk104_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); -int gk110_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); -int gk208_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); -int gk20a_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); -int gm107_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); -int gm200_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); -int gm20b_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); -int gp100_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); -int gp10b_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); -int gv100_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); -int tu102_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); +int nv04_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **); +int nv10_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **); +int nv17_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **); +int nv40_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **); +int nv50_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **); +int g84_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **); +int gf100_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **); +int gk104_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **); +int gk110_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **); +int gk208_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **); +int gk20a_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **); +int gm107_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **); +int gm200_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **); +int gm20b_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **); +int gp100_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **); +int gp10b_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **); +int gv100_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **); +int tu102_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h index 1530c81f86a2..b28b752ffaa2 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h @@ -14,44 +14,44 @@ int nvkm_gr_ctxsw_pause(struct nvkm_device *); int nvkm_gr_ctxsw_resume(struct nvkm_device *); u32 nvkm_gr_ctxsw_inst(struct nvkm_device *); -int nv04_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int nv10_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int nv15_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int nv17_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int nv20_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int nv25_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int nv2a_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int nv30_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int nv34_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int nv35_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int nv40_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int nv44_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int nv50_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int g84_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int gt200_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int mcp79_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int gt215_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int mcp89_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int gf100_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int gf104_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int gf108_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int gf110_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int gf117_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int gf119_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int gk104_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int gk110_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int gk110b_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int gk208_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int gk20a_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int gm107_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int gm200_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int gm20b_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int gp100_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int gp102_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int gp104_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int gp107_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int gp108_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int gp10b_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int gv100_gr_new(struct nvkm_device *, int, struct nvkm_gr **); -int tu102_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int nv04_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int nv10_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int nv15_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int nv17_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int nv20_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int nv25_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int nv2a_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int nv30_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int nv34_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int nv35_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int nv40_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int nv44_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int nv50_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int g84_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int gt200_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int mcp79_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int gt215_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int mcp89_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int gf100_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int gf104_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int gf108_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int gf110_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int gf117_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int gf119_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int gk104_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int gk110_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int gk110b_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int gk208_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int gk20a_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int gm107_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int gm200_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int gm20b_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int gp100_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int gp102_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int gp104_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int gp107_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int gp108_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int gp10b_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int gv100_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); +int tu102_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h index 8585a31f5943..f137f277935f 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h @@ -2,9 +2,9 @@ #ifndef __NVKM_MPEG_H__ #define __NVKM_MPEG_H__ #include <core/engine.h> -int nv31_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **); -int nv40_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **); -int nv44_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **); -int nv50_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **); -int g84_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **); +int nv31_mpeg_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); +int nv40_mpeg_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); +int nv44_mpeg_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); +int nv50_mpeg_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); +int g84_mpeg_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h index 83bb2fcb2cbf..ac8f08ce183c 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h @@ -2,8 +2,8 @@ #ifndef __NVKM_MSPDEC_H__ #define __NVKM_MSPDEC_H__ #include <engine/falcon.h> -int g98_mspdec_new(struct nvkm_device *, int, struct nvkm_engine **); -int gt215_mspdec_new(struct nvkm_device *, int, struct nvkm_engine **); -int gf100_mspdec_new(struct nvkm_device *, int, struct nvkm_engine **); -int gk104_mspdec_new(struct nvkm_device *, int, struct nvkm_engine **); +int g98_mspdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); +int gt215_mspdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); +int gf100_mspdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); +int gk104_mspdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h index 69e09fd96e0c..81c2b6f0ad84 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h @@ -2,7 +2,7 @@ #ifndef __NVKM_MSPPP_H__ #define __NVKM_MSPPP_H__ #include <engine/falcon.h> -int g98_msppp_new(struct nvkm_device *, int, struct nvkm_engine **); -int gt215_msppp_new(struct nvkm_device *, int, struct nvkm_engine **); -int gf100_msppp_new(struct nvkm_device *, int, struct nvkm_engine **); +int g98_msppp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); +int gt215_msppp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); +int gf100_msppp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h index 9e11cefc9649..2d5fa961ba66 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h @@ -2,9 +2,9 @@ #ifndef __NVKM_MSVLD_H__ #define __NVKM_MSVLD_H__ #include <engine/falcon.h> -int g98_msvld_new(struct nvkm_device *, int, struct nvkm_engine **); -int gt215_msvld_new(struct nvkm_device *, int, struct nvkm_engine **); -int mcp89_msvld_new(struct nvkm_device *, int, struct nvkm_engine **); -int gf100_msvld_new(struct nvkm_device *, int, struct nvkm_engine **); -int gk104_msvld_new(struct nvkm_device *, int, struct nvkm_engine **); +int g98_msvld_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); +int gt215_msvld_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); +int mcp89_msvld_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); +int gf100_msvld_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); +int gk104_msvld_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/nvdec.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/nvdec.h index 1b3183e31606..97bd3092f68a 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/nvdec.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/nvdec.h @@ -11,5 +11,5 @@ struct nvkm_nvdec { struct nvkm_falcon falcon; }; -int gm107_nvdec_new(struct nvkm_device *, int, struct nvkm_nvdec **); +int gm107_nvdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvdec **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h index 33e6ba8adc8d..1a259c5c9a71 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h @@ -11,5 +11,5 @@ struct nvkm_nvenc { struct nvkm_falcon falcon; }; -int gm107_nvenc_new(struct nvkm_device *, int, struct nvkm_nvenc **); +int gm107_nvenc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvenc **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h index 4d754e7650d9..af89d46ea360 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h @@ -7,20 +7,23 @@ struct nvkm_pm { const struct nvkm_pm_func *func; struct nvkm_engine engine; - struct nvkm_object *perfmon; + struct { + spinlock_t lock; + struct nvkm_object *object; + } client; struct list_head domains; struct list_head sources; u32 sequence; }; -int nv40_pm_new(struct nvkm_device *, int, struct nvkm_pm **); -int nv50_pm_new(struct nvkm_device *, int, struct nvkm_pm **); -int g84_pm_new(struct nvkm_device *, int, struct nvkm_pm **); -int gt200_pm_new(struct nvkm_device *, int, struct nvkm_pm **); -int gt215_pm_new(struct nvkm_device *, int, struct nvkm_pm **); -int gf100_pm_new(struct nvkm_device *, int, struct nvkm_pm **); -int gf108_pm_new(struct nvkm_device *, int, struct nvkm_pm **); -int gf117_pm_new(struct nvkm_device *, int, struct nvkm_pm **); -int gk104_pm_new(struct nvkm_device *, int, struct nvkm_pm **); +int nv40_pm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pm **); +int nv50_pm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pm **); +int g84_pm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pm **); +int gt200_pm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pm **); +int gt215_pm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pm **); +int gf100_pm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pm **); +int gf108_pm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pm **); +int gf117_pm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pm **); +int gk104_pm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pm **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h index f14e98a8a0ca..37ed7ab8d050 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h @@ -2,5 +2,5 @@ #ifndef __NVKM_SEC_H__ #define __NVKM_SEC_H__ #include <engine/falcon.h> -int g98_sec_new(struct nvkm_device *, int, struct nvkm_engine **); +int g98_sec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h index 34dc765648d5..06264c840eae 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h @@ -18,7 +18,7 @@ struct nvkm_sec2 { bool initmsg_received; }; -int gp102_sec2_new(struct nvkm_device *, int, struct nvkm_sec2 **); -int gp108_sec2_new(struct nvkm_device *, int, struct nvkm_sec2 **); -int tu102_sec2_new(struct nvkm_device *, int, struct nvkm_sec2 **); +int gp102_sec2_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_sec2 **); +int gp108_sec2_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_sec2 **); +int tu102_sec2_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_sec2 **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h index 2e91769e3ee2..b1a53ffbfdef 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h @@ -12,8 +12,8 @@ struct nvkm_sw { bool nvkm_sw_mthd(struct nvkm_sw *sw, int chid, int subc, u32 mthd, u32 data); -int nv04_sw_new(struct nvkm_device *, int, struct nvkm_sw **); -int nv10_sw_new(struct nvkm_device *, int, struct nvkm_sw **); -int nv50_sw_new(struct nvkm_device *, int, struct nvkm_sw **); -int gf100_sw_new(struct nvkm_device *, int, struct nvkm_sw **); +int nv04_sw_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_sw **); +int nv10_sw_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_sw **); +int nv50_sw_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_sw **); +int gf100_sw_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_sw **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h index 8984415b2a3d..1bab26858538 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h @@ -2,5 +2,5 @@ #ifndef __NVKM_VP_H__ #define __NVKM_VP_H__ #include <engine/xtensa.h> -int g84_vp_new(struct nvkm_device *, int, struct nvkm_engine **); +int g84_vp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h index fbf27b2293a9..3083a5866a55 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h @@ -13,7 +13,7 @@ struct nvkm_xtensa { }; int nvkm_xtensa_new_(const struct nvkm_xtensa_func *, struct nvkm_device *, - int index, bool enable, u32 addr, struct nvkm_engine **); + enum nvkm_subdev_type, int, bool enable, u32 addr, struct nvkm_engine **); struct nvkm_xtensa_func { u32 fifo_val; diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h index 836d8b932822..c0b254f7f0b5 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h @@ -59,12 +59,12 @@ struct nvkm_acr { bool nvkm_acr_managed_falcon(struct nvkm_device *, enum nvkm_acr_lsf_id); int nvkm_acr_bootstrap_falcons(struct nvkm_device *, unsigned long mask); -int gm200_acr_new(struct nvkm_device *, int, struct nvkm_acr **); -int gm20b_acr_new(struct nvkm_device *, int, struct nvkm_acr **); -int gp102_acr_new(struct nvkm_device *, int, struct nvkm_acr **); -int gp108_acr_new(struct nvkm_device *, int, struct nvkm_acr **); -int gp10b_acr_new(struct nvkm_device *, int, struct nvkm_acr **); -int tu102_acr_new(struct nvkm_device *, int, struct nvkm_acr **); +int gm200_acr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_acr **); +int gm20b_acr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_acr **); +int gp102_acr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_acr **); +int gp108_acr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_acr **); +int gp10b_acr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_acr **); +int tu102_acr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_acr **); struct nvkm_acr_lsfw { const struct nvkm_acr_lsf_func *func; diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h index 14b09f7e46a5..4f07836ab984 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h @@ -23,11 +23,11 @@ void nvkm_bar_bar2_reset(struct nvkm_device *); struct nvkm_vmm *nvkm_bar_bar2_vmm(struct nvkm_device *); void nvkm_bar_flush(struct nvkm_bar *); -int nv50_bar_new(struct nvkm_device *, int, struct nvkm_bar **); -int g84_bar_new(struct nvkm_device *, int, struct nvkm_bar **); -int gf100_bar_new(struct nvkm_device *, int, struct nvkm_bar **); -int gk20a_bar_new(struct nvkm_device *, int, struct nvkm_bar **); -int gm107_bar_new(struct nvkm_device *, int, struct nvkm_bar **); -int gm20b_bar_new(struct nvkm_device *, int, struct nvkm_bar **); -int tu102_bar_new(struct nvkm_device *, int, struct nvkm_bar **); +int nv50_bar_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bar **); +int g84_bar_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bar **); +int gf100_bar_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bar **); +int gk20a_bar_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bar **); +int gm107_bar_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bar **); +int gm20b_bar_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bar **); +int tu102_bar_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bar **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h index f2860f8e0c2e..b61cfb077533 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h @@ -30,5 +30,5 @@ u8 nvbios_rd08(struct nvkm_bios *, u32 addr); u16 nvbios_rd16(struct nvkm_bios *, u32 addr); u32 nvbios_rd32(struct nvkm_bios *, u32 addr); -int nvkm_bios_new(struct nvkm_device *, int, struct nvkm_bios **); +int nvkm_bios_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_bios **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h index ae9ad6c034fb..2ac03bbc6133 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h @@ -18,9 +18,9 @@ void nvkm_hwsq_wait(struct nvkm_hwsq *, u8 flag, u8 data); void nvkm_hwsq_wait_vblank(struct nvkm_hwsq *); void nvkm_hwsq_nsec(struct nvkm_hwsq *, u32 nsec); -int nv04_bus_new(struct nvkm_device *, int, struct nvkm_bus **); -int nv31_bus_new(struct nvkm_device *, int, struct nvkm_bus **); -int nv50_bus_new(struct nvkm_device *, int, struct nvkm_bus **); -int g94_bus_new(struct nvkm_device *, int, struct nvkm_bus **); -int gf100_bus_new(struct nvkm_device *, int, struct nvkm_bus **); +int nv04_bus_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bus **); +int nv31_bus_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bus **); +int nv50_bus_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bus **); +int g94_bus_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bus **); +int gf100_bus_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bus **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h index bf937e7dfd77..05b99c9e9a26 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h @@ -125,14 +125,14 @@ int nvkm_clk_astate(struct nvkm_clk *, int req, int rel, bool wait); int nvkm_clk_dstate(struct nvkm_clk *, int req, int rel); int nvkm_clk_tstate(struct nvkm_clk *, u8 temperature); -int nv04_clk_new(struct nvkm_device *, int, struct nvkm_clk **); -int nv40_clk_new(struct nvkm_device *, int, struct nvkm_clk **); -int nv50_clk_new(struct nvkm_device *, int, struct nvkm_clk **); -int g84_clk_new(struct nvkm_device *, int, struct nvkm_clk **); -int mcp77_clk_new(struct nvkm_device *, int, struct nvkm_clk **); -int gt215_clk_new(struct nvkm_device *, int, struct nvkm_clk **); -int gf100_clk_new(struct nvkm_device *, int, struct nvkm_clk **); -int gk104_clk_new(struct nvkm_device *, int, struct nvkm_clk **); -int gk20a_clk_new(struct nvkm_device *, int, struct nvkm_clk **); -int gm20b_clk_new(struct nvkm_device *, int, struct nvkm_clk **); +int nv04_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **); +int nv40_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **); +int nv50_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **); +int g84_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **); +int mcp77_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **); +int gt215_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **); +int gf100_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **); +int gk104_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **); +int gk20a_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **); +int gm20b_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h index 50cc7c05eac4..848b5d9ce705 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h @@ -14,23 +14,22 @@ struct nvkm_devinit { u32 nvkm_devinit_mmio(struct nvkm_devinit *, u32 addr); int nvkm_devinit_pll_set(struct nvkm_devinit *, u32 type, u32 khz); void nvkm_devinit_meminit(struct nvkm_devinit *); -u64 nvkm_devinit_disable(struct nvkm_devinit *); -int nvkm_devinit_post(struct nvkm_devinit *, u64 *disable); +int nvkm_devinit_post(struct nvkm_devinit *); -int nv04_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **); -int nv05_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **); -int nv10_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **); -int nv1a_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **); -int nv20_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **); -int nv50_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **); -int g84_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **); -int g98_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **); -int gt215_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **); -int mcp89_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **); -int gf100_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **); -int gm107_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **); -int gm200_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **); -int gv100_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **); -int tu102_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **); -int ga100_devinit_new(struct nvkm_device *, int, struct nvkm_devinit **); +int nv04_devinit_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_devinit **); +int nv05_devinit_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_devinit **); +int nv10_devinit_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_devinit **); +int nv1a_devinit_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_devinit **); +int nv20_devinit_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_devinit **); +int nv50_devinit_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_devinit **); +int g84_devinit_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_devinit **); +int g98_devinit_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_devinit **); +int gt215_devinit_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_devinit **); +int mcp89_devinit_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_devinit **); +int gf100_devinit_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_devinit **); +int gm107_devinit_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_devinit **); +int gm200_devinit_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_devinit **); +int gv100_devinit_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_devinit **); +int tu102_devinit_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_devinit **); +int ga100_devinit_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_devinit **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h index a513c16ab105..581458ad38e0 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h @@ -30,8 +30,8 @@ struct nvkm_fault_data { u8 reason; }; -int gp100_fault_new(struct nvkm_device *, int, struct nvkm_fault **); -int gp10b_fault_new(struct nvkm_device *, int, struct nvkm_fault **); -int gv100_fault_new(struct nvkm_device *, int, struct nvkm_fault **); -int tu102_fault_new(struct nvkm_device *, int, struct nvkm_fault **); +int gp100_fault_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fault **); +int gp10b_fault_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fault **); +int gv100_fault_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fault **); +int tu102_fault_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fault **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h index 2ecd52aec1d1..ef6a6297148c 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h @@ -36,7 +36,11 @@ struct nvkm_fb { struct nvkm_blob vpr_scrubber; struct nvkm_ram *ram; - struct nvkm_mm tags; + + struct { + struct mutex mutex; /* protects mm and nvkm_memory::tags */ + struct nvkm_mm mm; + } tags; struct { struct nvkm_fb_tile region[16]; @@ -54,40 +58,40 @@ void nvkm_fb_tile_init(struct nvkm_fb *, int region, u32 addr, u32 size, void nvkm_fb_tile_fini(struct nvkm_fb *, int region, struct nvkm_fb_tile *); void nvkm_fb_tile_prog(struct nvkm_fb *, int region, struct nvkm_fb_tile *); -int nv04_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int nv10_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int nv1a_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int nv20_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int nv25_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int nv30_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int nv35_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int nv36_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int nv40_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int nv41_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int nv44_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int nv46_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int nv47_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int nv49_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int nv4e_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int nv50_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int g84_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int gt215_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int mcp77_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int mcp89_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int gf100_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int gf108_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int gk104_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int gk110_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int gk20a_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int gm107_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int gm200_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int gm20b_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int gp100_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int gp102_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int gp10b_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int gv100_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int ga100_fb_new(struct nvkm_device *, int, struct nvkm_fb **); -int ga102_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int nv04_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int nv10_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int nv1a_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int nv20_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int nv25_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int nv30_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int nv35_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int nv36_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int nv40_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int nv41_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int nv44_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int nv46_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int nv47_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int nv49_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int nv4e_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int nv50_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int g84_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int gt215_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int mcp77_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int mcp89_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int gf100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int gf108_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int gk104_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int gk110_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int gk20a_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int gm107_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int gm200_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int gm20b_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int gp100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int gp102_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int gp10b_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int gv100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int ga100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); +int ga102_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **); #include <subdev/bios.h> #include <subdev/bios/ramcfg.h> @@ -128,6 +132,7 @@ struct nvkm_ram { #define NVKM_RAM_MM_MIXED (NVKM_MM_HEAP_ANY + 3) struct nvkm_mm vram; u64 stolen; + struct mutex mutex; int ranks; int parts; diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h index 00111c34311e..dabbef0ac96c 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h @@ -11,7 +11,7 @@ struct nvkm_fuse { u32 nvkm_fuse_read(struct nvkm_fuse *, u32 addr); -int nv50_fuse_new(struct nvkm_device *, int, struct nvkm_fuse **); -int gf100_fuse_new(struct nvkm_device *, int, struct nvkm_fuse **); -int gm107_fuse_new(struct nvkm_device *, int, struct nvkm_fuse **); +int nv50_fuse_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fuse **); +int gf100_fuse_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fuse **); +int gm107_fuse_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fuse **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h index cdcce5ece6ff..0e46ea1fe972 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h @@ -32,10 +32,10 @@ int nvkm_gpio_find(struct nvkm_gpio *, int idx, u8 tag, u8 line, int nvkm_gpio_set(struct nvkm_gpio *, int idx, u8 tag, u8 line, int state); int nvkm_gpio_get(struct nvkm_gpio *, int idx, u8 tag, u8 line); -int nv10_gpio_new(struct nvkm_device *, int, struct nvkm_gpio **); -int nv50_gpio_new(struct nvkm_device *, int, struct nvkm_gpio **); -int g94_gpio_new(struct nvkm_device *, int, struct nvkm_gpio **); -int gf119_gpio_new(struct nvkm_device *, int, struct nvkm_gpio **); -int gk104_gpio_new(struct nvkm_device *, int, struct nvkm_gpio **); -int ga102_gpio_new(struct nvkm_device *, int, struct nvkm_gpio **); +int nv10_gpio_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gpio **); +int nv50_gpio_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gpio **); +int g94_gpio_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gpio **); +int gf119_gpio_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gpio **); +int gk104_gpio_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gpio **); +int ga102_gpio_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gpio **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h index 06db67610a50..cf42a59d4e58 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h @@ -9,5 +9,5 @@ struct nvkm_gsp { struct nvkm_falcon falcon; }; -int gv100_gsp_new(struct nvkm_device *, int, struct nvkm_gsp **); +int gv100_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h index 640f649ce497..146e13292203 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h @@ -85,15 +85,15 @@ struct nvkm_i2c { struct nvkm_i2c_bus *nvkm_i2c_bus_find(struct nvkm_i2c *, int); struct nvkm_i2c_aux *nvkm_i2c_aux_find(struct nvkm_i2c *, int); -int nv04_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **); -int nv4e_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **); -int nv50_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **); -int g94_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **); -int gf117_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **); -int gf119_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **); -int gk104_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **); -int gk110_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **); -int gm200_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **); +int nv04_i2c_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_i2c **); +int nv4e_i2c_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_i2c **); +int nv50_i2c_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_i2c **); +int g94_i2c_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_i2c **); +int gf117_i2c_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_i2c **); +int gf119_i2c_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_i2c **); +int gk104_i2c_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_i2c **); +int gk110_i2c_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_i2c **); +int gm200_i2c_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_i2c **); static inline int nvkm_rdi2cr(struct i2c_adapter *adap, u8 addr, u8 reg) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h deleted file mode 100644 index db791411eaa8..000000000000 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef __NVKM_IBUS_H__ -#define __NVKM_IBUS_H__ -#include <core/subdev.h> - -int gf100_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **); -int gf117_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **); -int gk104_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **); -int gk20a_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **); -int gm200_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **); -int gp10b_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **); -#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/iccsense.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/iccsense.h index f483dcd7cd1c..7400d62dcbec 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/iccsense.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/iccsense.h @@ -14,6 +14,6 @@ struct nvkm_iccsense { u32 power_w_crit; }; -int gf100_iccsense_new(struct nvkm_device *, int index, struct nvkm_iccsense **); +int gf100_iccsense_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_iccsense **); int nvkm_iccsense_read_all(struct nvkm_iccsense *iccsense); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h index c74ab7c31d05..f967b97d163c 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h @@ -13,6 +13,11 @@ struct nvkm_instmem { struct list_head boot; u32 reserved; + /* <=nv4x: protects NV_PRAMIN/BAR2 MM + * >=nv50: protects BAR2 MM & LRU + */ + struct mutex mutex; + struct nvkm_memory *vbios; struct nvkm_ramht *ramht; struct nvkm_memory *ramro; @@ -25,8 +30,8 @@ int nvkm_instobj_new(struct nvkm_instmem *, u32 size, u32 align, bool zero, struct nvkm_memory **); -int nv04_instmem_new(struct nvkm_device *, int, struct nvkm_instmem **); -int nv40_instmem_new(struct nvkm_device *, int, struct nvkm_instmem **); -int nv50_instmem_new(struct nvkm_device *, int, struct nvkm_instmem **); -int gk20a_instmem_new(struct nvkm_device *, int, struct nvkm_instmem **); +int nv04_instmem_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_instmem **); +int nv40_instmem_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_instmem **); +int nv50_instmem_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_instmem **); +int gk20a_instmem_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_instmem **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h index d76f60d7d29a..d32a326a9290 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h @@ -13,6 +13,7 @@ struct nvkm_ltc { u32 ltc_nr; u32 lts_nr; + struct mutex mutex; /* serialises CBC operations */ u32 num_tags; u32 tag_base; struct nvkm_memory *tag_ram; @@ -33,12 +34,11 @@ int nvkm_ltc_zbc_stencil_get(struct nvkm_ltc *, int index, const u32); void nvkm_ltc_invalidate(struct nvkm_ltc *); void nvkm_ltc_flush(struct nvkm_ltc *); -int gf100_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); -int gk104_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); -int gk20a_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); -int gm107_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); -int gm200_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); -int gp100_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); -int gp102_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); -int gp10b_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); +int gf100_ltc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_ltc **); +int gk104_ltc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_ltc **); +int gm107_ltc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_ltc **); +int gm200_ltc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_ltc **); +int gp100_ltc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_ltc **); +int gp102_ltc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_ltc **); +int gp10b_ltc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_ltc **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h index e45ca4583967..cb86a56e68d4 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h @@ -8,29 +8,29 @@ struct nvkm_mc { struct nvkm_subdev subdev; }; -void nvkm_mc_enable(struct nvkm_device *, enum nvkm_devidx); -void nvkm_mc_disable(struct nvkm_device *, enum nvkm_devidx); -bool nvkm_mc_enabled(struct nvkm_device *, enum nvkm_devidx); -void nvkm_mc_reset(struct nvkm_device *, enum nvkm_devidx); +void nvkm_mc_enable(struct nvkm_device *, enum nvkm_subdev_type, int); +void nvkm_mc_disable(struct nvkm_device *, enum nvkm_subdev_type, int); +bool nvkm_mc_enabled(struct nvkm_device *, enum nvkm_subdev_type, int); +void nvkm_mc_reset(struct nvkm_device *, enum nvkm_subdev_type, int); void nvkm_mc_intr(struct nvkm_device *, bool *handled); void nvkm_mc_intr_unarm(struct nvkm_device *); void nvkm_mc_intr_rearm(struct nvkm_device *); -void nvkm_mc_intr_mask(struct nvkm_device *, enum nvkm_devidx, bool enable); +void nvkm_mc_intr_mask(struct nvkm_device *, enum nvkm_subdev_type, int, bool enable); void nvkm_mc_unk260(struct nvkm_device *, u32 data); -int nv04_mc_new(struct nvkm_device *, int, struct nvkm_mc **); -int nv11_mc_new(struct nvkm_device *, int, struct nvkm_mc **); -int nv17_mc_new(struct nvkm_device *, int, struct nvkm_mc **); -int nv44_mc_new(struct nvkm_device *, int, struct nvkm_mc **); -int nv50_mc_new(struct nvkm_device *, int, struct nvkm_mc **); -int g84_mc_new(struct nvkm_device *, int, struct nvkm_mc **); -int g98_mc_new(struct nvkm_device *, int, struct nvkm_mc **); -int gt215_mc_new(struct nvkm_device *, int, struct nvkm_mc **); -int gf100_mc_new(struct nvkm_device *, int, struct nvkm_mc **); -int gk104_mc_new(struct nvkm_device *, int, struct nvkm_mc **); -int gk20a_mc_new(struct nvkm_device *, int, struct nvkm_mc **); -int gp100_mc_new(struct nvkm_device *, int, struct nvkm_mc **); -int gp10b_mc_new(struct nvkm_device *, int, struct nvkm_mc **); -int tu102_mc_new(struct nvkm_device *, int, struct nvkm_mc **); -int ga100_mc_new(struct nvkm_device *, int, struct nvkm_mc **); +int nv04_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **); +int nv11_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **); +int nv17_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **); +int nv44_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **); +int nv50_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **); +int g84_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **); +int g98_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **); +int gt215_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **); +int gf100_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **); +int gk104_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **); +int gk20a_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **); +int gp100_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **); +int gp10b_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **); +int tu102_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **); +int ga100_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h index 54cdcb017518..0911e73f7424 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h @@ -117,22 +117,24 @@ struct nvkm_mmu { struct list_head list; } ptc, ptp; + struct mutex mutex; /* serialises mmu invalidations */ + struct nvkm_device_oclass user; }; -int nv04_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **); -int nv41_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **); -int nv44_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **); -int nv50_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **); -int g84_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **); -int mcp77_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **); -int gf100_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **); -int gk104_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **); -int gk20a_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **); -int gm200_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **); -int gm20b_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **); -int gp100_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **); -int gp10b_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **); -int gv100_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **); -int tu102_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **); +int nv04_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **); +int nv41_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **); +int nv44_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **); +int nv50_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **); +int g84_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **); +int mcp77_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **); +int gf100_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **); +int gk104_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **); +int gk20a_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **); +int gm200_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **); +int gm20b_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **); +int gp100_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **); +int gp10b_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **); +int gv100_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **); +int tu102_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h index 78df1e9def05..7d4132a17d0f 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h @@ -3,5 +3,5 @@ #define __NVKM_MXM_H__ #include <core/subdev.h> -int nv50_mxm_new(struct nvkm_device *, int, struct nvkm_subdev **); +int nv50_mxm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_subdev **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h index 4803a4fad4a2..74c19bdfb757 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h @@ -39,17 +39,17 @@ void nvkm_pci_wr32(struct nvkm_pci *, u16 addr, u32 data); u32 nvkm_pci_mask(struct nvkm_pci *, u16 addr, u32 mask, u32 value); void nvkm_pci_rom_shadow(struct nvkm_pci *, bool shadow); -int nv04_pci_new(struct nvkm_device *, int, struct nvkm_pci **); -int nv40_pci_new(struct nvkm_device *, int, struct nvkm_pci **); -int nv46_pci_new(struct nvkm_device *, int, struct nvkm_pci **); -int nv4c_pci_new(struct nvkm_device *, int, struct nvkm_pci **); -int g84_pci_new(struct nvkm_device *, int, struct nvkm_pci **); -int g92_pci_new(struct nvkm_device *, int, struct nvkm_pci **); -int g94_pci_new(struct nvkm_device *, int, struct nvkm_pci **); -int gf100_pci_new(struct nvkm_device *, int, struct nvkm_pci **); -int gf106_pci_new(struct nvkm_device *, int, struct nvkm_pci **); -int gk104_pci_new(struct nvkm_device *, int, struct nvkm_pci **); -int gp100_pci_new(struct nvkm_device *, int, struct nvkm_pci **); +int nv04_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **); +int nv40_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **); +int nv46_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **); +int nv4c_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **); +int g84_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **); +int g92_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **); +int g94_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **); +int gf100_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **); +int gf106_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **); +int gk104_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **); +int gp100_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **); /* pcie functions */ int nvkm_pcie_set_link(struct nvkm_pci *, enum nvkm_pcie_speed, u8 width); diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h index 5ff6d1f8985a..f57a3a5a288d 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h @@ -18,6 +18,7 @@ struct nvkm_pmu { struct completion wpr_ready; struct { + struct mutex mutex; u32 base; u32 size; } send; @@ -39,18 +40,18 @@ int nvkm_pmu_send(struct nvkm_pmu *, u32 reply[2], u32 process, void nvkm_pmu_pgob(struct nvkm_pmu *, bool enable); bool nvkm_pmu_fan_controlled(struct nvkm_device *); -int gt215_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); -int gf100_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); -int gf119_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); -int gk104_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); -int gk110_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); -int gk208_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); -int gk20a_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); -int gm107_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); -int gm200_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); -int gm20b_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); -int gp102_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); -int gp10b_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); +int gt215_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **); +int gf100_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **); +int gf119_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **); +int gk104_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **); +int gk110_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **); +int gk208_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **); +int gk20a_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **); +int gm107_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **); +int gm200_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **); +int gm20b_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **); +int gp102_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **); +int gp10b_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **); /* interface to MEMX process running on PMU */ struct nvkm_memx; diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/privring.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/privring.h new file mode 100644 index 000000000000..e1399f8a90ad --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/privring.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef __NVKM_PRIVRING_H__ +#define __NVKM_PRIVRING_H__ +#include <core/subdev.h> + +int gf100_privring_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_subdev **); +int gf117_privring_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_subdev **); +int gk104_privring_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_subdev **); +int gk20a_privring_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_subdev **); +int gm200_privring_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_subdev **); +int gp10b_privring_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_subdev **); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h index 62c34f98c930..bd04f49272a6 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h @@ -107,13 +107,13 @@ void nvkm_therm_clkgate_init(struct nvkm_therm *, void nvkm_therm_clkgate_enable(struct nvkm_therm *); void nvkm_therm_clkgate_fini(struct nvkm_therm *, bool); -int nv40_therm_new(struct nvkm_device *, int, struct nvkm_therm **); -int nv50_therm_new(struct nvkm_device *, int, struct nvkm_therm **); -int g84_therm_new(struct nvkm_device *, int, struct nvkm_therm **); -int gt215_therm_new(struct nvkm_device *, int, struct nvkm_therm **); -int gf119_therm_new(struct nvkm_device *, int, struct nvkm_therm **); -int gk104_therm_new(struct nvkm_device *, int, struct nvkm_therm **); -int gm107_therm_new(struct nvkm_device *, int, struct nvkm_therm **); -int gm200_therm_new(struct nvkm_device *, int, struct nvkm_therm **); -int gp100_therm_new(struct nvkm_device *, int, struct nvkm_therm **); +int nv40_therm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_therm **); +int nv50_therm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_therm **); +int g84_therm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_therm **); +int gt215_therm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_therm **); +int gf119_therm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_therm **); +int gk104_therm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_therm **); +int gm107_therm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_therm **); +int gm200_therm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_therm **); +int gp100_therm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_therm **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h index d06dcbe1faa6..439a3f72b0d7 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h @@ -76,8 +76,8 @@ s64 nvkm_timer_wait_test(struct nvkm_timer_wait *); #define nvkm_wait_msec(d,m,addr,mask,data) \ nvkm_wait_usec((d), (m) * 1000, (addr), (mask), (data)) -int nv04_timer_new(struct nvkm_device *, int, struct nvkm_timer **); -int nv40_timer_new(struct nvkm_device *, int, struct nvkm_timer **); -int nv41_timer_new(struct nvkm_device *, int, struct nvkm_timer **); -int gk20a_timer_new(struct nvkm_device *, int, struct nvkm_timer **); +int nv04_timer_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_timer **); +int nv40_timer_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_timer **); +int nv41_timer_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_timer **); +int gk20a_timer_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_timer **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h index 7be0e7e7bd77..ee75c5524c43 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h @@ -9,13 +9,24 @@ struct nvkm_top { struct list_head device; }; -u32 nvkm_top_addr(struct nvkm_device *, enum nvkm_devidx); -u32 nvkm_top_reset(struct nvkm_device *, enum nvkm_devidx); -u32 nvkm_top_intr(struct nvkm_device *, u32 intr, u64 *subdevs); -u32 nvkm_top_intr_mask(struct nvkm_device *, enum nvkm_devidx); -int nvkm_top_fault_id(struct nvkm_device *, enum nvkm_devidx); -enum nvkm_devidx nvkm_top_fault(struct nvkm_device *, int fault); -enum nvkm_devidx nvkm_top_engine(struct nvkm_device *, int, int *runl, int *engn); +struct nvkm_top_device { + enum nvkm_subdev_type type; + int inst; + u32 addr; + int fault; + int engine; + int runlist; + int reset; + int intr; + struct list_head head; +}; + +u32 nvkm_top_addr(struct nvkm_device *, enum nvkm_subdev_type, int); +u32 nvkm_top_reset(struct nvkm_device *, enum nvkm_subdev_type, int); +u32 nvkm_top_intr_mask(struct nvkm_device *, enum nvkm_subdev_type, int); +int nvkm_top_fault_id(struct nvkm_device *, enum nvkm_subdev_type, int); +struct nvkm_subdev *nvkm_top_fault(struct nvkm_device *, int fault); -int gk104_top_new(struct nvkm_device *, int, struct nvkm_top **); +int gk104_top_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_top **); +int ga100_top_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_top **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h index 45053a280930..0be86d5f0158 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h @@ -36,10 +36,10 @@ int nvkm_volt_get(struct nvkm_volt *); int nvkm_volt_set_id(struct nvkm_volt *, u8 id, u8 min_id, u8 temp, int condition); -int nv40_volt_new(struct nvkm_device *, int, struct nvkm_volt **); -int gf100_volt_new(struct nvkm_device *, int, struct nvkm_volt **); -int gf117_volt_new(struct nvkm_device *, int, struct nvkm_volt **); -int gk104_volt_new(struct nvkm_device *, int, struct nvkm_volt **); -int gk20a_volt_new(struct nvkm_device *, int, struct nvkm_volt **); -int gm20b_volt_new(struct nvkm_device *, int, struct nvkm_volt **); +int nv40_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **); +int gf100_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **); +int gf117_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **); +int gk104_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **); +int gk20a_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **); +int gm20b_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **); #endif diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c index f08b31d84d4d..0a9334deffe2 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c @@ -269,19 +269,19 @@ nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS) if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) { if (init->fb_ctxdma_handle == ~0) { switch (init->tt_ctxdma_handle) { - case 0x01: engine = NV_DEVICE_INFO_ENGINE_GR ; break; - case 0x02: engine = NV_DEVICE_INFO_ENGINE_MSPDEC; break; - case 0x04: engine = NV_DEVICE_INFO_ENGINE_MSPPP ; break; - case 0x08: engine = NV_DEVICE_INFO_ENGINE_MSVLD ; break; - case 0x30: engine = NV_DEVICE_INFO_ENGINE_CE ; break; + case 0x01: engine = NV_DEVICE_HOST_RUNLIST_ENGINES_GR ; break; + case 0x02: engine = NV_DEVICE_HOST_RUNLIST_ENGINES_MSPDEC; break; + case 0x04: engine = NV_DEVICE_HOST_RUNLIST_ENGINES_MSPPP ; break; + case 0x08: engine = NV_DEVICE_HOST_RUNLIST_ENGINES_MSVLD ; break; + case 0x30: engine = NV_DEVICE_HOST_RUNLIST_ENGINES_CE ; break; default: return nouveau_abi16_put(abi16, -ENOSYS); } } else { - engine = NV_DEVICE_INFO_ENGINE_GR; + engine = NV_DEVICE_HOST_RUNLIST_ENGINES_GR; } - if (engine != NV_DEVICE_INFO_ENGINE_CE) + if (engine != NV_DEVICE_HOST_RUNLIST_ENGINES_CE) engine = nvif_fifo_runlist(device, engine); else engine = nvif_fifo_runlist_ce(device); diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index e48f1f7eb370..7cfac265fd45 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -556,7 +556,7 @@ nouveau_channels_init(struct nouveau_drm *drm) } args = { .m.version = 1, .m.count = sizeof(args.v) / sizeof(args.v.channels), - .v.channels.mthd = NV_DEVICE_FIFO_CHANNELS, + .v.channels.mthd = NV_DEVICE_HOST_CHANNELS, }; struct nvif_object *device = &drm->client.device.object; int ret; diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 1b2169e9c295..885815ea917f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -344,7 +344,7 @@ nouveau_accel_gr_init(struct nouveau_drm *drm) /* Allocate channel that has access to the graphics engine. */ if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) { - arg0 = nvif_fifo_runlist(device, NV_DEVICE_INFO_ENGINE_GR); + arg0 = nvif_fifo_runlist(device, NV_DEVICE_HOST_RUNLIST_ENGINES_GR); arg1 = 1; } else { arg0 = NvDmaFB; diff --git a/drivers/gpu/drm/nouveau/nvif/fifo.c b/drivers/gpu/drm/nouveau/nvif/fifo.c index e84a2e2ff043..a463289962b2 100644 --- a/drivers/gpu/drm/nouveau/nvif/fifo.c +++ b/drivers/gpu/drm/nouveau/nvif/fifo.c @@ -41,9 +41,11 @@ nvif_fifo_runlists(struct nvif_device *device) return -ENOMEM; a->m.version = 1; a->m.count = sizeof(a->v) / sizeof(a->v.runlists); - a->v.runlists.mthd = NV_DEVICE_FIFO_RUNLISTS; - for (i = 0; i < ARRAY_SIZE(a->v.runlist); i++) - a->v.runlist[i].mthd = NV_DEVICE_FIFO_RUNLIST_ENGINES(i); + a->v.runlists.mthd = NV_DEVICE_HOST_RUNLISTS; + for (i = 0; i < ARRAY_SIZE(a->v.runlist); i++) { + a->v.runlist[i].mthd = NV_DEVICE_HOST_RUNLIST_ENGINES; + a->v.runlist[i].data = i; + } ret = nvif_object_mthd(object, NV_DEVICE_V0_INFO, a, sizeof(*a)); if (ret) @@ -58,7 +60,7 @@ nvif_fifo_runlists(struct nvif_device *device) } for (i = 0; i < device->runlists; i++) { - if (a->v.runlists.data & BIT_ULL(i)) + if (a->v.runlist[i].mthd != NV_DEVICE_INFO_INVALID) device->runlist[i].engines = a->v.runlist[i].data; } @@ -70,29 +72,15 @@ done: u64 nvif_fifo_runlist(struct nvif_device *device, u64 engine) { - struct nvif_object *object = &device->object; - struct { - struct nv_device_info_v1 m; - struct { - struct nv_device_info_v1_data engine; - } v; - } a = { - .m.version = 1, - .m.count = sizeof(a.v) / sizeof(a.v.engine), - .v.engine.mthd = engine, - }; u64 runm = 0; int ret, i; if ((ret = nvif_fifo_runlists(device))) return runm; - ret = nvif_object_mthd(object, NV_DEVICE_V0_INFO, &a, sizeof(a)); - if (ret == 0) { - for (i = 0; i < device->runlists; i++) { - if (device->runlist[i].engines & a.v.engine.data) - runm |= BIT_ULL(i); - } + for (i = 0; i < device->runlists; i++) { + if (device->runlist[i].engines & engine) + runm |= BIT_ULL(i); } return runm; diff --git a/drivers/gpu/drm/nouveau/nvkm/core/engine.c b/drivers/gpu/drm/nouveau/nvkm/core/engine.c index 1a47c40e171b..e41a39ae1597 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/engine.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/engine.c @@ -40,10 +40,11 @@ nvkm_engine_unref(struct nvkm_engine **pengine) { struct nvkm_engine *engine = *pengine; if (engine) { - mutex_lock(&engine->subdev.mutex); - if (--engine->usecount == 0) + if (refcount_dec_and_mutex_lock(&engine->use.refcount, &engine->use.mutex)) { nvkm_subdev_fini(&engine->subdev, false); - mutex_unlock(&engine->subdev.mutex); + engine->use.enabled = false; + mutex_unlock(&engine->use.mutex); + } *pengine = NULL; } } @@ -51,17 +52,21 @@ nvkm_engine_unref(struct nvkm_engine **pengine) struct nvkm_engine * nvkm_engine_ref(struct nvkm_engine *engine) { + int ret; if (engine) { - mutex_lock(&engine->subdev.mutex); - if (++engine->usecount == 1) { - int ret = nvkm_subdev_init(&engine->subdev); - if (ret) { - engine->usecount--; - mutex_unlock(&engine->subdev.mutex); - return ERR_PTR(ret); + if (!refcount_inc_not_zero(&engine->use.refcount)) { + mutex_lock(&engine->use.mutex); + if (!refcount_inc_not_zero(&engine->use.refcount)) { + engine->use.enabled = true; + if ((ret = nvkm_subdev_init(&engine->subdev))) { + engine->use.enabled = false; + mutex_unlock(&engine->use.mutex); + return ERR_PTR(ret); + } + refcount_set(&engine->use.refcount, 1); } + mutex_unlock(&engine->use.mutex); } - mutex_unlock(&engine->subdev.mutex); } return engine; } @@ -114,7 +119,7 @@ nvkm_engine_init(struct nvkm_subdev *subdev) int ret = 0, i; s64 time; - if (!engine->usecount) { + if (!engine->use.enabled) { nvkm_trace(subdev, "init skipped, engine has no users\n"); return ret; } @@ -156,11 +161,12 @@ nvkm_engine_dtor(struct nvkm_subdev *subdev) struct nvkm_engine *engine = nvkm_engine(subdev); if (engine->func->dtor) return engine->func->dtor(engine); + mutex_destroy(&engine->use.mutex); return engine; } -static const struct nvkm_subdev_func -nvkm_engine_func = { +const struct nvkm_subdev_func +nvkm_engine = { .dtor = nvkm_engine_dtor, .preinit = nvkm_engine_preinit, .init = nvkm_engine_init, @@ -170,14 +176,15 @@ nvkm_engine_func = { }; int -nvkm_engine_ctor(const struct nvkm_engine_func *func, - struct nvkm_device *device, int index, bool enable, - struct nvkm_engine *engine) +nvkm_engine_ctor(const struct nvkm_engine_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, bool enable, struct nvkm_engine *engine) { - nvkm_subdev_ctor(&nvkm_engine_func, device, index, &engine->subdev); + nvkm_subdev_ctor(&nvkm_engine, device, type, inst, &engine->subdev); engine->func = func; + refcount_set(&engine->use.refcount, 0); + mutex_init(&engine->use.mutex); - if (!nvkm_boolopt(device->cfgopt, nvkm_subdev_name[index], enable)) { + if (!nvkm_boolopt(device->cfgopt, engine->subdev.name, enable)) { nvkm_debug(&engine->subdev, "disabled\n"); return -ENODEV; } @@ -187,11 +194,11 @@ nvkm_engine_ctor(const struct nvkm_engine_func *func, } int -nvkm_engine_new_(const struct nvkm_engine_func *func, - struct nvkm_device *device, int index, bool enable, +nvkm_engine_new_(const struct nvkm_engine_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, bool enable, struct nvkm_engine **pengine) { if (!(*pengine = kzalloc(sizeof(**pengine), GFP_KERNEL))) return -ENOMEM; - return nvkm_engine_ctor(func, device, index, enable, *pengine); + return nvkm_engine_ctor(func, device, type, inst, enable, *pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/core/memory.c b/drivers/gpu/drm/nouveau/nvkm/core/memory.c index 38130ef272d6..c69daac9bac7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/memory.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/memory.c @@ -33,13 +33,13 @@ nvkm_memory_tags_put(struct nvkm_memory *memory, struct nvkm_device *device, struct nvkm_fb *fb = device->fb; struct nvkm_tags *tags = *ptags; if (tags) { - mutex_lock(&fb->subdev.mutex); + mutex_lock(&fb->tags.mutex); if (refcount_dec_and_test(&tags->refcount)) { - nvkm_mm_free(&fb->tags, &tags->mn); + nvkm_mm_free(&fb->tags.mm, &tags->mn); kfree(memory->tags); memory->tags = NULL; } - mutex_unlock(&fb->subdev.mutex); + mutex_unlock(&fb->tags.mutex); *ptags = NULL; } } @@ -52,29 +52,29 @@ nvkm_memory_tags_get(struct nvkm_memory *memory, struct nvkm_device *device, struct nvkm_fb *fb = device->fb; struct nvkm_tags *tags; - mutex_lock(&fb->subdev.mutex); + mutex_lock(&fb->tags.mutex); if ((tags = memory->tags)) { /* If comptags exist for the memory, but a different amount * than requested, the buffer is being mapped with settings * that are incompatible with existing mappings. */ if (tags->mn && tags->mn->length != nr) { - mutex_unlock(&fb->subdev.mutex); + mutex_unlock(&fb->tags.mutex); return -EINVAL; } refcount_inc(&tags->refcount); - mutex_unlock(&fb->subdev.mutex); + mutex_unlock(&fb->tags.mutex); *ptags = tags; return 0; } if (!(tags = kmalloc(sizeof(*tags), GFP_KERNEL))) { - mutex_unlock(&fb->subdev.mutex); + mutex_unlock(&fb->tags.mutex); return -ENOMEM; } - if (!nvkm_mm_head(&fb->tags, 0, 1, nr, nr, 1, &tags->mn)) { + if (!nvkm_mm_head(&fb->tags.mm, 0, 1, nr, nr, 1, &tags->mn)) { if (clr) clr(device, tags->mn->offset, tags->mn->length); } else { @@ -92,7 +92,7 @@ nvkm_memory_tags_get(struct nvkm_memory *memory, struct nvkm_device *device, refcount_set(&tags->refcount, 1); *ptags = memory->tags = tags; - mutex_unlock(&fb->subdev.mutex); + mutex_unlock(&fb->tags.mutex); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/core/subdev.c b/drivers/gpu/drm/nouveau/nvkm/core/subdev.c index 49d468b45d3f..a74b7acb6832 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/subdev.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/subdev.c @@ -26,69 +26,13 @@ #include <core/option.h> #include <subdev/mc.h> -static struct lock_class_key nvkm_subdev_lock_class[NVKM_SUBDEV_NR]; - const char * -nvkm_subdev_name[NVKM_SUBDEV_NR] = { - [NVKM_SUBDEV_ACR ] = "acr", - [NVKM_SUBDEV_BAR ] = "bar", - [NVKM_SUBDEV_VBIOS ] = "bios", - [NVKM_SUBDEV_BUS ] = "bus", - [NVKM_SUBDEV_CLK ] = "clk", - [NVKM_SUBDEV_DEVINIT ] = "devinit", - [NVKM_SUBDEV_FAULT ] = "fault", - [NVKM_SUBDEV_FB ] = "fb", - [NVKM_SUBDEV_FUSE ] = "fuse", - [NVKM_SUBDEV_GPIO ] = "gpio", - [NVKM_SUBDEV_GSP ] = "gsp", - [NVKM_SUBDEV_I2C ] = "i2c", - [NVKM_SUBDEV_IBUS ] = "priv", - [NVKM_SUBDEV_ICCSENSE] = "iccsense", - [NVKM_SUBDEV_INSTMEM ] = "imem", - [NVKM_SUBDEV_LTC ] = "ltc", - [NVKM_SUBDEV_MC ] = "mc", - [NVKM_SUBDEV_MMU ] = "mmu", - [NVKM_SUBDEV_MXM ] = "mxm", - [NVKM_SUBDEV_PCI ] = "pci", - [NVKM_SUBDEV_PMU ] = "pmu", - [NVKM_SUBDEV_THERM ] = "therm", - [NVKM_SUBDEV_TIMER ] = "tmr", - [NVKM_SUBDEV_TOP ] = "top", - [NVKM_SUBDEV_VOLT ] = "volt", - [NVKM_ENGINE_BSP ] = "bsp", - [NVKM_ENGINE_CE0 ] = "ce0", - [NVKM_ENGINE_CE1 ] = "ce1", - [NVKM_ENGINE_CE2 ] = "ce2", - [NVKM_ENGINE_CE3 ] = "ce3", - [NVKM_ENGINE_CE4 ] = "ce4", - [NVKM_ENGINE_CE5 ] = "ce5", - [NVKM_ENGINE_CE6 ] = "ce6", - [NVKM_ENGINE_CE7 ] = "ce7", - [NVKM_ENGINE_CE8 ] = "ce8", - [NVKM_ENGINE_CIPHER ] = "cipher", - [NVKM_ENGINE_DISP ] = "disp", - [NVKM_ENGINE_DMAOBJ ] = "dma", - [NVKM_ENGINE_FIFO ] = "fifo", - [NVKM_ENGINE_GR ] = "gr", - [NVKM_ENGINE_IFB ] = "ifb", - [NVKM_ENGINE_ME ] = "me", - [NVKM_ENGINE_MPEG ] = "mpeg", - [NVKM_ENGINE_MSENC ] = "msenc", - [NVKM_ENGINE_MSPDEC ] = "mspdec", - [NVKM_ENGINE_MSPPP ] = "msppp", - [NVKM_ENGINE_MSVLD ] = "msvld", - [NVKM_ENGINE_NVENC0 ] = "nvenc0", - [NVKM_ENGINE_NVENC1 ] = "nvenc1", - [NVKM_ENGINE_NVENC2 ] = "nvenc2", - [NVKM_ENGINE_NVDEC0 ] = "nvdec0", - [NVKM_ENGINE_NVDEC1 ] = "nvdec1", - [NVKM_ENGINE_NVDEC2 ] = "nvdec2", - [NVKM_ENGINE_PM ] = "pm", - [NVKM_ENGINE_SEC ] = "sec", - [NVKM_ENGINE_SEC2 ] = "sec2", - [NVKM_ENGINE_SW ] = "sw", - [NVKM_ENGINE_VIC ] = "vic", - [NVKM_ENGINE_VP ] = "vp", +nvkm_subdev_type[NVKM_SUBDEV_NR] = { +#define NVKM_LAYOUT_ONCE(type,data,ptr,...) [type] = #ptr, +#define NVKM_LAYOUT_INST(A...) NVKM_LAYOUT_ONCE(A) +#include <core/layout.h> +#undef NVKM_LAYOUT_ONCE +#undef NVKM_LAYOUT_INST }; void @@ -125,7 +69,7 @@ nvkm_subdev_fini(struct nvkm_subdev *subdev, bool suspend) } } - nvkm_mc_reset(device, subdev->index); + nvkm_mc_reset(device, subdev->type, subdev->inst); time = ktime_to_us(ktime_get()) - time; nvkm_trace(subdev, "%s completed in %lldus\n", action, time); @@ -199,6 +143,7 @@ nvkm_subdev_del(struct nvkm_subdev **psubdev) if (subdev && !WARN_ON(!subdev->func)) { nvkm_trace(subdev, "destroy running...\n"); time = ktime_to_us(ktime_get()); + list_del(&subdev->head); if (subdev->func->dtor) *psubdev = subdev->func->dtor(subdev); time = ktime_to_us(ktime_get()) - time; @@ -209,26 +154,41 @@ nvkm_subdev_del(struct nvkm_subdev **psubdev) } void -nvkm_subdev_ctor(const struct nvkm_subdev_func *func, - struct nvkm_device *device, int index, - struct nvkm_subdev *subdev) +nvkm_subdev_disable(struct nvkm_device *device, enum nvkm_subdev_type type, int inst) +{ + struct nvkm_subdev *subdev; + list_for_each_entry(subdev, &device->subdev, head) { + if (subdev->type == type && subdev->inst == inst) { + *subdev->pself = NULL; + nvkm_subdev_del(&subdev); + break; + } + } +} + +void +nvkm_subdev_ctor(const struct nvkm_subdev_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_subdev *subdev) { - const char *name = nvkm_subdev_name[index]; subdev->func = func; subdev->device = device; - subdev->index = index; - - __mutex_init(&subdev->mutex, name, &nvkm_subdev_lock_class[index]); - subdev->debug = nvkm_dbgopt(device->dbgopt, name); + subdev->type = type; + subdev->inst = inst < 0 ? 0 : inst; + + if (inst >= 0) + snprintf(subdev->name, sizeof(subdev->name), "%s%d", nvkm_subdev_type[type], inst); + else + strscpy(subdev->name, nvkm_subdev_type[type], sizeof(subdev->name)); + subdev->debug = nvkm_dbgopt(device->dbgopt, subdev->name); + list_add_tail(&subdev->head, &device->subdev); } int -nvkm_subdev_new_(const struct nvkm_subdev_func *func, - struct nvkm_device *device, int index, - struct nvkm_subdev **psubdev) +nvkm_subdev_new_(const struct nvkm_subdev_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_subdev **psubdev) { if (!(*psubdev = kzalloc(sizeof(**psubdev), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(func, device, index, *psubdev); + nvkm_subdev_ctor(func, device, type, inst, *psubdev); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c index 44e116f7880d..39f6db269c7a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c @@ -36,8 +36,9 @@ g84_bsp = { }; int -g84_bsp_new(struct nvkm_device *device, int index, struct nvkm_engine **pengine) +g84_bsp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pengine) { - return nvkm_xtensa_new_(&g84_bsp, device, index, + return nvkm_xtensa_new_(&g84_bsp, device, type, inst, device->chipset != 0x92, 0x103000, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c index ad9f855c9a40..b9cc39565985 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c @@ -29,9 +29,7 @@ static void gf100_ce_init(struct nvkm_falcon *ce) { - struct nvkm_device *device = ce->engine.subdev.device; - const int index = ce->engine.subdev.index - NVKM_ENGINE_CE0; - nvkm_wr32(device, ce->addr + 0x084, index); + nvkm_wr32(ce->engine.subdev.device, ce->addr + 0x084, ce->engine.subdev.inst); } static const struct nvkm_falcon_func @@ -63,16 +61,9 @@ gf100_ce1 = { }; int -gf100_ce_new(struct nvkm_device *device, int index, +gf100_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - if (index == NVKM_ENGINE_CE0) { - return nvkm_falcon_new_(&gf100_ce0, device, index, true, - 0x104000, pengine); - } else - if (index == NVKM_ENGINE_CE1) { - return nvkm_falcon_new_(&gf100_ce1, device, index, true, - 0x105000, pengine); - } - return -ENODEV; + return nvkm_falcon_new_(inst ? &gf100_ce1 : &gf100_ce0, device, type, inst, true, + 0x104000 + (inst * 0x1000), pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c index 9e0b53a10f77..27f29eb0494d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c @@ -58,9 +58,9 @@ gk104_ce_intr_launcherr(struct nvkm_engine *ce, const u32 base) void gk104_ce_intr(struct nvkm_engine *ce) { - const u32 base = (ce->subdev.index - NVKM_ENGINE_CE0) * 0x1000; struct nvkm_subdev *subdev = &ce->subdev; struct nvkm_device *device = subdev->device; + const u32 base = subdev->inst * 0x1000; u32 mask = nvkm_rd32(device, 0x104904 + base); u32 intr = nvkm_rd32(device, 0x104908 + base) & mask; if (intr & 0x00000001) { @@ -94,8 +94,8 @@ gk104_ce = { }; int -gk104_ce_new(struct nvkm_device *device, int index, +gk104_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_engine_new_(&gk104_ce, device, index, true, pengine); + return nvkm_engine_new_(&gk104_ce, device, type, inst, true, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm107.c index c0df7daa85e2..c3c476592c43 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm107.c @@ -36,8 +36,8 @@ gm107_ce = { }; int -gm107_ce_new(struct nvkm_device *device, int index, +gm107_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_engine_new_(&gm107_ce, device, index, true, pengine); + return nvkm_engine_new_(&gm107_ce, device, type, inst, true, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm200.c index c6fa8b20737e..d2db61865371 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm200.c @@ -35,8 +35,8 @@ gm200_ce = { }; int -gm200_ce_new(struct nvkm_device *device, int index, +gm200_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_engine_new_(&gm200_ce, device, index, true, pengine); + return nvkm_engine_new_(&gm200_ce, device, type, inst, true, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c index c7710456bc30..a4f08a4472c9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c @@ -59,9 +59,9 @@ gp100_ce_intr_launcherr(struct nvkm_engine *ce, const u32 base) void gp100_ce_intr(struct nvkm_engine *ce) { - const u32 base = (ce->subdev.index - NVKM_ENGINE_CE0) * 0x80; struct nvkm_subdev *subdev = &ce->subdev; struct nvkm_device *device = subdev->device; + const u32 base = subdev->inst * 0x80; u32 mask = nvkm_rd32(device, 0x10440c + base); u32 intr = nvkm_rd32(device, 0x104410 + base) & mask; if (intr & 0x00000001) { //XXX: guess @@ -95,8 +95,8 @@ gp100_ce = { }; int -gp100_ce_new(struct nvkm_device *device, int index, +gp100_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_engine_new_(&gp100_ce, device, index, true, pengine); + return nvkm_engine_new_(&gp100_ce, device, type, inst, true, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gp102.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gp102.c index 985c8f653874..180d497a95eb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gp102.c @@ -37,8 +37,8 @@ gp102_ce = { }; int -gp102_ce_new(struct nvkm_device *device, int index, +gp102_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_engine_new_(&gp102_ce, device, index, true, pengine); + return nvkm_engine_new_(&gp102_ce, device, type, inst, true, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c index 63ac51a54fd3..704df0f2d1f1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c @@ -44,7 +44,7 @@ gt215_ce_intr(struct nvkm_falcon *ce, struct nvkm_fifo_chan *chan) { struct nvkm_subdev *subdev = &ce->engine.subdev; struct nvkm_device *device = subdev->device; - const u32 base = (subdev->index - NVKM_ENGINE_CE0) * 0x1000; + const u32 base = subdev->inst * 0x1000; u32 ssta = nvkm_rd32(device, 0x104040 + base) & 0x0000ffff; u32 addr = nvkm_rd32(device, 0x104040 + base) >> 16; u32 mthd = (addr & 0x07ff) << 2; @@ -75,9 +75,9 @@ gt215_ce = { }; int -gt215_ce_new(struct nvkm_device *device, int index, +gt215_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_falcon_new_(>215_ce, device, index, + return nvkm_falcon_new_(>215_ce, device, type, inst, (device->chipset != 0xaf), 0x104000, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gv100.c index fcda3de45857..cd5e9cdca1cf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gv100.c @@ -33,8 +33,8 @@ gv100_ce = { }; int -gv100_ce_new(struct nvkm_device *device, int index, +gv100_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_engine_new_(&gv100_ce, device, index, true, pengine); + return nvkm_engine_new_(&gv100_ce, device, type, inst, true, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/tu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/tu102.c index b4308e2d8c75..e5ff92d9364c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/tu102.c @@ -33,8 +33,8 @@ tu102_ce = { }; int -tu102_ce_new(struct nvkm_device *device, int index, +tu102_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_engine_new_(&tu102_ce, device, index, true, pengine); + return nvkm_engine_new_(&tu102_ce, device, type, inst, true, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c index 68ffb520531e..be2a7181dc15 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c @@ -127,8 +127,8 @@ g84_cipher = { }; int -g84_cipher_new(struct nvkm_device *device, int index, +g84_cipher_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_engine_new_(&g84_cipher, device, index, true, pengine); + return nvkm_engine_new_(&g84_cipher, device, type, inst, true, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index cdcc851e06f9..b930f539feec 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -71,2640 +71,2557 @@ nvkm_device_list(u64 *name, int size) static const struct nvkm_device_chip null_chipset = { .name = "NULL", - .bios = nvkm_bios_new, + .bios = { 0x00000001, nvkm_bios_new }, }; static const struct nvkm_device_chip nv4_chipset = { .name = "NV04", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv04_devinit_new, - .fb = nv04_fb_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv04_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv04_fifo_new, - .gr = nv04_gr_new, - .sw = nv04_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv04_devinit_new }, + .fb = { 0x00000001, nv04_fb_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv04_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv04_fifo_new }, + .gr = { 0x00000001, nv04_gr_new }, + .sw = { 0x00000001, nv04_sw_new }, }; static const struct nvkm_device_chip nv5_chipset = { .name = "NV05", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv05_devinit_new, - .fb = nv04_fb_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv04_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv04_fifo_new, - .gr = nv04_gr_new, - .sw = nv04_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv05_devinit_new }, + .fb = { 0x00000001, nv04_fb_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv04_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv04_fifo_new }, + .gr = { 0x00000001, nv04_gr_new }, + .sw = { 0x00000001, nv04_sw_new }, }; static const struct nvkm_device_chip nv10_chipset = { .name = "NV10", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv10_devinit_new, - .fb = nv10_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv04_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .gr = nv10_gr_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv10_devinit_new }, + .fb = { 0x00000001, nv10_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv04_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .gr = { 0x00000001, nv10_gr_new }, }; static const struct nvkm_device_chip nv11_chipset = { .name = "NV11", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv10_devinit_new, - .fb = nv10_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv11_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv10_fifo_new, - .gr = nv15_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv10_devinit_new }, + .fb = { 0x00000001, nv10_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv11_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv10_fifo_new }, + .gr = { 0x00000001, nv15_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv15_chipset = { .name = "NV15", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv10_devinit_new, - .fb = nv10_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv04_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv10_fifo_new, - .gr = nv15_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv10_devinit_new }, + .fb = { 0x00000001, nv10_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv04_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv10_fifo_new }, + .gr = { 0x00000001, nv15_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv17_chipset = { .name = "NV17", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv10_devinit_new, - .fb = nv10_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv17_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv10_devinit_new }, + .fb = { 0x00000001, nv10_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv17_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv18_chipset = { .name = "NV18", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv10_devinit_new, - .fb = nv10_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv17_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv10_devinit_new }, + .fb = { 0x00000001, nv10_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv17_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv1a_chipset = { .name = "nForce", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv1a_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv04_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv10_fifo_new, - .gr = nv15_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv1a_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv04_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv10_fifo_new }, + .gr = { 0x00000001, nv15_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv1f_chipset = { .name = "nForce2", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv1a_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv17_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv1a_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv17_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv20_chipset = { .name = "NV20", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv20_devinit_new, - .fb = nv20_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv20_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv20_devinit_new }, + .fb = { 0x00000001, nv20_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv20_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv25_chipset = { .name = "NV25", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv20_devinit_new, - .fb = nv25_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv25_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv20_devinit_new }, + .fb = { 0x00000001, nv25_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv25_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv28_chipset = { .name = "NV28", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv20_devinit_new, - .fb = nv25_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv25_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv20_devinit_new }, + .fb = { 0x00000001, nv25_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv25_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv2a_chipset = { .name = "NV2A", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv20_devinit_new, - .fb = nv25_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv2a_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv20_devinit_new }, + .fb = { 0x00000001, nv25_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv2a_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv30_chipset = { .name = "NV30", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv20_devinit_new, - .fb = nv30_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv30_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv20_devinit_new }, + .fb = { 0x00000001, nv30_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv30_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv31_chipset = { .name = "NV31", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv04_clk_new, - .devinit = nv20_devinit_new, - .fb = nv30_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv30_gr_new, - .mpeg = nv31_mpeg_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv20_devinit_new }, + .fb = { 0x00000001, nv30_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv30_gr_new }, + .mpeg = { 0x00000001, nv31_mpeg_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv34_chipset = { .name = "NV34", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv04_clk_new, - .devinit = nv10_devinit_new, - .fb = nv10_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv34_gr_new, - .mpeg = nv31_mpeg_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv10_devinit_new }, + .fb = { 0x00000001, nv10_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv34_gr_new }, + .mpeg = { 0x00000001, nv31_mpeg_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv35_chipset = { .name = "NV35", - .bios = nvkm_bios_new, - .bus = nv04_bus_new, - .clk = nv04_clk_new, - .devinit = nv20_devinit_new, - .fb = nv35_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv35_gr_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv04_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv20_devinit_new }, + .fb = { 0x00000001, nv35_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv35_gr_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv36_chipset = { .name = "NV36", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv04_clk_new, - .devinit = nv20_devinit_new, - .fb = nv36_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv04_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv04_pci_new, - .timer = nv04_timer_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv17_fifo_new, - .gr = nv35_gr_new, - .mpeg = nv31_mpeg_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv04_clk_new }, + .devinit = { 0x00000001, nv20_devinit_new }, + .fb = { 0x00000001, nv36_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv04_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv04_pci_new }, + .timer = { 0x00000001, nv04_timer_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv17_fifo_new }, + .gr = { 0x00000001, nv35_gr_new }, + .mpeg = { 0x00000001, nv31_mpeg_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv40_chipset = { .name = "NV40", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv40_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv40_pci_new, - .therm = nv40_therm_new, - .timer = nv40_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv40_gr_new, - .mpeg = nv40_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv40_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv40_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv40_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv40_gr_new }, + .mpeg = { 0x00000001, nv40_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv41_chipset = { .name = "NV41", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv41_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv17_mc_new, - .mmu = nv41_mmu_new, - .pci = nv40_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv40_gr_new, - .mpeg = nv40_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv41_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv41_mmu_new }, + .pci = { 0x00000001, nv40_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv40_gr_new }, + .mpeg = { 0x00000001, nv40_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv42_chipset = { .name = "NV42", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv41_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv17_mc_new, - .mmu = nv41_mmu_new, - .pci = nv40_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv40_gr_new, - .mpeg = nv40_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv41_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv41_mmu_new }, + .pci = { 0x00000001, nv40_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv40_gr_new }, + .mpeg = { 0x00000001, nv40_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv43_chipset = { .name = "NV43", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv41_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv17_mc_new, - .mmu = nv41_mmu_new, - .pci = nv40_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv40_gr_new, - .mpeg = nv40_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv41_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv41_mmu_new }, + .pci = { 0x00000001, nv40_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv40_gr_new }, + .mpeg = { 0x00000001, nv40_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv44_chipset = { .name = "NV44", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv44_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv44_mc_new, - .mmu = nv44_mmu_new, - .pci = nv40_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv44_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv44_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv44_mc_new }, + .mmu = { 0x00000001, nv44_mmu_new }, + .pci = { 0x00000001, nv40_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv44_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv45_chipset = { .name = "NV45", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv40_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv17_mc_new, - .mmu = nv04_mmu_new, - .pci = nv40_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv40_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv40_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv40_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv40_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv46_chipset = { .name = "G72", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv46_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv44_mc_new, - .mmu = nv44_mmu_new, - .pci = nv46_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv44_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv46_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv44_mc_new }, + .mmu = { 0x00000001, nv44_mmu_new }, + .pci = { 0x00000001, nv46_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv44_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv47_chipset = { .name = "G70", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv47_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv17_mc_new, - .mmu = nv41_mmu_new, - .pci = nv40_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv40_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv47_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv41_mmu_new }, + .pci = { 0x00000001, nv40_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv40_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv49_chipset = { .name = "G71", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv49_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv17_mc_new, - .mmu = nv41_mmu_new, - .pci = nv40_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv40_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv49_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv41_mmu_new }, + .pci = { 0x00000001, nv40_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv40_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv4a_chipset = { .name = "NV44A", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv44_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv44_mc_new, - .mmu = nv04_mmu_new, - .pci = nv40_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv44_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv44_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv44_mc_new }, + .mmu = { 0x00000001, nv04_mmu_new }, + .pci = { 0x00000001, nv40_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv44_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv4b_chipset = { .name = "G73", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv49_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv17_mc_new, - .mmu = nv41_mmu_new, - .pci = nv40_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv40_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv49_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv17_mc_new }, + .mmu = { 0x00000001, nv41_mmu_new }, + .pci = { 0x00000001, nv40_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv40_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv4c_chipset = { .name = "C61", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv46_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv44_mc_new, - .mmu = nv44_mmu_new, - .pci = nv4c_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv44_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv46_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv44_mc_new }, + .mmu = { 0x00000001, nv44_mmu_new }, + .pci = { 0x00000001, nv4c_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv44_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv4e_chipset = { .name = "C51", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv4e_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv4e_i2c_new, - .imem = nv40_instmem_new, - .mc = nv44_mc_new, - .mmu = nv44_mmu_new, - .pci = nv4c_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv44_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv4e_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv4e_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv44_mc_new }, + .mmu = { 0x00000001, nv44_mmu_new }, + .pci = { 0x00000001, nv4c_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv44_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv50_chipset = { .name = "G80", - .bar = nv50_bar_new, - .bios = nvkm_bios_new, - .bus = nv50_bus_new, - .clk = nv50_clk_new, - .devinit = nv50_devinit_new, - .fb = nv50_fb_new, - .fuse = nv50_fuse_new, - .gpio = nv50_gpio_new, - .i2c = nv50_i2c_new, - .imem = nv50_instmem_new, - .mc = nv50_mc_new, - .mmu = nv50_mmu_new, - .mxm = nv50_mxm_new, - .pci = nv46_pci_new, - .therm = nv50_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv50_disp_new, - .dma = nv50_dma_new, - .fifo = nv50_fifo_new, - .gr = nv50_gr_new, - .mpeg = nv50_mpeg_new, - .pm = nv50_pm_new, - .sw = nv50_sw_new, + .bar = { 0x00000001, nv50_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv50_bus_new }, + .clk = { 0x00000001, nv50_clk_new }, + .devinit = { 0x00000001, nv50_devinit_new }, + .fb = { 0x00000001, nv50_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, nv50_gpio_new }, + .i2c = { 0x00000001, nv50_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, nv50_mc_new }, + .mmu = { 0x00000001, nv50_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, nv46_pci_new }, + .therm = { 0x00000001, nv50_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv50_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, nv50_fifo_new }, + .gr = { 0x00000001, nv50_gr_new }, + .mpeg = { 0x00000001, nv50_mpeg_new }, + .pm = { 0x00000001, nv50_pm_new }, + .sw = { 0x00000001, nv50_sw_new }, }; static const struct nvkm_device_chip nv63_chipset = { .name = "C73", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv46_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv44_mc_new, - .mmu = nv44_mmu_new, - .pci = nv4c_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv44_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv46_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv44_mc_new }, + .mmu = { 0x00000001, nv44_mmu_new }, + .pci = { 0x00000001, nv4c_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv44_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv67_chipset = { .name = "C67", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv46_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv44_mc_new, - .mmu = nv44_mmu_new, - .pci = nv4c_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv44_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv46_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv44_mc_new }, + .mmu = { 0x00000001, nv44_mmu_new }, + .pci = { 0x00000001, nv4c_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv44_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv68_chipset = { .name = "C68", - .bios = nvkm_bios_new, - .bus = nv31_bus_new, - .clk = nv40_clk_new, - .devinit = nv1a_devinit_new, - .fb = nv46_fb_new, - .gpio = nv10_gpio_new, - .i2c = nv04_i2c_new, - .imem = nv40_instmem_new, - .mc = nv44_mc_new, - .mmu = nv44_mmu_new, - .pci = nv4c_pci_new, - .therm = nv40_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = nv04_disp_new, - .dma = nv04_dma_new, - .fifo = nv40_fifo_new, - .gr = nv44_gr_new, - .mpeg = nv44_mpeg_new, - .pm = nv40_pm_new, - .sw = nv10_sw_new, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv31_bus_new }, + .clk = { 0x00000001, nv40_clk_new }, + .devinit = { 0x00000001, nv1a_devinit_new }, + .fb = { 0x00000001, nv46_fb_new }, + .gpio = { 0x00000001, nv10_gpio_new }, + .i2c = { 0x00000001, nv04_i2c_new }, + .imem = { 0x00000001, nv40_instmem_new }, + .mc = { 0x00000001, nv44_mc_new }, + .mmu = { 0x00000001, nv44_mmu_new }, + .pci = { 0x00000001, nv4c_pci_new }, + .therm = { 0x00000001, nv40_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, nv04_disp_new }, + .dma = { 0x00000001, nv04_dma_new }, + .fifo = { 0x00000001, nv40_fifo_new }, + .gr = { 0x00000001, nv44_gr_new }, + .mpeg = { 0x00000001, nv44_mpeg_new }, + .pm = { 0x00000001, nv40_pm_new }, + .sw = { 0x00000001, nv10_sw_new }, }; static const struct nvkm_device_chip nv84_chipset = { .name = "G84", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = nv50_bus_new, - .clk = g84_clk_new, - .devinit = g84_devinit_new, - .fb = g84_fb_new, - .fuse = nv50_fuse_new, - .gpio = nv50_gpio_new, - .i2c = nv50_i2c_new, - .imem = nv50_instmem_new, - .mc = g84_mc_new, - .mmu = g84_mmu_new, - .mxm = nv50_mxm_new, - .pci = g84_pci_new, - .therm = g84_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .bsp = g84_bsp_new, - .cipher = g84_cipher_new, - .disp = g84_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = g84_gr_new, - .mpeg = g84_mpeg_new, - .pm = g84_pm_new, - .sw = nv50_sw_new, - .vp = g84_vp_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv50_bus_new }, + .clk = { 0x00000001, g84_clk_new }, + .devinit = { 0x00000001, g84_devinit_new }, + .fb = { 0x00000001, g84_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, nv50_gpio_new }, + .i2c = { 0x00000001, nv50_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, g84_mc_new }, + .mmu = { 0x00000001, g84_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g84_pci_new }, + .therm = { 0x00000001, g84_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .bsp = { 0x00000001, g84_bsp_new }, + .cipher = { 0x00000001, g84_cipher_new }, + .disp = { 0x00000001, g84_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, g84_gr_new }, + .mpeg = { 0x00000001, g84_mpeg_new }, + .pm = { 0x00000001, g84_pm_new }, + .sw = { 0x00000001, nv50_sw_new }, + .vp = { 0x00000001, g84_vp_new }, }; static const struct nvkm_device_chip nv86_chipset = { .name = "G86", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = nv50_bus_new, - .clk = g84_clk_new, - .devinit = g84_devinit_new, - .fb = g84_fb_new, - .fuse = nv50_fuse_new, - .gpio = nv50_gpio_new, - .i2c = nv50_i2c_new, - .imem = nv50_instmem_new, - .mc = g84_mc_new, - .mmu = g84_mmu_new, - .mxm = nv50_mxm_new, - .pci = g84_pci_new, - .therm = g84_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .bsp = g84_bsp_new, - .cipher = g84_cipher_new, - .disp = g84_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = g84_gr_new, - .mpeg = g84_mpeg_new, - .pm = g84_pm_new, - .sw = nv50_sw_new, - .vp = g84_vp_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv50_bus_new }, + .clk = { 0x00000001, g84_clk_new }, + .devinit = { 0x00000001, g84_devinit_new }, + .fb = { 0x00000001, g84_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, nv50_gpio_new }, + .i2c = { 0x00000001, nv50_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, g84_mc_new }, + .mmu = { 0x00000001, g84_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g84_pci_new }, + .therm = { 0x00000001, g84_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .bsp = { 0x00000001, g84_bsp_new }, + .cipher = { 0x00000001, g84_cipher_new }, + .disp = { 0x00000001, g84_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, g84_gr_new }, + .mpeg = { 0x00000001, g84_mpeg_new }, + .pm = { 0x00000001, g84_pm_new }, + .sw = { 0x00000001, nv50_sw_new }, + .vp = { 0x00000001, g84_vp_new }, }; static const struct nvkm_device_chip nv92_chipset = { .name = "G92", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = nv50_bus_new, - .clk = g84_clk_new, - .devinit = g84_devinit_new, - .fb = g84_fb_new, - .fuse = nv50_fuse_new, - .gpio = nv50_gpio_new, - .i2c = nv50_i2c_new, - .imem = nv50_instmem_new, - .mc = g84_mc_new, - .mmu = g84_mmu_new, - .mxm = nv50_mxm_new, - .pci = g92_pci_new, - .therm = g84_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .bsp = g84_bsp_new, - .cipher = g84_cipher_new, - .disp = g84_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = g84_gr_new, - .mpeg = g84_mpeg_new, - .pm = g84_pm_new, - .sw = nv50_sw_new, - .vp = g84_vp_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, nv50_bus_new }, + .clk = { 0x00000001, g84_clk_new }, + .devinit = { 0x00000001, g84_devinit_new }, + .fb = { 0x00000001, g84_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, nv50_gpio_new }, + .i2c = { 0x00000001, nv50_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, g84_mc_new }, + .mmu = { 0x00000001, g84_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g92_pci_new }, + .therm = { 0x00000001, g84_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .bsp = { 0x00000001, g84_bsp_new }, + .cipher = { 0x00000001, g84_cipher_new }, + .disp = { 0x00000001, g84_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, g84_gr_new }, + .mpeg = { 0x00000001, g84_mpeg_new }, + .pm = { 0x00000001, g84_pm_new }, + .sw = { 0x00000001, nv50_sw_new }, + .vp = { 0x00000001, g84_vp_new }, }; static const struct nvkm_device_chip nv94_chipset = { .name = "G94", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = g94_bus_new, - .clk = g84_clk_new, - .devinit = g84_devinit_new, - .fb = g84_fb_new, - .fuse = nv50_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .imem = nv50_instmem_new, - .mc = g84_mc_new, - .mmu = g84_mmu_new, - .mxm = nv50_mxm_new, - .pci = g94_pci_new, - .therm = g84_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .bsp = g84_bsp_new, - .cipher = g84_cipher_new, - .disp = g94_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = g84_gr_new, - .mpeg = g84_mpeg_new, - .pm = g84_pm_new, - .sw = nv50_sw_new, - .vp = g84_vp_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, g94_bus_new }, + .clk = { 0x00000001, g84_clk_new }, + .devinit = { 0x00000001, g84_devinit_new }, + .fb = { 0x00000001, g84_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, g84_mc_new }, + .mmu = { 0x00000001, g84_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g94_pci_new }, + .therm = { 0x00000001, g84_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .bsp = { 0x00000001, g84_bsp_new }, + .cipher = { 0x00000001, g84_cipher_new }, + .disp = { 0x00000001, g94_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, g84_gr_new }, + .mpeg = { 0x00000001, g84_mpeg_new }, + .pm = { 0x00000001, g84_pm_new }, + .sw = { 0x00000001, nv50_sw_new }, + .vp = { 0x00000001, g84_vp_new }, }; static const struct nvkm_device_chip nv96_chipset = { .name = "G96", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = g94_bus_new, - .clk = g84_clk_new, - .devinit = g84_devinit_new, - .fb = g84_fb_new, - .fuse = nv50_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .imem = nv50_instmem_new, - .mc = g84_mc_new, - .mmu = g84_mmu_new, - .mxm = nv50_mxm_new, - .pci = g94_pci_new, - .therm = g84_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .bsp = g84_bsp_new, - .cipher = g84_cipher_new, - .disp = g94_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = g84_gr_new, - .mpeg = g84_mpeg_new, - .pm = g84_pm_new, - .sw = nv50_sw_new, - .vp = g84_vp_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, g94_bus_new }, + .clk = { 0x00000001, g84_clk_new }, + .devinit = { 0x00000001, g84_devinit_new }, + .fb = { 0x00000001, g84_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, g84_mc_new }, + .mmu = { 0x00000001, g84_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g94_pci_new }, + .therm = { 0x00000001, g84_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .bsp = { 0x00000001, g84_bsp_new }, + .cipher = { 0x00000001, g84_cipher_new }, + .disp = { 0x00000001, g94_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, g84_gr_new }, + .mpeg = { 0x00000001, g84_mpeg_new }, + .pm = { 0x00000001, g84_pm_new }, + .sw = { 0x00000001, nv50_sw_new }, + .vp = { 0x00000001, g84_vp_new }, }; static const struct nvkm_device_chip nv98_chipset = { .name = "G98", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = g94_bus_new, - .clk = g84_clk_new, - .devinit = g98_devinit_new, - .fb = g84_fb_new, - .fuse = nv50_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .imem = nv50_instmem_new, - .mc = g98_mc_new, - .mmu = g84_mmu_new, - .mxm = nv50_mxm_new, - .pci = g94_pci_new, - .therm = g84_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = g94_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = g84_gr_new, - .mspdec = g98_mspdec_new, - .msppp = g98_msppp_new, - .msvld = g98_msvld_new, - .pm = g84_pm_new, - .sec = g98_sec_new, - .sw = nv50_sw_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, g94_bus_new }, + .clk = { 0x00000001, g84_clk_new }, + .devinit = { 0x00000001, g98_devinit_new }, + .fb = { 0x00000001, g84_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, g98_mc_new }, + .mmu = { 0x00000001, g84_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g94_pci_new }, + .therm = { 0x00000001, g84_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, g94_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, g84_gr_new }, + .mspdec = { 0x00000001, g98_mspdec_new }, + .msppp = { 0x00000001, g98_msppp_new }, + .msvld = { 0x00000001, g98_msvld_new }, + .pm = { 0x00000001, g84_pm_new }, + .sec = { 0x00000001, g98_sec_new }, + .sw = { 0x00000001, nv50_sw_new }, }; static const struct nvkm_device_chip nva0_chipset = { .name = "GT200", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = g94_bus_new, - .clk = g84_clk_new, - .devinit = g84_devinit_new, - .fb = g84_fb_new, - .fuse = nv50_fuse_new, - .gpio = g94_gpio_new, - .i2c = nv50_i2c_new, - .imem = nv50_instmem_new, - .mc = g84_mc_new, - .mmu = g84_mmu_new, - .mxm = nv50_mxm_new, - .pci = g94_pci_new, - .therm = g84_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .bsp = g84_bsp_new, - .cipher = g84_cipher_new, - .disp = gt200_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = gt200_gr_new, - .mpeg = g84_mpeg_new, - .pm = gt200_pm_new, - .sw = nv50_sw_new, - .vp = g84_vp_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, g94_bus_new }, + .clk = { 0x00000001, g84_clk_new }, + .devinit = { 0x00000001, g84_devinit_new }, + .fb = { 0x00000001, g84_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, nv50_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, g84_mc_new }, + .mmu = { 0x00000001, g84_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g94_pci_new }, + .therm = { 0x00000001, g84_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .bsp = { 0x00000001, g84_bsp_new }, + .cipher = { 0x00000001, g84_cipher_new }, + .disp = { 0x00000001, gt200_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, gt200_gr_new }, + .mpeg = { 0x00000001, g84_mpeg_new }, + .pm = { 0x00000001, gt200_pm_new }, + .sw = { 0x00000001, nv50_sw_new }, + .vp = { 0x00000001, g84_vp_new }, }; static const struct nvkm_device_chip nva3_chipset = { .name = "GT215", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = g94_bus_new, - .clk = gt215_clk_new, - .devinit = gt215_devinit_new, - .fb = gt215_fb_new, - .fuse = nv50_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .imem = nv50_instmem_new, - .mc = gt215_mc_new, - .mmu = g84_mmu_new, - .mxm = nv50_mxm_new, - .pci = g94_pci_new, - .pmu = gt215_pmu_new, - .therm = gt215_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .ce[0] = gt215_ce_new, - .disp = gt215_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = gt215_gr_new, - .mpeg = g84_mpeg_new, - .mspdec = gt215_mspdec_new, - .msppp = gt215_msppp_new, - .msvld = gt215_msvld_new, - .pm = gt215_pm_new, - .sw = nv50_sw_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, g94_bus_new }, + .clk = { 0x00000001, gt215_clk_new }, + .devinit = { 0x00000001, gt215_devinit_new }, + .fb = { 0x00000001, gt215_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, gt215_mc_new }, + .mmu = { 0x00000001, g84_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g94_pci_new }, + .pmu = { 0x00000001, gt215_pmu_new }, + .therm = { 0x00000001, gt215_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .ce = { 0x00000001, gt215_ce_new }, + .disp = { 0x00000001, gt215_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, gt215_gr_new }, + .mpeg = { 0x00000001, g84_mpeg_new }, + .mspdec = { 0x00000001, gt215_mspdec_new }, + .msppp = { 0x00000001, gt215_msppp_new }, + .msvld = { 0x00000001, gt215_msvld_new }, + .pm = { 0x00000001, gt215_pm_new }, + .sw = { 0x00000001, nv50_sw_new }, }; static const struct nvkm_device_chip nva5_chipset = { .name = "GT216", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = g94_bus_new, - .clk = gt215_clk_new, - .devinit = gt215_devinit_new, - .fb = gt215_fb_new, - .fuse = nv50_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .imem = nv50_instmem_new, - .mc = gt215_mc_new, - .mmu = g84_mmu_new, - .mxm = nv50_mxm_new, - .pci = g94_pci_new, - .pmu = gt215_pmu_new, - .therm = gt215_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .ce[0] = gt215_ce_new, - .disp = gt215_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = gt215_gr_new, - .mspdec = gt215_mspdec_new, - .msppp = gt215_msppp_new, - .msvld = gt215_msvld_new, - .pm = gt215_pm_new, - .sw = nv50_sw_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, g94_bus_new }, + .clk = { 0x00000001, gt215_clk_new }, + .devinit = { 0x00000001, gt215_devinit_new }, + .fb = { 0x00000001, gt215_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, gt215_mc_new }, + .mmu = { 0x00000001, g84_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g94_pci_new }, + .pmu = { 0x00000001, gt215_pmu_new }, + .therm = { 0x00000001, gt215_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .ce = { 0x00000001, gt215_ce_new }, + .disp = { 0x00000001, gt215_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, gt215_gr_new }, + .mspdec = { 0x00000001, gt215_mspdec_new }, + .msppp = { 0x00000001, gt215_msppp_new }, + .msvld = { 0x00000001, gt215_msvld_new }, + .pm = { 0x00000001, gt215_pm_new }, + .sw = { 0x00000001, nv50_sw_new }, }; static const struct nvkm_device_chip nva8_chipset = { .name = "GT218", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = g94_bus_new, - .clk = gt215_clk_new, - .devinit = gt215_devinit_new, - .fb = gt215_fb_new, - .fuse = nv50_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .imem = nv50_instmem_new, - .mc = gt215_mc_new, - .mmu = g84_mmu_new, - .mxm = nv50_mxm_new, - .pci = g94_pci_new, - .pmu = gt215_pmu_new, - .therm = gt215_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .ce[0] = gt215_ce_new, - .disp = gt215_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = gt215_gr_new, - .mspdec = gt215_mspdec_new, - .msppp = gt215_msppp_new, - .msvld = gt215_msvld_new, - .pm = gt215_pm_new, - .sw = nv50_sw_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, g94_bus_new }, + .clk = { 0x00000001, gt215_clk_new }, + .devinit = { 0x00000001, gt215_devinit_new }, + .fb = { 0x00000001, gt215_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, gt215_mc_new }, + .mmu = { 0x00000001, g84_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g94_pci_new }, + .pmu = { 0x00000001, gt215_pmu_new }, + .therm = { 0x00000001, gt215_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .ce = { 0x00000001, gt215_ce_new }, + .disp = { 0x00000001, gt215_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, gt215_gr_new }, + .mspdec = { 0x00000001, gt215_mspdec_new }, + .msppp = { 0x00000001, gt215_msppp_new }, + .msvld = { 0x00000001, gt215_msvld_new }, + .pm = { 0x00000001, gt215_pm_new }, + .sw = { 0x00000001, nv50_sw_new }, }; static const struct nvkm_device_chip nvaa_chipset = { .name = "MCP77/MCP78", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = g94_bus_new, - .clk = mcp77_clk_new, - .devinit = g98_devinit_new, - .fb = mcp77_fb_new, - .fuse = nv50_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .imem = nv50_instmem_new, - .mc = g98_mc_new, - .mmu = mcp77_mmu_new, - .mxm = nv50_mxm_new, - .pci = g94_pci_new, - .therm = g84_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = mcp77_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = gt200_gr_new, - .mspdec = g98_mspdec_new, - .msppp = g98_msppp_new, - .msvld = g98_msvld_new, - .pm = g84_pm_new, - .sec = g98_sec_new, - .sw = nv50_sw_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, g94_bus_new }, + .clk = { 0x00000001, mcp77_clk_new }, + .devinit = { 0x00000001, g98_devinit_new }, + .fb = { 0x00000001, mcp77_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, g98_mc_new }, + .mmu = { 0x00000001, mcp77_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g94_pci_new }, + .therm = { 0x00000001, g84_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, mcp77_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, gt200_gr_new }, + .mspdec = { 0x00000001, g98_mspdec_new }, + .msppp = { 0x00000001, g98_msppp_new }, + .msvld = { 0x00000001, g98_msvld_new }, + .pm = { 0x00000001, g84_pm_new }, + .sec = { 0x00000001, g98_sec_new }, + .sw = { 0x00000001, nv50_sw_new }, }; static const struct nvkm_device_chip nvac_chipset = { .name = "MCP79/MCP7A", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = g94_bus_new, - .clk = mcp77_clk_new, - .devinit = g98_devinit_new, - .fb = mcp77_fb_new, - .fuse = nv50_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .imem = nv50_instmem_new, - .mc = g98_mc_new, - .mmu = mcp77_mmu_new, - .mxm = nv50_mxm_new, - .pci = g94_pci_new, - .therm = g84_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .disp = mcp77_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = mcp79_gr_new, - .mspdec = g98_mspdec_new, - .msppp = g98_msppp_new, - .msvld = g98_msvld_new, - .pm = g84_pm_new, - .sec = g98_sec_new, - .sw = nv50_sw_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, g94_bus_new }, + .clk = { 0x00000001, mcp77_clk_new }, + .devinit = { 0x00000001, g98_devinit_new }, + .fb = { 0x00000001, mcp77_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, g98_mc_new }, + .mmu = { 0x00000001, mcp77_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g94_pci_new }, + .therm = { 0x00000001, g84_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .disp = { 0x00000001, mcp77_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, mcp79_gr_new }, + .mspdec = { 0x00000001, g98_mspdec_new }, + .msppp = { 0x00000001, g98_msppp_new }, + .msvld = { 0x00000001, g98_msvld_new }, + .pm = { 0x00000001, g84_pm_new }, + .sec = { 0x00000001, g98_sec_new }, + .sw = { 0x00000001, nv50_sw_new }, }; static const struct nvkm_device_chip nvaf_chipset = { .name = "MCP89", - .bar = g84_bar_new, - .bios = nvkm_bios_new, - .bus = g94_bus_new, - .clk = gt215_clk_new, - .devinit = mcp89_devinit_new, - .fb = mcp89_fb_new, - .fuse = nv50_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .imem = nv50_instmem_new, - .mc = gt215_mc_new, - .mmu = mcp77_mmu_new, - .mxm = nv50_mxm_new, - .pci = g94_pci_new, - .pmu = gt215_pmu_new, - .therm = gt215_therm_new, - .timer = nv41_timer_new, - .volt = nv40_volt_new, - .ce[0] = gt215_ce_new, - .disp = mcp89_disp_new, - .dma = nv50_dma_new, - .fifo = g84_fifo_new, - .gr = mcp89_gr_new, - .mspdec = gt215_mspdec_new, - .msppp = gt215_msppp_new, - .msvld = mcp89_msvld_new, - .pm = gt215_pm_new, - .sw = nv50_sw_new, + .bar = { 0x00000001, g84_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, g94_bus_new }, + .clk = { 0x00000001, gt215_clk_new }, + .devinit = { 0x00000001, mcp89_devinit_new }, + .fb = { 0x00000001, mcp89_fb_new }, + .fuse = { 0x00000001, nv50_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, gt215_mc_new }, + .mmu = { 0x00000001, mcp77_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, g94_pci_new }, + .pmu = { 0x00000001, gt215_pmu_new }, + .therm = { 0x00000001, gt215_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, nv40_volt_new }, + .ce = { 0x00000001, gt215_ce_new }, + .disp = { 0x00000001, mcp89_disp_new }, + .dma = { 0x00000001, nv50_dma_new }, + .fifo = { 0x00000001, g84_fifo_new }, + .gr = { 0x00000001, mcp89_gr_new }, + .mspdec = { 0x00000001, gt215_mspdec_new }, + .msppp = { 0x00000001, gt215_msppp_new }, + .msvld = { 0x00000001, mcp89_msvld_new }, + .pm = { 0x00000001, gt215_pm_new }, + .sw = { 0x00000001, nv50_sw_new }, }; static const struct nvkm_device_chip nvc0_chipset = { .name = "GF100", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gf100_clk_new, - .devinit = gf100_devinit_new, - .fb = gf100_fb_new, - .fuse = gf100_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .ibus = gf100_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gf100_ltc_new, - .mc = gf100_mc_new, - .mmu = gf100_mmu_new, - .mxm = nv50_mxm_new, - .pci = gf100_pci_new, - .pmu = gf100_pmu_new, - .therm = gt215_therm_new, - .timer = nv41_timer_new, - .volt = gf100_volt_new, - .ce[0] = gf100_ce_new, - .ce[1] = gf100_ce_new, - .disp = gt215_disp_new, - .dma = gf100_dma_new, - .fifo = gf100_fifo_new, - .gr = gf100_gr_new, - .mspdec = gf100_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gf100_msvld_new, - .pm = gf100_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gf100_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gf100_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gf100_ltc_new }, + .mc = { 0x00000001, gf100_mc_new }, + .mmu = { 0x00000001, gf100_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gf100_pci_new }, + .pmu = { 0x00000001, gf100_pmu_new }, + .privring = { 0x00000001, gf100_privring_new }, + .therm = { 0x00000001, gt215_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, gf100_volt_new }, + .ce = { 0x00000003, gf100_ce_new }, + .disp = { 0x00000001, gt215_disp_new }, + .dma = { 0x00000001, gf100_dma_new }, + .fifo = { 0x00000001, gf100_fifo_new }, + .gr = { 0x00000001, gf100_gr_new }, + .mspdec = { 0x00000001, gf100_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gf100_msvld_new }, + .pm = { 0x00000001, gf100_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nvc1_chipset = { .name = "GF108", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gf100_clk_new, - .devinit = gf100_devinit_new, - .fb = gf108_fb_new, - .fuse = gf100_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .ibus = gf100_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gf100_ltc_new, - .mc = gf100_mc_new, - .mmu = gf100_mmu_new, - .mxm = nv50_mxm_new, - .pci = gf106_pci_new, - .pmu = gf100_pmu_new, - .therm = gt215_therm_new, - .timer = nv41_timer_new, - .volt = gf100_volt_new, - .ce[0] = gf100_ce_new, - .disp = gt215_disp_new, - .dma = gf100_dma_new, - .fifo = gf100_fifo_new, - .gr = gf108_gr_new, - .mspdec = gf100_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gf100_msvld_new, - .pm = gf108_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gf100_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gf108_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gf100_ltc_new }, + .mc = { 0x00000001, gf100_mc_new }, + .mmu = { 0x00000001, gf100_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gf106_pci_new }, + .pmu = { 0x00000001, gf100_pmu_new }, + .privring = { 0x00000001, gf100_privring_new }, + .therm = { 0x00000001, gt215_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, gf100_volt_new }, + .ce = { 0x00000001, gf100_ce_new }, + .disp = { 0x00000001, gt215_disp_new }, + .dma = { 0x00000001, gf100_dma_new }, + .fifo = { 0x00000001, gf100_fifo_new }, + .gr = { 0x00000001, gf108_gr_new }, + .mspdec = { 0x00000001, gf100_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gf100_msvld_new }, + .pm = { 0x00000001, gf108_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nvc3_chipset = { .name = "GF106", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gf100_clk_new, - .devinit = gf100_devinit_new, - .fb = gf100_fb_new, - .fuse = gf100_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .ibus = gf100_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gf100_ltc_new, - .mc = gf100_mc_new, - .mmu = gf100_mmu_new, - .mxm = nv50_mxm_new, - .pci = gf106_pci_new, - .pmu = gf100_pmu_new, - .therm = gt215_therm_new, - .timer = nv41_timer_new, - .volt = gf100_volt_new, - .ce[0] = gf100_ce_new, - .disp = gt215_disp_new, - .dma = gf100_dma_new, - .fifo = gf100_fifo_new, - .gr = gf104_gr_new, - .mspdec = gf100_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gf100_msvld_new, - .pm = gf100_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gf100_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gf100_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gf100_ltc_new }, + .mc = { 0x00000001, gf100_mc_new }, + .mmu = { 0x00000001, gf100_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gf106_pci_new }, + .pmu = { 0x00000001, gf100_pmu_new }, + .privring = { 0x00000001, gf100_privring_new }, + .therm = { 0x00000001, gt215_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, gf100_volt_new }, + .ce = { 0x00000001, gf100_ce_new }, + .disp = { 0x00000001, gt215_disp_new }, + .dma = { 0x00000001, gf100_dma_new }, + .fifo = { 0x00000001, gf100_fifo_new }, + .gr = { 0x00000001, gf104_gr_new }, + .mspdec = { 0x00000001, gf100_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gf100_msvld_new }, + .pm = { 0x00000001, gf100_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nvc4_chipset = { .name = "GF104", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gf100_clk_new, - .devinit = gf100_devinit_new, - .fb = gf100_fb_new, - .fuse = gf100_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .ibus = gf100_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gf100_ltc_new, - .mc = gf100_mc_new, - .mmu = gf100_mmu_new, - .mxm = nv50_mxm_new, - .pci = gf100_pci_new, - .pmu = gf100_pmu_new, - .therm = gt215_therm_new, - .timer = nv41_timer_new, - .volt = gf100_volt_new, - .ce[0] = gf100_ce_new, - .ce[1] = gf100_ce_new, - .disp = gt215_disp_new, - .dma = gf100_dma_new, - .fifo = gf100_fifo_new, - .gr = gf104_gr_new, - .mspdec = gf100_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gf100_msvld_new, - .pm = gf100_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gf100_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gf100_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gf100_ltc_new }, + .mc = { 0x00000001, gf100_mc_new }, + .mmu = { 0x00000001, gf100_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gf100_pci_new }, + .pmu = { 0x00000001, gf100_pmu_new }, + .privring = { 0x00000001, gf100_privring_new }, + .therm = { 0x00000001, gt215_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, gf100_volt_new }, + .ce = { 0x00000003, gf100_ce_new }, + .disp = { 0x00000001, gt215_disp_new }, + .dma = { 0x00000001, gf100_dma_new }, + .fifo = { 0x00000001, gf100_fifo_new }, + .gr = { 0x00000001, gf104_gr_new }, + .mspdec = { 0x00000001, gf100_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gf100_msvld_new }, + .pm = { 0x00000001, gf100_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nvc8_chipset = { .name = "GF110", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gf100_clk_new, - .devinit = gf100_devinit_new, - .fb = gf100_fb_new, - .fuse = gf100_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .ibus = gf100_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gf100_ltc_new, - .mc = gf100_mc_new, - .mmu = gf100_mmu_new, - .mxm = nv50_mxm_new, - .pci = gf100_pci_new, - .pmu = gf100_pmu_new, - .therm = gt215_therm_new, - .timer = nv41_timer_new, - .volt = gf100_volt_new, - .ce[0] = gf100_ce_new, - .ce[1] = gf100_ce_new, - .disp = gt215_disp_new, - .dma = gf100_dma_new, - .fifo = gf100_fifo_new, - .gr = gf110_gr_new, - .mspdec = gf100_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gf100_msvld_new, - .pm = gf100_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gf100_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gf100_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gf100_ltc_new }, + .mc = { 0x00000001, gf100_mc_new }, + .mmu = { 0x00000001, gf100_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gf100_pci_new }, + .pmu = { 0x00000001, gf100_pmu_new }, + .privring = { 0x00000001, gf100_privring_new }, + .therm = { 0x00000001, gt215_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, gf100_volt_new }, + .ce = { 0x00000003, gf100_ce_new }, + .disp = { 0x00000001, gt215_disp_new }, + .dma = { 0x00000001, gf100_dma_new }, + .fifo = { 0x00000001, gf100_fifo_new }, + .gr = { 0x00000001, gf110_gr_new }, + .mspdec = { 0x00000001, gf100_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gf100_msvld_new }, + .pm = { 0x00000001, gf100_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nvce_chipset = { .name = "GF114", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gf100_clk_new, - .devinit = gf100_devinit_new, - .fb = gf100_fb_new, - .fuse = gf100_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .ibus = gf100_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gf100_ltc_new, - .mc = gf100_mc_new, - .mmu = gf100_mmu_new, - .mxm = nv50_mxm_new, - .pci = gf100_pci_new, - .pmu = gf100_pmu_new, - .therm = gt215_therm_new, - .timer = nv41_timer_new, - .volt = gf100_volt_new, - .ce[0] = gf100_ce_new, - .ce[1] = gf100_ce_new, - .disp = gt215_disp_new, - .dma = gf100_dma_new, - .fifo = gf100_fifo_new, - .gr = gf104_gr_new, - .mspdec = gf100_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gf100_msvld_new, - .pm = gf100_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gf100_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gf100_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gf100_ltc_new }, + .mc = { 0x00000001, gf100_mc_new }, + .mmu = { 0x00000001, gf100_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gf100_pci_new }, + .pmu = { 0x00000001, gf100_pmu_new }, + .privring = { 0x00000001, gf100_privring_new }, + .therm = { 0x00000001, gt215_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, gf100_volt_new }, + .ce = { 0x00000003, gf100_ce_new }, + .disp = { 0x00000001, gt215_disp_new }, + .dma = { 0x00000001, gf100_dma_new }, + .fifo = { 0x00000001, gf100_fifo_new }, + .gr = { 0x00000001, gf104_gr_new }, + .mspdec = { 0x00000001, gf100_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gf100_msvld_new }, + .pm = { 0x00000001, gf100_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nvcf_chipset = { .name = "GF116", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gf100_clk_new, - .devinit = gf100_devinit_new, - .fb = gf100_fb_new, - .fuse = gf100_fuse_new, - .gpio = g94_gpio_new, - .i2c = g94_i2c_new, - .ibus = gf100_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gf100_ltc_new, - .mc = gf100_mc_new, - .mmu = gf100_mmu_new, - .mxm = nv50_mxm_new, - .pci = gf106_pci_new, - .pmu = gf100_pmu_new, - .therm = gt215_therm_new, - .timer = nv41_timer_new, - .volt = gf100_volt_new, - .ce[0] = gf100_ce_new, - .disp = gt215_disp_new, - .dma = gf100_dma_new, - .fifo = gf100_fifo_new, - .gr = gf104_gr_new, - .mspdec = gf100_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gf100_msvld_new, - .pm = gf100_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gf100_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gf100_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, g94_gpio_new }, + .i2c = { 0x00000001, g94_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gf100_ltc_new }, + .mc = { 0x00000001, gf100_mc_new }, + .mmu = { 0x00000001, gf100_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gf106_pci_new }, + .pmu = { 0x00000001, gf100_pmu_new }, + .privring = { 0x00000001, gf100_privring_new }, + .therm = { 0x00000001, gt215_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, gf100_volt_new }, + .ce = { 0x00000001, gf100_ce_new }, + .disp = { 0x00000001, gt215_disp_new }, + .dma = { 0x00000001, gf100_dma_new }, + .fifo = { 0x00000001, gf100_fifo_new }, + .gr = { 0x00000001, gf104_gr_new }, + .mspdec = { 0x00000001, gf100_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gf100_msvld_new }, + .pm = { 0x00000001, gf100_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nvd7_chipset = { .name = "GF117", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gf100_clk_new, - .devinit = gf100_devinit_new, - .fb = gf100_fb_new, - .fuse = gf100_fuse_new, - .gpio = gf119_gpio_new, - .i2c = gf117_i2c_new, - .ibus = gf117_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gf100_ltc_new, - .mc = gf100_mc_new, - .mmu = gf100_mmu_new, - .mxm = nv50_mxm_new, - .pci = gf106_pci_new, - .therm = gf119_therm_new, - .timer = nv41_timer_new, - .volt = gf117_volt_new, - .ce[0] = gf100_ce_new, - .disp = gf119_disp_new, - .dma = gf119_dma_new, - .fifo = gf100_fifo_new, - .gr = gf117_gr_new, - .mspdec = gf100_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gf100_msvld_new, - .pm = gf117_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gf100_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gf100_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, gf119_gpio_new }, + .i2c = { 0x00000001, gf117_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gf100_ltc_new }, + .mc = { 0x00000001, gf100_mc_new }, + .mmu = { 0x00000001, gf100_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gf106_pci_new }, + .privring = { 0x00000001, gf117_privring_new }, + .therm = { 0x00000001, gf119_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, gf117_volt_new }, + .ce = { 0x00000001, gf100_ce_new }, + .disp = { 0x00000001, gf119_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gf100_fifo_new }, + .gr = { 0x00000001, gf117_gr_new }, + .mspdec = { 0x00000001, gf100_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gf100_msvld_new }, + .pm = { 0x00000001, gf117_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nvd9_chipset = { .name = "GF119", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gf100_clk_new, - .devinit = gf100_devinit_new, - .fb = gf100_fb_new, - .fuse = gf100_fuse_new, - .gpio = gf119_gpio_new, - .i2c = gf119_i2c_new, - .ibus = gf117_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gf100_ltc_new, - .mc = gf100_mc_new, - .mmu = gf100_mmu_new, - .mxm = nv50_mxm_new, - .pci = gf106_pci_new, - .pmu = gf119_pmu_new, - .therm = gf119_therm_new, - .timer = nv41_timer_new, - .volt = gf100_volt_new, - .ce[0] = gf100_ce_new, - .disp = gf119_disp_new, - .dma = gf119_dma_new, - .fifo = gf100_fifo_new, - .gr = gf119_gr_new, - .mspdec = gf100_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gf100_msvld_new, - .pm = gf117_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gf100_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gf100_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, gf119_gpio_new }, + .i2c = { 0x00000001, gf119_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gf100_ltc_new }, + .mc = { 0x00000001, gf100_mc_new }, + .mmu = { 0x00000001, gf100_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gf106_pci_new }, + .pmu = { 0x00000001, gf119_pmu_new }, + .privring = { 0x00000001, gf117_privring_new }, + .therm = { 0x00000001, gf119_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .volt = { 0x00000001, gf100_volt_new }, + .ce = { 0x00000001, gf100_ce_new }, + .disp = { 0x00000001, gf119_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gf100_fifo_new }, + .gr = { 0x00000001, gf119_gr_new }, + .mspdec = { 0x00000001, gf100_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gf100_msvld_new }, + .pm = { 0x00000001, gf117_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nve4_chipset = { .name = "GK104", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gk104_clk_new, - .devinit = gf100_devinit_new, - .fb = gk104_fb_new, - .fuse = gf100_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gk104_i2c_new, - .ibus = gk104_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gk104_ltc_new, - .mc = gk104_mc_new, - .mmu = gk104_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gk104_pmu_new, - .therm = gk104_therm_new, - .timer = nv41_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gk104_ce_new, - .ce[1] = gk104_ce_new, - .ce[2] = gk104_ce_new, - .disp = gk104_disp_new, - .dma = gf119_dma_new, - .fifo = gk104_fifo_new, - .gr = gk104_gr_new, - .mspdec = gk104_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gk104_msvld_new, - .pm = gk104_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gk104_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gk104_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gk104_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gk104_ltc_new }, + .mc = { 0x00000001, gk104_mc_new }, + .mmu = { 0x00000001, gk104_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gk104_pmu_new }, + .privring = { 0x00000001, gk104_privring_new }, + .therm = { 0x00000001, gk104_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000007, gk104_ce_new }, + .disp = { 0x00000001, gk104_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gk104_fifo_new }, + .gr = { 0x00000001, gk104_gr_new }, + .mspdec = { 0x00000001, gk104_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gk104_msvld_new }, + .pm = { 0x00000001, gk104_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nve6_chipset = { .name = "GK106", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gk104_clk_new, - .devinit = gf100_devinit_new, - .fb = gk104_fb_new, - .fuse = gf100_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gk104_i2c_new, - .ibus = gk104_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gk104_ltc_new, - .mc = gk104_mc_new, - .mmu = gk104_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gk104_pmu_new, - .therm = gk104_therm_new, - .timer = nv41_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gk104_ce_new, - .ce[1] = gk104_ce_new, - .ce[2] = gk104_ce_new, - .disp = gk104_disp_new, - .dma = gf119_dma_new, - .fifo = gk104_fifo_new, - .gr = gk104_gr_new, - .mspdec = gk104_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gk104_msvld_new, - .pm = gk104_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gk104_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gk104_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gk104_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gk104_ltc_new }, + .mc = { 0x00000001, gk104_mc_new }, + .mmu = { 0x00000001, gk104_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gk104_pmu_new }, + .privring = { 0x00000001, gk104_privring_new }, + .therm = { 0x00000001, gk104_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000007, gk104_ce_new }, + .disp = { 0x00000001, gk104_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gk104_fifo_new }, + .gr = { 0x00000001, gk104_gr_new }, + .mspdec = { 0x00000001, gk104_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gk104_msvld_new }, + .pm = { 0x00000001, gk104_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nve7_chipset = { .name = "GK107", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gk104_clk_new, - .devinit = gf100_devinit_new, - .fb = gk104_fb_new, - .fuse = gf100_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gk104_i2c_new, - .ibus = gk104_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gk104_ltc_new, - .mc = gk104_mc_new, - .mmu = gk104_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gk104_pmu_new, - .therm = gk104_therm_new, - .timer = nv41_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gk104_ce_new, - .ce[1] = gk104_ce_new, - .ce[2] = gk104_ce_new, - .disp = gk104_disp_new, - .dma = gf119_dma_new, - .fifo = gk104_fifo_new, - .gr = gk104_gr_new, - .mspdec = gk104_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gk104_msvld_new, - .pm = gk104_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gk104_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gk104_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gk104_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gk104_ltc_new }, + .mc = { 0x00000001, gk104_mc_new }, + .mmu = { 0x00000001, gk104_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gk104_pmu_new }, + .privring = { 0x00000001, gk104_privring_new }, + .therm = { 0x00000001, gk104_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000007, gk104_ce_new }, + .disp = { 0x00000001, gk104_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gk104_fifo_new }, + .gr = { 0x00000001, gk104_gr_new }, + .mspdec = { 0x00000001, gk104_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gk104_msvld_new }, + .pm = { 0x00000001, gk104_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nvea_chipset = { .name = "GK20A", - .bar = gk20a_bar_new, - .bus = gf100_bus_new, - .clk = gk20a_clk_new, - .fb = gk20a_fb_new, - .fuse = gf100_fuse_new, - .ibus = gk20a_ibus_new, - .imem = gk20a_instmem_new, - .ltc = gk104_ltc_new, - .mc = gk20a_mc_new, - .mmu = gk20a_mmu_new, - .pmu = gk20a_pmu_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .volt = gk20a_volt_new, - .ce[2] = gk104_ce_new, - .dma = gf119_dma_new, - .fifo = gk20a_fifo_new, - .gr = gk20a_gr_new, - .pm = gk104_pm_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gk20a_bar_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gk20a_clk_new }, + .fb = { 0x00000001, gk20a_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .imem = { 0x00000001, gk20a_instmem_new }, + .ltc = { 0x00000001, gk104_ltc_new }, + .mc = { 0x00000001, gk20a_mc_new }, + .mmu = { 0x00000001, gk20a_mmu_new }, + .pmu = { 0x00000001, gk20a_pmu_new }, + .privring = { 0x00000001, gk20a_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk20a_volt_new }, + .ce = { 0x00000004, gk104_ce_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gk20a_fifo_new }, + .gr = { 0x00000001, gk20a_gr_new }, + .pm = { 0x00000001, gk104_pm_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nvf0_chipset = { .name = "GK110", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gk104_clk_new, - .devinit = gf100_devinit_new, - .fb = gk110_fb_new, - .fuse = gf100_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gk110_i2c_new, - .ibus = gk104_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gk104_ltc_new, - .mc = gk104_mc_new, - .mmu = gk104_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gk110_pmu_new, - .therm = gk104_therm_new, - .timer = nv41_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gk104_ce_new, - .ce[1] = gk104_ce_new, - .ce[2] = gk104_ce_new, - .disp = gk110_disp_new, - .dma = gf119_dma_new, - .fifo = gk110_fifo_new, - .gr = gk110_gr_new, - .mspdec = gk104_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gk104_msvld_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gk104_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gk110_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gk110_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gk104_ltc_new }, + .mc = { 0x00000001, gk104_mc_new }, + .mmu = { 0x00000001, gk104_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gk110_pmu_new }, + .privring = { 0x00000001, gk104_privring_new }, + .therm = { 0x00000001, gk104_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000007, gk104_ce_new }, + .disp = { 0x00000001, gk110_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gk110_fifo_new }, + .gr = { 0x00000001, gk110_gr_new }, + .mspdec = { 0x00000001, gk104_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gk104_msvld_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nvf1_chipset = { .name = "GK110B", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gk104_clk_new, - .devinit = gf100_devinit_new, - .fb = gk110_fb_new, - .fuse = gf100_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gk110_i2c_new, - .ibus = gk104_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gk104_ltc_new, - .mc = gk104_mc_new, - .mmu = gk104_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gk110_pmu_new, - .therm = gk104_therm_new, - .timer = nv41_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gk104_ce_new, - .ce[1] = gk104_ce_new, - .ce[2] = gk104_ce_new, - .disp = gk110_disp_new, - .dma = gf119_dma_new, - .fifo = gk110_fifo_new, - .gr = gk110b_gr_new, - .mspdec = gk104_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gk104_msvld_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gk104_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gk110_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gk110_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gk104_ltc_new }, + .mc = { 0x00000001, gk104_mc_new }, + .mmu = { 0x00000001, gk104_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gk110_pmu_new }, + .privring = { 0x00000001, gk104_privring_new }, + .therm = { 0x00000001, gk104_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000007, gk104_ce_new }, + .disp = { 0x00000001, gk110_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gk110_fifo_new }, + .gr = { 0x00000001, gk110b_gr_new }, + .mspdec = { 0x00000001, gk104_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gk104_msvld_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv106_chipset = { .name = "GK208B", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gk104_clk_new, - .devinit = gf100_devinit_new, - .fb = gk110_fb_new, - .fuse = gf100_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gk110_i2c_new, - .ibus = gk104_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gk104_ltc_new, - .mc = gk20a_mc_new, - .mmu = gk104_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gk208_pmu_new, - .therm = gk104_therm_new, - .timer = nv41_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gk104_ce_new, - .ce[1] = gk104_ce_new, - .ce[2] = gk104_ce_new, - .disp = gk110_disp_new, - .dma = gf119_dma_new, - .fifo = gk208_fifo_new, - .gr = gk208_gr_new, - .mspdec = gk104_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gk104_msvld_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gk104_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gk110_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gk110_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gk104_ltc_new }, + .mc = { 0x00000001, gk20a_mc_new }, + .mmu = { 0x00000001, gk104_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gk208_pmu_new }, + .privring = { 0x00000001, gk104_privring_new }, + .therm = { 0x00000001, gk104_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000007, gk104_ce_new }, + .disp = { 0x00000001, gk110_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gk208_fifo_new }, + .gr = { 0x00000001, gk208_gr_new }, + .mspdec = { 0x00000001, gk104_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gk104_msvld_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv108_chipset = { .name = "GK208", - .bar = gf100_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gk104_clk_new, - .devinit = gf100_devinit_new, - .fb = gk110_fb_new, - .fuse = gf100_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gk110_i2c_new, - .ibus = gk104_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gk104_ltc_new, - .mc = gk20a_mc_new, - .mmu = gk104_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gk208_pmu_new, - .therm = gk104_therm_new, - .timer = nv41_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gk104_ce_new, - .ce[1] = gk104_ce_new, - .ce[2] = gk104_ce_new, - .disp = gk110_disp_new, - .dma = gf119_dma_new, - .fifo = gk208_fifo_new, - .gr = gk208_gr_new, - .mspdec = gk104_mspdec_new, - .msppp = gf100_msppp_new, - .msvld = gk104_msvld_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gf100_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gk104_clk_new }, + .devinit = { 0x00000001, gf100_devinit_new }, + .fb = { 0x00000001, gk110_fb_new }, + .fuse = { 0x00000001, gf100_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gk110_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gk104_ltc_new }, + .mc = { 0x00000001, gk20a_mc_new }, + .mmu = { 0x00000001, gk104_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gk208_pmu_new }, + .privring = { 0x00000001, gk104_privring_new }, + .therm = { 0x00000001, gk104_therm_new }, + .timer = { 0x00000001, nv41_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000007, gk104_ce_new }, + .disp = { 0x00000001, gk110_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gk208_fifo_new }, + .gr = { 0x00000001, gk208_gr_new }, + .mspdec = { 0x00000001, gk104_mspdec_new }, + .msppp = { 0x00000001, gf100_msppp_new }, + .msvld = { 0x00000001, gk104_msvld_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv117_chipset = { .name = "GM107", - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gk104_clk_new, - .devinit = gm107_devinit_new, - .fb = gm107_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gk110_i2c_new, - .ibus = gk104_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gm107_ltc_new, - .mc = gk20a_mc_new, - .mmu = gk104_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gm107_pmu_new, - .therm = gm107_therm_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gm107_ce_new, - .ce[2] = gm107_ce_new, - .disp = gm107_disp_new, - .dma = gf119_dma_new, - .fifo = gm107_fifo_new, - .gr = gm107_gr_new, - .nvdec[0] = gm107_nvdec_new, - .nvenc[0] = gm107_nvenc_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gk104_clk_new }, + .devinit = { 0x00000001, gm107_devinit_new }, + .fb = { 0x00000001, gm107_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gk110_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gm107_ltc_new }, + .mc = { 0x00000001, gk20a_mc_new }, + .mmu = { 0x00000001, gk104_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gm107_pmu_new }, + .privring = { 0x00000001, gk104_privring_new }, + .therm = { 0x00000001, gm107_therm_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000005, gm107_ce_new }, + .disp = { 0x00000001, gm107_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gm107_fifo_new }, + .gr = { 0x00000001, gm107_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000001, gm107_nvenc_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv118_chipset = { .name = "GM108", - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .clk = gk104_clk_new, - .devinit = gm107_devinit_new, - .fb = gm107_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gk110_i2c_new, - .ibus = gk104_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gm107_ltc_new, - .mc = gk20a_mc_new, - .mmu = gk104_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gm107_pmu_new, - .therm = gm107_therm_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gm107_ce_new, - .ce[2] = gm107_ce_new, - .disp = gm107_disp_new, - .dma = gf119_dma_new, - .fifo = gm107_fifo_new, - .gr = gm107_gr_new, - .sw = gf100_sw_new, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gk104_clk_new }, + .devinit = { 0x00000001, gm107_devinit_new }, + .fb = { 0x00000001, gm107_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gk110_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gm107_ltc_new }, + .mc = { 0x00000001, gk20a_mc_new }, + .mmu = { 0x00000001, gk104_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gm107_pmu_new }, + .privring = { 0x00000001, gk104_privring_new }, + .therm = { 0x00000001, gm107_therm_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000005, gm107_ce_new }, + .disp = { 0x00000001, gm107_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gm107_fifo_new }, + .gr = { 0x00000001, gm107_gr_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv120_chipset = { .name = "GM200", - .acr = gm200_acr_new, - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = gm200_devinit_new, - .fb = gm200_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gm200_ltc_new, - .mc = gk20a_mc_new, - .mmu = gm200_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gm200_pmu_new, - .therm = gm200_therm_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gm200_ce_new, - .ce[1] = gm200_ce_new, - .ce[2] = gm200_ce_new, - .disp = gm200_disp_new, - .dma = gf119_dma_new, - .fifo = gm200_fifo_new, - .gr = gm200_gr_new, - .nvdec[0] = gm107_nvdec_new, - .nvenc[0] = gm107_nvenc_new, - .nvenc[1] = gm107_nvenc_new, - .sw = gf100_sw_new, + .acr = { 0x00000001, gm200_acr_new }, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, gm200_devinit_new }, + .fb = { 0x00000001, gm200_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gm200_ltc_new }, + .mc = { 0x00000001, gk20a_mc_new }, + .mmu = { 0x00000001, gm200_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gm200_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .therm = { 0x00000001, gm200_therm_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000007, gm200_ce_new }, + .disp = { 0x00000001, gm200_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gm200_fifo_new }, + .gr = { 0x00000001, gm200_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000003, gm107_nvenc_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv124_chipset = { .name = "GM204", - .acr = gm200_acr_new, - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = gm200_devinit_new, - .fb = gm200_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gm200_ltc_new, - .mc = gk20a_mc_new, - .mmu = gm200_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gm200_pmu_new, - .therm = gm200_therm_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gm200_ce_new, - .ce[1] = gm200_ce_new, - .ce[2] = gm200_ce_new, - .disp = gm200_disp_new, - .dma = gf119_dma_new, - .fifo = gm200_fifo_new, - .gr = gm200_gr_new, - .nvdec[0] = gm107_nvdec_new, - .nvenc[0] = gm107_nvenc_new, - .nvenc[1] = gm107_nvenc_new, - .sw = gf100_sw_new, + .acr = { 0x00000001, gm200_acr_new }, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, gm200_devinit_new }, + .fb = { 0x00000001, gm200_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gm200_ltc_new }, + .mc = { 0x00000001, gk20a_mc_new }, + .mmu = { 0x00000001, gm200_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gm200_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .therm = { 0x00000001, gm200_therm_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000007, gm200_ce_new }, + .disp = { 0x00000001, gm200_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gm200_fifo_new }, + .gr = { 0x00000001, gm200_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000003, gm107_nvenc_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv126_chipset = { .name = "GM206", - .acr = gm200_acr_new, - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = gm200_devinit_new, - .fb = gm200_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .iccsense = gf100_iccsense_new, - .imem = nv50_instmem_new, - .ltc = gm200_ltc_new, - .mc = gk20a_mc_new, - .mmu = gm200_mmu_new, - .mxm = nv50_mxm_new, - .pci = gk104_pci_new, - .pmu = gm200_pmu_new, - .therm = gm200_therm_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .volt = gk104_volt_new, - .ce[0] = gm200_ce_new, - .ce[1] = gm200_ce_new, - .ce[2] = gm200_ce_new, - .disp = gm200_disp_new, - .dma = gf119_dma_new, - .fifo = gm200_fifo_new, - .gr = gm200_gr_new, - .nvdec[0] = gm107_nvdec_new, - .nvenc[0] = gm107_nvenc_new, - .sw = gf100_sw_new, + .acr = { 0x00000001, gm200_acr_new }, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, gm200_devinit_new }, + .fb = { 0x00000001, gm200_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .iccsense = { 0x00000001, gf100_iccsense_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gm200_ltc_new }, + .mc = { 0x00000001, gk20a_mc_new }, + .mmu = { 0x00000001, gm200_mmu_new }, + .mxm = { 0x00000001, nv50_mxm_new }, + .pci = { 0x00000001, gk104_pci_new }, + .pmu = { 0x00000001, gm200_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .therm = { 0x00000001, gm200_therm_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gk104_volt_new }, + .ce = { 0x00000007, gm200_ce_new }, + .disp = { 0x00000001, gm200_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gm200_fifo_new }, + .gr = { 0x00000001, gm200_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000001, gm107_nvenc_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv12b_chipset = { .name = "GM20B", - .acr = gm20b_acr_new, - .bar = gm20b_bar_new, - .bus = gf100_bus_new, - .clk = gm20b_clk_new, - .fb = gm20b_fb_new, - .fuse = gm107_fuse_new, - .ibus = gk20a_ibus_new, - .imem = gk20a_instmem_new, - .ltc = gm200_ltc_new, - .mc = gk20a_mc_new, - .mmu = gm20b_mmu_new, - .pmu = gm20b_pmu_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[2] = gm200_ce_new, - .volt = gm20b_volt_new, - .dma = gf119_dma_new, - .fifo = gm20b_fifo_new, - .gr = gm20b_gr_new, - .sw = gf100_sw_new, + .acr = { 0x00000001, gm20b_acr_new }, + .bar = { 0x00000001, gm20b_bar_new }, + .bus = { 0x00000001, gf100_bus_new }, + .clk = { 0x00000001, gm20b_clk_new }, + .fb = { 0x00000001, gm20b_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .imem = { 0x00000001, gk20a_instmem_new }, + .ltc = { 0x00000001, gm200_ltc_new }, + .mc = { 0x00000001, gk20a_mc_new }, + .mmu = { 0x00000001, gm20b_mmu_new }, + .pmu = { 0x00000001, gm20b_pmu_new }, + .privring = { 0x00000001, gk20a_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .volt = { 0x00000001, gm20b_volt_new }, + .ce = { 0x00000004, gm200_ce_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gm20b_fifo_new }, + .gr = { 0x00000001, gm20b_gr_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv130_chipset = { .name = "GP100", - .acr = gm200_acr_new, - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = gm200_devinit_new, - .fault = gp100_fault_new, - .fb = gp100_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp100_ltc_new, - .mc = gp100_mc_new, - .mmu = gp100_mmu_new, - .therm = gp100_therm_new, - .pci = gp100_pci_new, - .pmu = gm200_pmu_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[0] = gp100_ce_new, - .ce[1] = gp100_ce_new, - .ce[2] = gp100_ce_new, - .ce[3] = gp100_ce_new, - .ce[4] = gp100_ce_new, - .ce[5] = gp100_ce_new, - .dma = gf119_dma_new, - .disp = gp100_disp_new, - .fifo = gp100_fifo_new, - .gr = gp100_gr_new, - .nvdec[0] = gm107_nvdec_new, - .nvenc[0] = gm107_nvenc_new, - .nvenc[1] = gm107_nvenc_new, - .nvenc[2] = gm107_nvenc_new, - .sw = gf100_sw_new, + .acr = { 0x00000001, gm200_acr_new }, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, gm200_devinit_new }, + .fault = { 0x00000001, gp100_fault_new }, + .fb = { 0x00000001, gp100_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp100_ltc_new }, + .mc = { 0x00000001, gp100_mc_new }, + .mmu = { 0x00000001, gp100_mmu_new }, + .therm = { 0x00000001, gp100_therm_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gm200_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x0000003f, gp100_ce_new }, + .dma = { 0x00000001, gf119_dma_new }, + .disp = { 0x00000001, gp100_disp_new }, + .fifo = { 0x00000001, gp100_fifo_new }, + .gr = { 0x00000001, gp100_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000007, gm107_nvenc_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv132_chipset = { .name = "GP102", - .acr = gp102_acr_new, - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = gm200_devinit_new, - .fault = gp100_fault_new, - .fb = gp102_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp102_ltc_new, - .mc = gp100_mc_new, - .mmu = gp100_mmu_new, - .therm = gp100_therm_new, - .pci = gp100_pci_new, - .pmu = gp102_pmu_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[0] = gp102_ce_new, - .ce[1] = gp102_ce_new, - .ce[2] = gp102_ce_new, - .ce[3] = gp102_ce_new, - .disp = gp102_disp_new, - .dma = gf119_dma_new, - .fifo = gp100_fifo_new, - .gr = gp102_gr_new, - .nvdec[0] = gm107_nvdec_new, - .nvenc[0] = gm107_nvenc_new, - .nvenc[1] = gm107_nvenc_new, - .sec2 = gp102_sec2_new, - .sw = gf100_sw_new, + .acr = { 0x00000001, gp102_acr_new }, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, gm200_devinit_new }, + .fault = { 0x00000001, gp100_fault_new }, + .fb = { 0x00000001, gp102_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp102_ltc_new }, + .mc = { 0x00000001, gp100_mc_new }, + .mmu = { 0x00000001, gp100_mmu_new }, + .therm = { 0x00000001, gp100_therm_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gp102_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x0000000f, gp102_ce_new }, + .disp = { 0x00000001, gp102_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gp100_fifo_new }, + .gr = { 0x00000001, gp102_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000003, gm107_nvenc_new }, + .sec2 = { 0x00000001, gp102_sec2_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv134_chipset = { .name = "GP104", - .acr = gp102_acr_new, - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = gm200_devinit_new, - .fault = gp100_fault_new, - .fb = gp102_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp102_ltc_new, - .mc = gp100_mc_new, - .mmu = gp100_mmu_new, - .therm = gp100_therm_new, - .pci = gp100_pci_new, - .pmu = gp102_pmu_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[0] = gp102_ce_new, - .ce[1] = gp102_ce_new, - .ce[2] = gp102_ce_new, - .ce[3] = gp102_ce_new, - .disp = gp102_disp_new, - .dma = gf119_dma_new, - .fifo = gp100_fifo_new, - .gr = gp104_gr_new, - .nvdec[0] = gm107_nvdec_new, - .nvenc[0] = gm107_nvenc_new, - .nvenc[1] = gm107_nvenc_new, - .sec2 = gp102_sec2_new, - .sw = gf100_sw_new, + .acr = { 0x00000001, gp102_acr_new }, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, gm200_devinit_new }, + .fault = { 0x00000001, gp100_fault_new }, + .fb = { 0x00000001, gp102_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp102_ltc_new }, + .mc = { 0x00000001, gp100_mc_new }, + .mmu = { 0x00000001, gp100_mmu_new }, + .therm = { 0x00000001, gp100_therm_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gp102_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x0000000f, gp102_ce_new }, + .disp = { 0x00000001, gp102_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gp100_fifo_new }, + .gr = { 0x00000001, gp104_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000003, gm107_nvenc_new }, + .sec2 = { 0x00000001, gp102_sec2_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv136_chipset = { .name = "GP106", - .acr = gp102_acr_new, - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = gm200_devinit_new, - .fault = gp100_fault_new, - .fb = gp102_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp102_ltc_new, - .mc = gp100_mc_new, - .mmu = gp100_mmu_new, - .therm = gp100_therm_new, - .pci = gp100_pci_new, - .pmu = gp102_pmu_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[0] = gp102_ce_new, - .ce[1] = gp102_ce_new, - .ce[2] = gp102_ce_new, - .ce[3] = gp102_ce_new, - .disp = gp102_disp_new, - .dma = gf119_dma_new, - .fifo = gp100_fifo_new, - .gr = gp104_gr_new, - .nvdec[0] = gm107_nvdec_new, - .nvenc[0] = gm107_nvenc_new, - .sec2 = gp102_sec2_new, - .sw = gf100_sw_new, + .acr = { 0x00000001, gp102_acr_new }, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, gm200_devinit_new }, + .fault = { 0x00000001, gp100_fault_new }, + .fb = { 0x00000001, gp102_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp102_ltc_new }, + .mc = { 0x00000001, gp100_mc_new }, + .mmu = { 0x00000001, gp100_mmu_new }, + .therm = { 0x00000001, gp100_therm_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gp102_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x0000000f, gp102_ce_new }, + .disp = { 0x00000001, gp102_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gp100_fifo_new }, + .gr = { 0x00000001, gp104_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000001, gm107_nvenc_new }, + .sec2 = { 0x00000001, gp102_sec2_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv137_chipset = { .name = "GP107", - .acr = gp102_acr_new, - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = gm200_devinit_new, - .fault = gp100_fault_new, - .fb = gp102_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp102_ltc_new, - .mc = gp100_mc_new, - .mmu = gp100_mmu_new, - .therm = gp100_therm_new, - .pci = gp100_pci_new, - .pmu = gp102_pmu_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[0] = gp102_ce_new, - .ce[1] = gp102_ce_new, - .ce[2] = gp102_ce_new, - .ce[3] = gp102_ce_new, - .disp = gp102_disp_new, - .dma = gf119_dma_new, - .fifo = gp100_fifo_new, - .gr = gp107_gr_new, - .nvdec[0] = gm107_nvdec_new, - .nvenc[0] = gm107_nvenc_new, - .nvenc[1] = gm107_nvenc_new, - .sec2 = gp102_sec2_new, - .sw = gf100_sw_new, + .acr = { 0x00000001, gp102_acr_new }, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, gm200_devinit_new }, + .fault = { 0x00000001, gp100_fault_new }, + .fb = { 0x00000001, gp102_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp102_ltc_new }, + .mc = { 0x00000001, gp100_mc_new }, + .mmu = { 0x00000001, gp100_mmu_new }, + .therm = { 0x00000001, gp100_therm_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gp102_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x0000000f, gp102_ce_new }, + .disp = { 0x00000001, gp102_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gp100_fifo_new }, + .gr = { 0x00000001, gp107_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000003, gm107_nvenc_new }, + .sec2 = { 0x00000001, gp102_sec2_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv138_chipset = { .name = "GP108", - .acr = gp108_acr_new, - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = gm200_devinit_new, - .fault = gp100_fault_new, - .fb = gp102_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp102_ltc_new, - .mc = gp100_mc_new, - .mmu = gp100_mmu_new, - .therm = gp100_therm_new, - .pci = gp100_pci_new, - .pmu = gp102_pmu_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[0] = gp102_ce_new, - .ce[1] = gp102_ce_new, - .ce[2] = gp102_ce_new, - .ce[3] = gp102_ce_new, - .disp = gp102_disp_new, - .dma = gf119_dma_new, - .fifo = gp100_fifo_new, - .gr = gp108_gr_new, - .nvdec[0] = gm107_nvdec_new, - .sec2 = gp108_sec2_new, - .sw = gf100_sw_new, + .acr = { 0x00000001, gp108_acr_new }, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, gm200_devinit_new }, + .fault = { 0x00000001, gp100_fault_new }, + .fb = { 0x00000001, gp102_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp102_ltc_new }, + .mc = { 0x00000001, gp100_mc_new }, + .mmu = { 0x00000001, gp100_mmu_new }, + .therm = { 0x00000001, gp100_therm_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gp102_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x0000000f, gp102_ce_new }, + .disp = { 0x00000001, gp102_disp_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gp100_fifo_new }, + .gr = { 0x00000001, gp108_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .sec2 = { 0x00000001, gp108_sec2_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv13b_chipset = { .name = "GP10B", - .acr = gp10b_acr_new, - .bar = gm20b_bar_new, - .bus = gf100_bus_new, - .fault = gp10b_fault_new, - .fb = gp10b_fb_new, - .fuse = gm107_fuse_new, - .ibus = gp10b_ibus_new, - .imem = gk20a_instmem_new, - .ltc = gp10b_ltc_new, - .mc = gp10b_mc_new, - .mmu = gp10b_mmu_new, - .pmu = gp10b_pmu_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[0] = gp100_ce_new, - .dma = gf119_dma_new, - .fifo = gp10b_fifo_new, - .gr = gp10b_gr_new, - .sw = gf100_sw_new, + .acr = { 0x00000001, gp10b_acr_new }, + .bar = { 0x00000001, gm20b_bar_new }, + .bus = { 0x00000001, gf100_bus_new }, + .fault = { 0x00000001, gp10b_fault_new }, + .fb = { 0x00000001, gp10b_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .imem = { 0x00000001, gk20a_instmem_new }, + .ltc = { 0x00000001, gp10b_ltc_new }, + .mc = { 0x00000001, gp10b_mc_new }, + .mmu = { 0x00000001, gp10b_mmu_new }, + .pmu = { 0x00000001, gp10b_pmu_new }, + .privring = { 0x00000001, gp10b_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x00000001, gp100_ce_new }, + .dma = { 0x00000001, gf119_dma_new }, + .fifo = { 0x00000001, gp10b_fifo_new }, + .gr = { 0x00000001, gp10b_gr_new }, + .sw = { 0x00000001, gf100_sw_new }, }; static const struct nvkm_device_chip nv140_chipset = { .name = "GV100", - .acr = gp108_acr_new, - .bar = gm107_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = gv100_devinit_new, - .fault = gv100_fault_new, - .fb = gv100_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .gsp = gv100_gsp_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp102_ltc_new, - .mc = gp100_mc_new, - .mmu = gv100_mmu_new, - .pci = gp100_pci_new, - .pmu = gp102_pmu_new, - .therm = gp100_therm_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .disp = gv100_disp_new, - .ce[0] = gv100_ce_new, - .ce[1] = gv100_ce_new, - .ce[2] = gv100_ce_new, - .ce[3] = gv100_ce_new, - .ce[4] = gv100_ce_new, - .ce[5] = gv100_ce_new, - .ce[6] = gv100_ce_new, - .ce[7] = gv100_ce_new, - .ce[8] = gv100_ce_new, - .dma = gv100_dma_new, - .fifo = gv100_fifo_new, - .gr = gv100_gr_new, - .nvdec[0] = gm107_nvdec_new, - .nvenc[0] = gm107_nvenc_new, - .nvenc[1] = gm107_nvenc_new, - .nvenc[2] = gm107_nvenc_new, - .sec2 = gp108_sec2_new, + .acr = { 0x00000001, gp108_acr_new }, + .bar = { 0x00000001, gm107_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, gv100_devinit_new }, + .fault = { 0x00000001, gv100_fault_new }, + .fb = { 0x00000001, gv100_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .gsp = { 0x00000001, gv100_gsp_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp102_ltc_new }, + .mc = { 0x00000001, gp100_mc_new }, + .mmu = { 0x00000001, gv100_mmu_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gp102_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .therm = { 0x00000001, gp100_therm_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x000001ff, gv100_ce_new }, + .disp = { 0x00000001, gv100_disp_new }, + .dma = { 0x00000001, gv100_dma_new }, + .fifo = { 0x00000001, gv100_fifo_new }, + .gr = { 0x00000001, gv100_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000007, gm107_nvenc_new }, + .sec2 = { 0x00000001, gp108_sec2_new }, }; static const struct nvkm_device_chip nv162_chipset = { .name = "TU102", - .acr = tu102_acr_new, - .bar = tu102_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = tu102_devinit_new, - .fault = tu102_fault_new, - .fb = gv100_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .gsp = gv100_gsp_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp102_ltc_new, - .mc = tu102_mc_new, - .mmu = tu102_mmu_new, - .pci = gp100_pci_new, - .pmu = gp102_pmu_new, - .therm = gp100_therm_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[0] = tu102_ce_new, - .ce[1] = tu102_ce_new, - .ce[2] = tu102_ce_new, - .ce[3] = tu102_ce_new, - .ce[4] = tu102_ce_new, - .disp = tu102_disp_new, - .dma = gv100_dma_new, - .fifo = tu102_fifo_new, - .gr = tu102_gr_new, - .nvdec[0] = gm107_nvdec_new, - .nvenc[0] = gm107_nvenc_new, - .sec2 = tu102_sec2_new, + .acr = { 0x00000001, tu102_acr_new }, + .bar = { 0x00000001, tu102_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, tu102_devinit_new }, + .fault = { 0x00000001, tu102_fault_new }, + .fb = { 0x00000001, gv100_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .gsp = { 0x00000001, gv100_gsp_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp102_ltc_new }, + .mc = { 0x00000001, tu102_mc_new }, + .mmu = { 0x00000001, tu102_mmu_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gp102_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .therm = { 0x00000001, gp100_therm_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x0000001f, tu102_ce_new }, + .disp = { 0x00000001, tu102_disp_new }, + .dma = { 0x00000001, gv100_dma_new }, + .fifo = { 0x00000001, tu102_fifo_new }, + .gr = { 0x00000001, tu102_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000001, gm107_nvenc_new }, + .sec2 = { 0x00000001, tu102_sec2_new }, }; static const struct nvkm_device_chip nv164_chipset = { .name = "TU104", - .acr = tu102_acr_new, - .bar = tu102_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = tu102_devinit_new, - .fault = tu102_fault_new, - .fb = gv100_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .gsp = gv100_gsp_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp102_ltc_new, - .mc = tu102_mc_new, - .mmu = tu102_mmu_new, - .pci = gp100_pci_new, - .pmu = gp102_pmu_new, - .therm = gp100_therm_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[0] = tu102_ce_new, - .ce[1] = tu102_ce_new, - .ce[2] = tu102_ce_new, - .ce[3] = tu102_ce_new, - .ce[4] = tu102_ce_new, - .disp = tu102_disp_new, - .dma = gv100_dma_new, - .fifo = tu102_fifo_new, - .gr = tu102_gr_new, - .nvdec[0] = gm107_nvdec_new, - .nvdec[1] = gm107_nvdec_new, - .nvenc[0] = gm107_nvenc_new, - .sec2 = tu102_sec2_new, + .acr = { 0x00000001, tu102_acr_new }, + .bar = { 0x00000001, tu102_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, tu102_devinit_new }, + .fault = { 0x00000001, tu102_fault_new }, + .fb = { 0x00000001, gv100_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .gsp = { 0x00000001, gv100_gsp_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp102_ltc_new }, + .mc = { 0x00000001, tu102_mc_new }, + .mmu = { 0x00000001, tu102_mmu_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gp102_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .therm = { 0x00000001, gp100_therm_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x0000001f, tu102_ce_new }, + .disp = { 0x00000001, tu102_disp_new }, + .dma = { 0x00000001, gv100_dma_new }, + .fifo = { 0x00000001, tu102_fifo_new }, + .gr = { 0x00000001, tu102_gr_new }, + .nvdec = { 0x00000003, gm107_nvdec_new }, + .nvenc = { 0x00000001, gm107_nvenc_new }, + .sec2 = { 0x00000001, tu102_sec2_new }, }; static const struct nvkm_device_chip nv166_chipset = { .name = "TU106", - .acr = tu102_acr_new, - .bar = tu102_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = tu102_devinit_new, - .fault = tu102_fault_new, - .fb = gv100_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .gsp = gv100_gsp_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp102_ltc_new, - .mc = tu102_mc_new, - .mmu = tu102_mmu_new, - .pci = gp100_pci_new, - .pmu = gp102_pmu_new, - .therm = gp100_therm_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[0] = tu102_ce_new, - .ce[1] = tu102_ce_new, - .ce[2] = tu102_ce_new, - .ce[3] = tu102_ce_new, - .ce[4] = tu102_ce_new, - .disp = tu102_disp_new, - .dma = gv100_dma_new, - .fifo = tu102_fifo_new, - .gr = tu102_gr_new, - .nvdec[0] = gm107_nvdec_new, - .nvdec[1] = gm107_nvdec_new, - .nvdec[2] = gm107_nvdec_new, - .nvenc[0] = gm107_nvenc_new, - .sec2 = tu102_sec2_new, + .acr = { 0x00000001, tu102_acr_new }, + .bar = { 0x00000001, tu102_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, tu102_devinit_new }, + .fault = { 0x00000001, tu102_fault_new }, + .fb = { 0x00000001, gv100_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .gsp = { 0x00000001, gv100_gsp_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp102_ltc_new }, + .mc = { 0x00000001, tu102_mc_new }, + .mmu = { 0x00000001, tu102_mmu_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gp102_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .therm = { 0x00000001, gp100_therm_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x0000001f, tu102_ce_new }, + .disp = { 0x00000001, tu102_disp_new }, + .dma = { 0x00000001, gv100_dma_new }, + .fifo = { 0x00000001, tu102_fifo_new }, + .gr = { 0x00000001, tu102_gr_new }, + .nvdec = { 0x00000007, gm107_nvdec_new }, + .nvenc = { 0x00000001, gm107_nvenc_new }, + .sec2 = { 0x00000001, tu102_sec2_new }, }; static const struct nvkm_device_chip nv167_chipset = { .name = "TU117", - .acr = tu102_acr_new, - .bar = tu102_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = tu102_devinit_new, - .fault = tu102_fault_new, - .fb = gv100_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .gsp = gv100_gsp_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp102_ltc_new, - .mc = tu102_mc_new, - .mmu = tu102_mmu_new, - .pci = gp100_pci_new, - .pmu = gp102_pmu_new, - .therm = gp100_therm_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[0] = tu102_ce_new, - .ce[1] = tu102_ce_new, - .ce[2] = tu102_ce_new, - .ce[3] = tu102_ce_new, - .ce[4] = tu102_ce_new, - .disp = tu102_disp_new, - .dma = gv100_dma_new, - .fifo = tu102_fifo_new, - .gr = tu102_gr_new, - .nvdec[0] = gm107_nvdec_new, - .nvenc[0] = gm107_nvenc_new, - .sec2 = tu102_sec2_new, + .acr = { 0x00000001, tu102_acr_new }, + .bar = { 0x00000001, tu102_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, tu102_devinit_new }, + .fault = { 0x00000001, tu102_fault_new }, + .fb = { 0x00000001, gv100_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .gsp = { 0x00000001, gv100_gsp_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp102_ltc_new }, + .mc = { 0x00000001, tu102_mc_new }, + .mmu = { 0x00000001, tu102_mmu_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gp102_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .therm = { 0x00000001, gp100_therm_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x0000001f, tu102_ce_new }, + .disp = { 0x00000001, tu102_disp_new }, + .dma = { 0x00000001, gv100_dma_new }, + .fifo = { 0x00000001, tu102_fifo_new }, + .gr = { 0x00000001, tu102_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000001, gm107_nvenc_new }, + .sec2 = { 0x00000001, tu102_sec2_new }, }; static const struct nvkm_device_chip nv168_chipset = { .name = "TU116", - .acr = tu102_acr_new, - .bar = tu102_bar_new, - .bios = nvkm_bios_new, - .bus = gf100_bus_new, - .devinit = tu102_devinit_new, - .fault = tu102_fault_new, - .fb = gv100_fb_new, - .fuse = gm107_fuse_new, - .gpio = gk104_gpio_new, - .gsp = gv100_gsp_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .ltc = gp102_ltc_new, - .mc = tu102_mc_new, - .mmu = tu102_mmu_new, - .pci = gp100_pci_new, - .pmu = gp102_pmu_new, - .therm = gp100_therm_new, - .timer = gk20a_timer_new, - .top = gk104_top_new, - .ce[0] = tu102_ce_new, - .ce[1] = tu102_ce_new, - .ce[2] = tu102_ce_new, - .ce[3] = tu102_ce_new, - .ce[4] = tu102_ce_new, - .disp = tu102_disp_new, - .dma = gv100_dma_new, - .fifo = tu102_fifo_new, - .gr = tu102_gr_new, - .nvdec[0] = gm107_nvdec_new, - .nvenc[0] = gm107_nvenc_new, - .sec2 = tu102_sec2_new, + .acr = { 0x00000001, tu102_acr_new }, + .bar = { 0x00000001, tu102_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .bus = { 0x00000001, gf100_bus_new }, + .devinit = { 0x00000001, tu102_devinit_new }, + .fault = { 0x00000001, tu102_fault_new }, + .fb = { 0x00000001, gv100_fb_new }, + .fuse = { 0x00000001, gm107_fuse_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .gsp = { 0x00000001, gv100_gsp_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .ltc = { 0x00000001, gp102_ltc_new }, + .mc = { 0x00000001, tu102_mc_new }, + .mmu = { 0x00000001, tu102_mmu_new }, + .pci = { 0x00000001, gp100_pci_new }, + .pmu = { 0x00000001, gp102_pmu_new }, + .privring = { 0x00000001, gm200_privring_new }, + .therm = { 0x00000001, gp100_therm_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, gk104_top_new }, + .ce = { 0x0000001f, tu102_ce_new }, + .disp = { 0x00000001, tu102_disp_new }, + .dma = { 0x00000001, gv100_dma_new }, + .fifo = { 0x00000001, tu102_fifo_new }, + .gr = { 0x00000001, tu102_gr_new }, + .nvdec = { 0x00000001, gm107_nvdec_new }, + .nvenc = { 0x00000001, gm107_nvenc_new }, + .sec2 = { 0x00000001, tu102_sec2_new }, }; static const struct nvkm_device_chip nv170_chipset = { .name = "GA100", - .bar = tu102_bar_new, - .bios = nvkm_bios_new, - .devinit = ga100_devinit_new, - .fb = ga100_fb_new, - .gpio = gk104_gpio_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .mc = ga100_mc_new, - .mmu = tu102_mmu_new, - .pci = gp100_pci_new, - .timer = gk20a_timer_new, + .bar = { 0x00000001, tu102_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .devinit = { 0x00000001, ga100_devinit_new }, + .fb = { 0x00000001, ga100_fb_new }, + .gpio = { 0x00000001, gk104_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, ga100_mc_new }, + .mmu = { 0x00000001, tu102_mmu_new }, + .pci = { 0x00000001, gp100_pci_new }, + .privring = { 0x00000001, gm200_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, ga100_top_new }, }; static const struct nvkm_device_chip nv172_chipset = { .name = "GA102", - .bar = tu102_bar_new, - .bios = nvkm_bios_new, - .devinit = ga100_devinit_new, - .fb = ga102_fb_new, - .gpio = ga102_gpio_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .mc = ga100_mc_new, - .mmu = tu102_mmu_new, - .pci = gp100_pci_new, - .timer = gk20a_timer_new, - .disp = ga102_disp_new, - .dma = gv100_dma_new, + .bar = { 0x00000001, tu102_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .devinit = { 0x00000001, ga100_devinit_new }, + .fb = { 0x00000001, ga102_fb_new }, + .gpio = { 0x00000001, ga102_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, ga100_mc_new }, + .mmu = { 0x00000001, tu102_mmu_new }, + .pci = { 0x00000001, gp100_pci_new }, + .privring = { 0x00000001, gm200_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, ga100_top_new }, + .disp = { 0x00000001, ga102_disp_new }, + .dma = { 0x00000001, gv100_dma_new }, }; static const struct nvkm_device_chip nv174_chipset = { .name = "GA104", - .bar = tu102_bar_new, - .bios = nvkm_bios_new, - .devinit = ga100_devinit_new, - .fb = ga102_fb_new, - .gpio = ga102_gpio_new, - .i2c = gm200_i2c_new, - .ibus = gm200_ibus_new, - .imem = nv50_instmem_new, - .mc = ga100_mc_new, - .mmu = tu102_mmu_new, - .pci = gp100_pci_new, - .timer = gk20a_timer_new, - .disp = ga102_disp_new, - .dma = gv100_dma_new, + .bar = { 0x00000001, tu102_bar_new }, + .bios = { 0x00000001, nvkm_bios_new }, + .devinit = { 0x00000001, ga100_devinit_new }, + .fb = { 0x00000001, ga102_fb_new }, + .gpio = { 0x00000001, ga102_gpio_new }, + .i2c = { 0x00000001, gm200_i2c_new }, + .imem = { 0x00000001, nv50_instmem_new }, + .mc = { 0x00000001, ga100_mc_new }, + .mmu = { 0x00000001, tu102_mmu_new }, + .pci = { 0x00000001, gp100_pci_new }, + .privring = { 0x00000001, gm200_privring_new }, + .timer = { 0x00000001, gk20a_timer_new }, + .top = { 0x00000001, ga100_top_new }, + .disp = { 0x00000001, ga102_disp_new }, + .dma = { 0x00000001, gv100_dma_new }, }; static int @@ -2726,97 +2643,24 @@ nvkm_device_event_func = { }; struct nvkm_subdev * -nvkm_device_subdev(struct nvkm_device *device, int index) +nvkm_device_subdev(struct nvkm_device *device, int type, int inst) { - struct nvkm_engine *engine; - - if (device->disable_mask & (1ULL << index)) - return NULL; - - switch (index) { -#define _(n,p,m) case NVKM_SUBDEV_##n: if (p) return (m); break - _(ACR , device->acr , &device->acr->subdev); - _(BAR , device->bar , &device->bar->subdev); - _(VBIOS , device->bios , &device->bios->subdev); - _(BUS , device->bus , &device->bus->subdev); - _(CLK , device->clk , &device->clk->subdev); - _(DEVINIT , device->devinit , &device->devinit->subdev); - _(FAULT , device->fault , &device->fault->subdev); - _(FB , device->fb , &device->fb->subdev); - _(FUSE , device->fuse , &device->fuse->subdev); - _(GPIO , device->gpio , &device->gpio->subdev); - _(GSP , device->gsp , &device->gsp->subdev); - _(I2C , device->i2c , &device->i2c->subdev); - _(IBUS , device->ibus , device->ibus); - _(ICCSENSE, device->iccsense, &device->iccsense->subdev); - _(INSTMEM , device->imem , &device->imem->subdev); - _(LTC , device->ltc , &device->ltc->subdev); - _(MC , device->mc , &device->mc->subdev); - _(MMU , device->mmu , &device->mmu->subdev); - _(MXM , device->mxm , device->mxm); - _(PCI , device->pci , &device->pci->subdev); - _(PMU , device->pmu , &device->pmu->subdev); - _(THERM , device->therm , &device->therm->subdev); - _(TIMER , device->timer , &device->timer->subdev); - _(TOP , device->top , &device->top->subdev); - _(VOLT , device->volt , &device->volt->subdev); -#undef _ - default: - engine = nvkm_device_engine(device, index); - if (engine) - return &engine->subdev; - break; + struct nvkm_subdev *subdev; + + list_for_each_entry(subdev, &device->subdev, head) { + if (subdev->type == type && subdev->inst == inst) + return subdev; } + return NULL; } struct nvkm_engine * -nvkm_device_engine(struct nvkm_device *device, int index) +nvkm_device_engine(struct nvkm_device *device, int type, int inst) { - if (device->disable_mask & (1ULL << index)) - return NULL; - - switch (index) { -#define _(n,p,m) case NVKM_ENGINE_##n: if (p) return (m); break - _(BSP , device->bsp , device->bsp); - _(CE0 , device->ce[0] , device->ce[0]); - _(CE1 , device->ce[1] , device->ce[1]); - _(CE2 , device->ce[2] , device->ce[2]); - _(CE3 , device->ce[3] , device->ce[3]); - _(CE4 , device->ce[4] , device->ce[4]); - _(CE5 , device->ce[5] , device->ce[5]); - _(CE6 , device->ce[6] , device->ce[6]); - _(CE7 , device->ce[7] , device->ce[7]); - _(CE8 , device->ce[8] , device->ce[8]); - _(CIPHER , device->cipher , device->cipher); - _(DISP , device->disp , &device->disp->engine); - _(DMAOBJ , device->dma , &device->dma->engine); - _(FIFO , device->fifo , &device->fifo->engine); - _(GR , device->gr , &device->gr->engine); - _(IFB , device->ifb , device->ifb); - _(ME , device->me , device->me); - _(MPEG , device->mpeg , device->mpeg); - _(MSENC , device->msenc , device->msenc); - _(MSPDEC , device->mspdec , device->mspdec); - _(MSPPP , device->msppp , device->msppp); - _(MSVLD , device->msvld , device->msvld); - _(NVENC0 , device->nvenc[0], &device->nvenc[0]->engine); - _(NVENC1 , device->nvenc[1], &device->nvenc[1]->engine); - _(NVENC2 , device->nvenc[2], &device->nvenc[2]->engine); - _(NVDEC0 , device->nvdec[0], &device->nvdec[0]->engine); - _(NVDEC1 , device->nvdec[1], &device->nvdec[1]->engine); - _(NVDEC2 , device->nvdec[2], &device->nvdec[2]->engine); - _(PM , device->pm , &device->pm->engine); - _(SEC , device->sec , device->sec); - _(SEC2 , device->sec2 , &device->sec2->engine); - _(SW , device->sw , &device->sw->engine); - _(VIC , device->vic , device->vic); - _(VP , device->vp , device->vp); -#undef _ - default: - WARN_ON(1); - break; - } + struct nvkm_subdev *subdev = nvkm_device_subdev(device, type, inst); + if (subdev && subdev->func == &nvkm_engine) + return container_of(subdev, struct nvkm_engine, subdev); return NULL; } @@ -2825,7 +2669,7 @@ nvkm_device_fini(struct nvkm_device *device, bool suspend) { const char *action = suspend ? "suspend" : "fini"; struct nvkm_subdev *subdev; - int ret, i; + int ret; s64 time; nvdev_trace(device, "%s running...\n", action); @@ -2833,12 +2677,10 @@ nvkm_device_fini(struct nvkm_device *device, bool suspend) nvkm_acpi_fini(device); - for (i = NVKM_SUBDEV_NR - 1; i >= 0; i--) { - if ((subdev = nvkm_device_subdev(device, i))) { - ret = nvkm_subdev_fini(subdev, suspend); - if (ret && suspend) - goto fail; - } + list_for_each_entry_reverse(subdev, &device->subdev, head) { + ret = nvkm_subdev_fini(subdev, suspend); + if (ret && suspend) + goto fail; } nvkm_therm_clkgate_fini(device->therm, suspend); @@ -2851,13 +2693,11 @@ nvkm_device_fini(struct nvkm_device *device, bool suspend) return 0; fail: - do { - if ((subdev = nvkm_device_subdev(device, i))) { - int rret = nvkm_subdev_init(subdev); - if (rret) - nvkm_fatal(subdev, "failed restart, %d\n", ret); - } - } while (++i < NVKM_SUBDEV_NR); + list_for_each_entry_from(subdev, &device->subdev, head) { + int rret = nvkm_subdev_init(subdev); + if (rret) + nvkm_fatal(subdev, "failed restart, %d\n", ret); + } nvdev_trace(device, "%s failed with %d\n", action, ret); return ret; @@ -2867,7 +2707,7 @@ static int nvkm_device_preinit(struct nvkm_device *device) { struct nvkm_subdev *subdev; - int ret, i; + int ret; s64 time; nvdev_trace(device, "preinit running...\n"); @@ -2879,15 +2719,13 @@ nvkm_device_preinit(struct nvkm_device *device) goto fail; } - for (i = 0; i < NVKM_SUBDEV_NR; i++) { - if ((subdev = nvkm_device_subdev(device, i))) { - ret = nvkm_subdev_preinit(subdev); - if (ret) - goto fail; - } + list_for_each_entry(subdev, &device->subdev, head) { + ret = nvkm_subdev_preinit(subdev); + if (ret) + goto fail; } - ret = nvkm_devinit_post(device->devinit, &device->disable_mask); + ret = nvkm_devinit_post(device->devinit); if (ret) goto fail; @@ -2904,7 +2742,7 @@ int nvkm_device_init(struct nvkm_device *device) { struct nvkm_subdev *subdev; - int ret, i; + int ret; s64 time; ret = nvkm_device_preinit(device); @@ -2922,12 +2760,10 @@ nvkm_device_init(struct nvkm_device *device) goto fail; } - for (i = 0; i < NVKM_SUBDEV_NR; i++) { - if ((subdev = nvkm_device_subdev(device, i))) { - ret = nvkm_subdev_init(subdev); - if (ret) - goto fail_subdev; - } + list_for_each_entry(subdev, &device->subdev, head) { + ret = nvkm_subdev_init(subdev); + if (ret) + goto fail_subdev; } nvkm_acpi_init(device); @@ -2938,11 +2774,8 @@ nvkm_device_init(struct nvkm_device *device) return 0; fail_subdev: - do { - if ((subdev = nvkm_device_subdev(device, i))) - nvkm_subdev_fini(subdev, false); - } while (--i >= 0); - + list_for_each_entry_from(subdev, &device->subdev, head) + nvkm_subdev_fini(subdev, false); fail: nvkm_device_fini(device, false); @@ -2954,15 +2787,12 @@ void nvkm_device_del(struct nvkm_device **pdevice) { struct nvkm_device *device = *pdevice; - int i; + struct nvkm_subdev *subdev, *subtmp; if (device) { mutex_lock(&nv_devices_mutex); - device->disable_mask = 0; - for (i = NVKM_SUBDEV_NR - 1; i >= 0; i--) { - struct nvkm_subdev *subdev = - nvkm_device_subdev(device, i); + + list_for_each_entry_safe_reverse(subdev, subtmp, &device->subdev, head) nvkm_subdev_del(&subdev); - } nvkm_event_fini(&device->event); @@ -3021,7 +2851,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, struct nvkm_subdev *subdev; u64 mmio_base, mmio_size; u32 boot0, boot1, strap; - int ret = -EEXIST, i; + int ret = -EEXIST, j; unsigned chipset; mutex_lock(&nv_devices_mutex); @@ -3038,6 +2868,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, device->name = name; list_add_tail(&device->head, &nv_devices); device->debug = nvkm_dbgopt(device->dbgopt, "device"); + INIT_LIST_HEAD(&device->subdev); ret = nvkm_event_init(&nvkm_device_event_func, 1, 1, &device->event); if (ret) @@ -3271,88 +3102,46 @@ nvkm_device_ctor(const struct nvkm_device_func *func, mutex_init(&device->mutex); - for (i = 0; i < NVKM_SUBDEV_NR; i++) { -#define _(s,m) case s: \ - if (device->chip->m && (subdev_mask & (1ULL << (s)))) { \ - ret = device->chip->m(device, (s), &device->m); \ - if (ret) { \ - subdev = nvkm_device_subdev(device, (s)); \ - nvkm_subdev_del(&subdev); \ - device->m = NULL; \ - if (ret != -ENODEV) { \ - nvdev_error(device, "%s ctor failed, %d\n", \ - nvkm_subdev_name[s], ret); \ - goto done; \ - } \ - } \ - } \ - break - switch (i) { - _(NVKM_SUBDEV_ACR , acr); - _(NVKM_SUBDEV_BAR , bar); - _(NVKM_SUBDEV_VBIOS , bios); - _(NVKM_SUBDEV_BUS , bus); - _(NVKM_SUBDEV_CLK , clk); - _(NVKM_SUBDEV_DEVINIT , devinit); - _(NVKM_SUBDEV_FAULT , fault); - _(NVKM_SUBDEV_FB , fb); - _(NVKM_SUBDEV_FUSE , fuse); - _(NVKM_SUBDEV_GPIO , gpio); - _(NVKM_SUBDEV_GSP , gsp); - _(NVKM_SUBDEV_I2C , i2c); - _(NVKM_SUBDEV_IBUS , ibus); - _(NVKM_SUBDEV_ICCSENSE, iccsense); - _(NVKM_SUBDEV_INSTMEM , imem); - _(NVKM_SUBDEV_LTC , ltc); - _(NVKM_SUBDEV_MC , mc); - _(NVKM_SUBDEV_MMU , mmu); - _(NVKM_SUBDEV_MXM , mxm); - _(NVKM_SUBDEV_PCI , pci); - _(NVKM_SUBDEV_PMU , pmu); - _(NVKM_SUBDEV_THERM , therm); - _(NVKM_SUBDEV_TIMER , timer); - _(NVKM_SUBDEV_TOP , top); - _(NVKM_SUBDEV_VOLT , volt); - _(NVKM_ENGINE_BSP , bsp); - _(NVKM_ENGINE_CE0 , ce[0]); - _(NVKM_ENGINE_CE1 , ce[1]); - _(NVKM_ENGINE_CE2 , ce[2]); - _(NVKM_ENGINE_CE3 , ce[3]); - _(NVKM_ENGINE_CE4 , ce[4]); - _(NVKM_ENGINE_CE5 , ce[5]); - _(NVKM_ENGINE_CE6 , ce[6]); - _(NVKM_ENGINE_CE7 , ce[7]); - _(NVKM_ENGINE_CE8 , ce[8]); - _(NVKM_ENGINE_CIPHER , cipher); - _(NVKM_ENGINE_DISP , disp); - _(NVKM_ENGINE_DMAOBJ , dma); - _(NVKM_ENGINE_FIFO , fifo); - _(NVKM_ENGINE_GR , gr); - _(NVKM_ENGINE_IFB , ifb); - _(NVKM_ENGINE_ME , me); - _(NVKM_ENGINE_MPEG , mpeg); - _(NVKM_ENGINE_MSENC , msenc); - _(NVKM_ENGINE_MSPDEC , mspdec); - _(NVKM_ENGINE_MSPPP , msppp); - _(NVKM_ENGINE_MSVLD , msvld); - _(NVKM_ENGINE_NVENC0 , nvenc[0]); - _(NVKM_ENGINE_NVENC1 , nvenc[1]); - _(NVKM_ENGINE_NVENC2 , nvenc[2]); - _(NVKM_ENGINE_NVDEC0 , nvdec[0]); - _(NVKM_ENGINE_NVDEC1 , nvdec[1]); - _(NVKM_ENGINE_NVDEC2 , nvdec[2]); - _(NVKM_ENGINE_PM , pm); - _(NVKM_ENGINE_SEC , sec); - _(NVKM_ENGINE_SEC2 , sec2); - _(NVKM_ENGINE_SW , sw); - _(NVKM_ENGINE_VIC , vic); - _(NVKM_ENGINE_VP , vp); - default: - WARN_ON(1); - continue; - } -#undef _ +#define NVKM_LAYOUT_ONCE(type,data,ptr) \ + if (device->chip->ptr.inst && (subdev_mask & (BIT_ULL(type)))) { \ + WARN_ON(device->chip->ptr.inst != 0x00000001); \ + ret = device->chip->ptr.ctor(device, (type), -1, &device->ptr); \ + subdev = nvkm_device_subdev(device, (type), 0); \ + if (ret) { \ + nvkm_subdev_del(&subdev); \ + device->ptr = NULL; \ + if (ret != -ENODEV) { \ + nvdev_error(device, "%s ctor failed: %d\n", \ + nvkm_subdev_type[(type)], ret); \ + goto done; \ + } \ + } else { \ + subdev->pself = (void **)&device->ptr; \ + } \ + } +#define NVKM_LAYOUT_INST(type,data,ptr,cnt) \ + WARN_ON(device->chip->ptr.inst & ~((1 << ARRAY_SIZE(device->ptr)) - 1)); \ + for (j = 0; device->chip->ptr.inst && j < ARRAY_SIZE(device->ptr); j++) { \ + if ((device->chip->ptr.inst & BIT(j)) && (subdev_mask & BIT_ULL(type))) { \ + int inst = (device->chip->ptr.inst == 1) ? -1 : (j); \ + ret = device->chip->ptr.ctor(device, (type), inst, &device->ptr[j]); \ + subdev = nvkm_device_subdev(device, (type), (j)); \ + if (ret) { \ + nvkm_subdev_del(&subdev); \ + device->ptr[j] = NULL; \ + if (ret != -ENODEV) { \ + nvdev_error(device, "%s%d ctor failed: %d\n", \ + nvkm_subdev_type[(type)], (j), ret); \ + goto done; \ + } \ + } else { \ + subdev->pself = (void **)&device->ptr[j]; \ + } \ + } \ } +#include <core/layout.h> +#undef NVKM_LAYOUT_INST +#undef NVKM_LAYOUT_ONCE ret = 0; done: diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h index 54eab5e04230..93949b3c7214 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h @@ -15,7 +15,6 @@ #include <subdev/gpio.h> #include <subdev/gsp.h> #include <subdev/i2c.h> -#include <subdev/ibus.h> #include <subdev/iccsense.h> #include <subdev/instmem.h> #include <subdev/ltc.h> @@ -24,6 +23,7 @@ #include <subdev/mxm.h> #include <subdev/pci.h> #include <subdev/pmu.h> +#include <subdev/privring.h> #include <subdev/therm.h> #include <subdev/timer.h> #include <subdev/top.h> diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c index 147894798786..fea9d8f2b10c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c @@ -43,15 +43,15 @@ static int nvkm_udevice_info_subdev(struct nvkm_device *device, u64 mthd, u64 *data) { struct nvkm_subdev *subdev; - enum nvkm_devidx subidx; + enum nvkm_subdev_type type; switch (mthd & NV_DEVICE_INFO_UNIT) { - case NV_DEVICE_FIFO(0): subidx = NVKM_ENGINE_FIFO; break; + case NV_DEVICE_HOST(0): type = NVKM_ENGINE_FIFO; break; default: return -EINVAL; } - subdev = nvkm_device_subdev(device, subidx); + subdev = nvkm_device_subdev(device, type, 0); if (subdev) return nvkm_subdev_info(subdev, mthd, data); return -ENODEV; @@ -66,37 +66,7 @@ nvkm_udevice_info_v1(struct nvkm_device *device, args->mthd = NV_DEVICE_INFO_INVALID; return; } - - switch (args->mthd) { -#define ENGINE__(A,B,C) NV_DEVICE_INFO_ENGINE_##A: { int _i; \ - for (_i = (B), args->data = 0ULL; _i <= (C); _i++) { \ - if (nvkm_device_engine(device, _i)) \ - args->data |= BIT_ULL(_i); \ - } \ -} -#define ENGINE_A(A) ENGINE__(A, NVKM_ENGINE_##A , NVKM_ENGINE_##A) -#define ENGINE_B(A) ENGINE__(A, NVKM_ENGINE_##A##0, NVKM_ENGINE_##A##_LAST) - case ENGINE_A(SW ); break; - case ENGINE_A(GR ); break; - case ENGINE_A(MPEG ); break; - case ENGINE_A(ME ); break; - case ENGINE_A(CIPHER); break; - case ENGINE_A(BSP ); break; - case ENGINE_A(VP ); break; - case ENGINE_B(CE ); break; - case ENGINE_A(SEC ); break; - case ENGINE_A(MSVLD ); break; - case ENGINE_A(MSPDEC); break; - case ENGINE_A(MSPPP ); break; - case ENGINE_A(MSENC ); break; - case ENGINE_A(VIC ); break; - case ENGINE_A(SEC2 ); break; - case ENGINE_B(NVDEC ); break; - case ENGINE_B(NVENC ); break; - default: - args->mthd = NV_DEVICE_INFO_INVALID; - break; - } + args->mthd = NV_DEVICE_INFO_INVALID; } static int @@ -357,7 +327,7 @@ nvkm_udevice_child_get(struct nvkm_object *object, int index, int i; for (; i = __ffs64(mask), mask && !sclass; mask &= ~(1ULL << i)) { - if (!(engine = nvkm_device_engine(device, i)) || + if (!(engine = nvkm_device_engine(device, i, 0)) || !(engine->func->base.sclass)) continue; oclass->engine = engine; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c index cbd33e87b799..5daa77755276 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c @@ -149,10 +149,10 @@ static void nvkm_disp_class_del(struct nvkm_oproxy *oproxy) { struct nvkm_disp *disp = nvkm_disp(oproxy->base.engine); - mutex_lock(&disp->engine.subdev.mutex); - if (disp->client == oproxy) - disp->client = NULL; - mutex_unlock(&disp->engine.subdev.mutex); + spin_lock(&disp->client.lock); + if (disp->client.object == oproxy) + disp->client.object = NULL; + spin_unlock(&disp->client.lock); } static const struct nvkm_oproxy_func @@ -175,13 +175,13 @@ nvkm_disp_class_new(struct nvkm_device *device, return ret; *pobject = &oproxy->base; - mutex_lock(&disp->engine.subdev.mutex); - if (disp->client) { - mutex_unlock(&disp->engine.subdev.mutex); + spin_lock(&disp->client.lock); + if (disp->client.object) { + spin_unlock(&disp->client.lock); return -EBUSY; } - disp->client = oproxy; - mutex_unlock(&disp->engine.subdev.mutex); + disp->client.object = oproxy; + spin_unlock(&disp->client.lock); return sclass->ctor(disp, oclass, data, size, &oproxy->object); } @@ -473,21 +473,22 @@ nvkm_disp = { int nvkm_disp_ctor(const struct nvkm_disp_func *func, struct nvkm_device *device, - int index, struct nvkm_disp *disp) + enum nvkm_subdev_type type, int inst, struct nvkm_disp *disp) { disp->func = func; INIT_LIST_HEAD(&disp->head); INIT_LIST_HEAD(&disp->ior); INIT_LIST_HEAD(&disp->outp); INIT_LIST_HEAD(&disp->conn); - return nvkm_engine_ctor(&nvkm_disp, device, index, true, &disp->engine); + spin_lock_init(&disp->client.lock); + return nvkm_engine_ctor(&nvkm_disp, device, type, inst, true, &disp->engine); } int nvkm_disp_new_(const struct nvkm_disp_func *func, struct nvkm_device *device, - int index, struct nvkm_disp **pdisp) + enum nvkm_subdev_type type, int inst, struct nvkm_disp **pdisp) { if (!(*pdisp = kzalloc(sizeof(**pdisp), GFP_KERNEL))) return -ENOMEM; - return nvkm_disp_ctor(func, device, index, *pdisp); + return nvkm_disp_ctor(func, device, type, inst, *pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c index 50e3539f33d2..a7a7eb041515 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c @@ -278,7 +278,7 @@ nv50_disp_chan_child_get(struct nvkm_object *object, int index, const struct nvkm_device_oclass *oclass = NULL; if (chan->func->bind) - sclass->engine = nvkm_device_engine(device, NVKM_ENGINE_DMAOBJ); + sclass->engine = nvkm_device_engine(device, NVKM_ENGINE_DMAOBJ, 0); else sclass->engine = NULL; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c index 731f188fc1ee..156bbe8b2de3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c @@ -41,7 +41,8 @@ g84_disp = { }; int -g84_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +g84_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&g84_disp, device, index, pdisp); + return nv50_disp_new_(&g84_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c index def54fe1951e..3425b5d3bc72 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c @@ -41,7 +41,8 @@ g94_disp = { }; int -g94_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +g94_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&g94_disp, device, index, pdisp); + return nv50_disp_new_(&g94_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.c index aa2e5645fe36..68aa52588d92 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.c @@ -40,7 +40,8 @@ ga102_disp = { }; int -ga102_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +ga102_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&ga102_disp, device, index, pdisp); + return nv50_disp_new_(&ga102_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c index e675d9b9d5d7..a6bafe7fea1f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c @@ -266,7 +266,8 @@ gf119_disp = { }; int -gf119_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +gf119_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&gf119_disp, device, index, pdisp); + return nv50_disp_new_(&gf119_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c index 4c3439b1a62d..3b79cf233ac5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c @@ -41,7 +41,8 @@ gk104_disp = { }; int -gk104_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +gk104_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&gk104_disp, device, index, pdisp); + return nv50_disp_new_(&gk104_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c index bc6f4750c942..988eb12237a6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c @@ -41,7 +41,8 @@ gk110_disp = { }; int -gk110_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +gk110_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&gk110_disp, device, index, pdisp); + return nv50_disp_new_(&gk110_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c index 031cf6b03a76..5d8108feeacd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c @@ -41,7 +41,8 @@ gm107_disp = { }; int -gm107_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +gm107_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&gm107_disp, device, index, pdisp); + return nv50_disp_new_(&gm107_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c index ec9c33a5162d..f7bb66087476 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c @@ -41,7 +41,8 @@ gm200_disp = { }; int -gm200_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +gm200_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&gm200_disp, device, index, pdisp); + return nv50_disp_new_(&gm200_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.c index 8471de3f3b61..af0ca812a394 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.c @@ -40,7 +40,8 @@ gp100_disp = { }; int -gp100_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +gp100_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&gp100_disp, device, index, pdisp); + return nv50_disp_new_(&gp100_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c index a3779c5046ea..065fea1bdfd1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c @@ -67,7 +67,8 @@ gp102_disp = { }; int -gp102_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +gp102_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&gp102_disp, device, index, pdisp); + return nv50_disp_new_(&gp102_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c index f80183701f44..22bc269df64a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c @@ -41,7 +41,8 @@ gt200_disp = { }; int -gt200_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +gt200_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(>200_disp, device, index, pdisp); + return nv50_disp_new_(>200_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c index 7581efc1357e..63a912b174d7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c @@ -41,7 +41,8 @@ gt215_disp = { }; int -gt215_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +gt215_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(>215_disp, device, index, pdisp); + return nv50_disp_new_(>215_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c index c1032527f791..53879d5271cf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c @@ -441,7 +441,8 @@ gv100_disp = { }; int -gv100_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +gv100_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&gv100_disp, device, index, pdisp); + return nv50_disp_new_(&gv100_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c index cfdce23ab83a..762a59f24bbb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c @@ -39,7 +39,8 @@ mcp77_disp = { }; int -mcp77_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +mcp77_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&mcp77_disp, device, index, pdisp); + return nv50_disp_new_(&mcp77_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c index 85d9329cfa0e..e5c58aae15de 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c @@ -39,7 +39,8 @@ mcp89_disp = { }; int -mcp89_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +mcp89_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&mcp89_disp, device, index, pdisp); + return nv50_disp_new_(&mcp89_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c index b780ba1a3bc7..a12097db2c2a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c @@ -64,11 +64,12 @@ nv04_disp = { }; int -nv04_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +nv04_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { int ret, i; - ret = nvkm_disp_new_(&nv04_disp, device, index, pdisp); + ret = nvkm_disp_new_(&nv04_disp, device, type, inst, pdisp); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c index e21556bf2cb1..3f20e49070ce 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c @@ -154,7 +154,7 @@ nv50_disp_ = { int nv50_disp_new_(const struct nv50_disp_func *func, struct nvkm_device *device, - int index, struct nvkm_disp **pdisp) + enum nvkm_subdev_type type, int inst, struct nvkm_disp **pdisp) { struct nv50_disp *disp; int ret; @@ -164,7 +164,7 @@ nv50_disp_new_(const struct nv50_disp_func *func, struct nvkm_device *device, disp->func = func; *pdisp = &disp->base; - ret = nvkm_disp_ctor(&nv50_disp_, device, index, &disp->base); + ret = nvkm_disp_ctor(&nv50_disp_, device, type, inst, &disp->base); if (ret) return ret; @@ -769,7 +769,8 @@ nv50_disp = { }; int -nv50_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +nv50_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&nv50_disp, device, index, pdisp); + return nv50_disp_new_(&nv50_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h index db31b37752a2..025cacd7c3b0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h @@ -47,8 +47,8 @@ void nv50_disp_super_2_1(struct nv50_disp *, struct nvkm_head *); void nv50_disp_super_2_2(struct nv50_disp *, struct nvkm_head *); void nv50_disp_super_3_0(struct nv50_disp *, struct nvkm_head *); -int nv50_disp_new_(const struct nv50_disp_func *, struct nvkm_device *, - int index, struct nvkm_disp **); +int nv50_disp_new_(const struct nv50_disp_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_disp **); struct nv50_disp_func { int (*init)(struct nv50_disp *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h index f815a5342880..ec57d8b6bce9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h @@ -4,10 +4,10 @@ #include <engine/disp.h> #include "outp.h" -int nvkm_disp_ctor(const struct nvkm_disp_func *, struct nvkm_device *, - int index, struct nvkm_disp *); -int nvkm_disp_new_(const struct nvkm_disp_func *, struct nvkm_device *, - int index, struct nvkm_disp **); +int nvkm_disp_ctor(const struct nvkm_disp_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_disp *); +int nvkm_disp_new_(const struct nvkm_disp_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_disp **); void nvkm_disp_vblank(struct nvkm_disp *, int head); struct nvkm_disp_func { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c index 4c85d1d4fbd4..f5f8dc8e8f35 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c @@ -146,7 +146,8 @@ tu102_disp = { }; int -tu102_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) +tu102_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_disp **pdisp) { - return nv50_disp_new_(&tu102_disp, device, index, pdisp); + return nv50_disp_new_(&tu102_disp, device, type, inst, pdisp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c index 11b7b8fd5dda..425cde35f128 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c @@ -104,7 +104,7 @@ nvkm_dma = { int nvkm_dma_new_(const struct nvkm_dma_func *func, struct nvkm_device *device, - int index, struct nvkm_dma **pdma) + enum nvkm_subdev_type type, int inst, struct nvkm_dma **pdma) { struct nvkm_dma *dma; @@ -112,5 +112,5 @@ nvkm_dma_new_(const struct nvkm_dma_func *func, struct nvkm_device *device, return -ENOMEM; dma->func = func; - return nvkm_engine_ctor(&nvkm_dma, device, index, true, &dma->engine); + return nvkm_engine_ctor(&nvkm_dma, device, type, inst, true, &dma->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.c index efec5d322179..99a1e07fa204 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.c @@ -30,7 +30,8 @@ gf100_dma = { }; int -gf100_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma) +gf100_dma_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_dma **pdma) { - return nvkm_dma_new_(&gf100_dma, device, index, pdma); + return nvkm_dma_new_(&gf100_dma, device, type, inst, pdma); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.c index 34c766039aed..fd1d1fc22dc6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.c @@ -30,7 +30,8 @@ gf119_dma = { }; int -gf119_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma) +gf119_dma_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_dma **pdma) { - return nvkm_dma_new_(&gf119_dma, device, index, pdma); + return nvkm_dma_new_(&gf119_dma, device, type, inst, pdma); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/gv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/gv100.c index c65a4c2ea93d..a5af0df30663 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/gv100.c @@ -28,7 +28,8 @@ gv100_dma = { }; int -gv100_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma) +gv100_dma_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_dma **pdma) { - return nvkm_dma_new_(&gv100_dma, device, index, pdma); + return nvkm_dma_new_(&gv100_dma, device, type, inst, pdma); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.c index 30747a0ce488..ea5a889f60c2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.c @@ -30,7 +30,8 @@ nv04_dma = { }; int -nv04_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma) +nv04_dma_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_dma **pdma) { - return nvkm_dma_new_(&nv04_dma, device, index, pdma); + return nvkm_dma_new_(&nv04_dma, device, type, inst, pdma); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.c index 77aca7b71c83..6e8f79660014 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.c @@ -30,7 +30,8 @@ nv50_dma = { }; int -nv50_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma) +nv50_dma_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_dma **pdma) { - return nvkm_dma_new_(&nv50_dma, device, index, pdma); + return nvkm_dma_new_(&nv50_dma, device, type, inst, pdma); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h index 0c9d9640a59d..d403bedb485a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h @@ -9,8 +9,8 @@ struct nvkm_dmaobj_func { struct nvkm_gpuobj **); }; -int nvkm_dma_new_(const struct nvkm_dma_func *, struct nvkm_device *, - int index, struct nvkm_dma **); +int nvkm_dma_new_(const struct nvkm_dma_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_dma **); struct nvkm_dma_func { int (*class_new)(struct nvkm_dma *, const struct nvkm_oclass *, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c index 8675613e142b..43b7dec45179 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c @@ -108,7 +108,7 @@ nvkm_falcon_fini(struct nvkm_engine *engine, bool suspend) } } - if (nvkm_mc_enabled(device, engine->subdev.index)) { + if (nvkm_mc_enabled(device, engine->subdev.type, engine->subdev.inst)) { nvkm_mask(device, base + 0x048, 0x00000003, 0x00000000); nvkm_wr32(device, base + 0x014, 0xffffffff); } @@ -335,9 +335,9 @@ nvkm_falcon = { }; int -nvkm_falcon_new_(const struct nvkm_falcon_func *func, - struct nvkm_device *device, int index, bool enable, - u32 addr, struct nvkm_engine **pengine) +nvkm_falcon_new_(const struct nvkm_falcon_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, bool enable, u32 addr, + struct nvkm_engine **pengine) { struct nvkm_falcon *falcon; @@ -351,6 +351,5 @@ nvkm_falcon_new_(const struct nvkm_falcon_func *func, falcon->data.size = func->data.size; *pengine = &falcon->engine; - return nvkm_engine_ctor(&nvkm_falcon, device, index, - enable, &falcon->engine); + return nvkm_engine_ctor(&nvkm_falcon, device, type, inst, enable, &falcon->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c index c773caf21f6b..2ed4ff05d207 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c @@ -292,7 +292,7 @@ nvkm_fifo_info(struct nvkm_engine *engine, u64 mthd, u64 *data) { struct nvkm_fifo *fifo = nvkm_fifo(engine); switch (mthd) { - case NV_DEVICE_FIFO_CHANNELS: *data = fifo->nr; return 0; + case NV_DEVICE_HOST_CHANNELS: *data = fifo->nr; return 0; default: if (fifo->func->info) return fifo->func->info(fifo, mthd, data); @@ -313,7 +313,7 @@ nvkm_fifo_oneinit(struct nvkm_engine *engine) static void nvkm_fifo_preinit(struct nvkm_engine *engine) { - nvkm_mc_reset(engine->subdev.device, NVKM_ENGINE_FIFO); + nvkm_mc_reset(engine->subdev.device, NVKM_ENGINE_FIFO, 0); } static int @@ -334,6 +334,7 @@ nvkm_fifo_dtor(struct nvkm_engine *engine) nvkm_event_fini(&fifo->kevent); nvkm_event_fini(&fifo->cevent); nvkm_event_fini(&fifo->uevent); + mutex_destroy(&fifo->mutex); return data; } @@ -351,13 +352,14 @@ nvkm_fifo = { int nvkm_fifo_ctor(const struct nvkm_fifo_func *func, struct nvkm_device *device, - int index, int nr, struct nvkm_fifo *fifo) + enum nvkm_subdev_type type, int inst, int nr, struct nvkm_fifo *fifo) { int ret; fifo->func = func; INIT_LIST_HEAD(&fifo->chan); spin_lock_init(&fifo->lock); + mutex_init(&fifo->mutex); if (WARN_ON(fifo->nr > NVKM_FIFO_CHID_NR)) fifo->nr = NVKM_FIFO_CHID_NR; @@ -365,7 +367,7 @@ nvkm_fifo_ctor(const struct nvkm_fifo_func *func, struct nvkm_device *device, fifo->nr = nr; bitmap_clear(fifo->mask, 0, fifo->nr); - ret = nvkm_engine_ctor(&nvkm_fifo, device, index, true, &fifo->engine); + ret = nvkm_engine_ctor(&nvkm_fifo, device, type, inst, true, &fifo->engine); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c index d83485385934..8d957643940a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c @@ -35,6 +35,15 @@ struct nvkm_fifo_chan_object { int hash; }; +static struct nvkm_fifo_engn * +nvkm_fifo_chan_engn(struct nvkm_fifo_chan *chan, struct nvkm_engine *engine) +{ + int engi = chan->fifo->func->engine_id(chan->fifo, engine); + if (engi >= 0) + return &chan->engn[engi]; + return NULL; +} + static int nvkm_fifo_chan_child_fini(struct nvkm_oproxy *base, bool suspend) { @@ -42,8 +51,8 @@ nvkm_fifo_chan_child_fini(struct nvkm_oproxy *base, bool suspend) container_of(base, typeof(*object), oproxy); struct nvkm_engine *engine = object->oproxy.object->engine; struct nvkm_fifo_chan *chan = object->chan; - struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index]; - const char *name = nvkm_subdev_name[engine->subdev.index]; + struct nvkm_fifo_engn *engn = nvkm_fifo_chan_engn(chan, engine); + const char *name = engine->subdev.name; int ret = 0; if (--engn->usecount) @@ -75,8 +84,8 @@ nvkm_fifo_chan_child_init(struct nvkm_oproxy *base) container_of(base, typeof(*object), oproxy); struct nvkm_engine *engine = object->oproxy.object->engine; struct nvkm_fifo_chan *chan = object->chan; - struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index]; - const char *name = nvkm_subdev_name[engine->subdev.index]; + struct nvkm_fifo_engn *engn = nvkm_fifo_chan_engn(chan, engine); + const char *name = engine->subdev.name; int ret; if (engn->usecount++) @@ -108,7 +117,7 @@ nvkm_fifo_chan_child_del(struct nvkm_oproxy *base) container_of(base, typeof(*object), oproxy); struct nvkm_engine *engine = object->oproxy.base.engine; struct nvkm_fifo_chan *chan = object->chan; - struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index]; + struct nvkm_fifo_engn *engn = nvkm_fifo_chan_engn(chan, engine); if (chan->func->object_dtor) chan->func->object_dtor(chan, object->hash); @@ -118,7 +127,7 @@ nvkm_fifo_chan_child_del(struct nvkm_oproxy *base) chan->func->engine_dtor(chan, engine); nvkm_object_del(&engn->object); if (chan->vmm) - atomic_dec(&chan->vmm->engref[engine->subdev.index]); + atomic_dec(&chan->vmm->engref[engine->subdev.type]); } } @@ -135,7 +144,7 @@ nvkm_fifo_chan_child_new(const struct nvkm_oclass *oclass, void *data, u32 size, { struct nvkm_engine *engine = oclass->engine; struct nvkm_fifo_chan *chan = nvkm_fifo_chan(oclass->parent); - struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index]; + struct nvkm_fifo_engn *engn = nvkm_fifo_chan_engn(chan, engine); struct nvkm_fifo_chan_object *object; int ret = 0; @@ -152,7 +161,7 @@ nvkm_fifo_chan_child_new(const struct nvkm_oclass *oclass, void *data, u32 size, }; if (chan->vmm) - atomic_inc(&chan->vmm->engref[engine->subdev.index]); + atomic_inc(&chan->vmm->engref[engine->subdev.type]); if (engine->func->fifo.cclass) { ret = engine->func->fifo.cclass(chan, &cclass, @@ -203,13 +212,12 @@ nvkm_fifo_chan_child_get(struct nvkm_object *object, int index, { struct nvkm_fifo_chan *chan = nvkm_fifo_chan(object); struct nvkm_fifo *fifo = chan->fifo; - struct nvkm_device *device = fifo->engine.subdev.device; struct nvkm_engine *engine; - u64 mask = chan->engines; - int ret, i, c; + u32 engm = chan->engm; + int engi, ret, c; - for (; c = 0, i = __ffs64(mask), mask; mask &= ~(1ULL << i)) { - if (!(engine = nvkm_device_engine(device, i))) + for (; c = 0, engi = __ffs(engm), engm; engm &= ~(1ULL << engi)) { + if (!(engine = fifo->func->id_engine(fifo, engi))) continue; oclass->engine = engine; oclass->base.oclass = 0; @@ -352,7 +360,7 @@ nvkm_fifo_chan_func = { int nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *func, struct nvkm_fifo *fifo, u32 size, u32 align, bool zero, - u64 hvmm, u64 push, u64 engines, int bar, u32 base, + u64 hvmm, u64 push, u32 engm, int bar, u32 base, u32 user, const struct nvkm_oclass *oclass, struct nvkm_fifo_chan *chan) { @@ -365,7 +373,7 @@ nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *func, nvkm_object_ctor(&nvkm_fifo_chan_func, oclass, &chan->object); chan->func = func; chan->fifo = fifo; - chan->engines = engines; + chan->engm = engm; INIT_LIST_HEAD(&chan->head); /* instance memory */ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h index 177e10562600..e53504354841 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h @@ -22,7 +22,7 @@ struct nvkm_fifo_chan_func { int nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *, struct nvkm_fifo *, u32 size, u32 align, bool zero, u64 vm, u64 push, - u64 engines, int bar, u32 base, u32 user, + u32 engm, int bar, u32 base, u32 user, const struct nvkm_oclass *, struct nvkm_fifo_chan *); struct nvkm_fifo_chan_oclass { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c index a5c998fe4485..353b77d9b3dc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c @@ -45,29 +45,9 @@ g84_fifo_chan_ntfy(struct nvkm_fifo_chan *chan, u32 type, } static int -g84_fifo_chan_engine(struct nvkm_engine *engine) -{ - switch (engine->subdev.index) { - case NVKM_ENGINE_GR : return 0; - case NVKM_ENGINE_MPEG : - case NVKM_ENGINE_MSPPP : return 1; - case NVKM_ENGINE_CE0 : return 2; - case NVKM_ENGINE_VP : - case NVKM_ENGINE_MSPDEC: return 3; - case NVKM_ENGINE_CIPHER: - case NVKM_ENGINE_SEC : return 4; - case NVKM_ENGINE_BSP : - case NVKM_ENGINE_MSVLD : return 5; - default: - WARN_ON(1); - return 0; - } -} - -static int g84_fifo_chan_engine_addr(struct nvkm_engine *engine) { - switch (engine->subdev.index) { + switch (engine->subdev.type) { case NVKM_ENGINE_DMAOBJ: case NVKM_ENGINE_SW : return -1; case NVKM_ENGINE_GR : return 0x0020; @@ -79,7 +59,7 @@ g84_fifo_chan_engine_addr(struct nvkm_engine *engine) case NVKM_ENGINE_MSVLD : return 0x0080; case NVKM_ENGINE_CIPHER: case NVKM_ENGINE_SEC : return 0x00a0; - case NVKM_ENGINE_CE0 : return 0x00c0; + case NVKM_ENGINE_CE : return 0x00c0; default: WARN_ON(1); return -1; @@ -102,7 +82,7 @@ g84_fifo_chan_engine_fini(struct nvkm_fifo_chan *base, if (offset < 0) return 0; - engn = g84_fifo_chan_engine(engine); + engn = fifo->base.func->engine_id(&fifo->base, engine); save = nvkm_mask(device, 0x002520, 0x0000003f, 1 << engn); nvkm_wr32(device, 0x0032fc, chan->base.inst->addr >> 12); done = nvkm_msec(device, 2000, @@ -134,7 +114,7 @@ g84_fifo_chan_engine_init(struct nvkm_fifo_chan *base, struct nvkm_engine *engine) { struct nv50_fifo_chan *chan = nv50_fifo_chan(base); - struct nvkm_gpuobj *engn = chan->engn[engine->subdev.index]; + struct nvkm_gpuobj *engn = *nv50_fifo_chan_engine(chan, engine); u64 limit, start; int offset; @@ -162,12 +142,11 @@ g84_fifo_chan_engine_ctor(struct nvkm_fifo_chan *base, struct nvkm_object *object) { struct nv50_fifo_chan *chan = nv50_fifo_chan(base); - int engn = engine->subdev.index; if (g84_fifo_chan_engine_addr(engine) < 0) return 0; - return nvkm_object_bind(object, NULL, 0, &chan->engn[engn]); + return nvkm_object_bind(object, NULL, 0, nv50_fifo_chan_engine(chan, engine)); } static int @@ -178,14 +157,14 @@ g84_fifo_chan_object_ctor(struct nvkm_fifo_chan *base, u32 handle = object->handle; u32 context; - switch (object->engine->subdev.index) { + switch (object->engine->subdev.type) { case NVKM_ENGINE_DMAOBJ: case NVKM_ENGINE_SW : context = 0x00000000; break; case NVKM_ENGINE_GR : context = 0x00100000; break; case NVKM_ENGINE_MPEG : case NVKM_ENGINE_MSPPP : context = 0x00200000; break; case NVKM_ENGINE_ME : - case NVKM_ENGINE_CE0 : context = 0x00300000; break; + case NVKM_ENGINE_CE : context = 0x00300000; break; case NVKM_ENGINE_VP : case NVKM_ENGINE_MSPDEC: context = 0x00400000; break; case NVKM_ENGINE_CIPHER: @@ -241,20 +220,20 @@ g84_fifo_chan_ctor(struct nv50_fifo *fifo, u64 vmm, u64 push, ret = nvkm_fifo_chan_ctor(&g84_fifo_chan_func, &fifo->base, 0x10000, 0x1000, false, vmm, push, - (1ULL << NVKM_ENGINE_BSP) | - (1ULL << NVKM_ENGINE_CE0) | - (1ULL << NVKM_ENGINE_CIPHER) | - (1ULL << NVKM_ENGINE_DMAOBJ) | - (1ULL << NVKM_ENGINE_GR) | - (1ULL << NVKM_ENGINE_ME) | - (1ULL << NVKM_ENGINE_MPEG) | - (1ULL << NVKM_ENGINE_MSPDEC) | - (1ULL << NVKM_ENGINE_MSPPP) | - (1ULL << NVKM_ENGINE_MSVLD) | - (1ULL << NVKM_ENGINE_SEC) | - (1ULL << NVKM_ENGINE_SW) | - (1ULL << NVKM_ENGINE_VIC) | - (1ULL << NVKM_ENGINE_VP), + BIT(G84_FIFO_ENGN_SW) | + BIT(G84_FIFO_ENGN_GR) | + BIT(G84_FIFO_ENGN_MPEG) | + BIT(G84_FIFO_ENGN_MSPPP) | + BIT(G84_FIFO_ENGN_ME) | + BIT(G84_FIFO_ENGN_CE0) | + BIT(G84_FIFO_ENGN_VP) | + BIT(G84_FIFO_ENGN_MSPDEC) | + BIT(G84_FIFO_ENGN_CIPHER) | + BIT(G84_FIFO_ENGN_SEC) | + BIT(G84_FIFO_ENGN_VIC) | + BIT(G84_FIFO_ENGN_BSP) | + BIT(G84_FIFO_ENGN_MSVLD) | + BIT(G84_FIFO_ENGN_DMA), 0, 0xc00000, 0x2000, oclass, &chan->base); chan->fifo = fifo; if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h index 7c125a15f963..f7ac1061fa84 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h @@ -12,10 +12,17 @@ struct gf100_fifo_chan { struct list_head head; bool killed; - struct { +#define GF100_FIFO_ENGN_GR 0 +#define GF100_FIFO_ENGN_MSPDEC 1 +#define GF100_FIFO_ENGN_MSPPP 2 +#define GF100_FIFO_ENGN_MSVLD 3 +#define GF100_FIFO_ENGN_CE0 4 +#define GF100_FIFO_ENGN_CE1 5 +#define GF100_FIFO_ENGN_SW 15 + struct gf100_fifo_engn { struct nvkm_gpuobj *inst; struct nvkm_vma *vma; - } engn[NVKM_SUBDEV_NR]; + } engn[NVKM_FIFO_ENGN_NR]; }; extern const struct nvkm_fifo_chan_oclass gf100_fifo_gpfifo_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h index 22698661aa85..cfbe096e604f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h @@ -16,10 +16,11 @@ struct gk104_fifo_chan { struct nvkm_memory *mthd; - struct { +#define GK104_FIFO_ENGN_SW 15 + struct gk104_fifo_engn { struct nvkm_gpuobj *inst; struct nvkm_vma *vma; - } engn[NVKM_SUBDEV_NR]; + } engn[NVKM_FIFO_ENGN_NR]; }; extern const struct nvkm_fifo_chan_func gk104_fifo_gpfifo_func; @@ -29,6 +30,7 @@ int gk104_fifo_gpfifo_new(struct gk104_fifo *, const struct nvkm_oclass *, void *gk104_fifo_gpfifo_dtor(struct nvkm_fifo_chan *); void gk104_fifo_gpfifo_init(struct nvkm_fifo_chan *); void gk104_fifo_gpfifo_fini(struct nvkm_fifo_chan *); +struct gk104_fifo_engn *gk104_fifo_gpfifo_engine(struct gk104_fifo_chan *, struct nvkm_engine *); int gk104_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *, struct nvkm_engine *, struct nvkm_object *); void gk104_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan *, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h index 60ca79465aff..727bc8976b40 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h @@ -9,7 +9,11 @@ struct nv04_fifo_chan { struct nvkm_fifo_chan base; struct nv04_fifo *fifo; u32 ramfc; - struct nvkm_gpuobj *engn[NVKM_SUBDEV_NR]; +#define NV04_FIFO_ENGN_SW 0 +#define NV04_FIFO_ENGN_GR 1 +#define NV04_FIFO_ENGN_MPEG 2 +#define NV04_FIFO_ENGN_DMA 3 + struct nvkm_gpuobj *engn[NVKM_FIFO_ENGN_NR]; }; extern const struct nvkm_fifo_chan_func nv04_fifo_dma_func; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c index 85f7dbf53c99..c44d7c81dd52 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c @@ -31,7 +31,7 @@ static int nv50_fifo_chan_engine_addr(struct nvkm_engine *engine) { - switch (engine->subdev.index) { + switch (engine->subdev.type) { case NVKM_ENGINE_DMAOBJ: case NVKM_ENGINE_SW : return -1; case NVKM_ENGINE_GR : return 0x0000; @@ -42,6 +42,15 @@ nv50_fifo_chan_engine_addr(struct nvkm_engine *engine) } } +struct nvkm_gpuobj ** +nv50_fifo_chan_engine(struct nv50_fifo_chan *chan, struct nvkm_engine *engine) +{ + int engi = chan->base.fifo->func->engine_id(chan->base.fifo, engine); + if (engi >= 0) + return &chan->engn[engi]; + return NULL; +} + static int nv50_fifo_chan_engine_fini(struct nvkm_fifo_chan *base, struct nvkm_engine *engine, bool suspend) @@ -103,7 +112,7 @@ nv50_fifo_chan_engine_init(struct nvkm_fifo_chan *base, struct nvkm_engine *engine) { struct nv50_fifo_chan *chan = nv50_fifo_chan(base); - struct nvkm_gpuobj *engn = chan->engn[engine->subdev.index]; + struct nvkm_gpuobj *engn = *nv50_fifo_chan_engine(chan, engine); u64 limit, start; int offset; @@ -130,7 +139,7 @@ nv50_fifo_chan_engine_dtor(struct nvkm_fifo_chan *base, struct nvkm_engine *engine) { struct nv50_fifo_chan *chan = nv50_fifo_chan(base); - nvkm_gpuobj_del(&chan->engn[engine->subdev.index]); + nvkm_gpuobj_del(nv50_fifo_chan_engine(chan, engine)); } static int @@ -139,12 +148,11 @@ nv50_fifo_chan_engine_ctor(struct nvkm_fifo_chan *base, struct nvkm_object *object) { struct nv50_fifo_chan *chan = nv50_fifo_chan(base); - int engn = engine->subdev.index; if (nv50_fifo_chan_engine_addr(engine) < 0) return 0; - return nvkm_object_bind(object, NULL, 0, &chan->engn[engn]); + return nvkm_object_bind(object, NULL, 0, nv50_fifo_chan_engine(chan, engine)); } void @@ -162,7 +170,7 @@ nv50_fifo_chan_object_ctor(struct nvkm_fifo_chan *base, u32 handle = object->handle; u32 context; - switch (object->engine->subdev.index) { + switch (object->engine->subdev.type) { case NVKM_ENGINE_DMAOBJ: case NVKM_ENGINE_SW : context = 0x00000000; break; case NVKM_ENGINE_GR : context = 0x00100000; break; @@ -240,10 +248,10 @@ nv50_fifo_chan_ctor(struct nv50_fifo *fifo, u64 vmm, u64 push, ret = nvkm_fifo_chan_ctor(&nv50_fifo_chan_func, &fifo->base, 0x10000, 0x1000, false, vmm, push, - (1ULL << NVKM_ENGINE_DMAOBJ) | - (1ULL << NVKM_ENGINE_SW) | - (1ULL << NVKM_ENGINE_GR) | - (1ULL << NVKM_ENGINE_MPEG), + BIT(NV50_FIFO_ENGN_SW) | + BIT(NV50_FIFO_ENGN_GR) | + BIT(NV50_FIFO_ENGN_MPEG) | + BIT(NV50_FIFO_ENGN_DMA), 0, 0xc00000, 0x2000, oclass, &chan->base); chan->fifo = fifo; if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h index 5735ff72a9d1..af8bdf275552 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h @@ -15,13 +15,33 @@ struct nv50_fifo_chan { struct nvkm_gpuobj *pgd; struct nvkm_ramht *ramht; - struct nvkm_gpuobj *engn[NVKM_SUBDEV_NR]; +#define NV50_FIFO_ENGN_SW 0 +#define NV50_FIFO_ENGN_GR 1 +#define NV50_FIFO_ENGN_MPEG 2 +#define NV50_FIFO_ENGN_DMA 3 + +#define G84_FIFO_ENGN_SW 0 +#define G84_FIFO_ENGN_GR 1 +#define G84_FIFO_ENGN_MPEG 2 +#define G84_FIFO_ENGN_MSPPP 2 +#define G84_FIFO_ENGN_ME 3 +#define G84_FIFO_ENGN_CE0 3 +#define G84_FIFO_ENGN_VP 4 +#define G84_FIFO_ENGN_MSPDEC 4 +#define G84_FIFO_ENGN_CIPHER 5 +#define G84_FIFO_ENGN_SEC 5 +#define G84_FIFO_ENGN_VIC 5 +#define G84_FIFO_ENGN_BSP 6 +#define G84_FIFO_ENGN_MSVLD 6 +#define G84_FIFO_ENGN_DMA 7 + struct nvkm_gpuobj *engn[NVKM_FIFO_ENGN_NR]; }; int nv50_fifo_chan_ctor(struct nv50_fifo *, u64 vmm, u64 push, const struct nvkm_oclass *, struct nv50_fifo_chan *); void *nv50_fifo_chan_dtor(struct nvkm_fifo_chan *); void nv50_fifo_chan_fini(struct nvkm_fifo_chan *); +struct nvkm_gpuobj **nv50_fifo_chan_engine(struct nv50_fifo_chan *, struct nvkm_engine *); void nv50_fifo_chan_engine_dtor(struct nvkm_fifo_chan *, struct nvkm_engine *); void nv50_fifo_chan_object_dtor(struct nvkm_fifo_chan *, int); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c index c213122cf088..dbcdc5fab990 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c @@ -38,9 +38,9 @@ nv04_fifo_dma_object_dtor(struct nvkm_fifo_chan *base, int cookie) struct nv04_fifo_chan *chan = nv04_fifo_chan(base); struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem; - mutex_lock(&chan->fifo->base.engine.subdev.mutex); + mutex_lock(&chan->fifo->base.mutex); nvkm_ramht_remove(imem->ramht, cookie); - mutex_unlock(&chan->fifo->base.engine.subdev.mutex); + mutex_unlock(&chan->fifo->base.mutex); } static int @@ -53,7 +53,7 @@ nv04_fifo_dma_object_ctor(struct nvkm_fifo_chan *base, u32 handle = object->handle; int hash; - switch (object->engine->subdev.index) { + switch (object->engine->subdev.type) { case NVKM_ENGINE_DMAOBJ: case NVKM_ENGINE_SW : context |= 0x00000000; break; case NVKM_ENGINE_GR : context |= 0x00010000; break; @@ -63,10 +63,10 @@ nv04_fifo_dma_object_ctor(struct nvkm_fifo_chan *base, return -EINVAL; } - mutex_lock(&chan->fifo->base.engine.subdev.mutex); + mutex_lock(&chan->fifo->base.mutex); hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4, handle, context); - mutex_unlock(&chan->fifo->base.engine.subdev.mutex); + mutex_unlock(&chan->fifo->base.mutex); return hash; } @@ -191,9 +191,9 @@ nv04_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base, 0x1000, 0x1000, false, 0, args->v0.pushbuf, - (1ULL << NVKM_ENGINE_DMAOBJ) | - (1ULL << NVKM_ENGINE_GR) | - (1ULL << NVKM_ENGINE_SW), + BIT(NV04_FIFO_ENGN_SW) | + BIT(NV04_FIFO_ENGN_GR) | + BIT(NV04_FIFO_ENGN_DMA), 0, 0x800000, 0x10000, oclass, &chan->base); chan->fifo = fifo; if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c index f5f355ff005d..07d80d54a07c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c @@ -62,9 +62,9 @@ nv10_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base, 0x1000, 0x1000, false, 0, args->v0.pushbuf, - (1ULL << NVKM_ENGINE_DMAOBJ) | - (1ULL << NVKM_ENGINE_GR) | - (1ULL << NVKM_ENGINE_SW), + BIT(NV04_FIFO_ENGN_SW) | + BIT(NV04_FIFO_ENGN_GR) | + BIT(NV04_FIFO_ENGN_DMA), 0, 0x800000, 0x10000, oclass, &chan->base); chan->fifo = fifo; if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c index 7edc6a564b5d..edd70a114218 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c @@ -62,10 +62,10 @@ nv17_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base, 0x1000, 0x1000, false, 0, args->v0.pushbuf, - (1ULL << NVKM_ENGINE_DMAOBJ) | - (1ULL << NVKM_ENGINE_GR) | - (1ULL << NVKM_ENGINE_MPEG) | /* NV31- */ - (1ULL << NVKM_ENGINE_SW), + BIT(NV04_FIFO_ENGN_SW) | + BIT(NV04_FIFO_ENGN_GR) | + BIT(NV04_FIFO_ENGN_MPEG) | /* NV31- */ + BIT(NV04_FIFO_ENGN_DMA), 0, 0x800000, 0x10000, oclass, &chan->base); chan->fifo = fifo; if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c index 5f722c6e8a2f..0411fb908457 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c @@ -35,7 +35,7 @@ static bool nv40_fifo_dma_engine(struct nvkm_engine *engine, u32 *reg, u32 *ctx) { - switch (engine->subdev.index) { + switch (engine->subdev.type) { case NVKM_ENGINE_DMAOBJ: case NVKM_ENGINE_SW: return false; @@ -55,6 +55,15 @@ nv40_fifo_dma_engine(struct nvkm_engine *engine, u32 *reg, u32 *ctx) } } +static struct nvkm_gpuobj ** +nv40_fifo_dma_engn(struct nv04_fifo_chan *chan, struct nvkm_engine *engine) +{ + int engi = chan->base.fifo->func->engine_id(chan->base.fifo, engine); + if (engi >= 0) + return &chan->engn[engi]; + return NULL; +} + static int nv40_fifo_dma_engine_fini(struct nvkm_fifo_chan *base, struct nvkm_engine *engine, bool suspend) @@ -99,7 +108,7 @@ nv40_fifo_dma_engine_init(struct nvkm_fifo_chan *base, if (!nv40_fifo_dma_engine(engine, ®, &ctx)) return 0; - inst = chan->engn[engine->subdev.index]->addr >> 4; + inst = (*nv40_fifo_dma_engn(chan, engine))->addr >> 4; spin_lock_irqsave(&fifo->base.lock, flags); nvkm_mask(device, 0x002500, 0x00000001, 0x00000000); @@ -121,7 +130,7 @@ nv40_fifo_dma_engine_dtor(struct nvkm_fifo_chan *base, struct nvkm_engine *engine) { struct nv04_fifo_chan *chan = nv04_fifo_chan(base); - nvkm_gpuobj_del(&chan->engn[engine->subdev.index]); + nvkm_gpuobj_del(nv40_fifo_dma_engn(chan, engine)); } static int @@ -130,13 +139,12 @@ nv40_fifo_dma_engine_ctor(struct nvkm_fifo_chan *base, struct nvkm_object *object) { struct nv04_fifo_chan *chan = nv04_fifo_chan(base); - const int engn = engine->subdev.index; u32 reg, ctx; if (!nv40_fifo_dma_engine(engine, ®, &ctx)) return 0; - return nvkm_object_bind(object, NULL, 0, &chan->engn[engn]); + return nvkm_object_bind(object, NULL, 0, nv40_fifo_dma_engn(chan, engine)); } static int @@ -149,7 +157,7 @@ nv40_fifo_dma_object_ctor(struct nvkm_fifo_chan *base, u32 handle = object->handle; int hash; - switch (object->engine->subdev.index) { + switch (object->engine->subdev.type) { case NVKM_ENGINE_DMAOBJ: case NVKM_ENGINE_SW : context |= 0x00000000; break; case NVKM_ENGINE_GR : context |= 0x00100000; break; @@ -159,10 +167,10 @@ nv40_fifo_dma_object_ctor(struct nvkm_fifo_chan *base, return -EINVAL; } - mutex_lock(&chan->fifo->base.engine.subdev.mutex); + mutex_lock(&chan->fifo->base.mutex); hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4, handle, context); - mutex_unlock(&chan->fifo->base.engine.subdev.mutex); + mutex_unlock(&chan->fifo->base.mutex); return hash; } @@ -209,10 +217,10 @@ nv40_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, ret = nvkm_fifo_chan_ctor(&nv40_fifo_dma_func, &fifo->base, 0x1000, 0x1000, false, 0, args->v0.pushbuf, - (1ULL << NVKM_ENGINE_DMAOBJ) | - (1ULL << NVKM_ENGINE_GR) | - (1ULL << NVKM_ENGINE_MPEG) | - (1ULL << NVKM_ENGINE_SW), + BIT(NV04_FIFO_ENGN_SW) | + BIT(NV04_FIFO_ENGN_GR) | + BIT(NV04_FIFO_ENGN_MPEG) | + BIT(NV04_FIFO_ENGN_DMA), 0, 0xc00000, 0x1000, oclass, &chan->base); chan->fifo = fifo; if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c index ff7b529764fe..c0a7d0f21dac 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c @@ -38,12 +38,82 @@ g84_fifo_uevent_init(struct nvkm_fifo *fifo) nvkm_mask(device, 0x002140, 0x40000000, 0x40000000); } +static struct nvkm_engine * +g84_fifo_id_engine(struct nvkm_fifo *fifo, int engi) +{ + struct nvkm_device *device = fifo->engine.subdev.device; + struct nvkm_engine *engine; + enum nvkm_subdev_type type; + + switch (engi) { + case G84_FIFO_ENGN_SW : type = NVKM_ENGINE_SW; break; + case G84_FIFO_ENGN_GR : type = NVKM_ENGINE_GR; break; + case G84_FIFO_ENGN_MPEG : + if ((engine = nvkm_device_engine(device, NVKM_ENGINE_MSPPP, 0))) + return engine; + type = NVKM_ENGINE_MPEG; + break; + case G84_FIFO_ENGN_ME : + if ((engine = nvkm_device_engine(device, NVKM_ENGINE_CE, 0))) + return engine; + type = NVKM_ENGINE_ME; + break; + case G84_FIFO_ENGN_VP : + if ((engine = nvkm_device_engine(device, NVKM_ENGINE_MSPDEC, 0))) + return engine; + type = NVKM_ENGINE_VP; + break; + case G84_FIFO_ENGN_CIPHER: + if ((engine = nvkm_device_engine(device, NVKM_ENGINE_VIC, 0))) + return engine; + if ((engine = nvkm_device_engine(device, NVKM_ENGINE_SEC, 0))) + return engine; + type = NVKM_ENGINE_CIPHER; + break; + case G84_FIFO_ENGN_BSP : + if ((engine = nvkm_device_engine(device, NVKM_ENGINE_MSVLD, 0))) + return engine; + type = NVKM_ENGINE_BSP; + break; + case G84_FIFO_ENGN_DMA : type = NVKM_ENGINE_DMAOBJ; break; + default: + WARN_ON(1); + return NULL; + } + + return nvkm_device_engine(fifo->engine.subdev.device, type, 0); +} + +static int +g84_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine) +{ + switch (engine->subdev.type) { + case NVKM_ENGINE_SW : return G84_FIFO_ENGN_SW; + case NVKM_ENGINE_GR : return G84_FIFO_ENGN_GR; + case NVKM_ENGINE_MPEG : + case NVKM_ENGINE_MSPPP : return G84_FIFO_ENGN_MPEG; + case NVKM_ENGINE_CE : return G84_FIFO_ENGN_CE0; + case NVKM_ENGINE_VP : + case NVKM_ENGINE_MSPDEC: return G84_FIFO_ENGN_VP; + case NVKM_ENGINE_CIPHER: + case NVKM_ENGINE_SEC : return G84_FIFO_ENGN_CIPHER; + case NVKM_ENGINE_BSP : + case NVKM_ENGINE_MSVLD : return G84_FIFO_ENGN_BSP; + case NVKM_ENGINE_DMAOBJ: return G84_FIFO_ENGN_DMA; + default: + WARN_ON(1); + return -1; + } +} + static const struct nvkm_fifo_func g84_fifo = { .dtor = nv50_fifo_dtor, .oneinit = nv50_fifo_oneinit, .init = nv50_fifo_init, .intr = nv04_fifo_intr, + .engine_id = g84_fifo_engine_id, + .id_engine = g84_fifo_id_engine, .pause = nv04_fifo_pause, .start = nv04_fifo_start, .uevent_init = g84_fifo_uevent_init, @@ -56,7 +126,8 @@ g84_fifo = { }; int -g84_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +g84_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return nv50_fifo_new_(&g84_fifo, device, index, pfifo); + return nv50_fifo_new_(&g84_fifo, device, type, inst, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c index 5a39e51d42d7..8b4f36b3e34b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c @@ -57,7 +57,7 @@ gf100_fifo_runlist_commit(struct gf100_fifo *fifo) int nr = 0; int target; - mutex_lock(&subdev->mutex); + mutex_lock(&fifo->base.mutex); cur = fifo->runlist.mem[fifo->runlist.active]; fifo->runlist.active = !fifo->runlist.active; @@ -73,7 +73,7 @@ gf100_fifo_runlist_commit(struct gf100_fifo *fifo) case NVKM_MEM_TARGET_VRAM: target = 0; break; case NVKM_MEM_TARGET_NCOH: target = 3; break; default: - mutex_unlock(&subdev->mutex); + mutex_unlock(&fifo->base.mutex); WARN_ON(1); return; } @@ -86,59 +86,61 @@ gf100_fifo_runlist_commit(struct gf100_fifo *fifo) !(nvkm_rd32(device, 0x00227c) & 0x00100000), msecs_to_jiffies(2000)) == 0) nvkm_error(subdev, "runlist update timeout\n"); - mutex_unlock(&subdev->mutex); + mutex_unlock(&fifo->base.mutex); } void gf100_fifo_runlist_remove(struct gf100_fifo *fifo, struct gf100_fifo_chan *chan) { - mutex_lock(&fifo->base.engine.subdev.mutex); + mutex_lock(&fifo->base.mutex); list_del_init(&chan->head); - mutex_unlock(&fifo->base.engine.subdev.mutex); + mutex_unlock(&fifo->base.mutex); } void gf100_fifo_runlist_insert(struct gf100_fifo *fifo, struct gf100_fifo_chan *chan) { - mutex_lock(&fifo->base.engine.subdev.mutex); + mutex_lock(&fifo->base.mutex); list_add_tail(&chan->head, &fifo->chan); - mutex_unlock(&fifo->base.engine.subdev.mutex); + mutex_unlock(&fifo->base.mutex); } -static inline int -gf100_fifo_engidx(struct gf100_fifo *fifo, u32 engn) +static struct nvkm_engine * +gf100_fifo_id_engine(struct nvkm_fifo *fifo, int engi) { - switch (engn) { - case NVKM_ENGINE_GR : engn = 0; break; - case NVKM_ENGINE_MSVLD : engn = 1; break; - case NVKM_ENGINE_MSPPP : engn = 2; break; - case NVKM_ENGINE_MSPDEC: engn = 3; break; - case NVKM_ENGINE_CE0 : engn = 4; break; - case NVKM_ENGINE_CE1 : engn = 5; break; + enum nvkm_subdev_type type; + int inst; + + switch (engi) { + case GF100_FIFO_ENGN_GR : type = NVKM_ENGINE_GR ; inst = 0; break; + case GF100_FIFO_ENGN_MSPDEC: type = NVKM_ENGINE_MSPDEC; inst = 0; break; + case GF100_FIFO_ENGN_MSPPP : type = NVKM_ENGINE_MSPPP ; inst = 0; break; + case GF100_FIFO_ENGN_MSVLD : type = NVKM_ENGINE_MSVLD ; inst = 0; break; + case GF100_FIFO_ENGN_CE0 : type = NVKM_ENGINE_CE ; inst = 0; break; + case GF100_FIFO_ENGN_CE1 : type = NVKM_ENGINE_CE ; inst = 1; break; + case GF100_FIFO_ENGN_SW : type = NVKM_ENGINE_SW ; inst = 0; break; default: - return -1; + WARN_ON(1); + return NULL; } - return engn; + return nvkm_device_engine(fifo->engine.subdev.device, type, inst); } -static inline struct nvkm_engine * -gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn) +static int +gf100_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine) { - struct nvkm_device *device = fifo->base.engine.subdev.device; - - switch (engn) { - case 0: engn = NVKM_ENGINE_GR; break; - case 1: engn = NVKM_ENGINE_MSVLD; break; - case 2: engn = NVKM_ENGINE_MSPPP; break; - case 3: engn = NVKM_ENGINE_MSPDEC; break; - case 4: engn = NVKM_ENGINE_CE0; break; - case 5: engn = NVKM_ENGINE_CE1; break; + switch (engine->subdev.type) { + case NVKM_ENGINE_GR : return GF100_FIFO_ENGN_GR; + case NVKM_ENGINE_MSPDEC: return GF100_FIFO_ENGN_MSPDEC; + case NVKM_ENGINE_MSPPP : return GF100_FIFO_ENGN_MSPPP; + case NVKM_ENGINE_MSVLD : return GF100_FIFO_ENGN_MSVLD; + case NVKM_ENGINE_CE : return GF100_FIFO_ENGN_CE0 + engine->subdev.inst; + case NVKM_ENGINE_SW : return GF100_FIFO_ENGN_SW; default: - return NULL; + WARN_ON(1); + return -1; } - - return nvkm_device_engine(device, engn); } static void @@ -148,20 +150,17 @@ gf100_fifo_recover_work(struct work_struct *w) struct nvkm_device *device = fifo->base.engine.subdev.device; struct nvkm_engine *engine; unsigned long flags; - u32 engn, engm = 0; - u64 mask, todo; + u32 engm, engn, todo; spin_lock_irqsave(&fifo->base.lock, flags); - mask = fifo->recover.mask; + engm = fifo->recover.mask; fifo->recover.mask = 0ULL; spin_unlock_irqrestore(&fifo->base.lock, flags); - for (todo = mask; engn = __ffs64(todo), todo; todo &= ~BIT_ULL(engn)) - engm |= 1 << gf100_fifo_engidx(fifo, engn); nvkm_mask(device, 0x002630, engm, engm); - for (todo = mask; engn = __ffs64(todo), todo; todo &= ~BIT_ULL(engn)) { - if ((engine = nvkm_device_engine(device, engn))) { + for (todo = engm; engn = __ffs(todo), todo; todo &= ~BIT_ULL(engn)) { + if ((engine = gf100_fifo_id_engine(&fifo->base, engn))) { nvkm_subdev_fini(&engine->subdev, false); WARN_ON(nvkm_subdev_init(&engine->subdev)); } @@ -179,17 +178,18 @@ gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine, struct nvkm_subdev *subdev = &fifo->base.engine.subdev; struct nvkm_device *device = subdev->device; u32 chid = chan->base.chid; + int engi = gf100_fifo_engine_id(&fifo->base, engine); nvkm_error(subdev, "%s engine fault on channel %d, recovering...\n", - nvkm_subdev_name[engine->subdev.index], chid); + engine->subdev.name, chid); assert_spin_locked(&fifo->base.lock); nvkm_mask(device, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000); list_del_init(&chan->head); chan->killed = true; - if (engine != &fifo->base.engine) - fifo->recover.mask |= 1ULL << engine->subdev.index; + if (engi >= 0 && engi != GF100_FIFO_ENGN_SW) + fifo->recover.mask |= BIT(engi); schedule_work(&fifo->recover.work); nvkm_fifo_kevent(&fifo->base, chid); } @@ -205,8 +205,8 @@ gf100_fifo_fault_engine[] = { { 0x11, "PMSPPP", NULL, NVKM_ENGINE_MSPPP }, { 0x13, "PCOUNTER" }, { 0x14, "PMSPDEC", NULL, NVKM_ENGINE_MSPDEC }, - { 0x15, "PCE0", NULL, NVKM_ENGINE_CE0 }, - { 0x16, "PCE1", NULL, NVKM_ENGINE_CE1 }, + { 0x15, "PCE0", NULL, NVKM_ENGINE_CE, 0 }, + { 0x16, "PCE1", NULL, NVKM_ENGINE_CE, 1 }, { 0x17, "PMU" }, {} }; @@ -286,7 +286,7 @@ gf100_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info) nvkm_mask(device, 0x001718, 0x00000000, 0x00000000); break; default: - engine = nvkm_device_engine(device, eu->data2); + engine = nvkm_device_engine(device, eu->data2, eu->inst); break; } } @@ -335,7 +335,7 @@ gf100_fifo_intr_sched_ctxsw(struct gf100_fifo *fifo) if (busy && unk0 && unk1) { list_for_each_entry(chan, &fifo->chan, head) { if (chan->base.chid == chid) { - engine = gf100_fifo_engine(fifo, engn); + engine = gf100_fifo_id_engine(&fifo->base, engn); if (!engine) break; gf100_fifo_recover(fifo, engine, chan); @@ -673,6 +673,8 @@ gf100_fifo = { .fini = gf100_fifo_fini, .intr = gf100_fifo_intr, .fault = gf100_fifo_fault, + .engine_id = gf100_fifo_engine_id, + .id_engine = gf100_fifo_id_engine, .uevent_init = gf100_fifo_uevent_init, .uevent_fini = gf100_fifo_uevent_fini, .chan = { @@ -682,7 +684,8 @@ gf100_fifo = { }; int -gf100_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +gf100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { struct gf100_fifo *fifo; @@ -692,5 +695,5 @@ gf100_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) INIT_WORK(&fifo->recover.work, gf100_fifo_recover_work); *pfifo = &fifo->base; - return nvkm_fifo_ctor(&gf100_fifo, device, index, 128, &fifo->base); + return nvkm_fifo_ctor(&gf100_fifo, device, type, inst, 128, &fifo->base); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index c73b7eab776e..69da601f1754 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -168,12 +168,11 @@ gk104_fifo_runlist_update(struct gk104_fifo *fifo, int runl) { const struct gk104_fifo_runlist_func *func = fifo->func->runlist; struct gk104_fifo_chan *chan; - struct nvkm_subdev *subdev = &fifo->base.engine.subdev; struct nvkm_memory *mem; struct nvkm_fifo_cgrp *cgrp; int nr = 0; - mutex_lock(&subdev->mutex); + mutex_lock(&fifo->base.mutex); mem = fifo->runlist[runl].mem[fifo->runlist[runl].next]; fifo->runlist[runl].next = !fifo->runlist[runl].next; @@ -191,27 +190,27 @@ gk104_fifo_runlist_update(struct gk104_fifo *fifo, int runl) nvkm_done(mem); func->commit(fifo, runl, mem, nr); - mutex_unlock(&subdev->mutex); + mutex_unlock(&fifo->base.mutex); } void gk104_fifo_runlist_remove(struct gk104_fifo *fifo, struct gk104_fifo_chan *chan) { struct nvkm_fifo_cgrp *cgrp = chan->cgrp; - mutex_lock(&fifo->base.engine.subdev.mutex); + mutex_lock(&fifo->base.mutex); if (!list_empty(&chan->head)) { list_del_init(&chan->head); if (cgrp && !--cgrp->chan_nr) list_del_init(&cgrp->head); } - mutex_unlock(&fifo->base.engine.subdev.mutex); + mutex_unlock(&fifo->base.mutex); } void gk104_fifo_runlist_insert(struct gk104_fifo *fifo, struct gk104_fifo_chan *chan) { struct nvkm_fifo_cgrp *cgrp = chan->cgrp; - mutex_lock(&fifo->base.engine.subdev.mutex); + mutex_lock(&fifo->base.mutex); if (cgrp) { if (!cgrp->chan_nr++) list_add_tail(&cgrp->head, &fifo->runlist[chan->runl].cgrp); @@ -219,7 +218,7 @@ gk104_fifo_runlist_insert(struct gk104_fifo *fifo, struct gk104_fifo_chan *chan) } else { list_add_tail(&chan->head, &fifo->runlist[chan->runl].chan); } - mutex_unlock(&fifo->base.engine.subdev.mutex); + mutex_unlock(&fifo->base.mutex); } void @@ -259,6 +258,30 @@ gk104_fifo_pbdma = { .init = gk104_fifo_pbdma_init, }; +struct nvkm_engine * +gk104_fifo_id_engine(struct nvkm_fifo *base, int engi) +{ + return gk104_fifo(base)->engine[engi].engine; +} + +int +gk104_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine) +{ + struct gk104_fifo *fifo = gk104_fifo(base); + int engn; + + if (engine->subdev.type == NVKM_ENGINE_SW) + return GK104_FIFO_ENGN_SW; + + for (engn = 0; engn < fifo->engine_nr && engine; engn++) { + if (fifo->engine[engn].engine == engine) + return engn; + } + + WARN_ON(1); + return -1; +} + static void gk104_fifo_recover_work(struct work_struct *w) { @@ -410,11 +433,12 @@ gk104_fifo_recover_engn(struct gk104_fifo *fifo, int engn) * called from the fault handler already. */ if (!status.faulted && engine) { - mmui = nvkm_top_fault_id(device, engine->subdev.index); + mmui = nvkm_top_fault_id(device, engine->subdev.type, engine->subdev.inst); if (mmui < 0) { const struct nvkm_enum *en = fifo->func->fault.engine; for (; en && en->name; en++) { - if (en->data2 == engine->subdev.index) { + if (en->data2 == engine->subdev.type && + en->inst == engine->subdev.inst) { mmui = en->value; break; } @@ -459,8 +483,8 @@ gk104_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info) struct nvkm_engine *engine = NULL; struct nvkm_fifo_chan *chan; unsigned long flags; - char ct[8] = "HUB/", en[16] = ""; - int engn; + const char *en = ""; + char ct[8] = "HUB/"; er = nvkm_enum_find(fifo->func->fault.reason, info->reason); ee = nvkm_enum_find(fifo->func->fault.engine, info->engine); @@ -484,23 +508,20 @@ gk104_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info) nvkm_mask(device, 0x001718, 0x00000000, 0x00000000); break; default: - engine = nvkm_device_engine(device, ee->data2); + engine = nvkm_device_engine(device, ee->data2, 0); break; } } if (ee == NULL) { - enum nvkm_devidx engidx = nvkm_top_fault(device, info->engine); - if (engidx < NVKM_SUBDEV_NR) { - const char *src = nvkm_subdev_name[engidx]; - char *dst = en; - do { - *dst++ = toupper(*src++); - } while(*src); - engine = nvkm_device_engine(device, engidx); + struct nvkm_subdev *subdev = nvkm_top_fault(device, info->engine); + if (subdev) { + if (subdev->func == &nvkm_engine) + engine = container_of(subdev, typeof(*engine), subdev); + en = engine->subdev.name; } } else { - snprintf(en, sizeof(en), "%s", ee->name); + en = ee->name; } spin_lock_irqsave(&fifo->base.lock, flags); @@ -523,11 +544,10 @@ gk104_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info) * correct engine(s), but just in case we can't find the channel * information... */ - for (engn = 0; engn < fifo->engine_nr && engine; engn++) { - if (fifo->engine[engn].engine == engine) { + if (engine) { + int engn = fifo->base.func->engine_id(&fifo->base, engine); + if (engn >= 0 && engn != GK104_FIFO_ENGN_SW) gk104_fifo_recover_engn(fifo, engn); - break; - } } spin_unlock_irqrestore(&fifo->base.lock, flags); @@ -864,19 +884,41 @@ gk104_fifo_info(struct nvkm_fifo *base, u64 mthd, u64 *data) { struct gk104_fifo *fifo = gk104_fifo(base); switch (mthd) { - case NV_DEVICE_FIFO_RUNLISTS: + case NV_DEVICE_HOST_RUNLISTS: *data = (1ULL << fifo->runlist_nr) - 1; return 0; - case NV_DEVICE_FIFO_RUNLIST_ENGINES(0)... - NV_DEVICE_FIFO_RUNLIST_ENGINES(63): { - int runl = mthd - NV_DEVICE_FIFO_RUNLIST_ENGINES(0), engn; - if (runl < fifo->runlist_nr) { - unsigned long engm = fifo->runlist[runl].engm; + case NV_DEVICE_HOST_RUNLIST_ENGINES: { + if (*data < fifo->runlist_nr) { + unsigned long engm = fifo->runlist[*data].engm; struct nvkm_engine *engine; + int engn; *data = 0; for_each_set_bit(engn, &engm, fifo->engine_nr) { - if ((engine = fifo->engine[engn].engine)) - *data |= BIT_ULL(engine->subdev.index); + if ((engine = fifo->engine[engn].engine)) { +#define CASE(n) case NVKM_ENGINE_##n: *data |= NV_DEVICE_HOST_RUNLIST_ENGINES_##n; break + switch (engine->subdev.type) { + CASE(SW ); + CASE(GR ); + CASE(MPEG ); + CASE(ME ); + CASE(CIPHER); + CASE(BSP ); + CASE(VP ); + CASE(CE ); + CASE(SEC ); + CASE(MSVLD ); + CASE(MSPDEC); + CASE(MSPPP ); + CASE(MSENC ); + CASE(VIC ); + CASE(SEC2 ); + CASE(NVDEC ); + CASE(NVENC ); + default: + WARN_ON(1); + break; + } + } } return 0; } @@ -894,8 +936,8 @@ gk104_fifo_oneinit(struct nvkm_fifo *base) struct nvkm_subdev *subdev = &fifo->base.engine.subdev; struct nvkm_device *device = subdev->device; struct nvkm_vmm *bar = nvkm_bar_bar1_vmm(device); - int engn, runl, pbid, ret, i, j; - enum nvkm_devidx engidx; + struct nvkm_top_device *tdev; + int pbid, ret, i, j; u32 *map; fifo->pbdma_nr = fifo->func->pbdma->nr(fifo); @@ -909,25 +951,41 @@ gk104_fifo_oneinit(struct nvkm_fifo *base) map[i] = nvkm_rd32(device, 0x002390 + (i * 0x04)); /* Determine runlist configuration from topology device info. */ - i = 0; - while ((int)(engidx = nvkm_top_engine(device, i++, &runl, &engn)) >= 0) { + list_for_each_entry(tdev, &device->top->device, head) { + const int engn = tdev->engine; + char _en[16], *en; + + if (engn < 0) + continue; + /* Determine which PBDMA handles requests for this engine. */ for (j = 0, pbid = -1; j < fifo->pbdma_nr; j++) { - if (map[j] & (1 << runl)) { + if (map[j] & BIT(tdev->runlist)) { pbid = j; break; } } + fifo->engine[engn].engine = nvkm_device_engine(device, tdev->type, tdev->inst); + if (!fifo->engine[engn].engine) { + snprintf(_en, sizeof(_en), "%s, %d", + nvkm_subdev_type[tdev->type], tdev->inst); + en = _en; + } else { + en = fifo->engine[engn].engine->subdev.name; + } + nvkm_debug(subdev, "engine %2d: runlist %2d pbdma %2d (%s)\n", - engn, runl, pbid, nvkm_subdev_name[engidx]); + tdev->engine, tdev->runlist, pbid, en); - fifo->engine[engn].engine = nvkm_device_engine(device, engidx); - fifo->engine[engn].runl = runl; + fifo->engine[engn].runl = tdev->runlist; fifo->engine[engn].pbid = pbid; fifo->engine_nr = max(fifo->engine_nr, engn + 1); - fifo->runlist[runl].engm |= 1 << engn; - fifo->runlist_nr = max(fifo->runlist_nr, runl + 1); + fifo->runlist[tdev->runlist].engm |= BIT(engn); + fifo->runlist[tdev->runlist].engm_sw |= BIT(engn); + if (tdev->type == NVKM_ENGINE_GR) + fifo->runlist[tdev->runlist].engm_sw |= BIT(GK104_FIFO_ENGN_SW); + fifo->runlist_nr = max(fifo->runlist_nr, tdev->runlist + 1); } kfree(map); @@ -1021,6 +1079,8 @@ gk104_fifo_ = { .fini = gk104_fifo_fini, .intr = gk104_fifo_intr, .fault = gk104_fifo_fault, + .engine_id = gk104_fifo_engine_id, + .id_engine = gk104_fifo_id_engine, .uevent_init = gk104_fifo_uevent_init, .uevent_fini = gk104_fifo_uevent_fini, .recover_chan = gk104_fifo_recover_chan, @@ -1030,7 +1090,7 @@ gk104_fifo_ = { int gk104_fifo_new_(const struct gk104_fifo_func *func, struct nvkm_device *device, - int index, int nr, struct nvkm_fifo **pfifo) + enum nvkm_subdev_type type, int inst, int nr, struct nvkm_fifo **pfifo) { struct gk104_fifo *fifo; @@ -1040,7 +1100,7 @@ gk104_fifo_new_(const struct gk104_fifo_func *func, struct nvkm_device *device, INIT_WORK(&fifo->recover.work, gk104_fifo_recover_work); *pfifo = &fifo->base; - return nvkm_fifo_ctor(&gk104_fifo_, device, index, nr, &fifo->base); + return nvkm_fifo_ctor(&gk104_fifo_, device, type, inst, nr, &fifo->base); } const struct nvkm_enum @@ -1072,12 +1132,12 @@ gk104_fifo_fault_engine[] = { { 0x11, "MSPPP", NULL, NVKM_ENGINE_MSPPP }, { 0x13, "PERF" }, { 0x14, "MSPDEC", NULL, NVKM_ENGINE_MSPDEC }, - { 0x15, "CE0", NULL, NVKM_ENGINE_CE0 }, - { 0x16, "CE1", NULL, NVKM_ENGINE_CE1 }, + { 0x15, "CE0", NULL, NVKM_ENGINE_CE, 0 }, + { 0x16, "CE1", NULL, NVKM_ENGINE_CE, 1 }, { 0x17, "PMU" }, { 0x18, "PTP" }, { 0x19, "MSENC", NULL, NVKM_ENGINE_MSENC }, - { 0x1b, "CE2", NULL, NVKM_ENGINE_CE2 }, + { 0x1b, "CE2", NULL, NVKM_ENGINE_CE, 2 }, {} }; @@ -1179,7 +1239,8 @@ gk104_fifo = { }; int -gk104_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +gk104_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return gk104_fifo_new_(&gk104_fifo, device, index, 4096, pfifo); + return gk104_fifo_new_(&gk104_fifo, device, type, inst, 4096, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h index 4398b340e514..f2d12ae73944 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h @@ -35,6 +35,7 @@ struct gk104_fifo { struct list_head cgrp; struct list_head chan; u32 engm; + u32 engm_sw; } runlist[16]; int runlist_nr; @@ -99,7 +100,7 @@ struct gk104_fifo_engine_status { } prev, next, *chan; }; -int gk104_fifo_new_(const struct gk104_fifo_func *, struct nvkm_device *, +int gk104_fifo_new_(const struct gk104_fifo_func *, struct nvkm_device *, enum nvkm_subdev_type, int index, int nr, struct nvkm_fifo **); void gk104_fifo_runlist_insert(struct gk104_fifo *, struct gk104_fifo_chan *); void gk104_fifo_runlist_remove(struct gk104_fifo *, struct gk104_fifo_chan *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c index f820969e4405..915278c7e012 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c @@ -60,7 +60,8 @@ gk110_fifo = { }; int -gk110_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +gk110_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return gk104_fifo_new_(&gk110_fifo, device, index, 4096, pfifo); + return gk104_fifo_new_(&gk110_fifo, device, type, inst, 4096, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c index 2f54787b5fd0..cb703693de52 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c @@ -57,7 +57,8 @@ gk208_fifo = { }; int -gk208_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +gk208_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return gk104_fifo_new_(&gk208_fifo, device, index, 1024, pfifo); + return gk104_fifo_new_(&gk208_fifo, device, type, inst, 1024, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c index a814c4e0ed3e..6e35cf44c640 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c @@ -38,7 +38,8 @@ gk20a_fifo = { }; int -gk20a_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +gk20a_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return gk104_fifo_new_(&gk20a_fifo, device, index, 128, pfifo); + return gk104_fifo_new_(&gk20a_fifo, device, type, inst, 128, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c index c2a2e4572f6c..7af6e687d474 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c @@ -106,7 +106,8 @@ gm107_fifo = { }; int -gm107_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +gm107_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return gk104_fifo_new_(&gm107_fifo, device, index, 2048, pfifo); + return gk104_fifo_new_(&gm107_fifo, device, type, inst, 2048, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c index b8cfe3b28c4f..573658cb6c73 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c @@ -54,7 +54,8 @@ gm200_fifo = { }; int -gm200_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +gm200_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return gk104_fifo_new_(&gm200_fifo, device, index, 4096, pfifo); + return gk104_fifo_new_(&gm200_fifo, device, type, inst, 4096, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c index 70b4feebc1fa..556c97e54f14 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c @@ -38,7 +38,8 @@ gm20b_fifo = { }; int -gm20b_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +gm20b_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return gk104_fifo_new_(&gm20b_fifo, device, index, 512, pfifo); + return gk104_fifo_new_(&gm20b_fifo, device, type, inst, 512, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c index 2c7a0176b3c8..6b46b6b65b87 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c @@ -91,7 +91,8 @@ gp100_fifo = { }; int -gp100_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +gp100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return gk104_fifo_new_(&gp100_fifo, device, index, 4096, pfifo); + return gk104_fifo_new_(&gp100_fifo, device, type, inst, 4096, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp10b.c index 8c65ad4feedb..7a5929cb4d29 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp10b.c @@ -39,7 +39,8 @@ gp10b_fifo = { }; int -gp10b_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +gp10b_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return gk104_fifo_new_(&gp10b_fifo, device, index, 512, pfifo); + return gk104_fifo_new_(&gp10b_fifo, device, type, inst, 512, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c index 75f9632789b3..4e78bbe3b94b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c @@ -52,11 +52,10 @@ gf100_fifo_chan_ntfy(struct nvkm_fifo_chan *chan, u32 type, static u32 gf100_fifo_gpfifo_engine_addr(struct nvkm_engine *engine) { - switch (engine->subdev.index) { + switch (engine->subdev.type) { case NVKM_ENGINE_SW : return 0; case NVKM_ENGINE_GR : return 0x0210; - case NVKM_ENGINE_CE0 : return 0x0230; - case NVKM_ENGINE_CE1 : return 0x0240; + case NVKM_ENGINE_CE : return 0x0230 + (engine->subdev.inst * 0x10); case NVKM_ENGINE_MSPDEC: return 0x0250; case NVKM_ENGINE_MSPPP : return 0x0260; case NVKM_ENGINE_MSVLD : return 0x0270; @@ -66,6 +65,15 @@ gf100_fifo_gpfifo_engine_addr(struct nvkm_engine *engine) } } +static struct gf100_fifo_engn * +gf100_fifo_gpfifo_engine(struct gf100_fifo_chan *chan, struct nvkm_engine *engine) +{ + int engi = chan->base.fifo->func->engine_id(chan->base.fifo, engine); + if (engi >= 0) + return &chan->engn[engi]; + return NULL; +} + static int gf100_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base, struct nvkm_engine *engine, bool suspend) @@ -77,7 +85,7 @@ gf100_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base, struct nvkm_gpuobj *inst = chan->base.inst; int ret = 0; - mutex_lock(&subdev->mutex); + mutex_lock(&chan->fifo->base.mutex); nvkm_wr32(device, 0x002634, chan->base.chid); if (nvkm_msec(device, 2000, if (nvkm_rd32(device, 0x002634) == chan->base.chid) @@ -87,7 +95,7 @@ gf100_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base, chan->base.chid, chan->base.object.client->name); ret = -ETIMEDOUT; } - mutex_unlock(&subdev->mutex); + mutex_unlock(&chan->fifo->base.mutex); if (ret && suspend) return ret; @@ -108,13 +116,13 @@ gf100_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base, { const u32 offset = gf100_fifo_gpfifo_engine_addr(engine); struct gf100_fifo_chan *chan = gf100_fifo_chan(base); + struct gf100_fifo_engn *engn = gf100_fifo_gpfifo_engine(chan, engine); struct nvkm_gpuobj *inst = chan->base.inst; if (offset) { - u64 addr = chan->engn[engine->subdev.index].vma->addr; nvkm_kmap(inst); - nvkm_wo32(inst, offset + 0x00, lower_32_bits(addr) | 4); - nvkm_wo32(inst, offset + 0x04, upper_32_bits(addr)); + nvkm_wo32(inst, offset + 0x00, lower_32_bits(engn->vma->addr) | 4); + nvkm_wo32(inst, offset + 0x04, upper_32_bits(engn->vma->addr)); nvkm_done(inst); } @@ -126,8 +134,9 @@ gf100_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan *base, struct nvkm_engine *engine) { struct gf100_fifo_chan *chan = gf100_fifo_chan(base); - nvkm_vmm_put(chan->base.vmm, &chan->engn[engine->subdev.index].vma); - nvkm_gpuobj_del(&chan->engn[engine->subdev.index].inst); + struct gf100_fifo_engn *engn = gf100_fifo_gpfifo_engine(chan, engine); + nvkm_vmm_put(chan->base.vmm, &engn->vma); + nvkm_gpuobj_del(&engn->inst); } static int @@ -136,23 +145,21 @@ gf100_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base, struct nvkm_object *object) { struct gf100_fifo_chan *chan = gf100_fifo_chan(base); - int engn = engine->subdev.index; + struct gf100_fifo_engn *engn = gf100_fifo_gpfifo_engine(chan, engine); int ret; if (!gf100_fifo_gpfifo_engine_addr(engine)) return 0; - ret = nvkm_object_bind(object, NULL, 0, &chan->engn[engn].inst); + ret = nvkm_object_bind(object, NULL, 0, &engn->inst); if (ret) return ret; - ret = nvkm_vmm_get(chan->base.vmm, 12, chan->engn[engn].inst->size, - &chan->engn[engn].vma); + ret = nvkm_vmm_get(chan->base.vmm, 12, engn->inst->size, &engn->vma); if (ret) return ret; - return nvkm_memory_map(chan->engn[engn].inst, 0, chan->base.vmm, - chan->engn[engn].vma, NULL, 0); + return nvkm_memory_map(engn->inst, 0, chan->base.vmm, engn->vma, NULL, 0); } static void @@ -243,13 +250,13 @@ gf100_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, ret = nvkm_fifo_chan_ctor(&gf100_fifo_gpfifo_func, &fifo->base, 0x1000, 0x1000, true, args->v0.vmm, 0, - (1ULL << NVKM_ENGINE_CE0) | - (1ULL << NVKM_ENGINE_CE1) | - (1ULL << NVKM_ENGINE_GR) | - (1ULL << NVKM_ENGINE_MSPDEC) | - (1ULL << NVKM_ENGINE_MSPPP) | - (1ULL << NVKM_ENGINE_MSVLD) | - (1ULL << NVKM_ENGINE_SW), + BIT(GF100_FIFO_ENGN_GR) | + BIT(GF100_FIFO_ENGN_MSPDEC) | + BIT(GF100_FIFO_ENGN_MSPPP) | + BIT(GF100_FIFO_ENGN_MSVLD) | + BIT(GF100_FIFO_ENGN_CE0) | + BIT(GF100_FIFO_ENGN_CE1) | + BIT(GF100_FIFO_ENGN_SW), 1, fifo->user.bar->addr, 0x1000, oclass, &chan->base); if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c index 728a1edbf98c..b6900a52bcce 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c @@ -65,19 +65,18 @@ int gk104_fifo_gpfifo_kick(struct gk104_fifo_chan *chan) { int ret; - mutex_lock(&chan->base.fifo->engine.subdev.mutex); + mutex_lock(&chan->base.fifo->mutex); ret = gk104_fifo_gpfifo_kick_locked(chan); - mutex_unlock(&chan->base.fifo->engine.subdev.mutex); + mutex_unlock(&chan->base.fifo->mutex); return ret; } static u32 gk104_fifo_gpfifo_engine_addr(struct nvkm_engine *engine) { - switch (engine->subdev.index) { + switch (engine->subdev.type) { case NVKM_ENGINE_SW : - case NVKM_ENGINE_CE0...NVKM_ENGINE_CE_LAST: - return 0; + case NVKM_ENGINE_CE : return 0; case NVKM_ENGINE_GR : return 0x0210; case NVKM_ENGINE_SEC : return 0x0220; case NVKM_ENGINE_MSPDEC: return 0x0250; @@ -85,15 +84,26 @@ gk104_fifo_gpfifo_engine_addr(struct nvkm_engine *engine) case NVKM_ENGINE_MSVLD : return 0x0270; case NVKM_ENGINE_VIC : return 0x0280; case NVKM_ENGINE_MSENC : return 0x0290; - case NVKM_ENGINE_NVDEC0: return 0x02100270; - case NVKM_ENGINE_NVENC0: return 0x02100290; - case NVKM_ENGINE_NVENC1: return 0x0210; + case NVKM_ENGINE_NVDEC : return 0x02100270; + case NVKM_ENGINE_NVENC : + if (engine->subdev.inst) + return 0x0210; + return 0x02100290; default: WARN_ON(1); return 0; } } +struct gk104_fifo_engn * +gk104_fifo_gpfifo_engine(struct gk104_fifo_chan *chan, struct nvkm_engine *engine) +{ + int engi = chan->base.fifo->func->engine_id(chan->base.fifo, engine); + if (engi >= 0) + return &chan->engn[engi]; + return NULL; +} + static int gk104_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base, struct nvkm_engine *engine, bool suspend) @@ -126,13 +136,13 @@ gk104_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base, struct nvkm_engine *engine) { struct gk104_fifo_chan *chan = gk104_fifo_chan(base); + struct gk104_fifo_engn *engn = gk104_fifo_gpfifo_engine(chan, engine); struct nvkm_gpuobj *inst = chan->base.inst; u32 offset = gk104_fifo_gpfifo_engine_addr(engine); if (offset) { - u64 addr = chan->engn[engine->subdev.index].vma->addr; - u32 datalo = lower_32_bits(addr) | 0x00000004; - u32 datahi = upper_32_bits(addr); + u32 datalo = lower_32_bits(engn->vma->addr) | 0x00000004; + u32 datahi = upper_32_bits(engn->vma->addr); nvkm_kmap(inst); nvkm_wo32(inst, (offset & 0xffff) + 0x00, datalo); nvkm_wo32(inst, (offset & 0xffff) + 0x04, datahi); @@ -151,8 +161,9 @@ gk104_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan *base, struct nvkm_engine *engine) { struct gk104_fifo_chan *chan = gk104_fifo_chan(base); - nvkm_vmm_put(chan->base.vmm, &chan->engn[engine->subdev.index].vma); - nvkm_gpuobj_del(&chan->engn[engine->subdev.index].inst); + struct gk104_fifo_engn *engn = gk104_fifo_gpfifo_engine(chan, engine); + nvkm_vmm_put(chan->base.vmm, &engn->vma); + nvkm_gpuobj_del(&engn->inst); } int @@ -161,23 +172,21 @@ gk104_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base, struct nvkm_object *object) { struct gk104_fifo_chan *chan = gk104_fifo_chan(base); - int engn = engine->subdev.index; + struct gk104_fifo_engn *engn = gk104_fifo_gpfifo_engine(chan, engine); int ret; if (!gk104_fifo_gpfifo_engine_addr(engine)) return 0; - ret = nvkm_object_bind(object, NULL, 0, &chan->engn[engn].inst); + ret = nvkm_object_bind(object, NULL, 0, &engn->inst); if (ret) return ret; - ret = nvkm_vmm_get(chan->base.vmm, 12, chan->engn[engn].inst->size, - &chan->engn[engn].vma); + ret = nvkm_vmm_get(chan->base.vmm, 12, engn->inst->size, &engn->vma); if (ret) return ret; - return nvkm_memory_map(chan->engn[engn].inst, 0, chan->base.vmm, - chan->engn[engn].vma, NULL, 0); + return nvkm_memory_map(engn->inst, 0, chan->base.vmm, engn->vma, NULL, 0); } void @@ -247,23 +256,12 @@ gk104_fifo_gpfifo_new_(struct gk104_fifo *fifo, u64 *runlists, u16 *chid, { struct gk104_fifo_chan *chan; int runlist = ffs(*runlists) -1, ret, i; - unsigned long engm; - u64 subdevs = 0; u64 usermem; if (!vmm || runlist < 0 || runlist >= fifo->runlist_nr) return -EINVAL; *runlists = BIT_ULL(runlist); - engm = fifo->runlist[runlist].engm; - for_each_set_bit(i, &engm, fifo->engine_nr) { - if (fifo->engine[i].engine) - subdevs |= BIT_ULL(fifo->engine[i].engine->subdev.index); - } - - if (subdevs & BIT_ULL(NVKM_ENGINE_GR)) - subdevs |= BIT_ULL(NVKM_ENGINE_SW); - /* Allocate the channel. */ if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) return -ENOMEM; @@ -273,7 +271,7 @@ gk104_fifo_gpfifo_new_(struct gk104_fifo *fifo, u64 *runlists, u16 *chid, INIT_LIST_HEAD(&chan->head); ret = nvkm_fifo_chan_ctor(&gk104_fifo_gpfifo_func, &fifo->base, - 0x1000, 0x1000, true, vmm, 0, subdevs, + 0x1000, 0x1000, true, vmm, 0, fifo->runlist[runlist].engm_sw, 1, fifo->user.bar->addr, 0x200, oclass, &chan->base); if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c index a7462cf59d65..ee4967b706a7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c @@ -44,7 +44,7 @@ gv100_fifo_gpfifo_engine_valid(struct gk104_fifo_chan *chan, bool ce, bool valid int ret; /* Block runlist to prevent the channel from being rescheduled. */ - mutex_lock(&subdev->mutex); + mutex_lock(&chan->fifo->base.mutex); nvkm_mask(device, 0x002630, BIT(chan->runl), BIT(chan->runl)); /* Preempt the channel. */ @@ -58,7 +58,7 @@ gv100_fifo_gpfifo_engine_valid(struct gk104_fifo_chan *chan, bool ce, bool valid /* Resume runlist. */ nvkm_mask(device, 0x002630, BIT(chan->runl), 0); - mutex_unlock(&subdev->mutex); + mutex_unlock(&chan->fifo->base.mutex); return ret; } @@ -70,8 +70,7 @@ gv100_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base, struct nvkm_gpuobj *inst = chan->base.inst; int ret; - if (engine->subdev.index >= NVKM_ENGINE_CE0 && - engine->subdev.index <= NVKM_ENGINE_CE_LAST) + if (engine->subdev.type == NVKM_ENGINE_CE) return gk104_fifo_gpfifo_kick(chan); ret = gv100_fifo_gpfifo_engine_valid(chan, false, false); @@ -90,17 +89,15 @@ gv100_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base, struct nvkm_engine *engine) { struct gk104_fifo_chan *chan = gk104_fifo_chan(base); + struct gk104_fifo_engn *engn = gk104_fifo_gpfifo_engine(chan, engine); struct nvkm_gpuobj *inst = chan->base.inst; - u64 addr; - if (engine->subdev.index >= NVKM_ENGINE_CE0 && - engine->subdev.index <= NVKM_ENGINE_CE_LAST) + if (engine->subdev.type == NVKM_ENGINE_CE) return 0; - addr = chan->engn[engine->subdev.index].vma->addr; nvkm_kmap(inst); - nvkm_wo32(inst, 0x210, lower_32_bits(addr) | 0x00000004); - nvkm_wo32(inst, 0x214, upper_32_bits(addr)); + nvkm_wo32(inst, 0x210, lower_32_bits(engn->vma->addr) | 0x00000004); + nvkm_wo32(inst, 0x214, upper_32_bits(engn->vma->addr)); nvkm_done(inst); return gv100_fifo_gpfifo_engine_valid(chan, false, true); @@ -129,8 +126,6 @@ gv100_fifo_gpfifo_new_(const struct nvkm_fifo_chan_func *func, struct nvkm_device *device = fifo->base.engine.subdev.device; struct gk104_fifo_chan *chan; int runlist = ffs(*runlists) -1, ret, i; - unsigned long engm; - u64 subdevs = 0; u64 usermem, mthd; u32 size; @@ -138,12 +133,6 @@ gv100_fifo_gpfifo_new_(const struct nvkm_fifo_chan_func *func, return -EINVAL; *runlists = BIT_ULL(runlist); - engm = fifo->runlist[runlist].engm; - for_each_set_bit(i, &engm, fifo->engine_nr) { - if (fifo->engine[i].engine) - subdevs |= BIT_ULL(fifo->engine[i].engine->subdev.index); - } - /* Allocate the channel. */ if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) return -ENOMEM; @@ -153,7 +142,7 @@ gv100_fifo_gpfifo_new_(const struct nvkm_fifo_chan_func *func, INIT_LIST_HEAD(&chan->head); ret = nvkm_fifo_chan_ctor(func, &fifo->base, 0x1000, 0x1000, true, vmm, - 0, subdevs, 1, fifo->user.bar->addr, 0x200, + 0, fifo->runlist[runlist].engm, 1, fifo->user.bar->addr, 0x200, oclass, &chan->base); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c index 6ee1bb32a071..70e16a91ac12 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c @@ -301,7 +301,8 @@ gv100_fifo = { }; int -gv100_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +gv100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return gk104_fifo_new_(&gv100_fifo, device, index, 4096, pfifo); + return gk104_fifo_new_(&gv100_fifo, device, type, inst, 4096, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c index c1d1b1aa5bc6..c6730c124769 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c @@ -94,6 +94,38 @@ __releases(fifo->base.lock) spin_unlock_irqrestore(&fifo->base.lock, flags); } +struct nvkm_engine * +nv04_fifo_id_engine(struct nvkm_fifo *fifo, int engi) +{ + enum nvkm_subdev_type type; + + switch (engi) { + case NV04_FIFO_ENGN_SW : type = NVKM_ENGINE_SW; break; + case NV04_FIFO_ENGN_GR : type = NVKM_ENGINE_GR; break; + case NV04_FIFO_ENGN_MPEG: type = NVKM_ENGINE_MPEG; break; + case NV04_FIFO_ENGN_DMA : type = NVKM_ENGINE_DMAOBJ; break; + default: + WARN_ON(1); + return NULL; + } + + return nvkm_device_engine(fifo->engine.subdev.device, type, 0); +} + +int +nv04_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine) +{ + switch (engine->subdev.type) { + case NVKM_ENGINE_SW : return NV04_FIFO_ENGN_SW; + case NVKM_ENGINE_GR : return NV04_FIFO_ENGN_GR; + case NVKM_ENGINE_MPEG : return NV04_FIFO_ENGN_MPEG; + case NVKM_ENGINE_DMAOBJ: return NV04_FIFO_ENGN_DMA; + default: + WARN_ON(1); + return 0; + } +} + static const char * nv_dma_state_err(u32 state) { @@ -326,7 +358,7 @@ nv04_fifo_init(struct nvkm_fifo *base) int nv04_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device, - int index, int nr, const struct nv04_fifo_ramfc *ramfc, + enum nvkm_subdev_type type, int inst, int nr, const struct nv04_fifo_ramfc *ramfc, struct nvkm_fifo **pfifo) { struct nv04_fifo *fifo; @@ -337,7 +369,7 @@ nv04_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device, fifo->ramfc = ramfc; *pfifo = &fifo->base; - ret = nvkm_fifo_ctor(func, device, index, nr, &fifo->base); + ret = nvkm_fifo_ctor(func, device, type, inst, nr, &fifo->base); if (ret) return ret; @@ -349,6 +381,8 @@ static const struct nvkm_fifo_func nv04_fifo = { .init = nv04_fifo_init, .intr = nv04_fifo_intr, + .engine_id = nv04_fifo_engine_id, + .id_engine = nv04_fifo_id_engine, .pause = nv04_fifo_pause, .start = nv04_fifo_start, .chan = { @@ -358,8 +392,8 @@ nv04_fifo = { }; int -nv04_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +nv04_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return nv04_fifo_new_(&nv04_fifo, device, index, 16, - nv04_fifo_ramfc, pfifo); + return nv04_fifo_new_(&nv04_fifo, device, type, inst, 16, nv04_fifo_ramfc, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h index e5ecceee77ae..3f23bcde4a54 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h @@ -17,8 +17,7 @@ struct nv04_fifo { const struct nv04_fifo_ramfc *ramfc; }; -int nv04_fifo_new_(const struct nvkm_fifo_func *, struct nvkm_device *, - int index, int nr, const struct nv04_fifo_ramfc *, - struct nvkm_fifo **); +int nv04_fifo_new_(const struct nvkm_fifo_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + int nr, const struct nv04_fifo_ramfc *, struct nvkm_fifo **); void nv04_fifo_init(struct nvkm_fifo *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c index f9a87deb2b3d..f8887f0f2f82 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c @@ -43,6 +43,8 @@ static const struct nvkm_fifo_func nv10_fifo = { .init = nv04_fifo_init, .intr = nv04_fifo_intr, + .engine_id = nv04_fifo_engine_id, + .id_engine = nv04_fifo_id_engine, .pause = nv04_fifo_pause, .start = nv04_fifo_start, .chan = { @@ -52,8 +54,8 @@ nv10_fifo = { }; int -nv10_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +nv10_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return nv04_fifo_new_(&nv10_fifo, device, index, 32, - nv10_fifo_ramfc, pfifo); + return nv04_fifo_new_(&nv10_fifo, device, type, inst, 32, nv10_fifo_ramfc, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c index f6d383a21222..3f94c7b5b054 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c @@ -81,6 +81,8 @@ static const struct nvkm_fifo_func nv17_fifo = { .init = nv17_fifo_init, .intr = nv04_fifo_intr, + .engine_id = nv04_fifo_engine_id, + .id_engine = nv04_fifo_id_engine, .pause = nv04_fifo_pause, .start = nv04_fifo_start, .chan = { @@ -90,8 +92,8 @@ nv17_fifo = { }; int -nv17_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +nv17_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return nv04_fifo_new_(&nv17_fifo, device, index, 32, - nv17_fifo_ramfc, pfifo); + return nv04_fifo_new_(&nv17_fifo, device, type, inst, 32, nv17_fifo_ramfc, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c index 2d61fd832ddb..f9ea46809bc0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c @@ -112,6 +112,8 @@ static const struct nvkm_fifo_func nv40_fifo = { .init = nv40_fifo_init, .intr = nv04_fifo_intr, + .engine_id = nv04_fifo_engine_id, + .id_engine = nv04_fifo_id_engine, .pause = nv04_fifo_pause, .start = nv04_fifo_start, .chan = { @@ -121,8 +123,8 @@ nv40_fifo = { }; int -nv40_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +nv40_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return nv04_fifo_new_(&nv40_fifo, device, index, 32, - nv40_fifo_ramfc, pfifo); + return nv04_fifo_new_(&nv40_fifo, device, type, inst, 32, nv40_fifo_ramfc, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c index fa6e094d8068..be94156ea248 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c @@ -51,9 +51,9 @@ nv50_fifo_runlist_update_locked(struct nv50_fifo *fifo) void nv50_fifo_runlist_update(struct nv50_fifo *fifo) { - mutex_lock(&fifo->base.engine.subdev.mutex); + mutex_lock(&fifo->base.mutex); nv50_fifo_runlist_update_locked(fifo); - mutex_unlock(&fifo->base.engine.subdev.mutex); + mutex_unlock(&fifo->base.mutex); } int @@ -107,7 +107,7 @@ nv50_fifo_dtor(struct nvkm_fifo *base) int nv50_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device, - int index, struct nvkm_fifo **pfifo) + enum nvkm_subdev_type type, int inst, struct nvkm_fifo **pfifo) { struct nv50_fifo *fifo; int ret; @@ -116,7 +116,7 @@ nv50_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device, return -ENOMEM; *pfifo = &fifo->base; - ret = nvkm_fifo_ctor(func, device, index, 128, &fifo->base); + ret = nvkm_fifo_ctor(func, device, type, inst, 128, &fifo->base); if (ret) return ret; @@ -131,6 +131,8 @@ nv50_fifo = { .oneinit = nv50_fifo_oneinit, .init = nv50_fifo_init, .intr = nv04_fifo_intr, + .engine_id = nv04_fifo_engine_id, + .id_engine = nv04_fifo_id_engine, .pause = nv04_fifo_pause, .start = nv04_fifo_start, .chan = { @@ -141,7 +143,8 @@ nv50_fifo = { }; int -nv50_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +nv50_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { - return nv50_fifo_new_(&nv50_fifo, device, index, pfifo); + return nv50_fifo_new_(&nv50_fifo, device, type, inst, pfifo); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h index 87d30b6bd2ea..0111e7e5a4e3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h @@ -10,8 +10,8 @@ struct nv50_fifo { int cur_runlist; }; -int nv50_fifo_new_(const struct nvkm_fifo_func *, struct nvkm_device *, - int index, struct nvkm_fifo **); +int nv50_fifo_new_(const struct nvkm_fifo_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_fifo **); void *nv50_fifo_dtor(struct nvkm_fifo *); int nv50_fifo_oneinit(struct nvkm_fifo *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h index 0ef8baab513e..899272801a8b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h @@ -4,8 +4,8 @@ #define nvkm_fifo(p) container_of((p), struct nvkm_fifo, engine) #include <engine/fifo.h> -int nvkm_fifo_ctor(const struct nvkm_fifo_func *, struct nvkm_device *, - int index, int nr, struct nvkm_fifo *); +int nvkm_fifo_ctor(const struct nvkm_fifo_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + int nr, struct nvkm_fifo *); void nvkm_fifo_uevent(struct nvkm_fifo *); void nvkm_fifo_cevent(struct nvkm_fifo *); void nvkm_fifo_kevent(struct nvkm_fifo *, int chid); @@ -23,6 +23,8 @@ struct nvkm_fifo_func { void (*fini)(struct nvkm_fifo *); void (*intr)(struct nvkm_fifo *); void (*fault)(struct nvkm_fifo *, struct nvkm_fault_data *); + int (*engine_id)(struct nvkm_fifo *, struct nvkm_engine *); + struct nvkm_engine *(*id_engine)(struct nvkm_fifo *, int engi); void (*pause)(struct nvkm_fifo *, unsigned long *); void (*start)(struct nvkm_fifo *, unsigned long *); void (*uevent_init)(struct nvkm_fifo *); @@ -35,8 +37,13 @@ struct nvkm_fifo_func { }; void nv04_fifo_intr(struct nvkm_fifo *); +int nv04_fifo_engine_id(struct nvkm_fifo *, struct nvkm_engine *); +struct nvkm_engine *nv04_fifo_id_engine(struct nvkm_fifo *, int); void nv04_fifo_pause(struct nvkm_fifo *, unsigned long *); void nv04_fifo_start(struct nvkm_fifo *, unsigned long *); void gf100_fifo_intr_fault(struct nvkm_fifo *, int); + +int gk104_fifo_engine_id(struct nvkm_fifo *, struct nvkm_engine *); +struct nvkm_engine *gk104_fifo_id_engine(struct nvkm_fifo *, int); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c index 14e5b70e0255..e417044cc347 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c @@ -278,7 +278,8 @@ tu102_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info) struct nvkm_engine *engine = NULL; struct nvkm_fifo_chan *chan; unsigned long flags; - char ct[8] = "HUB/", en[16] = ""; + const char *en = ""; + char ct[8] = "HUB/"; int engn; er = nvkm_enum_find(fifo->func->fault.reason, info->reason); @@ -303,25 +304,20 @@ tu102_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info) nvkm_mask(device, 0x001718, 0x00000000, 0x00000000); break; default: - engine = nvkm_device_engine(device, ee->data2); + engine = nvkm_device_engine(device, ee->data2, 0); break; } } if (ee == NULL) { - enum nvkm_devidx engidx = nvkm_top_fault(device, info->engine); - - if (engidx < NVKM_SUBDEV_NR) { - const char *src = nvkm_subdev_name[engidx]; - char *dst = en; - - do { - *dst++ = toupper(*src++); - } while (*src); - engine = nvkm_device_engine(device, engidx); + struct nvkm_subdev *subdev = nvkm_top_fault(device, info->engine); + if (subdev) { + if (subdev->func == &nvkm_engine) + engine = container_of(subdev, typeof(*engine), subdev); + en = engine->subdev.name; } } else { - snprintf(en, sizeof(en), "%s", ee->name); + en = ee->name; } spin_lock_irqsave(&fifo->base.lock, flags); @@ -456,6 +452,8 @@ tu102_fifo_ = { .fini = gk104_fifo_fini, .intr = tu102_fifo_intr, .fault = tu102_fifo_fault, + .engine_id = gk104_fifo_engine_id, + .id_engine = gk104_fifo_id_engine, .uevent_init = gk104_fifo_uevent_init, .uevent_fini = gk104_fifo_uevent_fini, .recover_chan = tu102_fifo_recover_chan, @@ -464,7 +462,8 @@ tu102_fifo_ = { }; int -tu102_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +tu102_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fifo **pfifo) { struct gk104_fifo *fifo; @@ -474,5 +473,5 @@ tu102_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) INIT_WORK(&fifo->recover.work, tu102_fifo_recover_work); *pfifo = &fifo->base; - return nvkm_fifo_ctor(&tu102_fifo_, device, index, 4096, &fifo->base); + return nvkm_fifo_ctor(&tu102_fifo_, device, type, inst, 4096, &fifo->base); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c index d41fb94524e9..61759f54406e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c @@ -175,8 +175,8 @@ nvkm_gr = { int nvkm_gr_ctor(const struct nvkm_gr_func *func, struct nvkm_device *device, - int index, bool enable, struct nvkm_gr *gr) + enum nvkm_subdev_type type, int inst, bool enable, struct nvkm_gr *gr) { gr->func = func; - return nvkm_engine_ctor(&nvkm_gr, device, index, enable, &gr->engine); + return nvkm_engine_ctor(&nvkm_gr, device, type, inst, enable, &gr->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c index da1ba74682b4..65c332118fd6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c @@ -192,7 +192,7 @@ g84_gr = { }; int -g84_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +g84_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv50_gr_new_(&g84_gr, device, index, pgr); + return nv50_gr_new_(&g84_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index 749f73fc45a8..397ff4fe9df8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -2087,8 +2087,8 @@ gf100_gr_flcn = { }; int -gf100_gr_new_(const struct gf100_gr_fwif *fwif, - struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gf100_gr_new_(const struct gf100_gr_fwif *fwif, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { struct gf100_gr *gr; int ret; @@ -2097,7 +2097,7 @@ gf100_gr_new_(const struct gf100_gr_fwif *fwif, return -ENOMEM; *pgr = &gr->base; - ret = nvkm_gr_ctor(&gf100_gr_, device, index, true, &gr->base); + ret = nvkm_gr_ctor(&gf100_gr_, device, type, inst, true, &gr->base); if (ret) return ret; @@ -2483,7 +2483,7 @@ gf100_gr_fwif[] = { }; int -gf100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gf100_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(gf100_gr_fwif, device, index, pgr); + return gf100_gr_new_(gf100_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h index dfd5dd74f0d5..c0038f906135 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h @@ -416,6 +416,6 @@ void gm20b_gr_acr_bld_patch(struct nvkm_acr *, u32, s64); extern const struct nvkm_acr_lsf_func gp108_gr_gpccs_acr; extern const struct nvkm_acr_lsf_func gp108_gr_fecs_acr; -int gf100_gr_new_(const struct gf100_gr_fwif *, struct nvkm_device *, int, +int gf100_gr_new_(const struct gf100_gr_fwif *, struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gr **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c index 0536fe8b2b92..3acd99c306f2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c @@ -152,7 +152,7 @@ gf104_gr_fwif[] = { }; int -gf104_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gf104_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(gf104_gr_fwif, device, index, pgr); + return gf100_gr_new_(gf104_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c index 14284b06112f..030640bb3dca 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c @@ -151,7 +151,7 @@ gf108_gr_fwif[] = { }; int -gf108_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gf108_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(gf108_gr_fwif, device, index, pgr); + return gf100_gr_new_(gf108_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c index 280752551a3a..616e2def1865 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c @@ -127,7 +127,7 @@ gf110_gr_fwif[] = { }; int -gf110_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gf110_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(gf110_gr_fwif, device, index, pgr); + return gf100_gr_new_(gf110_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c index 235c3fbe4b95..669e7536970e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c @@ -192,7 +192,7 @@ gf117_gr_fwif[] = { }; int -gf117_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gf117_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(gf117_gr_fwif, device, index, pgr); + return gf100_gr_new_(gf117_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c index 7eac385ece97..5b09bda8110c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c @@ -218,7 +218,7 @@ gf119_gr_fwif[] = { }; int -gf119_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gf119_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(gf119_gr_fwif, device, index, pgr); + return gf100_gr_new_(gf119_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c index 89f51d76082b..b680eaa0f350 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c @@ -497,7 +497,7 @@ gk104_gr_fwif[] = { }; int -gk104_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gk104_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(gk104_gr_fwif, device, index, pgr); + return gf100_gr_new_(gk104_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c index 735f05e54d62..103e06a77e65 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c @@ -393,7 +393,7 @@ gk110_gr_fwif[] = { }; int -gk110_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gk110_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(gk110_gr_fwif, device, index, pgr); + return gf100_gr_new_(gk110_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c index adc971be8f3b..034d0b11a17d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c @@ -144,7 +144,8 @@ gk110b_gr_fwif[] = { }; int -gk110b_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gk110b_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_gr **pgr) { - return gf100_gr_new_(gk110b_gr_fwif, device, index, pgr); + return gf100_gr_new_(gk110b_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c index aa0eff6795ac..116d682f9f96 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c @@ -202,7 +202,7 @@ gk208_gr_fwif[] = { }; int -gk208_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gk208_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(gk208_gr_fwif, device, index, pgr); + return gf100_gr_new_(gk208_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c index 6d4d72851610..be0b2cefd8e8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c @@ -357,7 +357,7 @@ gk20a_gr_fwif[] = { }; int -gk20a_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gk20a_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(gk20a_gr_fwif, device, index, pgr); + return gf100_gr_new_(gk20a_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c index 09bb78ba9d00..310987174cb5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c @@ -437,7 +437,7 @@ gm107_gr_fwif[] = { }; int -gm107_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gm107_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(gm107_gr_fwif, device, index, pgr); + return gf100_gr_new_(gm107_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c index 815137047518..5c38ff0fe7f9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c @@ -288,7 +288,7 @@ gm200_gr_fwif[] = { }; int -gm200_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gm200_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(gm200_gr_fwif, device, index, pgr); + return gf100_gr_new_(gm200_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c index 1aab691fa71c..ec1c46e47e00 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c @@ -181,7 +181,7 @@ gm20b_gr_fwif[] = { }; int -gm20b_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gm20b_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(gm20b_gr_fwif, device, index, pgr); + return gf100_gr_new_(gm20b_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c index ddba7ce937c7..0550dd6f46f1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c @@ -156,7 +156,7 @@ gp100_gr_fwif[] = { }; int -gp100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gp100_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(gp100_gr_fwif, device, index, pgr); + return gf100_gr_new_(gp100_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c index c083f3757ff7..5b001f374be0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c @@ -152,7 +152,7 @@ gp102_gr_fwif[] = { }; int -gp102_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gp102_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(gp102_gr_fwif, device, index, pgr); + return gf100_gr_new_(gp102_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp104.c index f6a31e9a8cc8..2655574ec63b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp104.c @@ -93,7 +93,7 @@ gp104_gr_fwif[] = { }; int -gp104_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gp104_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(gp104_gr_fwif, device, index, pgr); + return gf100_gr_new_(gp104_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c index 2c80c6a75b56..adabc04d4f3a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c @@ -82,7 +82,7 @@ gp107_gr_fwif[] = { }; int -gp107_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gp107_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(gp107_gr_fwif, device, index, pgr); + return gf100_gr_new_(gp107_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp108.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp108.c index 2be8f416dd6f..7310f0466bb7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp108.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp108.c @@ -92,7 +92,7 @@ gp108_gr_fwif[] = { }; int -gp108_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gp108_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(gp108_gr_fwif, device, index, pgr); + return gf100_gr_new_(gp108_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c index 6edc4bc7ed44..e13683b6e7b1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c @@ -94,7 +94,7 @@ gp10b_gr_fwif[] = { }; int -gp10b_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gp10b_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(gp10b_gr_fwif, device, index, pgr); + return gf100_gr_new_(gp10b_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.c index c711a55ce392..1dfc65d45b52 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.c @@ -43,7 +43,7 @@ gt200_gr = { }; int -gt200_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gt200_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv50_gr_new_(>200_gr, device, index, pgr); + return nv50_gr_new_(>200_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.c index fa103df32ec7..fcb5ead345a3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.c @@ -44,7 +44,7 @@ gt215_gr = { }; int -gt215_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gt215_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv50_gr_new_(>215_gr, device, index, pgr); + return nv50_gr_new_(>215_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c index 2189a8f4e644..4d043c1173ea 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c @@ -141,7 +141,7 @@ gv100_gr_fwif[] = { }; int -gv100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +gv100_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(gv100_gr_fwif, device, index, pgr); + return gf100_gr_new_(gv100_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.c index eb1a90644752..cf782b64f62e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.c @@ -42,7 +42,7 @@ mcp79_gr = { }; int -mcp79_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +mcp79_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv50_gr_new_(&mcp79_gr, device, index, pgr); + return nv50_gr_new_(&mcp79_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.c index c91eb56e9327..6f90a6395453 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.c @@ -44,7 +44,7 @@ mcp89_gr = { }; int -mcp89_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +mcp89_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv50_gr_new_(&mcp89_gr, device, index, pgr); + return nv50_gr_new_(&mcp89_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c index 9c2e985dc079..0bc1a238de43 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c @@ -1413,7 +1413,7 @@ nv04_gr = { }; int -nv04_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv04_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { struct nv04_gr *gr; @@ -1422,5 +1422,5 @@ nv04_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) spin_lock_init(&gr->lock); *pgr = &gr->base; - return nvkm_gr_ctor(&nv04_gr, device, index, true, &gr->base); + return nvkm_gr_ctor(&nv04_gr, device, type, inst, true, &gr->base); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c index 4ebbfbdd8240..942450b33bc6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c @@ -1173,7 +1173,7 @@ nv10_gr_init(struct nvkm_gr *base) int nv10_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, - int index, struct nvkm_gr **pgr) + enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { struct nv10_gr *gr; @@ -1182,7 +1182,7 @@ nv10_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, spin_lock_init(&gr->lock); *pgr = &gr->base; - return nvkm_gr_ctor(func, device, index, true, &gr->base); + return nvkm_gr_ctor(func, device, type, inst, true, &gr->base); } static const struct nvkm_gr_func @@ -1215,7 +1215,7 @@ nv10_gr = { }; int -nv10_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv10_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv10_gr_new_(&nv10_gr, device, index, pgr); + return nv10_gr_new_(&nv10_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.h index 4327baea02af..5cfe927c9123 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.h @@ -3,7 +3,7 @@ #define __NV10_GR_H__ #include "priv.h" -int nv10_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, int index, +int nv10_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gr **); int nv10_gr_init(struct nvkm_gr *); void nv10_gr_intr(struct nvkm_gr *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.c index 3e2c6856b4c4..69ece259df86 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.c @@ -53,7 +53,7 @@ nv15_gr = { }; int -nv15_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv15_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv10_gr_new_(&nv15_gr, device, index, pgr); + return nv10_gr_new_(&nv15_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.c index 12437d085a73..e39dfc7d4077 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.c @@ -53,7 +53,7 @@ nv17_gr = { }; int -nv17_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv17_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv10_gr_new_(&nv17_gr, device, index, pgr); + return nv10_gr_new_(&nv17_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c index d837630a3625..6bff10cee71b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c @@ -330,7 +330,7 @@ nv20_gr_dtor(struct nvkm_gr *base) int nv20_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, - int index, struct nvkm_gr **pgr) + enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { struct nv20_gr *gr; @@ -338,7 +338,7 @@ nv20_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, return -ENOMEM; *pgr = &gr->base; - return nvkm_gr_ctor(func, device, index, true, &gr->base); + return nvkm_gr_ctor(func, device, type, inst, true, &gr->base); } static const struct nvkm_gr_func @@ -370,7 +370,7 @@ nv20_gr = { }; int -nv20_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv20_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv20_gr_new_(&nv20_gr, device, index, pgr); + return nv20_gr_new_(&nv20_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h index e57407a8a7c3..c0d2be53413e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h @@ -9,8 +9,8 @@ struct nv20_gr { struct nvkm_memory *ctxtab; }; -int nv20_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, - int, struct nvkm_gr **); +int nv20_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_gr **); void *nv20_gr_dtor(struct nvkm_gr *); int nv20_gr_oneinit(struct nvkm_gr *); int nv20_gr_init(struct nvkm_gr *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c index 32d29d3faee0..f3a56f17d94a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c @@ -129,7 +129,7 @@ nv25_gr = { }; int -nv25_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv25_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv20_gr_new_(&nv25_gr, device, index, pgr); + return nv20_gr_new_(&nv25_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c index f941062c66f0..f268d2642d29 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c @@ -120,7 +120,7 @@ nv2a_gr = { }; int -nv2a_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv2a_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv20_gr_new_(&nv2a_gr, device, index, pgr); + return nv20_gr_new_(&nv2a_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c index 785ec956df0f..e5737cdf2fa1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c @@ -194,7 +194,7 @@ nv30_gr = { }; int -nv30_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv30_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv20_gr_new_(&nv30_gr, device, index, pgr); + return nv20_gr_new_(&nv30_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c index bd610d75c677..1ab2da8ebf4e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c @@ -131,7 +131,7 @@ nv34_gr = { }; int -nv34_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv34_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv20_gr_new_(&nv34_gr, device, index, pgr); + return nv20_gr_new_(&nv34_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c index 89db7f523037..591260f5676b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c @@ -131,7 +131,7 @@ nv35_gr = { }; int -nv35_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv35_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv20_gr_new_(&nv35_gr, device, index, pgr); + return nv20_gr_new_(&nv35_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c index 5f1ad8344ea9..67f3535ff97e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c @@ -429,7 +429,7 @@ nv40_gr_init(struct nvkm_gr *base) int nv40_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, - int index, struct nvkm_gr **pgr) + enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { struct nv40_gr *gr; @@ -438,7 +438,7 @@ nv40_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, *pgr = &gr->base; INIT_LIST_HEAD(&gr->chan); - return nvkm_gr_ctor(func, device, index, true, &gr->base); + return nvkm_gr_ctor(func, device, type, inst, true, &gr->base); } static const struct nvkm_gr_func @@ -470,7 +470,7 @@ nv40_gr = { }; int -nv40_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv40_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv40_gr_new_(&nv40_gr, device, index, pgr); + return nv40_gr_new_(&nv40_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h index e6128791b2d2..f3d3d3a5ae5b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h @@ -10,7 +10,7 @@ struct nv40_gr { struct list_head chan; }; -int nv40_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, int index, +int nv40_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gr **); int nv40_gr_init(struct nvkm_gr *); void nv40_gr_intr(struct nvkm_gr *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c index 45ff80254eb4..22b6a38a7031 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c @@ -102,7 +102,7 @@ nv44_gr = { }; int -nv44_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv44_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv40_gr_new_(&nv44_gr, device, index, pgr); + return nv40_gr_new_(&nv44_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c index df16ffda1749..563a10097e95 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c @@ -761,7 +761,7 @@ nv50_gr_init(struct nvkm_gr *base) int nv50_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, - int index, struct nvkm_gr **pgr) + enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { struct nv50_gr *gr; @@ -770,7 +770,7 @@ nv50_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, spin_lock_init(&gr->lock); *pgr = &gr->base; - return nvkm_gr_ctor(func, device, index, true, &gr->base); + return nvkm_gr_ctor(func, device, type, inst, true, &gr->base); } static const struct nvkm_gr_func @@ -790,7 +790,7 @@ nv50_gr = { }; int -nv50_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +nv50_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return nv50_gr_new_(&nv50_gr, device, index, pgr); + return nv50_gr_new_(&nv50_gr, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h index 465f4da0ddfc..84388c42e5c6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h @@ -11,7 +11,7 @@ struct nv50_gr { u32 size; }; -int nv50_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, int index, +int nv50_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gr **); int nv50_gr_init(struct nvkm_gr *); void nv50_gr_intr(struct nvkm_gr *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h index 3b30f24032cc..9b2c66e8be90 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h @@ -7,8 +7,8 @@ struct nvkm_fb_tile; struct nvkm_fifo_chan; -int nvkm_gr_ctor(const struct nvkm_gr_func *, struct nvkm_device *, - int index, bool enable, struct nvkm_gr *); +int nvkm_gr_ctor(const struct nvkm_gr_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + bool enable, struct nvkm_gr *); bool nv04_gr_idle(struct nvkm_gr *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c index 6039f9948aa2..1a8a21844e12 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c @@ -198,7 +198,7 @@ tu102_gr_fwif[] = { }; int -tu102_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +tu102_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { - return gf100_gr_new_(tu102_gr_fwif, device, index, pgr); + return gf100_gr_new_(tu102_gr_fwif, device, type, inst, pgr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c index c0e11a071843..0fcc0ffa1e40 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c @@ -37,7 +37,8 @@ g84_mpeg = { }; int -g84_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg) +g84_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pmpeg) { - return nvkm_engine_new_(&g84_mpeg, device, index, true, pmpeg); + return nvkm_engine_new_(&g84_mpeg, device, type, inst, true, pmpeg); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c index 7fea7d45202f..b1054db4c1b8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c @@ -274,7 +274,7 @@ nv31_mpeg_ = { int nv31_mpeg_new_(const struct nv31_mpeg_func *func, struct nvkm_device *device, - int index, struct nvkm_engine **pmpeg) + enum nvkm_subdev_type type, int inst, struct nvkm_engine **pmpeg) { struct nv31_mpeg *mpeg; @@ -283,8 +283,7 @@ nv31_mpeg_new_(const struct nv31_mpeg_func *func, struct nvkm_device *device, mpeg->func = func; *pmpeg = &mpeg->engine; - return nvkm_engine_ctor(&nv31_mpeg_, device, index, - true, &mpeg->engine); + return nvkm_engine_ctor(&nv31_mpeg_, device, type, inst, true, &mpeg->engine); } static const struct nv31_mpeg_func @@ -293,7 +292,8 @@ nv31_mpeg = { }; int -nv31_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg) +nv31_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pmpeg) { - return nv31_mpeg_new_(&nv31_mpeg, device, index, pmpeg); + return nv31_mpeg_new_(&nv31_mpeg, device, type, inst, pmpeg); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h index b3e131538858..9f30aaaf809e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h @@ -11,8 +11,8 @@ struct nv31_mpeg { struct nv31_mpeg_chan *chan; }; -int nv31_mpeg_new_(const struct nv31_mpeg_func *, struct nvkm_device *, - int index, struct nvkm_engine **); +int nv31_mpeg_new_(const struct nv31_mpeg_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_engine **); struct nv31_mpeg_func { bool (*mthd_dma)(struct nvkm_device *, u32 mthd, u32 data); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c index b5ec7c504dc6..179167484ef1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c @@ -76,7 +76,8 @@ nv40_mpeg = { }; int -nv40_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg) +nv40_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pmpeg) { - return nv31_mpeg_new_(&nv40_mpeg, device, index, pmpeg); + return nv31_mpeg_new_(&nv40_mpeg, device, type, inst, pmpeg); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c index c3cf02ed468e..521ce43a2871 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c @@ -203,7 +203,8 @@ nv44_mpeg = { }; int -nv44_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg) +nv44_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pmpeg) { struct nv44_mpeg *mpeg; @@ -212,5 +213,5 @@ nv44_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg) INIT_LIST_HEAD(&mpeg->chan); *pmpeg = &mpeg->engine; - return nvkm_engine_ctor(&nv44_mpeg, device, index, true, &mpeg->engine); + return nvkm_engine_ctor(&nv44_mpeg, device, type, inst, true, &mpeg->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c index 6df880a39019..e6374f36961c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c @@ -129,7 +129,8 @@ nv50_mpeg = { }; int -nv50_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg) +nv50_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pmpeg) { - return nvkm_engine_new_(&nv50_mpeg, device, index, true, pmpeg); + return nvkm_engine_new_(&nv50_mpeg, device, type, inst, true, pmpeg); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/base.c index 80211f76093b..842fcfbd28b8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/base.c @@ -24,9 +24,8 @@ #include "priv.h" int -nvkm_mspdec_new_(const struct nvkm_falcon_func *func, - struct nvkm_device *device, int index, - struct nvkm_engine **pengine) +nvkm_mspdec_new_(const struct nvkm_falcon_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_falcon_new_(func, device, index, true, 0x085000, pengine); + return nvkm_falcon_new_(func, device, type, inst, true, 0x085000, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c index f30cf1dcfb30..ecb06d68f544 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c @@ -43,8 +43,8 @@ g98_mspdec = { }; int -g98_mspdec_new(struct nvkm_device *device, int index, - struct nvkm_engine **pengine) +g98_mspdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pengine) { - return nvkm_mspdec_new_(&g98_mspdec, device, index, pengine); + return nvkm_mspdec_new_(&g98_mspdec, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c index cfe1aa81bd14..0a69bd767d69 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c @@ -43,8 +43,8 @@ gf100_mspdec = { }; int -gf100_mspdec_new(struct nvkm_device *device, int index, +gf100_mspdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_mspdec_new_(&gf100_mspdec, device, index, pengine); + return nvkm_mspdec_new_(&gf100_mspdec, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c index 24272b4927bc..a08991dca428 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c @@ -35,8 +35,8 @@ gk104_mspdec = { }; int -gk104_mspdec_new(struct nvkm_device *device, int index, +gk104_mspdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_mspdec_new_(&gk104_mspdec, device, index, pengine); + return nvkm_mspdec_new_(&gk104_mspdec, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c index cf6e59ad6ee2..791fb03a32ad 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c @@ -35,8 +35,8 @@ gt215_mspdec = { }; int -gt215_mspdec_new(struct nvkm_device *device, int index, - struct nvkm_engine **pengine) +gt215_mspdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pengine) { - return nvkm_mspdec_new_(>215_mspdec, device, index, pengine); + return nvkm_mspdec_new_(>215_mspdec, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/priv.h index 86445a2600d0..2bc5537d40a3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/priv.h @@ -3,8 +3,8 @@ #define __NVKM_MSPDEC_PRIV_H__ #include <engine/mspdec.h> -int nvkm_mspdec_new_(const struct nvkm_falcon_func *, struct nvkm_device *, - int index, struct nvkm_engine **); +int nvkm_mspdec_new_(const struct nvkm_falcon_func *, struct nvkm_device *, enum nvkm_subdev_type, + int, struct nvkm_engine **); void g98_mspdec_init(struct nvkm_falcon *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/base.c index bfae5e60e925..45a9411ab2e2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/base.c @@ -25,7 +25,7 @@ int nvkm_msppp_new_(const struct nvkm_falcon_func *func, struct nvkm_device *device, - int index, struct nvkm_engine **pengine) + enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_falcon_new_(func, device, index, true, 0x086000, pengine); + return nvkm_falcon_new_(func, device, type, inst, true, 0x086000, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c index c45dbf79d1f9..160120b9bd64 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c @@ -43,8 +43,8 @@ g98_msppp = { }; int -g98_msppp_new(struct nvkm_device *device, int index, +g98_msppp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_msppp_new_(&g98_msppp, device, index, pengine); + return nvkm_msppp_new_(&g98_msppp, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c index 803c62ab516e..debed9ae8731 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c @@ -43,8 +43,8 @@ gf100_msppp = { }; int -gf100_msppp_new(struct nvkm_device *device, int index, +gf100_msppp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_msppp_new_(&gf100_msppp, device, index, pengine); + return nvkm_msppp_new_(&gf100_msppp, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c index 49cbf72cee4b..a2fd736fef94 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c @@ -35,8 +35,8 @@ gt215_msppp = { }; int -gt215_msppp_new(struct nvkm_device *device, int index, - struct nvkm_engine **pengine) +gt215_msppp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pengine) { - return nvkm_msppp_new_(>215_msppp, device, index, pengine); + return nvkm_msppp_new_(>215_msppp, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/priv.h index f20b10915db2..582ab8ce1425 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/priv.h @@ -3,8 +3,8 @@ #define __NVKM_MSPPP_PRIV_H__ #include <engine/msppp.h> -int nvkm_msppp_new_(const struct nvkm_falcon_func *, struct nvkm_device *, - int index, struct nvkm_engine **); +int nvkm_msppp_new_(const struct nvkm_falcon_func *, struct nvkm_device *, enum nvkm_subdev_type, + int, struct nvkm_engine **); void g98_msppp_init(struct nvkm_falcon *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/base.c index 745bbb653dc0..7be42b980e57 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/base.c @@ -25,7 +25,7 @@ int nvkm_msvld_new_(const struct nvkm_falcon_func *func, struct nvkm_device *device, - int index, struct nvkm_engine **pengine) + enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_falcon_new_(func, device, index, true, 0x084000, pengine); + return nvkm_falcon_new_(func, device, type, inst, true, 0x084000, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c index 4a2a9f0494af..cfa2065319a6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c @@ -43,8 +43,8 @@ g98_msvld = { }; int -g98_msvld_new(struct nvkm_device *device, int index, +g98_msvld_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_msvld_new_(&g98_msvld, device, index, pengine); + return nvkm_msvld_new_(&g98_msvld, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c index 1695e532c081..8d58ad8e04d3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c @@ -43,8 +43,8 @@ gf100_msvld = { }; int -gf100_msvld_new(struct nvkm_device *device, int index, +gf100_msvld_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_msvld_new_(&gf100_msvld, device, index, pengine); + return nvkm_msvld_new_(&gf100_msvld, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c index b640cd63ebe8..b28be28046f1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c @@ -35,8 +35,8 @@ gk104_msvld = { }; int -gk104_msvld_new(struct nvkm_device *device, int index, +gk104_msvld_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_msvld_new_(&gk104_msvld, device, index, pengine); + return nvkm_msvld_new_(&gk104_msvld, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.c index 201e8ef3519e..d7489f972c99 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.c @@ -35,8 +35,8 @@ gt215_msvld = { }; int -gt215_msvld_new(struct nvkm_device *device, int index, - struct nvkm_engine **pengine) +gt215_msvld_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pengine) { - return nvkm_msvld_new_(>215_msvld, device, index, pengine); + return nvkm_msvld_new_(>215_msvld, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.c index a0f540ef257b..16c30b62ab09 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.c @@ -35,8 +35,8 @@ mcp89_msvld = { }; int -mcp89_msvld_new(struct nvkm_device *device, int index, - struct nvkm_engine **pengine) +mcp89_msvld_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pengine) { - return nvkm_msvld_new_(&mcp89_msvld, device, index, pengine); + return nvkm_msvld_new_(&mcp89_msvld, device, type, inst, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/priv.h index 5cd1e83badbb..f729d919b054 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/priv.h @@ -3,8 +3,8 @@ #define __NVKM_MSVLD_PRIV_H__ #include <engine/msvld.h> -int nvkm_msvld_new_(const struct nvkm_falcon_func *, struct nvkm_device *, - int index, struct nvkm_engine **); +int nvkm_msvld_new_(const struct nvkm_falcon_func *, struct nvkm_device *, enum nvkm_subdev_type, + int, struct nvkm_engine **); void g98_msvld_init(struct nvkm_falcon *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c index 9b23c1b70ebf..b0181cc5953b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c @@ -37,7 +37,7 @@ nvkm_nvdec = { int nvkm_nvdec_new_(const struct nvkm_nvdec_fwif *fwif, struct nvkm_device *device, - int index, struct nvkm_nvdec **pnvdec) + enum nvkm_subdev_type type, int inst, struct nvkm_nvdec **pnvdec) { struct nvkm_nvdec *nvdec; int ret; @@ -45,7 +45,7 @@ nvkm_nvdec_new_(const struct nvkm_nvdec_fwif *fwif, struct nvkm_device *device, if (!(nvdec = *pnvdec = kzalloc(sizeof(*nvdec), GFP_KERNEL))) return -ENOMEM; - ret = nvkm_engine_ctor(&nvkm_nvdec, device, index, true, + ret = nvkm_engine_ctor(&nvkm_nvdec, device, type, inst, true, &nvdec->engine); if (ret) return ret; @@ -57,5 +57,5 @@ nvkm_nvdec_new_(const struct nvkm_nvdec_fwif *fwif, struct nvkm_device *device, nvdec->func = fwif->func; return nvkm_falcon_ctor(nvdec->func->flcn, &nvdec->engine.subdev, - nvkm_subdev_name[index], 0, &nvdec->falcon); + nvdec->engine.subdev.name, 0, &nvdec->falcon); }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/gm107.c index 0ab27ab4d8ee..8c44ce44a6d7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/gm107.c @@ -56,8 +56,8 @@ gm107_nvdec_fwif[] = { }; int -gm107_nvdec_new(struct nvkm_device *device, int index, +gm107_nvdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_nvdec **pnvdec) { - return nvkm_nvdec_new_(gm107_nvdec_fwif, device, index, pnvdec); + return nvkm_nvdec_new_(gm107_nvdec_fwif, device, type, inst, pnvdec); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/priv.h index e14da8b000d0..0920f6a887e2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/priv.h @@ -14,6 +14,6 @@ struct nvkm_nvdec_fwif { const struct nvkm_nvdec_func *func; }; -int nvkm_nvdec_new_(const struct nvkm_nvdec_fwif *fwif, - struct nvkm_device *, int, struct nvkm_nvdec **); +int nvkm_nvdec_new_(const struct nvkm_nvdec_fwif *fwif, struct nvkm_device *, + enum nvkm_subdev_type, int, struct nvkm_nvdec **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/base.c index 484100e15668..c39e797dc7c9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/base.c @@ -39,7 +39,7 @@ nvkm_nvenc = { int nvkm_nvenc_new_(const struct nvkm_nvenc_fwif *fwif, struct nvkm_device *device, - int index, struct nvkm_nvenc **pnvenc) + enum nvkm_subdev_type type, int inst, struct nvkm_nvenc **pnvenc) { struct nvkm_nvenc *nvenc; int ret; @@ -47,7 +47,7 @@ nvkm_nvenc_new_(const struct nvkm_nvenc_fwif *fwif, struct nvkm_device *device, if (!(nvenc = *pnvenc = kzalloc(sizeof(*nvenc), GFP_KERNEL))) return -ENOMEM; - ret = nvkm_engine_ctor(&nvkm_nvenc, device, index, true, + ret = nvkm_engine_ctor(&nvkm_nvenc, device, type, inst, true, &nvenc->engine); if (ret) return ret; @@ -59,5 +59,5 @@ nvkm_nvenc_new_(const struct nvkm_nvenc_fwif *fwif, struct nvkm_device *device, nvenc->func = fwif->func; return nvkm_falcon_ctor(nvenc->func->flcn, &nvenc->engine.subdev, - nvkm_subdev_name[index], 0, &nvenc->falcon); + nvenc->engine.subdev.name, 0, &nvenc->falcon); }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/gm107.c index d249c8ffb2d5..f44d41bf2034 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/gm107.c @@ -56,8 +56,8 @@ gm107_nvenc_fwif[] = { }; int -gm107_nvenc_new(struct nvkm_device *device, int index, +gm107_nvenc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_nvenc **pnvenc) { - return nvkm_nvenc_new_(gm107_nvenc_fwif, device, index, pnvenc); + return nvkm_nvenc_new_(gm107_nvenc_fwif, device, type, inst, pnvenc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/priv.h index 100fa5ebbeef..4130a2bfbb4f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/priv.h @@ -14,6 +14,6 @@ struct nvkm_nvenc_fwif { const struct nvkm_nvenc_func *func; }; -int nvkm_nvenc_new_(const struct nvkm_nvenc_fwif *, struct nvkm_device *, +int nvkm_nvenc_new_(const struct nvkm_nvenc_fwif *, struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_nvenc **pnvenc); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c index b2785bee418e..8fe0444f761e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c @@ -628,10 +628,10 @@ nvkm_perfmon_dtor(struct nvkm_object *object) { struct nvkm_perfmon *perfmon = nvkm_perfmon(object); struct nvkm_pm *pm = perfmon->pm; - mutex_lock(&pm->engine.subdev.mutex); - if (pm->perfmon == &perfmon->object) - pm->perfmon = NULL; - mutex_unlock(&pm->engine.subdev.mutex); + spin_lock(&pm->client.lock); + if (pm->client.object == &perfmon->object) + pm->client.object = NULL; + spin_unlock(&pm->client.lock); return perfmon; } @@ -671,11 +671,11 @@ nvkm_pm_oclass_new(struct nvkm_device *device, const struct nvkm_oclass *oclass, if (ret) return ret; - mutex_lock(&pm->engine.subdev.mutex); - if (pm->perfmon == NULL) - pm->perfmon = *pobject; - ret = (pm->perfmon == *pobject) ? 0 : -EBUSY; - mutex_unlock(&pm->engine.subdev.mutex); + spin_lock(&pm->client.lock); + if (pm->client.object == NULL) + pm->client.object = *pobject; + ret = (pm->client.object == *pobject) ? 0 : -EBUSY; + spin_unlock(&pm->client.lock); return ret; } @@ -858,10 +858,11 @@ nvkm_pm = { int nvkm_pm_ctor(const struct nvkm_pm_func *func, struct nvkm_device *device, - int index, struct nvkm_pm *pm) + enum nvkm_subdev_type type, int inst, struct nvkm_pm *pm) { pm->func = func; INIT_LIST_HEAD(&pm->domains); INIT_LIST_HEAD(&pm->sources); - return nvkm_engine_ctor(&nvkm_pm, device, index, true, &pm->engine); + spin_lock_init(&pm->client.lock); + return nvkm_engine_ctor(&nvkm_pm, device, type, inst, true, &pm->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c index 6e441ddafd86..0086d00eb162 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c @@ -159,7 +159,7 @@ g84_pm[] = { }; int -g84_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm) +g84_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm) { - return nv40_pm_new_(g84_pm, device, index, ppm); + return nv40_pm_new_(g84_pm, device, type, inst, ppm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c index fe2532ee4145..8e02701def8e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c @@ -187,7 +187,7 @@ gf100_pm_ = { int gf100_pm_new_(const struct gf100_pm_func *func, struct nvkm_device *device, - int index, struct nvkm_pm **ppm) + enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm) { struct nvkm_pm *pm; u32 mask; @@ -196,7 +196,7 @@ gf100_pm_new_(const struct gf100_pm_func *func, struct nvkm_device *device, if (!(pm = *ppm = kzalloc(sizeof(*pm), GFP_KERNEL))) return -ENOMEM; - ret = nvkm_pm_ctor(&gf100_pm_, device, index, pm); + ret = nvkm_pm_ctor(&gf100_pm_, device, type, inst, pm); if (ret) return ret; @@ -237,7 +237,7 @@ gf100_pm = { }; int -gf100_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm) +gf100_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm) { - return gf100_pm_new_(&gf100_pm, device, index, ppm); + return gf100_pm_new_(&gf100_pm, device, type, inst, ppm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h index 461bb219b1c0..bc4b014c4e8e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h @@ -9,8 +9,8 @@ struct gf100_pm_func { const struct nvkm_specdom *doms_part; }; -int gf100_pm_new_(const struct gf100_pm_func *, struct nvkm_device *, - int index, struct nvkm_pm **); +int gf100_pm_new_(const struct gf100_pm_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_pm **); extern const struct nvkm_funcdom gf100_perfctr_func; extern const struct nvkm_specdom gf100_pm_gpc[]; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf108.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf108.c index 49b24c98a7f7..505565866b59 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf108.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf108.c @@ -60,7 +60,7 @@ gf108_pm = { }; int -gf108_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm) +gf108_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm) { - return gf100_pm_new_(&gf108_pm, device, index, ppm); + return gf100_pm_new_(&gf108_pm, device, type, inst, ppm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf117.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf117.c index 9170025fc988..c61e8c010bb3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf117.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf117.c @@ -74,7 +74,7 @@ gf117_pm = { }; int -gf117_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm) +gf117_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm) { - return gf100_pm_new_(&gf117_pm, device, index, ppm); + return gf100_pm_new_(&gf117_pm, device, type, inst, ppm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.c index 07f946d26ac6..75bf3df1cb18 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.c @@ -178,7 +178,7 @@ gk104_pm = { }; int -gk104_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm) +gk104_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm) { - return gf100_pm_new_(&gk104_pm, device, index, ppm); + return gf100_pm_new_(&gk104_pm, device, type, inst, ppm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.c index 5cf5dd536fd0..25874c541486 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.c @@ -151,7 +151,7 @@ gt200_pm[] = { }; int -gt200_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm) +gt200_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm) { - return nv40_pm_new_(gt200_pm, device, index, ppm); + return nv40_pm_new_(gt200_pm, device, type, inst, ppm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.c index c9227ad41b04..54c23e2b6645 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.c @@ -132,7 +132,7 @@ gt215_pm[] = { }; int -gt215_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm) +gt215_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm) { - return nv40_pm_new_(gt215_pm, device, index, ppm); + return nv40_pm_new_(gt215_pm, device, type, inst, ppm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c index 3fda594700e0..eba5b3b79340 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c @@ -80,7 +80,7 @@ nv40_pm_ = { int nv40_pm_new_(const struct nvkm_specdom *doms, struct nvkm_device *device, - int index, struct nvkm_pm **ppm) + enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm) { struct nv40_pm *pm; int ret; @@ -89,7 +89,7 @@ nv40_pm_new_(const struct nvkm_specdom *doms, struct nvkm_device *device, return -ENOMEM; *ppm = &pm->base; - ret = nvkm_pm_ctor(&nv40_pm_, device, index, &pm->base); + ret = nvkm_pm_ctor(&nv40_pm_, device, type, inst, &pm->base); if (ret) return ret; @@ -117,7 +117,7 @@ nv40_pm[] = { }; int -nv40_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm) +nv40_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm) { - return nv40_pm_new_(nv40_pm, device, index, ppm); + return nv40_pm_new_(nv40_pm, device, type, inst, ppm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h index 8ed19320fda1..afb79843723d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h @@ -9,7 +9,7 @@ struct nv40_pm { u32 sequence; }; -int nv40_pm_new_(const struct nvkm_specdom *, struct nvkm_device *, - int index, struct nvkm_pm **); +int nv40_pm_new_(const struct nvkm_specdom *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_pm **); extern const struct nvkm_funcdom nv40_perfctr_func; #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c index cc5a41d4c6f2..bbd3404901f9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c @@ -169,7 +169,7 @@ nv50_pm[] = { }; int -nv50_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm) +nv50_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm) { - return nv40_pm_new_(nv50_pm, device, index, ppm); + return nv40_pm_new_(nv50_pm, device, type, inst, ppm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h index cd6f8f79b235..6ae25d3e7f45 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h @@ -4,8 +4,8 @@ #define nvkm_pm(p) container_of((p), struct nvkm_pm, engine) #include <engine/pm.h> -int nvkm_pm_ctor(const struct nvkm_pm_func *, struct nvkm_device *, - int index, struct nvkm_pm *); +int nvkm_pm_ctor(const struct nvkm_pm_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_pm *); struct nvkm_pm_func { void (*fini)(struct nvkm_pm *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c index 6d2a7f0afbb5..1b87df03c823 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c @@ -74,9 +74,8 @@ g98_sec = { }; int -g98_sec_new(struct nvkm_device *device, int index, +g98_sec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine) { - return nvkm_falcon_new_(&g98_sec, device, index, - true, 0x087000, pengine); + return nvkm_falcon_new_(&g98_sec, device, type, inst, true, 0x087000, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c index 41318aa0d481..092c6d0b8e01 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c @@ -85,7 +85,7 @@ nvkm_sec2 = { int nvkm_sec2_new_(const struct nvkm_sec2_fwif *fwif, struct nvkm_device *device, - int index, u32 addr, struct nvkm_sec2 **psec2) + enum nvkm_subdev_type type, int inst, u32 addr, struct nvkm_sec2 **psec2) { struct nvkm_sec2 *sec2; int ret; @@ -93,7 +93,7 @@ nvkm_sec2_new_(const struct nvkm_sec2_fwif *fwif, struct nvkm_device *device, if (!(sec2 = *psec2 = kzalloc(sizeof(*sec2), GFP_KERNEL))) return -ENOMEM; - ret = nvkm_engine_ctor(&nvkm_sec2, device, index, true, &sec2->engine); + ret = nvkm_engine_ctor(&nvkm_sec2, device, type, inst, true, &sec2->engine); if (ret) return ret; @@ -104,7 +104,7 @@ nvkm_sec2_new_(const struct nvkm_sec2_fwif *fwif, struct nvkm_device *device, sec2->func = fwif->func; ret = nvkm_falcon_ctor(sec2->func->flcn, &sec2->engine.subdev, - nvkm_subdev_name[index], addr, &sec2->falcon); + sec2->engine.subdev.name, addr, &sec2->falcon); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c index bccf7acb7f98..44e39f5743d5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c @@ -343,7 +343,8 @@ gp102_sec2_fwif[] = { }; int -gp102_sec2_new(struct nvkm_device *device, int index, struct nvkm_sec2 **psec2) +gp102_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_sec2 **psec2) { - return nvkm_sec2_new_(gp102_sec2_fwif, device, index, 0, psec2); + return nvkm_sec2_new_(gp102_sec2_fwif, device, type, inst, 0, psec2); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp108.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp108.c index e770c9497871..3e9f5c842f3c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp108.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp108.c @@ -36,7 +36,8 @@ gp108_sec2_fwif[] = { }; int -gp108_sec2_new(struct nvkm_device *device, int index, struct nvkm_sec2 **psec2) +gp108_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_sec2 **psec2) { - return nvkm_sec2_new_(gp108_sec2_fwif, device, index, 0, psec2); + return nvkm_sec2_new_(gp108_sec2_fwif, device, type, inst, 0, psec2); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h index 8cbc0b7d0a27..af19229e885d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h @@ -25,6 +25,6 @@ int gp102_sec2_load(struct nvkm_sec2 *, int, const struct nvkm_sec2_fwif *); extern const struct nvkm_sec2_func gp102_sec2; extern const struct nvkm_acr_lsf_func gp102_sec2_acr_1; -int nvkm_sec2_new_(const struct nvkm_sec2_fwif *, struct nvkm_device *, +int nvkm_sec2_new_(const struct nvkm_sec2_fwif *, struct nvkm_device *, enum nvkm_subdev_type, int, u32 addr, struct nvkm_sec2 **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c index a231c1c6c0a5..f3faeb705575 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c @@ -72,10 +72,11 @@ tu102_sec2_fwif[] = { }; int -tu102_sec2_new(struct nvkm_device *device, int index, struct nvkm_sec2 **psec2) +tu102_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_sec2 **psec2) { /* TOP info wasn't updated on Turing to reflect the PRI * address change for some reason. We override it here. */ - return nvkm_sec2_new_(tu102_sec2_fwif, device, index, 0x840000, psec2); + return nvkm_sec2_new_(tu102_sec2_fwif, device, type, inst, 0x840000, psec2); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c index 7be3198e11de..14871d0bd746 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c @@ -97,7 +97,7 @@ nvkm_sw = { int nvkm_sw_new_(const struct nvkm_sw_func *func, struct nvkm_device *device, - int index, struct nvkm_sw **psw) + enum nvkm_subdev_type type, int inst, struct nvkm_sw **psw) { struct nvkm_sw *sw; @@ -106,5 +106,5 @@ nvkm_sw_new_(const struct nvkm_sw_func *func, struct nvkm_device *device, INIT_LIST_HEAD(&sw->chan); sw->func = func; - return nvkm_engine_ctor(&nvkm_sw, device, index, true, &sw->engine); + return nvkm_engine_ctor(&nvkm_sw, device, type, inst, true, &sw->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c index ea8f4247b628..55abf839f29d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c @@ -149,7 +149,7 @@ gf100_sw = { }; int -gf100_sw_new(struct nvkm_device *device, int index, struct nvkm_sw **psw) +gf100_sw_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_sw **psw) { - return nvkm_sw_new_(&gf100_sw, device, index, psw); + return nvkm_sw_new_(&gf100_sw, device, type, inst, psw); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c index b6675fe1b0ce..4aa57573869c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c @@ -133,7 +133,7 @@ nv04_sw = { }; int -nv04_sw_new(struct nvkm_device *device, int index, struct nvkm_sw **psw) +nv04_sw_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_sw **psw) { - return nvkm_sw_new_(&nv04_sw, device, index, psw); + return nvkm_sw_new_(&nv04_sw, device, type, inst, psw); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c index 09d22fcd194c..e79e640ae535 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c @@ -62,7 +62,7 @@ nv10_sw = { }; int -nv10_sw_new(struct nvkm_device *device, int index, struct nvkm_sw **psw) +nv10_sw_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_sw **psw) { - return nvkm_sw_new_(&nv10_sw, device, index, psw); + return nvkm_sw_new_(&nv10_sw, device, type, inst, psw); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c index 01573d187f2c..1fdd094c8b7e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c @@ -142,7 +142,7 @@ nv50_sw = { }; int -nv50_sw_new(struct nvkm_device *device, int index, struct nvkm_sw **psw) +nv50_sw_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_sw **psw) { - return nvkm_sw_new_(&nv50_sw, device, index, psw); + return nvkm_sw_new_(&nv50_sw, device, type, inst, psw); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/sw/priv.h index 6d18fc6180f2..d9d83b1b8849 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/priv.h @@ -5,8 +5,8 @@ #include <engine/sw.h> struct nvkm_sw_chan; -int nvkm_sw_new_(const struct nvkm_sw_func *, struct nvkm_device *, - int index, struct nvkm_sw **); +int nvkm_sw_new_(const struct nvkm_sw_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_sw **); struct nvkm_sw_chan_sclass { int (*ctor)(struct nvkm_sw_chan *, const struct nvkm_oclass *, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c index 7a96178786c4..b502266c76fd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c @@ -36,8 +36,8 @@ g84_vp = { }; int -g84_vp_new(struct nvkm_device *device, int index, struct nvkm_engine **pengine) +g84_vp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_engine **pengine) { - return nvkm_xtensa_new_(&g84_vp, device, index, - true, 0x00f000, pengine); + return nvkm_xtensa_new_(&g84_vp, device, type, inst, true, 0x00f000, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c index 70549381e082..f7d3ba0afb55 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c @@ -175,9 +175,9 @@ nvkm_xtensa = { }; int -nvkm_xtensa_new_(const struct nvkm_xtensa_func *func, - struct nvkm_device *device, int index, bool enable, - u32 addr, struct nvkm_engine **pengine) +nvkm_xtensa_new_(const struct nvkm_xtensa_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, bool enable, u32 addr, + struct nvkm_engine **pengine) { struct nvkm_xtensa *xtensa; @@ -187,6 +187,5 @@ nvkm_xtensa_new_(const struct nvkm_xtensa_func *func, xtensa->addr = addr; *pengine = &xtensa->engine; - return nvkm_engine_ctor(&nvkm_xtensa, device, index, - enable, &xtensa->engine); + return nvkm_engine_ctor(&nvkm_xtensa, device, type, inst, enable, &xtensa->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/base.c b/drivers/gpu/drm/nouveau/nvkm/falcon/base.c index c6a3448180d6..262641a014b0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/falcon/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/base.c @@ -88,13 +88,12 @@ int nvkm_falcon_enable(struct nvkm_falcon *falcon) { struct nvkm_device *device = falcon->owner->device; - enum nvkm_devidx id = falcon->owner->index; int ret; - nvkm_mc_enable(device, id); + nvkm_mc_enable(device, falcon->owner->type, falcon->owner->inst); ret = falcon->func->enable(falcon); if (ret) { - nvkm_mc_disable(device, id); + nvkm_mc_disable(device, falcon->owner->type, falcon->owner->inst); return ret; } @@ -105,15 +104,14 @@ void nvkm_falcon_disable(struct nvkm_falcon *falcon) { struct nvkm_device *device = falcon->owner->device; - enum nvkm_devidx id = falcon->owner->index; /* already disabled, return or wait_idle will timeout */ - if (!nvkm_mc_enabled(device, id)) + if (!nvkm_mc_enabled(device, falcon->owner->type, falcon->owner->inst)) return; falcon->func->disable(falcon); - nvkm_mc_disable(device, id); + nvkm_mc_disable(device, falcon->owner->type, falcon->owner->inst); } int @@ -143,7 +141,7 @@ nvkm_falcon_oneinit(struct nvkm_falcon *falcon) u32 reg; if (!falcon->addr) { - falcon->addr = nvkm_top_addr(subdev->device, subdev->index); + falcon->addr = nvkm_top_addr(subdev->device, subdev->type, subdev->inst); if (WARN_ON(!falcon->addr)) return -ENODEV; } @@ -188,7 +186,7 @@ nvkm_falcon_get(struct nvkm_falcon *falcon, const struct nvkm_subdev *user) mutex_lock(&falcon->mutex); if (falcon->user) { nvkm_error(user, "%s falcon already acquired by %s!\n", - falcon->name, nvkm_subdev_name[falcon->user->index]); + falcon->name, falcon->user->name); mutex_unlock(&falcon->mutex); return -EBUSY; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild index fb4fff1222af..2cb24fff7e32 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild @@ -11,7 +11,6 @@ include $(src)/nvkm/subdev/fuse/Kbuild include $(src)/nvkm/subdev/gpio/Kbuild include $(src)/nvkm/subdev/gsp/Kbuild include $(src)/nvkm/subdev/i2c/Kbuild -include $(src)/nvkm/subdev/ibus/Kbuild include $(src)/nvkm/subdev/iccsense/Kbuild include $(src)/nvkm/subdev/instmem/Kbuild include $(src)/nvkm/subdev/ltc/Kbuild @@ -20,6 +19,7 @@ include $(src)/nvkm/subdev/mmu/Kbuild include $(src)/nvkm/subdev/mxm/Kbuild include $(src)/nvkm/subdev/pci/Kbuild include $(src)/nvkm/subdev/pmu/Kbuild +include $(src)/nvkm/subdev/privring/Kbuild include $(src)/nvkm/subdev/therm/Kbuild include $(src)/nvkm/subdev/timer/Kbuild include $(src)/nvkm/subdev/top/Kbuild diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c index c962df9910dd..af6cac696d43 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c @@ -410,14 +410,14 @@ nvkm_acr_ctor_wpr(struct nvkm_acr *acr, int ver) int nvkm_acr_new_(const struct nvkm_acr_fwif *fwif, struct nvkm_device *device, - int index, struct nvkm_acr **pacr) + enum nvkm_subdev_type type, int inst, struct nvkm_acr **pacr) { struct nvkm_acr *acr; long wprfw; if (!(acr = *pacr = kzalloc(sizeof(*acr), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_acr, device, index, &acr->subdev); + nvkm_subdev_ctor(&nvkm_acr, device, type, inst, &acr->subdev); INIT_LIST_HEAD(&acr->hsfw); INIT_LIST_HEAD(&acr->lsfw); INIT_LIST_HEAD(&acr->hsf); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c index cd41b2e6cc87..cdb1ead26d84 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c @@ -262,7 +262,7 @@ gm200_acr_hsfw_boot(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf, hsf->func->bld(acr, hsf); /* Boot the falcon. */ - nvkm_mc_intr_mask(device, falcon->owner->index, false); + nvkm_mc_intr_mask(device, falcon->owner->type, falcon->owner->inst, false); nvkm_falcon_wr32(falcon, 0x040, 0xdeada5a5); nvkm_falcon_set_start_addr(falcon, hsf->imem_tag << 8); @@ -279,7 +279,7 @@ gm200_acr_hsfw_boot(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf, return -EIO; nvkm_falcon_clear_interrupt(falcon, intr_clear); - nvkm_mc_intr_mask(device, falcon->owner->index, true); + nvkm_mc_intr_mask(device, falcon->owner->type, falcon->owner->inst, true); return ret; } @@ -478,7 +478,8 @@ gm200_acr_fwif[] = { }; int -gm200_acr_new(struct nvkm_device *device, int index, struct nvkm_acr **pacr) +gm200_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_acr **pacr) { - return nvkm_acr_new_(gm200_acr_fwif, device, index, pacr); + return nvkm_acr_new_(gm200_acr_fwif, device, type, inst, pacr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.c index b1ecc58152cc..54e996f2f630 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.c @@ -129,7 +129,8 @@ gm20b_acr_fwif[] = { }; int -gm20b_acr_new(struct nvkm_device *device, int index, struct nvkm_acr **pacr) +gm20b_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_acr **pacr) { - return nvkm_acr_new_(gm20b_acr_fwif, device, index, pacr); + return nvkm_acr_new_(gm20b_acr_fwif, device, type, inst, pacr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.c index 80eb9d8dbc80..fb9132a39bb1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.c @@ -276,7 +276,8 @@ gp102_acr_fwif[] = { }; int -gp102_acr_new(struct nvkm_device *device, int index, struct nvkm_acr **pacr) +gp102_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_acr **pacr) { - return nvkm_acr_new_(gp102_acr_fwif, device, index, pacr); + return nvkm_acr_new_(gp102_acr_fwif, device, type, inst, pacr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp108.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp108.c index 67a7c141004b..373d638a2177 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp108.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp108.c @@ -106,7 +106,8 @@ gp108_acr_fwif[] = { }; int -gp108_acr_new(struct nvkm_device *device, int index, struct nvkm_acr **pacr) +gp108_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_acr **pacr) { - return nvkm_acr_new_(gp108_acr_fwif, device, index, pacr); + return nvkm_acr_new_(gp108_acr_fwif, device, type, inst, pacr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp10b.c index 8249f0d2d81d..f03ba028867b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp10b.c @@ -52,7 +52,8 @@ gp10b_acr_fwif[] = { }; int -gp10b_acr_new(struct nvkm_device *device, int index, struct nvkm_acr **pacr) +gp10b_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_acr **pacr) { - return nvkm_acr_new_(gp10b_acr_fwif, device, index, pacr); + return nvkm_acr_new_(gp10b_acr_fwif, device, type, inst, pacr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/priv.h index d71af17a169a..c30b841c9d35 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/priv.h @@ -135,8 +135,8 @@ int gp102_acr_load_load(struct nvkm_acr *, struct nvkm_acr_hsfw *); extern const struct nvkm_acr_hsf_func gp108_acr_unload_0; void gp108_acr_hsfw_bld(struct nvkm_acr *, struct nvkm_acr_hsf *); -int nvkm_acr_new_(const struct nvkm_acr_fwif *, struct nvkm_device *, int, - struct nvkm_acr **); +int nvkm_acr_new_(const struct nvkm_acr_fwif *, struct nvkm_device *, enum nvkm_subdev_type, + int inst, struct nvkm_acr **); int nvkm_acr_hsf_boot(struct nvkm_acr *, const char *name); struct nvkm_acr_lsf { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c index c4981bce9a2b..05a87e77525f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c @@ -224,7 +224,8 @@ tu102_acr_fwif[] = { }; int -tu102_acr_new(struct nvkm_device *device, int index, struct nvkm_acr **pacr) +tu102_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_acr **pacr) { - return nvkm_acr_new_(tu102_acr_fwif, device, index, pacr); + return nvkm_acr_new_(tu102_acr_fwif, device, type, inst, pacr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c index 209a6a40834a..d017a1b5e5dd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c @@ -134,9 +134,9 @@ nvkm_bar = { void nvkm_bar_ctor(const struct nvkm_bar_func *func, struct nvkm_device *device, - int index, struct nvkm_bar *bar) + enum nvkm_subdev_type type, int inst, struct nvkm_bar *bar) { - nvkm_subdev_ctor(&nvkm_bar, device, index, &bar->subdev); + nvkm_subdev_ctor(&nvkm_bar, device, type, inst, &bar->subdev); bar->func = func; spin_lock_init(&bar->lock); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.c index 87f26f54b481..77a41bcf860e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.c @@ -56,7 +56,8 @@ g84_bar_func = { }; int -g84_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar) +g84_bar_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bar **pbar) { - return nv50_bar_new_(&g84_bar_func, device, index, 0x200, pbar); + return nv50_bar_new_(&g84_bar_func, device, type, inst, 0x200, pbar); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c index a3dcb09a40ee..51070b7dda85 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c @@ -162,12 +162,12 @@ gf100_bar_dtor(struct nvkm_bar *base) int gf100_bar_new_(const struct nvkm_bar_func *func, struct nvkm_device *device, - int index, struct nvkm_bar **pbar) + enum nvkm_subdev_type type, int inst, struct nvkm_bar **pbar) { struct gf100_bar *bar; if (!(bar = kzalloc(sizeof(*bar), GFP_KERNEL))) return -ENOMEM; - nvkm_bar_ctor(func, device, index, &bar->base); + nvkm_bar_ctor(func, device, type, inst, &bar->base); bar->bar2_halve = nvkm_boolopt(device->cfgopt, "NvBar2Halve", false); *pbar = &bar->base; return 0; @@ -189,7 +189,8 @@ gf100_bar_func = { }; int -gf100_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar) +gf100_bar_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bar **pbar) { - return gf100_bar_new_(&gf100_bar_func, device, index, pbar); + return gf100_bar_new_(&gf100_bar_func, device, type, inst, pbar); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h index 4ae4c7145712..328a68b418d9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h @@ -15,7 +15,7 @@ struct gf100_bar { struct gf100_barN bar[2]; }; -int gf100_bar_new_(const struct nvkm_bar_func *, struct nvkm_device *, +int gf100_bar_new_(const struct nvkm_bar_func *, struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_bar **); void *gf100_bar_dtor(struct nvkm_bar *); int gf100_bar_oneinit(struct nvkm_bar *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c index 35878fb538f2..eead8ab88393 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c @@ -32,9 +32,10 @@ gk20a_bar_func = { }; int -gk20a_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar) +gk20a_bar_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bar **pbar) { - int ret = gf100_bar_new_(&gk20a_bar_func, device, index, pbar); + int ret = gf100_bar_new_(&gk20a_bar_func, device, type, inst, pbar); if (ret == 0) (*pbar)->iomap_uncached = true; return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm107.c index 3ddf9222d935..da95307a7912 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm107.c @@ -59,7 +59,8 @@ gm107_bar_func = { }; int -gm107_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar) +gm107_bar_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bar **pbar) { - return gf100_bar_new_(&gm107_bar_func, device, index, pbar); + return gf100_bar_new_(&gm107_bar_func, device, type, inst, pbar); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm20b.c index 1ed6170891c4..4acdb4fb0107 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm20b.c @@ -32,9 +32,10 @@ gm20b_bar_func = { }; int -gm20b_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar) +gm20b_bar_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bar **pbar) { - int ret = gf100_bar_new_(&gm20b_bar_func, device, index, pbar); + int ret = gf100_bar_new_(&gm20b_bar_func, device, type, inst, pbar); if (ret == 0) (*pbar)->iomap_uncached = true; return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c index f23a0ccc2bec..27d8a1be43e4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c @@ -220,12 +220,12 @@ nv50_bar_dtor(struct nvkm_bar *base) int nv50_bar_new_(const struct nvkm_bar_func *func, struct nvkm_device *device, - int index, u32 pgd_addr, struct nvkm_bar **pbar) + enum nvkm_subdev_type type, int inst, u32 pgd_addr, struct nvkm_bar **pbar) { struct nv50_bar *bar; if (!(bar = kzalloc(sizeof(*bar), GFP_KERNEL))) return -ENOMEM; - nvkm_bar_ctor(func, device, index, &bar->base); + nvkm_bar_ctor(func, device, type, inst, &bar->base); bar->pgd_addr = pgd_addr; *pbar = &bar->base; return 0; @@ -248,7 +248,8 @@ nv50_bar_func = { }; int -nv50_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar) +nv50_bar_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bar **pbar) { - return nv50_bar_new_(&nv50_bar_func, device, index, 0x1400, pbar); + return nv50_bar_new_(&nv50_bar_func, device, type, inst, 0x1400, pbar); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h index e4193deb2e51..dedee9394079 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h @@ -16,7 +16,7 @@ struct nv50_bar { struct nvkm_gpuobj *bar2; }; -int nv50_bar_new_(const struct nvkm_bar_func *, struct nvkm_device *, +int nv50_bar_new_(const struct nvkm_bar_func *, struct nvkm_device *, enum nvkm_subdev_type, int, u32 pgd_addr, struct nvkm_bar **); void *nv50_bar_dtor(struct nvkm_bar *); int nv50_bar_oneinit(struct nvkm_bar *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h index 869ad184f923..daebfc991c76 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h @@ -5,7 +5,7 @@ #include <subdev/bar.h> void nvkm_bar_ctor(const struct nvkm_bar_func *, struct nvkm_device *, - int, struct nvkm_bar *); + enum nvkm_subdev_type, int, struct nvkm_bar *); struct nvkm_bar_func { void *(*dtor)(struct nvkm_bar *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c index 798f65ec3a86..c25ab407b85d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c @@ -92,7 +92,8 @@ tu102_bar = { }; int -tu102_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar) +tu102_bar_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bar **pbar) { - return gf100_bar_new_(&tu102_bar, device, index, pbar); + return gf100_bar_new_(&tu102_bar, device, type, inst, pbar); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c index f3c30b2a788e..d0f52d59fc2f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c @@ -140,7 +140,8 @@ nvkm_bios = { }; int -nvkm_bios_new(struct nvkm_device *device, int index, struct nvkm_bios **pbios) +nvkm_bios_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bios **pbios) { struct nvkm_bios *bios; struct nvbios_image image; @@ -149,7 +150,7 @@ nvkm_bios_new(struct nvkm_device *device, int index, struct nvkm_bios **pbios) if (!(bios = *pbios = kzalloc(sizeof(*bios), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_bios, device, index, &bios->subdev); + nvkm_subdev_ctor(&nvkm_bios, device, type, inst, &bios->subdev); ret = nvbios_shadow(bios); if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/base.c index 52ad73bce5fe..0e5a46db52ea 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/base.c @@ -53,12 +53,12 @@ nvkm_bus = { int nvkm_bus_new_(const struct nvkm_bus_func *func, struct nvkm_device *device, - int index, struct nvkm_bus **pbus) + enum nvkm_subdev_type type, int inst, struct nvkm_bus **pbus) { struct nvkm_bus *bus; if (!(bus = *pbus = kzalloc(sizeof(*bus), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_bus, device, index, &bus->subdev); + nvkm_subdev_ctor(&nvkm_bus, device, type, inst, &bus->subdev); bus->func = func; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c index 9700b5c01cc6..a0d6e2d3f804 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c @@ -58,7 +58,8 @@ g94_bus = { }; int -g94_bus_new(struct nvkm_device *device, int index, struct nvkm_bus **pbus) +g94_bus_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bus **pbus) { - return nvkm_bus_new_(&g94_bus, device, index, pbus); + return nvkm_bus_new_(&g94_bus, device, type, inst, pbus); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c index e0930d5fdfb1..53a6651ac225 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c @@ -40,7 +40,7 @@ gf100_bus_intr(struct nvkm_bus *bus) (addr & 0x00000002) ? "write" : "read", data, (addr & 0x00fffffc), (stat & 0x00000002) ? "!ENGINE " : "", - (stat & 0x00000004) ? "IBUS " : "", + (stat & 0x00000004) ? "PRIVRING " : "", (stat & 0x00000008) ? "TIMEOUT " : ""); nvkm_wr32(device, 0x009084, 0x00000000); @@ -69,7 +69,8 @@ gf100_bus = { }; int -gf100_bus_new(struct nvkm_device *device, int index, struct nvkm_bus **pbus) +gf100_bus_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bus **pbus) { - return nvkm_bus_new_(&gf100_bus, device, index, pbus); + return nvkm_bus_new_(&gf100_bus, device, type, inst, pbus); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c index 2b44ba5cf4b0..cfed17c062ea 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c @@ -68,7 +68,8 @@ nv04_bus = { }; int -nv04_bus_new(struct nvkm_device *device, int index, struct nvkm_bus **pbus) +nv04_bus_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bus **pbus) { - return nvkm_bus_new_(&nv04_bus, device, index, pbus); + return nvkm_bus_new_(&nv04_bus, device, type, inst, pbus); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c index 5153d89e1f0b..ad8da523bb22 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c @@ -82,7 +82,8 @@ nv31_bus = { }; int -nv31_bus_new(struct nvkm_device *device, int index, struct nvkm_bus **pbus) +nv31_bus_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bus **pbus) { - return nvkm_bus_new_(&nv31_bus, device, index, pbus); + return nvkm_bus_new_(&nv31_bus, device, type, inst, pbus); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c index 19e10fdc9291..3a1e45adeedc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c @@ -99,7 +99,8 @@ nv50_bus = { }; int -nv50_bus_new(struct nvkm_device *device, int index, struct nvkm_bus **pbus) +nv50_bus_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_bus **pbus) { - return nvkm_bus_new_(&nv50_bus, device, index, pbus); + return nvkm_bus_new_(&nv50_bus, device, type, inst, pbus); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/priv.h index 76f7ba1c6494..2e9345b17cf8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/priv.h @@ -11,7 +11,7 @@ struct nvkm_bus_func { u32 hwsq_size; }; -int nvkm_bus_new_(const struct nvkm_bus_func *, struct nvkm_device *, int, +int nvkm_bus_new_(const struct nvkm_bus_func *, struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_bus **); void nv50_bus_init(struct nvkm_bus *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c index dc184e857f85..57199be082fd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c @@ -649,7 +649,7 @@ nvkm_clk = { int nvkm_clk_ctor(const struct nvkm_clk_func *func, struct nvkm_device *device, - int index, bool allow_reclock, struct nvkm_clk *clk) + enum nvkm_subdev_type type, int inst, bool allow_reclock, struct nvkm_clk *clk) { struct nvkm_subdev *subdev = &clk->subdev; struct nvkm_bios *bios = device->bios; @@ -657,7 +657,7 @@ nvkm_clk_ctor(const struct nvkm_clk_func *func, struct nvkm_device *device, const char *mode; struct nvbios_vpstate_header h; - nvkm_subdev_ctor(&nvkm_clk, device, index, subdev); + nvkm_subdev_ctor(&nvkm_clk, device, type, inst, subdev); if (bios && !nvbios_vpstate_parse(bios, &h)) { struct nvbios_vpstate_entry base, boost; @@ -716,9 +716,9 @@ nvkm_clk_ctor(const struct nvkm_clk_func *func, struct nvkm_device *device, int nvkm_clk_new_(const struct nvkm_clk_func *func, struct nvkm_device *device, - int index, bool allow_reclock, struct nvkm_clk **pclk) + enum nvkm_subdev_type type, int inst, bool allow_reclock, struct nvkm_clk **pclk) { if (!(*pclk = kzalloc(sizeof(**pclk), GFP_KERNEL))) return -ENOMEM; - return nvkm_clk_ctor(func, device, index, allow_reclock, *pclk); + return nvkm_clk_ctor(func, device, type, inst, allow_reclock, *pclk); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c index f97e3ec196bb..07157cf53c9e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c @@ -41,8 +41,8 @@ g84_clk = { }; int -g84_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) +g84_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_clk **pclk) { - return nv50_clk_new_(&g84_clk, device, index, - (device->chipset >= 0x94), pclk); + return nv50_clk_new_(&g84_clk, device, type, inst, (device->chipset >= 0x94), pclk); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c index 7f67f9f5a550..6eea11aefb70 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c @@ -468,7 +468,8 @@ gf100_clk = { }; int -gf100_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) +gf100_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_clk **pclk) { struct gf100_clk *clk; @@ -476,5 +477,5 @@ gf100_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) return -ENOMEM; *pclk = &clk->base; - return nvkm_clk_ctor(&gf100_clk, device, index, false, &clk->base); + return nvkm_clk_ctor(&gf100_clk, device, type, inst, false, &clk->base); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c index 0b37e3da7feb..0d8e2ddcc5ee 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c @@ -504,7 +504,8 @@ gk104_clk = { }; int -gk104_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) +gk104_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_clk **pclk) { struct gk104_clk *clk; @@ -512,5 +513,5 @@ gk104_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) return -ENOMEM; *pclk = &clk->base; - return nvkm_clk_ctor(&gk104_clk, device, index, true, &clk->base); + return nvkm_clk_ctor(&gk104_clk, device, type, inst, true, &clk->base); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c index 218893e3e5f9..d573fb0917fc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c @@ -610,10 +610,9 @@ gk20a_clk = { }; int -gk20a_clk_ctor(struct nvkm_device *device, int index, - const struct nvkm_clk_func *func, - const struct gk20a_clk_pllg_params *params, - struct gk20a_clk *clk) +gk20a_clk_ctor(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + const struct nvkm_clk_func *func, const struct gk20a_clk_pllg_params *params, + struct gk20a_clk *clk) { struct nvkm_device_tegra *tdev = device->func->tegra(device); int ret; @@ -628,7 +627,7 @@ gk20a_clk_ctor(struct nvkm_device *device, int index, clk->params = params; clk->parent_rate = clk_get_rate(tdev->clk); - ret = nvkm_clk_ctor(func, device, index, true, &clk->base); + ret = nvkm_clk_ctor(func, device, type, inst, true, &clk->base); if (ret) return ret; @@ -639,7 +638,8 @@ gk20a_clk_ctor(struct nvkm_device *device, int index, } int -gk20a_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) +gk20a_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_clk **pclk) { struct gk20a_clk *clk; int ret; @@ -649,11 +649,9 @@ gk20a_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) return -ENOMEM; *pclk = &clk->base; - ret = gk20a_clk_ctor(device, index, &gk20a_clk, &gk20a_pllg_params, - clk); + ret = gk20a_clk_ctor(device, type, inst, &gk20a_clk, &gk20a_pllg_params, clk); clk->pl_to_div = pl_to_div; clk->div_to_pl = div_to_pl; - return ret; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h index 0d1450972162..286413ff4a9e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h @@ -146,8 +146,8 @@ gk20a_pllg_n_lo(struct gk20a_clk *clk, struct gk20a_pll *pll) clk->parent_rate / KHZ); } -int gk20a_clk_ctor(struct nvkm_device *, int, const struct nvkm_clk_func *, - const struct gk20a_clk_pllg_params *, struct gk20a_clk *); +int gk20a_clk_ctor(struct nvkm_device *, enum nvkm_subdev_type, int, const struct nvkm_clk_func *, + const struct gk20a_clk_pllg_params *, struct gk20a_clk *); void gk20a_clk_fini(struct nvkm_clk *); int gk20a_clk_read(struct nvkm_clk *, enum nv_clk_src); int gk20a_clk_calc(struct nvkm_clk *, struct nvkm_cstate *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c index b284e949f732..a139dafffe06 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c @@ -908,7 +908,7 @@ gm20b_clk = { }; static int -gm20b_clk_new_speedo0(struct nvkm_device *device, int index, +gm20b_clk_new_speedo0(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_clk **pclk) { struct gk20a_clk *clk; @@ -919,12 +919,9 @@ gm20b_clk_new_speedo0(struct nvkm_device *device, int index, return -ENOMEM; *pclk = &clk->base; - ret = gk20a_clk_ctor(device, index, &gm20b_clk_speedo0, - &gm20b_pllg_params, clk); - + ret = gk20a_clk_ctor(device, type, inst, &gm20b_clk_speedo0, &gm20b_pllg_params, clk); clk->pl_to_div = pl_to_div; clk->div_to_pl = div_to_pl; - return ret; } @@ -1014,7 +1011,8 @@ gm20b_clk_init_safe_fmax(struct gm20b_clk *clk) } int -gm20b_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) +gm20b_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_clk **pclk) { struct nvkm_device_tegra *tdev = device->func->tegra(device); struct gm20b_clk *clk; @@ -1024,7 +1022,7 @@ gm20b_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) /* Speedo 0 GPUs cannot use noise-aware PLL */ if (tdev->gpu_speedo_id == 0) - return gm20b_clk_new_speedo0(device, index, pclk); + return gm20b_clk_new_speedo0(device, type, inst, pclk); /* Speedo >= 1, use NAPLL */ clk = kzalloc(sizeof(*clk) + sizeof(*clk_params), GFP_KERNEL); @@ -1036,8 +1034,7 @@ gm20b_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) /* duplicate the clock parameters since we will patch them below */ clk_params = (void *) (clk + 1); *clk_params = gm20b_pllg_params; - ret = gk20a_clk_ctor(device, index, &gm20b_clk, clk_params, - &clk->base); + ret = gk20a_clk_ctor(device, type, inst, &gm20b_clk, clk_params, &clk->base); if (ret) return ret; @@ -1050,7 +1047,7 @@ gm20b_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) if (clk_params->max_m == 0) { nvkm_warn(subdev, "cannot use NAPLL, using legacy clock...\n"); kfree(clk); - return gm20b_clk_new_speedo0(device, index, pclk); + return gm20b_clk_new_speedo0(device, type, inst, pclk); } clk->base.pl_to_div = pl_to_div; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c index f0a26881d9b9..b5f3969727a2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c @@ -537,7 +537,8 @@ gt215_clk = { }; int -gt215_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) +gt215_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_clk **pclk) { struct gt215_clk *clk; @@ -545,5 +546,5 @@ gt215_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) return -ENOMEM; *pclk = &clk->base; - return nvkm_clk_ctor(>215_clk, device, index, true, &clk->base); + return nvkm_clk_ctor(>215_clk, device, type, inst, true, &clk->base); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c index 4884eb4a9221..81f103f88dc8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c @@ -409,7 +409,8 @@ mcp77_clk = { }; int -mcp77_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) +mcp77_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_clk **pclk) { struct mcp77_clk *clk; @@ -417,5 +418,5 @@ mcp77_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) return -ENOMEM; *pclk = &clk->base; - return nvkm_clk_ctor(&mcp77_clk, device, index, true, &clk->base); + return nvkm_clk_ctor(&mcp77_clk, device, type, inst, true, &clk->base); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c index b280f85e8827..ca13598c2caa 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c @@ -72,9 +72,10 @@ nv04_clk = { }; int -nv04_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) +nv04_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_clk **pclk) { - int ret = nvkm_clk_new_(&nv04_clk, device, index, false, pclk); + int ret = nvkm_clk_new_(&nv04_clk, device, type, inst, false, pclk); if (ret == 0) { (*pclk)->pll_calc = nv04_clk_pll_calc; (*pclk)->pll_prog = nv04_clk_pll_prog; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c index 2ab9b9b84018..7ddd8cecb805 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c @@ -218,7 +218,8 @@ nv40_clk = { }; int -nv40_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) +nv40_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_clk **pclk) { struct nv40_clk *clk; @@ -228,5 +229,5 @@ nv40_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) clk->base.pll_prog = nv04_clk_pll_prog; *pclk = &clk->base; - return nvkm_clk_ctor(&nv40_clk, device, index, true, &clk->base); + return nvkm_clk_ctor(&nv40_clk, device, type, inst, true, &clk->base); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c index da1770e47490..83067763c0ec 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c @@ -507,14 +507,14 @@ nv50_clk_tidy(struct nvkm_clk *base) int nv50_clk_new_(const struct nvkm_clk_func *func, struct nvkm_device *device, - int index, bool allow_reclock, struct nvkm_clk **pclk) + enum nvkm_subdev_type type, int inst, bool allow_reclock, struct nvkm_clk **pclk) { struct nv50_clk *clk; int ret; if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) return -ENOMEM; - ret = nvkm_clk_ctor(func, device, index, allow_reclock, &clk->base); + ret = nvkm_clk_ctor(func, device, type, inst, allow_reclock, &clk->base); *pclk = &clk->base; if (ret) return ret; @@ -555,7 +555,8 @@ nv50_clk = { }; int -nv50_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) +nv50_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_clk **pclk) { - return nv50_clk_new_(&nv50_clk, device, index, false, pclk); + return nv50_clk_new_(&nv50_clk, device, type, inst, false, pclk); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h index 7c7713238ec4..5b4cb7e5cff6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h @@ -20,7 +20,7 @@ struct nv50_clk { struct nv50_clk_hwsq hwsq; }; -int nv50_clk_new_(const struct nvkm_clk_func *, struct nvkm_device *, int, +int nv50_clk_new_(const struct nvkm_clk_func *, struct nvkm_device *, enum nvkm_subdev_type, int, bool, struct nvkm_clk **); int nv50_clk_read(struct nvkm_clk *, enum nv_clk_src); int nv50_clk_calc(struct nvkm_clk *, struct nvkm_cstate *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/priv.h index 81dfb37480ae..810cc572cd30 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/priv.h @@ -16,9 +16,9 @@ struct nvkm_clk_func { struct nvkm_domain domains[]; }; -int nvkm_clk_ctor(const struct nvkm_clk_func *, struct nvkm_device *, int, +int nvkm_clk_ctor(const struct nvkm_clk_func *, struct nvkm_device *, enum nvkm_subdev_type, int, bool allow_reclock, struct nvkm_clk *); -int nvkm_clk_new_(const struct nvkm_clk_func *, struct nvkm_device *, int, +int nvkm_clk_new_(const struct nvkm_clk_func *, struct nvkm_device *, enum nvkm_subdev_type, int, bool allow_reclock, struct nvkm_clk **); int nv04_clk_pll_calc(struct nvkm_clk *, struct nvbios_pll *, int clk, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c index 4756019ddf3f..dd4981708fe4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c @@ -56,12 +56,12 @@ nvkm_devinit_disable(struct nvkm_devinit *init) } int -nvkm_devinit_post(struct nvkm_devinit *init, u64 *disable) +nvkm_devinit_post(struct nvkm_devinit *init) { int ret = 0; if (init && init->func->post) ret = init->func->post(init, init->post); - *disable = nvkm_devinit_disable(init); + nvkm_devinit_disable(init); return ret; } @@ -126,11 +126,10 @@ nvkm_devinit = { }; void -nvkm_devinit_ctor(const struct nvkm_devinit_func *func, - struct nvkm_device *device, int index, - struct nvkm_devinit *init) +nvkm_devinit_ctor(const struct nvkm_devinit_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_devinit *init) { - nvkm_subdev_ctor(&nvkm_devinit, device, index, &init->subdev); + nvkm_subdev_ctor(&nvkm_devinit, device, type, inst, &init->subdev); init->func = func; init->force_post = nvkm_boolopt(device->cfgopt, "NvForcePost", false); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c index e895289bf3c1..c224702b7bed 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c @@ -35,18 +35,18 @@ g84_devinit_disable(struct nvkm_devinit *init) u64 disable = 0ULL; if (!(r001540 & 0x40000000)) { - disable |= (1ULL << NVKM_ENGINE_MPEG); - disable |= (1ULL << NVKM_ENGINE_VP); - disable |= (1ULL << NVKM_ENGINE_BSP); - disable |= (1ULL << NVKM_ENGINE_CIPHER); + nvkm_subdev_disable(device, NVKM_ENGINE_MPEG, 0); + nvkm_subdev_disable(device, NVKM_ENGINE_VP, 0); + nvkm_subdev_disable(device, NVKM_ENGINE_BSP, 0); + nvkm_subdev_disable(device, NVKM_ENGINE_CIPHER, 0); } if (!(r00154c & 0x00000004)) - disable |= (1ULL << NVKM_ENGINE_DISP); + nvkm_subdev_disable(device, NVKM_ENGINE_DISP, 0); if (!(r00154c & 0x00000020)) - disable |= (1ULL << NVKM_ENGINE_BSP); + nvkm_subdev_disable(device, NVKM_ENGINE_BSP, 0); if (!(r00154c & 0x00000040)) - disable |= (1ULL << NVKM_ENGINE_CIPHER); + nvkm_subdev_disable(device, NVKM_ENGINE_CIPHER, 0); return disable; } @@ -61,8 +61,8 @@ g84_devinit = { }; int -g84_devinit_new(struct nvkm_device *device, int index, +g84_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit) { - return nv50_devinit_new_(&g84_devinit, device, index, pinit); + return nv50_devinit_new_(&g84_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c index a9d45844df5a..05729ca19e9a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c @@ -35,17 +35,17 @@ g98_devinit_disable(struct nvkm_devinit *init) u64 disable = 0ULL; if (!(r001540 & 0x40000000)) { - disable |= (1ULL << NVKM_ENGINE_MSPDEC); - disable |= (1ULL << NVKM_ENGINE_MSVLD); - disable |= (1ULL << NVKM_ENGINE_MSPPP); + nvkm_subdev_disable(device, NVKM_ENGINE_MSPDEC, 0); + nvkm_subdev_disable(device, NVKM_ENGINE_MSVLD, 0); + nvkm_subdev_disable(device, NVKM_ENGINE_MSPPP, 0); } if (!(r00154c & 0x00000004)) - disable |= (1ULL << NVKM_ENGINE_DISP); + nvkm_subdev_disable(device, NVKM_ENGINE_DISP, 0); if (!(r00154c & 0x00000020)) - disable |= (1ULL << NVKM_ENGINE_MSVLD); + nvkm_subdev_disable(device, NVKM_ENGINE_MSVLD, 0); if (!(r00154c & 0x00000040)) - disable |= (1ULL << NVKM_ENGINE_SEC); + nvkm_subdev_disable(device, NVKM_ENGINE_SEC, 0); return disable; } @@ -60,8 +60,8 @@ g98_devinit = { }; int -g98_devinit_new(struct nvkm_device *device, int index, +g98_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit) { - return nv50_devinit_new_(&g98_devinit, device, index, pinit); + return nv50_devinit_new_(&g98_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.c index 636a92128f6c..6b280b05c4ca 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.c @@ -70,7 +70,8 @@ ga100_devinit = { }; int -ga100_devinit_new(struct nvkm_device *device, int index, struct nvkm_devinit **pinit) +ga100_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_devinit **pinit) { - return nv50_devinit_new_(&ga100_devinit, device, index, pinit); + return nv50_devinit_new_(&ga100_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c index 8b1b34c3ad26..051cfd6a5caf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c @@ -71,21 +71,21 @@ gf100_devinit_disable(struct nvkm_devinit *init) u64 disable = 0ULL; if (r022500 & 0x00000001) - disable |= (1ULL << NVKM_ENGINE_DISP); + nvkm_subdev_disable(device, NVKM_ENGINE_DISP, 0); if (r022500 & 0x00000002) { - disable |= (1ULL << NVKM_ENGINE_MSPDEC); - disable |= (1ULL << NVKM_ENGINE_MSPPP); + nvkm_subdev_disable(device, NVKM_ENGINE_MSPDEC, 0); + nvkm_subdev_disable(device, NVKM_ENGINE_MSPPP, 0); } if (r022500 & 0x00000004) - disable |= (1ULL << NVKM_ENGINE_MSVLD); + nvkm_subdev_disable(device, NVKM_ENGINE_MSVLD, 0); if (r022500 & 0x00000008) - disable |= (1ULL << NVKM_ENGINE_MSENC); + nvkm_subdev_disable(device, NVKM_ENGINE_MSENC, 0); if (r022500 & 0x00000100) - disable |= (1ULL << NVKM_ENGINE_CE0); + nvkm_subdev_disable(device, NVKM_ENGINE_CE, 0); if (r022500 & 0x00000200) - disable |= (1ULL << NVKM_ENGINE_CE1); + nvkm_subdev_disable(device, NVKM_ENGINE_CE, 1); return disable; } @@ -114,8 +114,8 @@ gf100_devinit = { }; int -gf100_devinit_new(struct nvkm_device *device, int index, - struct nvkm_devinit **pinit) +gf100_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_devinit **pinit) { - return nv50_devinit_new_(&gf100_devinit, device, index, pinit); + return nv50_devinit_new_(&gf100_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c index 28ca01be3d38..4323732a3cb2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c @@ -35,11 +35,11 @@ gm107_devinit_disable(struct nvkm_devinit *init) u64 disable = 0ULL; if (r021c00 & 0x00000001) - disable |= (1ULL << NVKM_ENGINE_CE0); + nvkm_subdev_disable(device, NVKM_ENGINE_CE, 0); if (r021c00 & 0x00000004) - disable |= (1ULL << NVKM_ENGINE_CE2); + nvkm_subdev_disable(device, NVKM_ENGINE_CE, 2); if (r021c04 & 0x00000001) - disable |= (1ULL << NVKM_ENGINE_DISP); + nvkm_subdev_disable(device, NVKM_ENGINE_DISP, 0); return disable; } @@ -54,8 +54,8 @@ gm107_devinit = { }; int -gm107_devinit_new(struct nvkm_device *device, int index, - struct nvkm_devinit **pinit) +gm107_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_devinit **pinit) { - return nv50_devinit_new_(&gm107_devinit, device, index, pinit); + return nv50_devinit_new_(&gm107_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c index 59940dacc2ba..a308b9bde449 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c @@ -179,8 +179,8 @@ gm200_devinit = { }; int -gm200_devinit_new(struct nvkm_device *device, int index, - struct nvkm_devinit **pinit) +gm200_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_devinit **pinit) { - return nv50_devinit_new_(&gm200_devinit, device, index, pinit); + return nv50_devinit_new_(&gm200_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c index 9a8522fa9c65..dc026ac1b595 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c @@ -71,16 +71,16 @@ gt215_devinit_disable(struct nvkm_devinit *init) u64 disable = 0ULL; if (!(r001540 & 0x40000000)) { - disable |= (1ULL << NVKM_ENGINE_MSPDEC); - disable |= (1ULL << NVKM_ENGINE_MSPPP); + nvkm_subdev_disable(device, NVKM_ENGINE_MSPDEC, 0); + nvkm_subdev_disable(device, NVKM_ENGINE_MSPPP, 0); } if (!(r00154c & 0x00000004)) - disable |= (1ULL << NVKM_ENGINE_DISP); + nvkm_subdev_disable(device, NVKM_ENGINE_DISP, 0); if (!(r00154c & 0x00000020)) - disable |= (1ULL << NVKM_ENGINE_MSVLD); + nvkm_subdev_disable(device, NVKM_ENGINE_MSVLD, 0); if (!(r00154c & 0x00000200)) - disable |= (1ULL << NVKM_ENGINE_CE0); + nvkm_subdev_disable(device, NVKM_ENGINE_CE, 0); return disable; } @@ -146,8 +146,8 @@ gt215_devinit = { }; int -gt215_devinit_new(struct nvkm_device *device, int index, - struct nvkm_devinit **pinit) +gt215_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_devinit **pinit) { - return nv50_devinit_new_(>215_devinit, device, index, pinit); + return nv50_devinit_new_(>215_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gv100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gv100.c index fbde6828bd38..b4d1688517d5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gv100.c @@ -72,8 +72,8 @@ gv100_devinit = { }; int -gv100_devinit_new(struct nvkm_device *device, int index, - struct nvkm_devinit **pinit) +gv100_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_devinit **pinit) { - return nv50_devinit_new_(&gv100_devinit, device, index, pinit); + return nv50_devinit_new_(&gv100_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c index ce4f718e98a1..fb90d47e1225 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c @@ -35,18 +35,18 @@ mcp89_devinit_disable(struct nvkm_devinit *init) u64 disable = 0; if (!(r001540 & 0x40000000)) { - disable |= (1ULL << NVKM_ENGINE_MSPDEC); - disable |= (1ULL << NVKM_ENGINE_MSPPP); + nvkm_subdev_disable(device, NVKM_ENGINE_MSPDEC, 0); + nvkm_subdev_disable(device, NVKM_ENGINE_MSPPP, 0); } if (!(r00154c & 0x00000004)) - disable |= (1ULL << NVKM_ENGINE_DISP); + nvkm_subdev_disable(device, NVKM_ENGINE_DISP, 0); if (!(r00154c & 0x00000020)) - disable |= (1ULL << NVKM_ENGINE_MSVLD); + nvkm_subdev_disable(device, NVKM_ENGINE_MSVLD, 0); if (!(r00154c & 0x00000040)) - disable |= (1ULL << NVKM_ENGINE_VIC); + nvkm_subdev_disable(device, NVKM_ENGINE_VIC, 0); if (!(r00154c & 0x00000200)) - disable |= (1ULL << NVKM_ENGINE_CE0); + nvkm_subdev_disable(device, NVKM_ENGINE_CE, 0); return disable; } @@ -61,8 +61,8 @@ mcp89_devinit = { }; int -mcp89_devinit_new(struct nvkm_device *device, int index, - struct nvkm_devinit **pinit) +mcp89_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_devinit **pinit) { - return nv50_devinit_new_(&mcp89_devinit, device, index, pinit); + return nv50_devinit_new_(&mcp89_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c index 317ce9fb8225..88bc890f89a2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c @@ -434,9 +434,8 @@ nv04_devinit_dtor(struct nvkm_devinit *base) } int -nv04_devinit_new_(const struct nvkm_devinit_func *func, - struct nvkm_device *device, int index, - struct nvkm_devinit **pinit) +nv04_devinit_new_(const struct nvkm_devinit_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit) { struct nv04_devinit *init; @@ -444,7 +443,7 @@ nv04_devinit_new_(const struct nvkm_devinit_func *func, return -ENOMEM; *pinit = &init->base; - nvkm_devinit_ctor(func, device, index, &init->base); + nvkm_devinit_ctor(func, device, type, inst, &init->base); init->owner = -1; return 0; } @@ -459,8 +458,8 @@ nv04_devinit = { }; int -nv04_devinit_new(struct nvkm_device *device, int index, +nv04_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit) { - return nv04_devinit_new_(&nv04_devinit, device, index, pinit); + return nv04_devinit_new_(&nv04_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h index 15b029ddf6df..06ad8a606bb8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h @@ -11,7 +11,7 @@ struct nv04_devinit { }; int nv04_devinit_new_(const struct nvkm_devinit_func *, struct nvkm_device *, - int, struct nvkm_devinit **); + enum nvkm_subdev_type, int, struct nvkm_devinit **); void *nv04_devinit_dtor(struct nvkm_devinit *); void nv04_devinit_preinit(struct nvkm_devinit *); void nv04_devinit_fini(struct nvkm_devinit *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c index 9891eadca1ce..1410befd2285 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c @@ -136,8 +136,8 @@ nv05_devinit = { }; int -nv05_devinit_new(struct nvkm_device *device, int index, +nv05_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit) { - return nv04_devinit_new_(&nv05_devinit, device, index, pinit); + return nv04_devinit_new_(&nv05_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c index 570822f83acf..a6aa8786d610 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c @@ -106,8 +106,8 @@ nv10_devinit = { }; int -nv10_devinit_new(struct nvkm_device *device, int index, +nv10_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit) { - return nv04_devinit_new_(&nv10_devinit, device, index, pinit); + return nv04_devinit_new_(&nv10_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.c index fefafec7e2a7..4cc5ef9a5a63 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.c @@ -35,8 +35,8 @@ nv1a_devinit = { }; int -nv1a_devinit_new(struct nvkm_device *device, int index, +nv1a_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit) { - return nv04_devinit_new_(&nv1a_devinit, device, index, pinit); + return nv04_devinit_new_(&nv1a_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c index 4ef04e0d8826..67f46df723e4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c @@ -72,8 +72,8 @@ nv20_devinit = { }; int -nv20_devinit_new(struct nvkm_device *device, int index, +nv20_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit) { - return nv04_devinit_new_(&nv20_devinit, device, index, pinit); + return nv04_devinit_new_(&nv20_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c index d7947c4391dc..380995d398b1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c @@ -85,7 +85,7 @@ nv50_devinit_disable(struct nvkm_devinit *init) u64 disable = 0ULL; if (!(r001540 & 0x40000000)) - disable |= (1ULL << NVKM_ENGINE_MPEG); + nvkm_subdev_disable(device, NVKM_ENGINE_MPEG, 0); return disable; } @@ -101,8 +101,8 @@ nv50_devinit_preinit(struct nvkm_devinit *base) * missing, assume it's a secondary gpu which requires post */ if (!base->post) { - u64 disable = nvkm_devinit_disable(base); - if (disable & (1ULL << NVKM_ENGINE_DISP)) + nvkm_devinit_disable(base); + if (!device->disp) base->post = true; } @@ -148,9 +148,8 @@ nv50_devinit_init(struct nvkm_devinit *base) } int -nv50_devinit_new_(const struct nvkm_devinit_func *func, - struct nvkm_device *device, int index, - struct nvkm_devinit **pinit) +nv50_devinit_new_(const struct nvkm_devinit_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit) { struct nv50_devinit *init; @@ -158,7 +157,7 @@ nv50_devinit_new_(const struct nvkm_devinit_func *func, return -ENOMEM; *pinit = &init->base; - nvkm_devinit_ctor(func, device, index, &init->base); + nvkm_devinit_ctor(func, device, type, inst, &init->base); return 0; } @@ -172,8 +171,8 @@ nv50_devinit = { }; int -nv50_devinit_new(struct nvkm_device *device, int index, +nv50_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit) { - return nv50_devinit_new_(&nv50_devinit, device, index, pinit); + return nv50_devinit_new_(&nv50_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h index e8d37a6145a2..987a7f478b84 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h @@ -9,7 +9,7 @@ struct nv50_devinit { u32 r001540; }; -int nv50_devinit_new_(const struct nvkm_devinit_func *, struct nvkm_device *, +int nv50_devinit_new_(const struct nvkm_devinit_func *, struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_devinit **); void nv50_devinit_preinit(struct nvkm_devinit *); void nv50_devinit_init(struct nvkm_devinit *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h index 05961e624264..dd8b038a8cee 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h @@ -16,7 +16,8 @@ struct nvkm_devinit_func { }; void nvkm_devinit_ctor(const struct nvkm_devinit_func *, struct nvkm_device *, - int index, struct nvkm_devinit *); + enum nvkm_subdev_type, int inst, struct nvkm_devinit *); +u64 nvkm_devinit_disable(struct nvkm_devinit *); int nv04_devinit_post(struct nvkm_devinit *, bool); int tu102_devinit_post(struct nvkm_devinit *, bool); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c index 9a469bf482f2..634f64f88fc8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c @@ -82,8 +82,8 @@ tu102_devinit = { }; int -tu102_devinit_new(struct nvkm_device *device, int index, - struct nvkm_devinit **pinit) +tu102_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_devinit **pinit) { - return nv50_devinit_new_(&tu102_devinit, device, index, pinit); + return nv50_devinit_new_(&tu102_devinit, device, type, inst, pinit); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.c index f6dca97140d6..fd54fa504efa 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.c @@ -170,12 +170,12 @@ nvkm_fault = { int nvkm_fault_new_(const struct nvkm_fault_func *func, struct nvkm_device *device, - int index, struct nvkm_fault **pfault) + enum nvkm_subdev_type type, int inst, struct nvkm_fault **pfault) { struct nvkm_fault *fault; if (!(fault = *pfault = kzalloc(sizeof(*fault), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_fault, device, index, &fault->subdev); + nvkm_subdev_ctor(&nvkm_fault, device, type, inst, &fault->subdev); fault->func = func; fault->user.ctor = nvkm_ufault_new; fault->user.base = func->user.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp100.c index f6b189cc4330..6af7959e02ea 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp100.c @@ -30,7 +30,7 @@ void gp100_fault_buffer_intr(struct nvkm_fault_buffer *buffer, bool enable) { struct nvkm_device *device = buffer->fault->subdev.device; - nvkm_mc_intr_mask(device, NVKM_SUBDEV_FAULT, enable); + nvkm_mc_intr_mask(device, NVKM_SUBDEV_FAULT, 0, enable); } void @@ -82,8 +82,8 @@ gp100_fault = { }; int -gp100_fault_new(struct nvkm_device *device, int index, +gp100_fault_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fault **pfault) { - return nvkm_fault_new_(&gp100_fault, device, index, pfault); + return nvkm_fault_new_(&gp100_fault, device, type, inst, pfault); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp10b.c index 9e66d1f7654d..89e0bc96fb92 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp10b.c @@ -46,8 +46,8 @@ gp10b_fault = { }; int -gp10b_fault_new(struct nvkm_device *device, int index, +gp10b_fault_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fault **pfault) { - return nvkm_fault_new_(&gp10b_fault, device, index, pfault); + return nvkm_fault_new_(&gp10b_fault, device, type, inst, pfault); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c index 2707be4ffabc..cd9d2ade5ac7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c @@ -228,8 +228,8 @@ gv100_fault = { }; int -gv100_fault_new(struct nvkm_device *device, int index, +gv100_fault_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fault **pfault) { - return nvkm_fault_new_(&gv100_fault, device, index, pfault); + return nvkm_fault_new_(&gv100_fault, device, type, inst, pfault); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/priv.h index f6f1dd7eee1f..36681c347fb5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/priv.h @@ -18,8 +18,8 @@ struct nvkm_fault_buffer { u64 addr; }; -int nvkm_fault_new_(const struct nvkm_fault_func *, struct nvkm_device *, - int index, struct nvkm_fault **); +int nvkm_fault_new_(const struct nvkm_fault_func *, struct nvkm_device *, enum nvkm_subdev_type, + int inst, struct nvkm_fault **); struct nvkm_fault_func { int (*oneinit)(struct nvkm_fault *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c index f080051b0c65..91eb6729c84d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c @@ -37,7 +37,7 @@ tu102_fault_buffer_intr(struct nvkm_fault_buffer *buffer, bool enable) */ struct nvkm_device *device = buffer->fault->subdev.device; - nvkm_mc_intr_mask(device, NVKM_SUBDEV_FAULT, enable); + nvkm_mc_intr_mask(device, NVKM_SUBDEV_FAULT, 0, enable); } static void @@ -181,8 +181,8 @@ tu102_fault = { }; int -tu102_fault_new(struct nvkm_device *device, int index, +tu102_fault_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fault **pfault) { - return nvkm_fault_new_(&tu102_fault, device, index, pfault); + return nvkm_fault_new_(&tu102_fault, device, type, inst, pfault); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c index 5940e0dea2f8..6faaea948fc4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c @@ -122,7 +122,7 @@ nvkm_fb_oneinit(struct nvkm_subdev *subdev) nvkm_debug(subdev, "%d comptags\n", tags); } - return nvkm_mm_init(&fb->tags, 0, 0, tags, 1); + return nvkm_mm_init(&fb->tags.mm, 0, 0, tags, 1); } static int @@ -205,7 +205,9 @@ nvkm_fb_dtor(struct nvkm_subdev *subdev) for (i = 0; i < fb->tile.regions; i++) fb->func->tile.fini(fb, i, &fb->tile.region[i]); - nvkm_mm_fini(&fb->tags); + nvkm_mm_fini(&fb->tags.mm); + mutex_destroy(&fb->tags.mutex); + nvkm_ram_del(&fb->ram); nvkm_blob_dtor(&fb->vpr_scrubber); @@ -225,21 +227,21 @@ nvkm_fb = { void nvkm_fb_ctor(const struct nvkm_fb_func *func, struct nvkm_device *device, - int index, struct nvkm_fb *fb) + enum nvkm_subdev_type type, int inst, struct nvkm_fb *fb) { - nvkm_subdev_ctor(&nvkm_fb, device, index, &fb->subdev); + nvkm_subdev_ctor(&nvkm_fb, device, type, inst, &fb->subdev); fb->func = func; fb->tile.regions = fb->func->tile.regions; - fb->page = nvkm_longopt(device->cfgopt, "NvFbBigPage", - fb->func->default_bigpage); + fb->page = nvkm_longopt(device->cfgopt, "NvFbBigPage", fb->func->default_bigpage); + mutex_init(&fb->tags.mutex); } int nvkm_fb_new_(const struct nvkm_fb_func *func, struct nvkm_device *device, - int index, struct nvkm_fb **pfb) + enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { if (!(*pfb = kzalloc(sizeof(**pfb), GFP_KERNEL))) return -ENOMEM; - nvkm_fb_ctor(func, device, index, *pfb); + nvkm_fb_ctor(func, device, type, inst, *pfb); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c index 06bf95c0c549..770a4ad39122 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c @@ -32,7 +32,7 @@ g84_fb = { }; int -g84_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +g84_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nv50_fb_new_(&g84_fb, device, index, pfb); + return nv50_fb_new_(&g84_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga100.c index bf82686851cd..b47bebfbc26f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga100.c @@ -34,7 +34,7 @@ ga100_fb = { }; int -ga100_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +ga100_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gp102_fb_new_(&ga100_fb, device, index, pfb); + return gp102_fb_new_(&ga100_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.c index bcecf84a6e67..6ea7908f0563 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.c @@ -34,7 +34,7 @@ ga102_fb = { }; int -ga102_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +ga102_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gp102_fb_new_(&ga102_fb, device, index, pfb); + return gp102_fb_new_(&ga102_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c index e8dc4e913494..9dcc40f9ef79 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c @@ -117,13 +117,13 @@ gf100_fb_dtor(struct nvkm_fb *base) int gf100_fb_new_(const struct nvkm_fb_func *func, struct nvkm_device *device, - int index, struct nvkm_fb **pfb) + enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { struct gf100_fb *fb; if (!(fb = kzalloc(sizeof(*fb), GFP_KERNEL))) return -ENOMEM; - nvkm_fb_ctor(func, device, index, &fb->base); + nvkm_fb_ctor(func, device, type, inst, &fb->base); *pfb = &fb->base; return 0; @@ -141,7 +141,7 @@ gf100_fb = { }; int -gf100_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gf100_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gf100_fb_new_(&gf100_fb, device, index, pfb); + return gf100_fb_new_(&gf100_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h index 2ed7cdaab37c..0cac7b06acc8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h @@ -10,8 +10,8 @@ struct gf100_fb { dma_addr_t r100c10; }; -int gf100_fb_new_(const struct nvkm_fb_func *, struct nvkm_device *, - int index, struct nvkm_fb **); +int gf100_fb_new_(const struct nvkm_fb_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_fb **); void *gf100_fb_dtor(struct nvkm_fb *); void gf100_fb_init(struct nvkm_fb *); void gf100_fb_intr(struct nvkm_fb *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf108.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf108.c index 4a9f463745b5..76678dd60f93 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf108.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf108.c @@ -36,7 +36,7 @@ gf108_fb = { }; int -gf108_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gf108_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gf100_fb_new_(&gf108_fb, device, index, pfb); + return gf100_fb_new_(&gf108_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c index 48fd98e08baa..f73442ccb424 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c @@ -83,7 +83,7 @@ gk104_fb = { }; int -gk104_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gk104_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gf100_fb_new_(&gk104_fb, device, index, pfb); + return gf100_fb_new_(&gk104_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk110.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk110.c index 0695e5dd360e..45d6cdffafee 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk110.c @@ -65,7 +65,7 @@ gk110_fb = { }; int -gk110_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gk110_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gf100_fb_new_(&gk110_fb, device, index, pfb); + return gf100_fb_new_(&gk110_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c index a7e29b125094..6bc42f89d8c4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c @@ -34,7 +34,7 @@ gk20a_fb = { }; int -gk20a_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gk20a_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gf100_fb_new_(&gk20a_fb, device, index, pfb); + return gf100_fb_new_(&gk20a_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c index 69c876d5d1c1..de52462a92bf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c @@ -36,7 +36,7 @@ gm107_fb = { }; int -gm107_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gm107_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gf100_fb_new_(&gm107_fb, device, index, pfb); + return gf100_fb_new_(&gm107_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm200.c index d3b8c3367152..5acf8d15d06f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm200.c @@ -67,7 +67,7 @@ gm200_fb = { }; int -gm200_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gm200_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gf100_fb_new_(&gm200_fb, device, index, pfb); + return gf100_fb_new_(&gm200_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm20b.c index 12db61e31128..86f61a3f2fea 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm20b.c @@ -34,7 +34,7 @@ gm20b_fb = { }; int -gm20b_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gm20b_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gf100_fb_new_(&gm20b_fb, device, index, pfb); + return gf100_fb_new_(&gm20b_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c index 8205ce436b3e..09e943edc362 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c @@ -71,7 +71,7 @@ gp100_fb = { }; int -gp100_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gp100_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gf100_fb_new_(&gp100_fb, device, index, pfb); + return gf100_fb_new_(&gp100_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.c index fc8c93aa3da5..0e78b3d734a0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.c @@ -114,9 +114,9 @@ gp102_fb = { int gp102_fb_new_(const struct nvkm_fb_func *func, struct nvkm_device *device, - int index, struct nvkm_fb **pfb) + enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - int ret = gf100_fb_new_(func, device, index, pfb); + int ret = gf100_fb_new_(func, device, type, inst, pfb); if (ret) return ret; @@ -126,9 +126,9 @@ gp102_fb_new_(const struct nvkm_fb_func *func, struct nvkm_device *device, } int -gp102_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gp102_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gp102_fb_new_(&gp102_fb, device, index, pfb); + return gp102_fb_new_(&gp102_fb, device, type, inst, pfb); } MODULE_FIRMWARE("nvidia/gp102/nvdec/scrubber.bin"); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp10b.c index af8e43979dc1..84c9815a6d48 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp10b.c @@ -31,7 +31,7 @@ gp10b_fb = { }; int -gp10b_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gp10b_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gf100_fb_new_(&gp10b_fb, device, index, pfb); + return gf100_fb_new_(&gp10b_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c index 9266559b45f9..c1ec9758617c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c @@ -32,7 +32,7 @@ gt215_fb = { }; int -gt215_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gt215_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nv50_fb_new_(>215_fb, device, index, pfb); + return nv50_fb_new_(>215_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c index feda86a5fba8..63daa83ae12d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c @@ -42,9 +42,9 @@ gv100_fb = { }; int -gv100_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +gv100_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return gp102_fb_new_(&gv100_fb, device, index, pfb); + return gp102_fb_new_(&gv100_fb, device, type, inst, pfb); } MODULE_FIRMWARE("nvidia/gv100/nvdec/scrubber.bin"); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c index 73b3b86a2826..70c7b08ee0a6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c @@ -31,7 +31,7 @@ mcp77_fb = { }; int -mcp77_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +mcp77_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nv50_fb_new_(&mcp77_fb, device, index, pfb); + return nv50_fb_new_(&mcp77_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c index 6d11e32ec7ad..308d955168e8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c @@ -31,7 +31,7 @@ mcp89_fb = { }; int -mcp89_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +mcp89_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nv50_fb_new_(&mcp89_fb, device, index, pfb); + return nv50_fb_new_(&mcp89_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c index c886664533c8..8d5a007ecc47 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c @@ -44,7 +44,7 @@ nv04_fb = { }; int -nv04_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv04_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv04_fb, device, index, pfb); + return nvkm_fb_new_(&nv04_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c index c998b7e96aa3..7d2c16b27032 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c @@ -64,7 +64,7 @@ nv10_fb = { }; int -nv10_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv10_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv10_fb, device, index, pfb); + return nvkm_fb_new_(&nv10_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c index 7b9f04f44af8..4bdad2abd56f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c @@ -36,7 +36,7 @@ nv1a_fb = { }; int -nv1a_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv1a_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv1a_fb, device, index, pfb); + return nvkm_fb_new_(&nv1a_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c index a021d21ff153..d254f27f9b37 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c @@ -45,7 +45,7 @@ nv20_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / fb->ram->parts, 0x40); - if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */ else tile->zcomp = 0x04000000; /* Z24S8 */ tile->zcomp |= tile->tag->offset; @@ -63,7 +63,7 @@ nv20_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) tile->limit = 0; tile->pitch = 0; tile->zcomp = 0; - nvkm_mm_free(&fb->tags, &tile->tag); + nvkm_mm_free(&fb->tags.mm, &tile->tag); } void @@ -96,7 +96,7 @@ nv20_fb = { }; int -nv20_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv20_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv20_fb, device, index, pfb); + return nvkm_fb_new_(&nv20_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c index 7709f5fe9a45..47da66dea6e6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c @@ -32,7 +32,7 @@ nv25_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / fb->ram->parts, 0x40); - if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */ else tile->zcomp = 0x00200000; /* Z24S8 */ tile->zcomp |= tile->tag->offset; @@ -54,7 +54,7 @@ nv25_fb = { }; int -nv25_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv25_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv25_fb, device, index, pfb); + return nvkm_fb_new_(&nv25_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c index 8aa782666507..0f87efb636d5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c @@ -51,7 +51,7 @@ nv30_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / fb->ram->parts, 0x40); - if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { if (flags & 2) tile->zcomp |= 0x01000000; /* Z16 */ else tile->zcomp |= 0x02000000; /* Z24S8 */ tile->zcomp |= ((tile->tag->offset ) >> 6); @@ -127,7 +127,7 @@ nv30_fb = { }; int -nv30_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv30_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv30_fb, device, index, pfb); + return nvkm_fb_new_(&nv30_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c index 6e83dcff72e0..0694dcfd107e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c @@ -32,7 +32,7 @@ nv35_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / fb->ram->parts, 0x40); - if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */ else tile->zcomp |= 0x08000000; /* Z24S8 */ tile->zcomp |= ((tile->tag->offset ) >> 6); @@ -56,7 +56,7 @@ nv35_fb = { }; int -nv35_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv35_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv35_fb, device, index, pfb); + return nvkm_fb_new_(&nv35_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c index 2a07617bb44c..1a39770372f1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c @@ -32,7 +32,7 @@ nv36_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / fb->ram->parts, 0x40); - if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */ else tile->zcomp |= 0x20000000; /* Z24S8 */ tile->zcomp |= ((tile->tag->offset ) >> 6); @@ -56,7 +56,7 @@ nv36_fb = { }; int -nv36_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv36_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv36_fb, device, index, pfb); + return nvkm_fb_new_(&nv36_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c index 955160778b5b..77dbb9d6ba48 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c @@ -33,7 +33,7 @@ nv40_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, u32 tiles = DIV_ROUND_UP(size, 0x80); u32 tags = round_up(tiles / fb->ram->parts, 0x100); if ( (flags & 2) && - !nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + !nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ tile->zcomp |= ((tile->tag->offset ) >> 8); tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13; @@ -62,7 +62,7 @@ nv40_fb = { }; int -nv40_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv40_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv40_fb, device, index, pfb); + return nvkm_fb_new_(&nv40_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c index b77f08d34cc3..0f9d9e48e7ad 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c @@ -56,7 +56,7 @@ nv41_fb = { }; int -nv41_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv41_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv41_fb, device, index, pfb); + return nvkm_fb_new_(&nv41_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c index b59dc486083d..b1046ee9f0ea 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c @@ -65,7 +65,7 @@ nv44_fb = { }; int -nv44_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv44_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv44_fb, device, index, pfb); + return nvkm_fb_new_(&nv44_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c index cab7d20fa039..0d78de422dfa 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c @@ -51,7 +51,7 @@ nv46_fb = { }; int -nv46_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv46_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv46_fb, device, index, pfb); + return nvkm_fb_new_(&nv46_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c index a8b0ad4c871d..5cedde29c8ee 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c @@ -39,7 +39,7 @@ nv47_fb = { }; int -nv47_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv47_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv47_fb, device, index, pfb); + return nvkm_fb_new_(&nv47_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c index d0b317bb0252..95cc099603d8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c @@ -39,7 +39,7 @@ nv49_fb = { }; int -nv49_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv49_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv49_fb, device, index, pfb); + return nvkm_fb_new_(&nv49_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c index 6a6f0c086071..c9f3148f4e75 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c @@ -37,7 +37,7 @@ nv4e_fb = { }; int -nv4e_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv4e_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nvkm_fb_new_(&nv4e_fb, device, index, pfb); + return nvkm_fb_new_(&nv4e_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c index b2f5bf8144ea..95fd8f834010 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c @@ -262,16 +262,15 @@ nv50_fb_ = { int nv50_fb_new_(const struct nv50_fb_func *func, struct nvkm_device *device, - int index, struct nvkm_fb **pfb) + enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { struct nv50_fb *fb; if (!(fb = kzalloc(sizeof(*fb), GFP_KERNEL))) return -ENOMEM; - nvkm_fb_ctor(&nv50_fb_, device, index, &fb->base); + nvkm_fb_ctor(&nv50_fb_, device, type, inst, &fb->base); fb->func = func; *pfb = &fb->base; - return 0; } @@ -283,7 +282,7 @@ nv50_fb = { }; int -nv50_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +nv50_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb) { - return nv50_fb_new_(&nv50_fb, device, index, pfb); + return nv50_fb_new_(&nv50_fb, device, type, inst, pfb); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h index 5e2b0c9539ed..a5e673859a90 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h @@ -17,6 +17,6 @@ struct nv50_fb_func { u32 trap; }; -int nv50_fb_new_(const struct nv50_fb_func *, struct nvkm_device *, int index, +int nv50_fb_new_(const struct nv50_fb_func *, struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_fb **pfb); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h index 66932ac10d15..3f1be9780c65 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h @@ -38,9 +38,9 @@ struct nvkm_fb_func { }; void nvkm_fb_ctor(const struct nvkm_fb_func *, struct nvkm_device *device, - int index, struct nvkm_fb *); + enum nvkm_subdev_type type, int inst, struct nvkm_fb *); int nvkm_fb_new_(const struct nvkm_fb_func *, struct nvkm_device *device, - int index, struct nvkm_fb **); + enum nvkm_subdev_type type, int inst, struct nvkm_fb **); int nvkm_fb_bios_memtype(struct nvkm_bios *); void nv10_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size, @@ -78,7 +78,7 @@ int gm200_fb_init_page(struct nvkm_fb *); void gp100_fb_init_remapper(struct nvkm_fb *); void gp100_fb_init_unkn(struct nvkm_fb *); -int gp102_fb_new_(const struct nvkm_fb_func *, struct nvkm_device *, int, +int gp102_fb_new_(const struct nvkm_fb_func *, struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_fb **); bool gp102_fb_vpr_scrub_required(struct nvkm_fb *); int gp102_fb_vpr_scrub(struct nvkm_fb *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.c index b11867f682cb..03b1bdb27770 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.c @@ -81,12 +81,12 @@ nvkm_vram_dtor(struct nvkm_memory *memory) struct nvkm_vram *vram = nvkm_vram(memory); struct nvkm_mm_node *next = vram->mn; struct nvkm_mm_node *node; - mutex_lock(&vram->ram->fb->subdev.mutex); + mutex_lock(&vram->ram->mutex); while ((node = next)) { next = node->next; nvkm_mm_free(&vram->ram->vram, &node); } - mutex_unlock(&vram->ram->fb->subdev.mutex); + mutex_unlock(&vram->ram->mutex); return vram; } @@ -126,7 +126,7 @@ nvkm_ram_get(struct nvkm_device *device, u8 heap, u8 type, u8 rpage, u64 size, vram->page = page; *pmemory = &vram->memory; - mutex_lock(&ram->fb->subdev.mutex); + mutex_lock(&ram->mutex); node = &vram->mn; do { if (back) @@ -134,7 +134,7 @@ nvkm_ram_get(struct nvkm_device *device, u8 heap, u8 type, u8 rpage, u64 size, else ret = nvkm_mm_head(mm, heap, type, max, min, align, &r); if (ret) { - mutex_unlock(&ram->fb->subdev.mutex); + mutex_unlock(&ram->mutex); nvkm_memory_unref(pmemory); return ret; } @@ -143,7 +143,7 @@ nvkm_ram_get(struct nvkm_device *device, u8 heap, u8 type, u8 rpage, u64 size, node = &r->next; max -= r->length; } while (max); - mutex_unlock(&ram->fb->subdev.mutex); + mutex_unlock(&ram->mutex); return 0; } @@ -163,6 +163,7 @@ nvkm_ram_del(struct nvkm_ram **pram) if (ram->func->dtor) *pram = ram->func->dtor(ram); nvkm_mm_fini(&ram->vram); + mutex_destroy(&ram->mutex); kfree(*pram); *pram = NULL; } @@ -196,6 +197,7 @@ nvkm_ram_ctor(const struct nvkm_ram_func *func, struct nvkm_fb *fb, ram->fb = fb; ram->type = type; ram->size = size; + mutex_init(&ram->mutex); if (!nvkm_mm_initialised(&ram->vram)) { ret = nvkm_mm_init(&ram->vram, NVKM_RAM_MM_NORMAL, 0, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c index d350d92852d2..2b678b60b4d3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c @@ -260,7 +260,7 @@ gk104_ram_calc_gddr5(struct gk104_ram *ram, u32 freq) ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); ram_block(fuc); - if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP)) + if (ram->base.fb->subdev.device->disp) ram_wr32(fuc, 0x62c000, 0x0f0f0000); /* MR1: turn termination on early, for some reason.. */ @@ -661,7 +661,7 @@ gk104_ram_calc_gddr5(struct gk104_ram *ram, u32 freq) ram_unblock(fuc); - if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP)) + if (ram->base.fb->subdev.device->disp) ram_wr32(fuc, 0x62c000, 0x0f0f0f00); if (next->bios.rammap_11_08_01) @@ -711,7 +711,7 @@ gk104_ram_calc_sddr3(struct gk104_ram *ram, u32 freq) ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); ram_block(fuc); - if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP)) + if (ram->base.fb->subdev.device->disp) ram_wr32(fuc, 0x62c000, 0x0f0f0000); if (vc == 1 && ram_have(fuc, gpio2E)) { @@ -943,7 +943,7 @@ gk104_ram_calc_sddr3(struct gk104_ram *ram, u32 freq) ram_unblock(fuc); - if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP)) + if (ram->base.fb->subdev.device->disp) ram_wr32(fuc, 0x62c000, 0x0f0f0f00); if (next->bios.rammap_11_08_01) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c index 1c3c18ea8ced..375dfce09f84 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c @@ -42,12 +42,12 @@ nvkm_fuse = { int nvkm_fuse_new_(const struct nvkm_fuse_func *func, struct nvkm_device *device, - int index, struct nvkm_fuse **pfuse) + enum nvkm_subdev_type type, int inst, struct nvkm_fuse **pfuse) { struct nvkm_fuse *fuse; if (!(fuse = *pfuse = kzalloc(sizeof(*fuse), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_fuse, device, index, &fuse->subdev); + nvkm_subdev_ctor(&nvkm_fuse, device, type, inst, &fuse->subdev); fuse->func = func; spin_lock_init(&fuse->lock); return 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c index 13671fedc805..01f770654b1d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c @@ -47,7 +47,8 @@ gf100_fuse = { }; int -gf100_fuse_new(struct nvkm_device *device, int index, struct nvkm_fuse **pfuse) +gf100_fuse_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fuse **pfuse) { - return nvkm_fuse_new_(&gf100_fuse, device, index, pfuse); + return nvkm_fuse_new_(&gf100_fuse, device, type, inst, pfuse); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c index 9aff4ea04506..7dc99492f536 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c @@ -36,7 +36,8 @@ gm107_fuse = { }; int -gm107_fuse_new(struct nvkm_device *device, int index, struct nvkm_fuse **pfuse) +gm107_fuse_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fuse **pfuse) { - return nvkm_fuse_new_(&gm107_fuse, device, index, pfuse); + return nvkm_fuse_new_(&gm107_fuse, device, type, inst, pfuse); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c index 514c193db25d..2505e8e1c1d3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c @@ -45,7 +45,8 @@ nv50_fuse = { }; int -nv50_fuse_new(struct nvkm_device *device, int index, struct nvkm_fuse **pfuse) +nv50_fuse_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_fuse **pfuse) { - return nvkm_fuse_new_(&nv50_fuse, device, index, pfuse); + return nvkm_fuse_new_(&nv50_fuse, device, type, inst, pfuse); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/priv.h index 2edc612408dd..e83d0c30dff6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/priv.h @@ -8,6 +8,6 @@ struct nvkm_fuse_func { u32 (*read)(struct nvkm_fuse *, u32 addr); }; -int nvkm_fuse_new_(const struct nvkm_fuse_func *, struct nvkm_device *, - int index, struct nvkm_fuse **); +int nvkm_fuse_new_(const struct nvkm_fuse_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_fuse **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c index 914276410ef8..048bcc70c3f4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c @@ -241,14 +241,14 @@ nvkm_gpio = { int nvkm_gpio_new_(const struct nvkm_gpio_func *func, struct nvkm_device *device, - int index, struct nvkm_gpio **pgpio) + enum nvkm_subdev_type type, int inst, struct nvkm_gpio **pgpio) { struct nvkm_gpio *gpio; if (!(gpio = *pgpio = kzalloc(sizeof(*gpio), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_gpio, device, index, &gpio->subdev); + nvkm_subdev_ctor(&nvkm_gpio, device, type, inst, &gpio->subdev); gpio->func = func; return nvkm_event_init(&nvkm_gpio_intr_func, 2, func->lines, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c index 6dcda55fb865..114728ccdf8e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c @@ -68,7 +68,8 @@ g94_gpio = { }; int -g94_gpio_new(struct nvkm_device *device, int index, struct nvkm_gpio **pgpio) +g94_gpio_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_gpio **pgpio) { - return nvkm_gpio_new_(&g94_gpio, device, index, pgpio); + return nvkm_gpio_new_(&g94_gpio, device, type, inst, pgpio); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ga102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ga102.c index 62c791baf400..4a96f926b66d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ga102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ga102.c @@ -112,7 +112,8 @@ ga102_gpio = { }; int -ga102_gpio_new(struct nvkm_device *device, int index, struct nvkm_gpio **pgpio) +ga102_gpio_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_gpio **pgpio) { - return nvkm_gpio_new_(&ga102_gpio, device, index, pgpio); + return nvkm_gpio_new_(&ga102_gpio, device, type, inst, pgpio); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf119.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf119.c index bb7400dfaef8..ecb19e4f5c48 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf119.c @@ -80,7 +80,8 @@ gf119_gpio = { }; int -gf119_gpio_new(struct nvkm_device *device, int index, struct nvkm_gpio **pgpio) +gf119_gpio_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_gpio **pgpio) { - return nvkm_gpio_new_(&gf119_gpio, device, index, pgpio); + return nvkm_gpio_new_(&gf119_gpio, device, type, inst, pgpio); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c index 2ead515b8530..c0e4cdb45520 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c @@ -68,7 +68,8 @@ gk104_gpio = { }; int -gk104_gpio_new(struct nvkm_device *device, int index, struct nvkm_gpio **pgpio) +gk104_gpio_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_gpio **pgpio) { - return nvkm_gpio_new_(&gk104_gpio, device, index, pgpio); + return nvkm_gpio_new_(&gk104_gpio, device, type, inst, pgpio); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c index ae3499b48330..48ad29b5638f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c @@ -112,7 +112,8 @@ nv10_gpio = { }; int -nv10_gpio_new(struct nvkm_device *device, int index, struct nvkm_gpio **pgpio) +nv10_gpio_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_gpio **pgpio) { - return nvkm_gpio_new_(&nv10_gpio, device, index, pgpio); + return nvkm_gpio_new_(&nv10_gpio, device, type, inst, pgpio); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c index 73923fd5f7f2..b86c49762f11 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c @@ -126,7 +126,8 @@ nv50_gpio = { }; int -nv50_gpio_new(struct nvkm_device *device, int index, struct nvkm_gpio **pgpio) +nv50_gpio_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_gpio **pgpio) { - return nvkm_gpio_new_(&nv50_gpio, device, index, pgpio); + return nvkm_gpio_new_(&nv50_gpio, device, type, inst, pgpio); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/priv.h index 59e39affe2a0..6590d81164e7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/priv.h @@ -28,8 +28,8 @@ struct nvkm_gpio_func { void (*reset)(struct nvkm_gpio *, u8); }; -int nvkm_gpio_new_(const struct nvkm_gpio_func *, struct nvkm_device *, - int index, struct nvkm_gpio **); +int nvkm_gpio_new_(const struct nvkm_gpio_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_gpio **); void nv50_gpio_reset(struct nvkm_gpio *, u8); int nv50_gpio_drive(struct nvkm_gpio *, int, int, int); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c index 5a32df0f9992..22574886b819 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c @@ -40,20 +40,18 @@ nvkm_gsp = { int nvkm_gsp_new_(const struct nvkm_gsp_fwif *fwif, struct nvkm_device *device, - int index, struct nvkm_gsp **pgsp) + enum nvkm_subdev_type type, int inst, struct nvkm_gsp **pgsp) { struct nvkm_gsp *gsp; if (!(gsp = *pgsp = kzalloc(sizeof(*gsp), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_gsp, device, index, &gsp->subdev); + nvkm_subdev_ctor(&nvkm_gsp, device, type, inst, &gsp->subdev); fwif = nvkm_firmware_load(&gsp->subdev, fwif, "Gsp", gsp); if (IS_ERR(fwif)) return PTR_ERR(fwif); - return nvkm_falcon_ctor(fwif->flcn, &gsp->subdev, - nvkm_subdev_name[gsp->subdev.index], 0, - &gsp->falcon); + return nvkm_falcon_ctor(fwif->flcn, &gsp->subdev, gsp->subdev.name, 0, &gsp->falcon); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.c index 2114f9b00a28..2ac7fc934c09 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.c @@ -49,7 +49,8 @@ gv100_gsp[] = { }; int -gv100_gsp_new(struct nvkm_device *device, int index, struct nvkm_gsp **pgsp) +gv100_gsp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_gsp **pgsp) { - return nvkm_gsp_new_(gv100_gsp, device, index, pgsp); + return nvkm_gsp_new_(gv100_gsp, device, type, inst, pgsp); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/priv.h index 92820fb997c1..19381ddd38d4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/priv.h @@ -10,6 +10,6 @@ struct nvkm_gsp_fwif { const struct nvkm_falcon_func *flcn; }; -int nvkm_gsp_new_(const struct nvkm_gsp_fwif *, struct nvkm_device *, int, +int nvkm_gsp_new_(const struct nvkm_gsp_fwif *, struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c index 719345074711..cb5cb533d91c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c @@ -277,7 +277,7 @@ nvkm_i2c_drv[] = { int nvkm_i2c_new_(const struct nvkm_i2c_func *func, struct nvkm_device *device, - int index, struct nvkm_i2c **pi2c) + enum nvkm_subdev_type type, int inst, struct nvkm_i2c **pi2c) { struct nvkm_bios *bios = device->bios; struct nvkm_i2c *i2c; @@ -289,7 +289,7 @@ nvkm_i2c_new_(const struct nvkm_i2c_func *func, struct nvkm_device *device, if (!(i2c = *pi2c = kzalloc(sizeof(*i2c), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_i2c, device, index, &i2c->subdev); + nvkm_subdev_ctor(&nvkm_i2c, device, type, inst, &i2c->subdev); i2c->func = func; INIT_LIST_HEAD(&i2c->pad); INIT_LIST_HEAD(&i2c->bus); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.c index bb2a31d88161..e5bad085c06f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.c @@ -66,7 +66,8 @@ g94_i2c = { }; int -g94_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c) +g94_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_i2c **pi2c) { - return nvkm_i2c_new_(&g94_i2c, device, index, pi2c); + return nvkm_i2c_new_(&g94_i2c, device, type, inst, pi2c); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.c index ae4aad3fcd2e..cda30ee6767d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.c @@ -30,7 +30,8 @@ gf117_i2c = { }; int -gf117_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c) +gf117_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_i2c **pi2c) { - return nvkm_i2c_new_(&gf117_i2c, device, index, pi2c); + return nvkm_i2c_new_(&gf117_i2c, device, type, inst, pi2c); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf119.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf119.c index 6f2b02af42c8..e9c6a6cca09d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf119.c @@ -34,7 +34,8 @@ gf119_i2c = { }; int -gf119_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c) +gf119_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_i2c **pi2c) { - return nvkm_i2c_new_(&gf119_i2c, device, index, pi2c); + return nvkm_i2c_new_(&gf119_i2c, device, type, inst, pi2c); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.c index f9f6bf4b66c9..d35aa6fe3015 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.c @@ -66,7 +66,8 @@ gk104_i2c = { }; int -gk104_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c) +gk104_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_i2c **pi2c) { - return nvkm_i2c_new_(&gk104_i2c, device, index, pi2c); + return nvkm_i2c_new_(&gk104_i2c, device, type, inst, pi2c); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk110.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk110.c index 8e3bfa1af52a..9fec6af56e07 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk110.c @@ -39,7 +39,8 @@ gk110_i2c = { }; int -gk110_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c) +gk110_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_i2c **pi2c) { - return nvkm_i2c_new_(&gk110_i2c, device, index, pi2c); + return nvkm_i2c_new_(&gk110_i2c, device, type, inst, pi2c); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm200.c index 7b2375bff8a9..46917eb600f9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm200.c @@ -41,7 +41,8 @@ gm200_i2c = { }; int -gm200_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c) +gm200_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_i2c **pi2c) { - return nvkm_i2c_new_(&gm200_i2c, device, index, pi2c); + return nvkm_i2c_new_(&gm200_i2c, device, type, inst, pi2c); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.c index 18776f49355c..ecfcf147c789 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.c @@ -30,7 +30,8 @@ nv04_i2c = { }; int -nv04_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c) +nv04_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_i2c **pi2c) { - return nvkm_i2c_new_(&nv04_i2c, device, index, pi2c); + return nvkm_i2c_new_(&nv04_i2c, device, type, inst, pi2c); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.c index 6b762f7cee9e..ad1d3fd2bcbc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.c @@ -30,7 +30,8 @@ nv4e_i2c = { }; int -nv4e_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c) +nv4e_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_i2c **pi2c) { - return nvkm_i2c_new_(&nv4e_i2c, device, index, pi2c); + return nvkm_i2c_new_(&nv4e_i2c, device, type, inst, pi2c); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.c index 75640ab97d6a..2f94bed2c056 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.c @@ -30,7 +30,8 @@ nv50_i2c = { }; int -nv50_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c) +nv50_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_i2c **pi2c) { - return nvkm_i2c_new_(&nv50_i2c, device, index, pi2c); + return nvkm_i2c_new_(&nv50_i2c, device, type, inst, pi2c); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h index e35f6036fcfc..f9d79f72f7e7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h @@ -4,8 +4,8 @@ #define nvkm_i2c(p) container_of((p), struct nvkm_i2c, subdev) #include <subdev/i2c.h> -int nvkm_i2c_new_(const struct nvkm_i2c_func *, struct nvkm_device *, - int index, struct nvkm_i2c **); +int nvkm_i2c_new_(const struct nvkm_i2c_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_i2c **); struct nvkm_i2c_func { int (*pad_x_new)(struct nvkm_i2c *, int id, struct nvkm_i2c_pad **); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild deleted file mode 100644 index 127efb51f67d..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: MIT -nvkm-y += nvkm/subdev/ibus/gf100.o -nvkm-y += nvkm/subdev/ibus/gf117.o -nvkm-y += nvkm/subdev/ibus/gk104.o -nvkm-y += nvkm/subdev/ibus/gk20a.o -nvkm-y += nvkm/subdev/ibus/gm200.o -nvkm-y += nvkm/subdev/ibus/gp10b.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/priv.h deleted file mode 100644 index 302d69e384d8..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/priv.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef __NVKM_IBUS_PRIV_H__ -#define __NVKM_IBUS_PRIV_H__ - -#include <subdev/ibus.h> - -void gf100_ibus_intr(struct nvkm_subdev *); -void gk104_ibus_intr(struct nvkm_subdev *); -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.c index fecfa6afcf54..8f0ccd3664eb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.c @@ -312,20 +312,20 @@ iccsense_func = { }; void -nvkm_iccsense_ctor(struct nvkm_device *device, int index, +nvkm_iccsense_ctor(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_iccsense *iccsense) { - nvkm_subdev_ctor(&iccsense_func, device, index, &iccsense->subdev); + nvkm_subdev_ctor(&iccsense_func, device, type, inst, &iccsense->subdev); } int -nvkm_iccsense_new_(struct nvkm_device *device, int index, +nvkm_iccsense_new_(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_iccsense **iccsense) { if (!(*iccsense = kzalloc(sizeof(**iccsense), GFP_KERNEL))) return -ENOMEM; INIT_LIST_HEAD(&(*iccsense)->sensors); INIT_LIST_HEAD(&(*iccsense)->rails); - nvkm_iccsense_ctor(device, index, *iccsense); + nvkm_iccsense_ctor(device, type, inst, *iccsense); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/gf100.c index cccff1c8a409..3eabf4944395 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/gf100.c @@ -24,8 +24,8 @@ #include "priv.h" int -gf100_iccsense_new(struct nvkm_device *device, int index, +gf100_iccsense_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_iccsense **piccsense) { - return nvkm_iccsense_new_(device, index, piccsense); + return nvkm_iccsense_new_(device, type, inst, piccsense); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/priv.h index cc09c6c504af..c33441124241 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/priv.h @@ -22,6 +22,6 @@ struct nvkm_iccsense_rail { u8 mohm; }; -void nvkm_iccsense_ctor(struct nvkm_device *, int, struct nvkm_iccsense *); -int nvkm_iccsense_new_(struct nvkm_device *, int, struct nvkm_iccsense **); +void nvkm_iccsense_ctor(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_iccsense *); +int nvkm_iccsense_new_(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_iccsense **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c index 364ea4492acc..cd8163a52bb6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c @@ -218,9 +218,11 @@ static void * nvkm_instmem_dtor(struct nvkm_subdev *subdev) { struct nvkm_instmem *imem = nvkm_instmem(subdev); + void *data = imem; if (imem->func->dtor) - return imem->func->dtor(imem); - return imem; + data = imem->func->dtor(imem); + mutex_destroy(&imem->mutex); + return data; } static const struct nvkm_subdev_func @@ -232,13 +234,13 @@ nvkm_instmem = { }; void -nvkm_instmem_ctor(const struct nvkm_instmem_func *func, - struct nvkm_device *device, int index, - struct nvkm_instmem *imem) +nvkm_instmem_ctor(const struct nvkm_instmem_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, struct nvkm_instmem *imem) { - nvkm_subdev_ctor(&nvkm_instmem, device, index, &imem->subdev); + nvkm_subdev_ctor(&nvkm_instmem, device, type, inst, &imem->subdev); imem->func = func; spin_lock_init(&imem->lock); INIT_LIST_HEAD(&imem->list); INIT_LIST_HEAD(&imem->boot); + mutex_init(&imem->mutex); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c index 13d4d7ac0697..648ecf5a8fbc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c @@ -568,7 +568,7 @@ gk20a_instmem = { }; int -gk20a_instmem_new(struct nvkm_device *device, int index, +gk20a_instmem_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_instmem **pimem) { struct nvkm_device_tegra *tdev = device->func->tegra(device); @@ -576,7 +576,7 @@ gk20a_instmem_new(struct nvkm_device *device, int index, if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL))) return -ENOMEM; - nvkm_instmem_ctor(&gk20a_instmem, device, index, &imem->base); + nvkm_instmem_ctor(&gk20a_instmem, device, type, inst, &imem->base); mutex_init(&imem->lock); *pimem = &imem->base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c index 6bf0dad46919..25603b01d6f8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c @@ -99,9 +99,9 @@ static void * nv04_instobj_dtor(struct nvkm_memory *memory) { struct nv04_instobj *iobj = nv04_instobj(memory); - mutex_lock(&iobj->imem->base.subdev.mutex); + mutex_lock(&iobj->imem->base.mutex); nvkm_mm_free(&iobj->imem->heap, &iobj->node); - mutex_unlock(&iobj->imem->base.subdev.mutex); + mutex_unlock(&iobj->imem->base.mutex); nvkm_instobj_dtor(&iobj->imem->base, &iobj->base); return iobj; } @@ -132,10 +132,9 @@ nv04_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, iobj->base.memory.ptrs = &nv04_instobj_ptrs; iobj->imem = imem; - mutex_lock(&imem->base.subdev.mutex); - ret = nvkm_mm_head(&imem->heap, 0, 1, size, size, - align ? align : 1, &iobj->node); - mutex_unlock(&imem->base.subdev.mutex); + mutex_lock(&imem->base.mutex); + ret = nvkm_mm_head(&imem->heap, 0, 1, size, size, align ? align : 1, &iobj->node); + mutex_unlock(&imem->base.mutex); return ret; } @@ -218,14 +217,14 @@ nv04_instmem = { }; int -nv04_instmem_new(struct nvkm_device *device, int index, +nv04_instmem_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_instmem **pimem) { struct nv04_instmem *imem; if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL))) return -ENOMEM; - nvkm_instmem_ctor(&nv04_instmem, device, index, &imem->base); + nvkm_instmem_ctor(&nv04_instmem, device, type, inst, &imem->base); *pimem = &imem->base; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c index 086c118488ef..6b462f960922 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c @@ -99,9 +99,9 @@ static void * nv40_instobj_dtor(struct nvkm_memory *memory) { struct nv40_instobj *iobj = nv40_instobj(memory); - mutex_lock(&iobj->imem->base.subdev.mutex); + mutex_lock(&iobj->imem->base.mutex); nvkm_mm_free(&iobj->imem->heap, &iobj->node); - mutex_unlock(&iobj->imem->base.subdev.mutex); + mutex_unlock(&iobj->imem->base.mutex); nvkm_instobj_dtor(&iobj->imem->base, &iobj->base); return iobj; } @@ -132,10 +132,9 @@ nv40_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, iobj->base.memory.ptrs = &nv40_instobj_ptrs; iobj->imem = imem; - mutex_lock(&imem->base.subdev.mutex); - ret = nvkm_mm_head(&imem->heap, 0, 1, size, size, - align ? align : 1, &iobj->node); - mutex_unlock(&imem->base.subdev.mutex); + mutex_lock(&imem->base.mutex); + ret = nvkm_mm_head(&imem->heap, 0, 1, size, size, align ? align : 1, &iobj->node); + mutex_unlock(&imem->base.mutex); return ret; } @@ -236,7 +235,7 @@ nv40_instmem = { }; int -nv40_instmem_new(struct nvkm_device *device, int index, +nv40_instmem_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_instmem **pimem) { struct nv40_instmem *imem; @@ -244,7 +243,7 @@ nv40_instmem_new(struct nvkm_device *device, int index, if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL))) return -ENOMEM; - nvkm_instmem_ctor(&nv40_instmem, device, index, &imem->base); + nvkm_instmem_ctor(&nv40_instmem, device, type, inst, &imem->base); *pimem = &imem->base; /* map bar */ diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c index 02c4eb28cef4..96aca0edfa3c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c @@ -133,12 +133,12 @@ nv50_instobj_kmap(struct nv50_instobj *iobj, struct nvkm_vmm *vmm) * into it. The lock has to be dropped while doing this due * to the possibility of recursion for page table allocation. */ - mutex_unlock(&subdev->mutex); + mutex_unlock(&imem->base.mutex); while ((ret = nvkm_vmm_get(vmm, 12, size, &bar))) { /* Evict unused mappings, and keep retrying until we either * succeed,or there's no more objects left on the LRU. */ - mutex_lock(&subdev->mutex); + mutex_lock(&imem->base.mutex); eobj = list_first_entry_or_null(&imem->lru, typeof(*eobj), lru); if (eobj) { nvkm_debug(subdev, "evict %016llx %016llx @ %016llx\n", @@ -151,7 +151,7 @@ nv50_instobj_kmap(struct nv50_instobj *iobj, struct nvkm_vmm *vmm) emap = eobj->map; eobj->map = NULL; } - mutex_unlock(&subdev->mutex); + mutex_unlock(&imem->base.mutex); if (!eobj) break; iounmap(emap); @@ -160,12 +160,12 @@ nv50_instobj_kmap(struct nv50_instobj *iobj, struct nvkm_vmm *vmm) if (ret == 0) ret = nvkm_memory_map(memory, 0, vmm, bar, NULL, 0); - mutex_lock(&subdev->mutex); + mutex_lock(&imem->base.mutex); if (ret || iobj->bar) { /* We either failed, or another thread beat us. */ - mutex_unlock(&subdev->mutex); + mutex_unlock(&imem->base.mutex); nvkm_vmm_put(vmm, &bar); - mutex_lock(&subdev->mutex); + mutex_lock(&imem->base.mutex); return; } @@ -197,7 +197,7 @@ nv50_instobj_release(struct nvkm_memory *memory) wmb(); nvkm_bar_flush(subdev->device->bar); - if (refcount_dec_and_mutex_lock(&iobj->maps, &subdev->mutex)) { + if (refcount_dec_and_mutex_lock(&iobj->maps, &imem->base.mutex)) { /* Add the now-unused mapping to the LRU instead of directly * unmapping it here, in case we need to map it again later. */ @@ -208,7 +208,7 @@ nv50_instobj_release(struct nvkm_memory *memory) /* Switch back to NULL accessors when last map is gone. */ iobj->base.memory.ptrs = NULL; - mutex_unlock(&subdev->mutex); + mutex_unlock(&imem->base.mutex); } } @@ -227,9 +227,9 @@ nv50_instobj_acquire(struct nvkm_memory *memory) /* Take the lock, and re-check that another thread hasn't * already mapped the object in the meantime. */ - mutex_lock(&imem->subdev.mutex); + mutex_lock(&imem->mutex); if (refcount_inc_not_zero(&iobj->maps)) { - mutex_unlock(&imem->subdev.mutex); + mutex_unlock(&imem->mutex); return iobj->map; } @@ -252,7 +252,7 @@ nv50_instobj_acquire(struct nvkm_memory *memory) refcount_set(&iobj->maps, 1); } - mutex_unlock(&imem->subdev.mutex); + mutex_unlock(&imem->mutex); return map; } @@ -265,7 +265,7 @@ nv50_instobj_boot(struct nvkm_memory *memory, struct nvkm_vmm *vmm) /* Exclude bootstrapped objects (ie. the page tables for the * instmem BAR itself) from eviction. */ - mutex_lock(&imem->subdev.mutex); + mutex_lock(&imem->mutex); if (likely(iobj->lru.next)) { list_del_init(&iobj->lru); iobj->lru.next = NULL; @@ -273,7 +273,7 @@ nv50_instobj_boot(struct nvkm_memory *memory, struct nvkm_vmm *vmm) nv50_instobj_kmap(iobj, vmm); nvkm_instmem_boot(imem); - mutex_unlock(&imem->subdev.mutex); + mutex_unlock(&imem->mutex); } static u64 @@ -315,12 +315,12 @@ nv50_instobj_dtor(struct nvkm_memory *memory) struct nvkm_vma *bar; void *map = map; - mutex_lock(&imem->subdev.mutex); + mutex_lock(&imem->mutex); if (likely(iobj->lru.next)) list_del(&iobj->lru); map = iobj->map; bar = iobj->bar; - mutex_unlock(&imem->subdev.mutex); + mutex_unlock(&imem->mutex); if (map) { struct nvkm_vmm *vmm = nvkm_bar_bar2_vmm(imem->subdev.device); @@ -386,14 +386,14 @@ nv50_instmem = { }; int -nv50_instmem_new(struct nvkm_device *device, int index, +nv50_instmem_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_instmem **pimem) { struct nv50_instmem *imem; if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL))) return -ENOMEM; - nvkm_instmem_ctor(&nv50_instmem, device, index, &imem->base); + nvkm_instmem_ctor(&nv50_instmem, device, type, inst, &imem->base); INIT_LIST_HEAD(&imem->lru); *pimem = &imem->base; return 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h index f5da8fcbdde3..56c15e30a5dd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h @@ -16,7 +16,7 @@ struct nvkm_instmem_func { }; void nvkm_instmem_ctor(const struct nvkm_instmem_func *, struct nvkm_device *, - int index, struct nvkm_instmem *); + enum nvkm_subdev_type, int, struct nvkm_instmem *); void nvkm_instmem_boot(struct nvkm_instmem *); #include <core/memory.h> diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c index 23242179e600..fa683c190795 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c @@ -33,10 +33,10 @@ nvkm_ltc_tags_clear(struct nvkm_device *device, u32 first, u32 count) BUG_ON((first > limit) || (limit >= ltc->num_tags)); - mutex_lock(<c->subdev.mutex); + mutex_lock(<c->mutex); ltc->func->cbc_clear(ltc, first, limit); ltc->func->cbc_wait(ltc); - mutex_unlock(<c->subdev.mutex); + mutex_unlock(<c->mutex); } int @@ -113,6 +113,7 @@ nvkm_ltc_dtor(struct nvkm_subdev *subdev) { struct nvkm_ltc *ltc = nvkm_ltc(subdev); nvkm_memory_unref(<c->tag_ram); + mutex_destroy(<c->mutex); return ltc; } @@ -126,15 +127,16 @@ nvkm_ltc = { int nvkm_ltc_new_(const struct nvkm_ltc_func *func, struct nvkm_device *device, - int index, struct nvkm_ltc **pltc) + enum nvkm_subdev_type type, int inst, struct nvkm_ltc **pltc) { struct nvkm_ltc *ltc; if (!(ltc = *pltc = kzalloc(sizeof(*ltc), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_ltc, device, index, <c->subdev); + nvkm_subdev_ctor(&nvkm_ltc, device, type, inst, <c->subdev); ltc->func = func; + mutex_init(<c->mutex); ltc->zbc_min = 1; /* reserve 0 for disabled */ ltc->zbc_max = min(func->zbc, NVKM_LTC_MAX_ZBC_CNT) - 1; return 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c index a21ef45b8572..fd8aeafc812d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c @@ -200,8 +200,8 @@ gf100_ltc_oneinit_tag_ram(struct nvkm_ltc *ltc) } mm_init: - nvkm_mm_fini(&fb->tags); - return nvkm_mm_init(&fb->tags, 0, 0, ltc->num_tags, 1); + nvkm_mm_fini(&fb->tags.mm); + return nvkm_mm_init(&fb->tags.mm, 0, 0, ltc->num_tags, 1); } int @@ -249,7 +249,8 @@ gf100_ltc = { }; int -gf100_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc) +gf100_ltc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_ltc **pltc) { - return nvkm_ltc_new_(&gf100_ltc, device, index, pltc); + return nvkm_ltc_new_(&gf100_ltc, device, type, inst, pltc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c index b4f6e0034d58..94aa09244d67 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c @@ -50,7 +50,8 @@ gk104_ltc = { }; int -gk104_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc) +gk104_ltc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_ltc **pltc) { - return nvkm_ltc_new_(&gk104_ltc, device, index, pltc); + return nvkm_ltc_new_(&gk104_ltc, device, type, inst, pltc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c index ec0a3844b2d1..54d1d65d5a85 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c @@ -145,7 +145,8 @@ gm107_ltc = { }; int -gm107_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc) +gm107_ltc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_ltc **pltc) { - return nvkm_ltc_new_(&gm107_ltc, device, index, pltc); + return nvkm_ltc_new_(&gm107_ltc, device, type, inst, pltc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.c index e18e0dc19ec8..8cfdbbdd8e8d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.c @@ -57,7 +57,8 @@ gm200_ltc = { }; int -gm200_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc) +gm200_ltc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_ltc **pltc) { - return nvkm_ltc_new_(&gm200_ltc, device, index, pltc); + return nvkm_ltc_new_(&gm200_ltc, device, type, inst, pltc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.c index e923ed76d37a..a4a6cd9b435a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.c @@ -69,7 +69,8 @@ gp100_ltc = { }; int -gp100_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc) +gp100_ltc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_ltc **pltc) { - return nvkm_ltc_new_(&gp100_ltc, device, index, pltc); + return nvkm_ltc_new_(&gp100_ltc, device, type, inst, pltc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp102.c index 601747ada655..ff05d617e7f4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp102.c @@ -45,7 +45,8 @@ gp102_ltc = { }; int -gp102_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc) +gp102_ltc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_ltc **pltc) { - return nvkm_ltc_new_(&gp102_ltc, device, index, pltc); + return nvkm_ltc_new_(&gp102_ltc, device, type, inst, pltc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c index c0063c7caa50..dfebd796cb4b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c @@ -59,7 +59,8 @@ gp10b_ltc = { }; int -gp10b_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc) +gp10b_ltc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_ltc **pltc) { - return nvkm_ltc_new_(&gp10b_ltc, device, index, pltc); + return nvkm_ltc_new_(&gp10b_ltc, device, type, inst, pltc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h index eca5a711b1b8..2bebe139005d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h @@ -5,8 +5,8 @@ #include <subdev/ltc.h> #include <core/enum.h> -int nvkm_ltc_new_(const struct nvkm_ltc_func *, struct nvkm_device *, - int index, struct nvkm_ltc **); +int nvkm_ltc_new_(const struct nvkm_ltc_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_ltc **); struct nvkm_ltc_func { int (*oneinit)(struct nvkm_ltc *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c index 09f669ac6630..21c4af3f81d5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c @@ -35,14 +35,14 @@ nvkm_mc_unk260(struct nvkm_device *device, u32 data) } void -nvkm_mc_intr_mask(struct nvkm_device *device, enum nvkm_devidx devidx, bool en) +nvkm_mc_intr_mask(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, bool en) { struct nvkm_mc *mc = device->mc; const struct nvkm_mc_map *map; if (likely(mc) && mc->func->intr_mask) { - u32 mask = nvkm_top_intr_mask(device, devidx); + u32 mask = nvkm_top_intr_mask(device, type, inst); for (map = mc->func->intr; !mask && map->stat; map++) { - if (map->unit == devidx) + if (map->type == type && map->inst == inst) mask = map->stat; } mc->func->intr_mask(mc, mask, en ? mask : 0); @@ -78,27 +78,34 @@ void nvkm_mc_intr(struct nvkm_device *device, bool *handled) { struct nvkm_mc *mc = device->mc; + struct nvkm_top *top = device->top; + struct nvkm_top_device *tdev; struct nvkm_subdev *subdev; const struct nvkm_mc_map *map; u32 stat, intr; - u64 subdevs; if (unlikely(!mc)) return; - intr = nvkm_mc_intr_stat(mc); - stat = nvkm_top_intr(device, intr, &subdevs); - while (subdevs) { - enum nvkm_devidx subidx = __ffs64(subdevs); - subdev = nvkm_device_subdev(device, subidx); - if (subdev) - nvkm_subdev_intr(subdev); - subdevs &= ~BIT_ULL(subidx); + stat = intr = nvkm_mc_intr_stat(mc); + + if (top) { + list_for_each_entry(tdev, &top->device, head) { + if (tdev->intr >= 0 && (stat & BIT(tdev->intr))) { + subdev = nvkm_device_subdev(device, tdev->type, tdev->inst); + if (subdev) { + nvkm_subdev_intr(subdev); + stat &= ~BIT(tdev->intr); + if (!stat) + break; + } + } + } } for (map = mc->func->intr; map->stat; map++) { if (intr & map->stat) { - subdev = nvkm_device_subdev(device, map->unit); + subdev = nvkm_device_subdev(device, map->type, map->inst); if (subdev) nvkm_subdev_intr(subdev); stat &= ~map->stat; @@ -111,17 +118,16 @@ nvkm_mc_intr(struct nvkm_device *device, bool *handled) } static u32 -nvkm_mc_reset_mask(struct nvkm_device *device, bool isauto, - enum nvkm_devidx devidx) +nvkm_mc_reset_mask(struct nvkm_device *device, bool isauto, enum nvkm_subdev_type type, int inst) { struct nvkm_mc *mc = device->mc; const struct nvkm_mc_map *map; u64 pmc_enable = 0; if (likely(mc)) { - if (!(pmc_enable = nvkm_top_reset(device, devidx))) { + if (!(pmc_enable = nvkm_top_reset(device, type, inst))) { for (map = mc->func->reset; map && map->stat; map++) { if (!isauto || !map->noauto) { - if (map->unit == devidx) { + if (map->type == type && map->inst == inst) { pmc_enable = map->stat; break; } @@ -133,9 +139,9 @@ nvkm_mc_reset_mask(struct nvkm_device *device, bool isauto, } void -nvkm_mc_reset(struct nvkm_device *device, enum nvkm_devidx devidx) +nvkm_mc_reset(struct nvkm_device *device, enum nvkm_subdev_type type, int inst) { - u64 pmc_enable = nvkm_mc_reset_mask(device, true, devidx); + u64 pmc_enable = nvkm_mc_reset_mask(device, true, type, inst); if (pmc_enable) { nvkm_mask(device, 0x000200, pmc_enable, 0x00000000); nvkm_mask(device, 0x000200, pmc_enable, pmc_enable); @@ -144,17 +150,17 @@ nvkm_mc_reset(struct nvkm_device *device, enum nvkm_devidx devidx) } void -nvkm_mc_disable(struct nvkm_device *device, enum nvkm_devidx devidx) +nvkm_mc_disable(struct nvkm_device *device, enum nvkm_subdev_type type, int inst) { - u64 pmc_enable = nvkm_mc_reset_mask(device, false, devidx); + u64 pmc_enable = nvkm_mc_reset_mask(device, false, type, inst); if (pmc_enable) nvkm_mask(device, 0x000200, pmc_enable, 0x00000000); } void -nvkm_mc_enable(struct nvkm_device *device, enum nvkm_devidx devidx) +nvkm_mc_enable(struct nvkm_device *device, enum nvkm_subdev_type type, int inst) { - u64 pmc_enable = nvkm_mc_reset_mask(device, false, devidx); + u64 pmc_enable = nvkm_mc_reset_mask(device, false, type, inst); if (pmc_enable) { nvkm_mask(device, 0x000200, pmc_enable, pmc_enable); nvkm_rd32(device, 0x000200); @@ -162,9 +168,9 @@ nvkm_mc_enable(struct nvkm_device *device, enum nvkm_devidx devidx) } bool -nvkm_mc_enabled(struct nvkm_device *device, enum nvkm_devidx devidx) +nvkm_mc_enabled(struct nvkm_device *device, enum nvkm_subdev_type type, int inst) { - u64 pmc_enable = nvkm_mc_reset_mask(device, false, devidx); + u64 pmc_enable = nvkm_mc_reset_mask(device, false, type, inst); return (pmc_enable != 0) && ((nvkm_rd32(device, 0x000200) & pmc_enable) == pmc_enable); @@ -203,19 +209,19 @@ nvkm_mc = { void nvkm_mc_ctor(const struct nvkm_mc_func *func, struct nvkm_device *device, - int index, struct nvkm_mc *mc) + enum nvkm_subdev_type type, int inst, struct nvkm_mc *mc) { - nvkm_subdev_ctor(&nvkm_mc, device, index, &mc->subdev); + nvkm_subdev_ctor(&nvkm_mc, device, type, inst, &mc->subdev); mc->func = func; } int nvkm_mc_new_(const struct nvkm_mc_func *func, struct nvkm_device *device, - int index, struct nvkm_mc **pmc) + enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { struct nvkm_mc *mc; if (!(mc = *pmc = kzalloc(sizeof(*mc), GFP_KERNEL))) return -ENOMEM; - nvkm_mc_ctor(func, device, index, *pmc); + nvkm_mc_ctor(func, device, type, inst, *pmc); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g84.c index 430a61c3df44..4cfc1c984006 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g84.c @@ -62,7 +62,7 @@ g84_mc = { }; int -g84_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +g84_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return nvkm_mc_new_(&g84_mc, device, index, pmc); + return nvkm_mc_new_(&g84_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c index 93ad4982ce5f..b7e58d75d894 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c @@ -62,7 +62,7 @@ g98_mc = { }; int -g98_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +g98_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return nvkm_mc_new_(&g98_mc, device, index, pmc); + return nvkm_mc_new_(&g98_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/ga100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/ga100.c index 967eb3af11eb..4105175dfccd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/ga100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/ga100.c @@ -68,7 +68,7 @@ ga100_mc = { }; int -ga100_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +ga100_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return nvkm_mc_new_(&ga100_mc, device, index, pmc); + return nvkm_mc_new_(&ga100_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c index f93766418056..3a589c6f7fad 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c @@ -27,11 +27,11 @@ static const struct nvkm_mc_map gf100_mc_reset[] = { { 0x00020000, NVKM_ENGINE_MSPDEC }, { 0x00008000, NVKM_ENGINE_MSVLD }, - { 0x00002000, NVKM_SUBDEV_PMU, true }, + { 0x00002000, NVKM_SUBDEV_PMU, 0, true }, { 0x00001000, NVKM_ENGINE_GR }, { 0x00000100, NVKM_ENGINE_FIFO }, - { 0x00000080, NVKM_ENGINE_CE1 }, - { 0x00000040, NVKM_ENGINE_CE0 }, + { 0x00000080, NVKM_ENGINE_CE, 1 }, + { 0x00000040, NVKM_ENGINE_CE, 0 }, { 0x00000002, NVKM_ENGINE_MSPPP }, {} }; @@ -43,10 +43,10 @@ gf100_mc_intr[] = { { 0x00008000, NVKM_ENGINE_MSVLD }, { 0x00001000, NVKM_ENGINE_GR }, { 0x00000100, NVKM_ENGINE_FIFO }, - { 0x00000040, NVKM_ENGINE_CE1 }, - { 0x00000020, NVKM_ENGINE_CE0 }, + { 0x00000040, NVKM_ENGINE_CE, 1 }, + { 0x00000020, NVKM_ENGINE_CE, 0 }, { 0x00000001, NVKM_ENGINE_MSPPP }, - { 0x40000000, NVKM_SUBDEV_IBUS }, + { 0x40000000, NVKM_SUBDEV_PRIVRING }, { 0x10000000, NVKM_SUBDEV_BUS }, { 0x08000000, NVKM_SUBDEV_FB }, { 0x02000000, NVKM_SUBDEV_LTC }, @@ -112,7 +112,7 @@ gf100_mc = { }; int -gf100_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +gf100_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return nvkm_mc_new_(&gf100_mc, device, index, pmc); + return nvkm_mc_new_(&gf100_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk104.c index 7b8c6ecad1a5..d9b9067fa93f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk104.c @@ -26,7 +26,7 @@ const struct nvkm_mc_map gk104_mc_reset[] = { { 0x00000100, NVKM_ENGINE_FIFO }, - { 0x00002000, NVKM_SUBDEV_PMU, true }, + { 0x00002000, NVKM_SUBDEV_PMU, 0, true }, {} }; @@ -34,7 +34,7 @@ const struct nvkm_mc_map gk104_mc_intr[] = { { 0x04000000, NVKM_ENGINE_DISP }, { 0x00000100, NVKM_ENGINE_FIFO }, - { 0x40000000, NVKM_SUBDEV_IBUS }, + { 0x40000000, NVKM_SUBDEV_PRIVRING }, { 0x10000000, NVKM_SUBDEV_BUS }, { 0x08000000, NVKM_SUBDEV_FB }, { 0x02000000, NVKM_SUBDEV_LTC }, @@ -60,7 +60,7 @@ gk104_mc = { }; int -gk104_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +gk104_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return nvkm_mc_new_(&gk104_mc, device, index, pmc); + return nvkm_mc_new_(&gk104_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c index ca1bf3279dbe..03590292749a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c @@ -35,7 +35,7 @@ gk20a_mc = { }; int -gk20a_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +gk20a_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return nvkm_mc_new_(&gk20a_mc, device, index, pmc); + return nvkm_mc_new_(&gk20a_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c index 43db245eec9a..5fd1a0595c33 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c @@ -80,7 +80,7 @@ gp100_mc_intr[] = { { 0x04000000, NVKM_ENGINE_DISP }, { 0x00000100, NVKM_ENGINE_FIFO }, { 0x00000200, NVKM_SUBDEV_FAULT }, - { 0x40000000, NVKM_SUBDEV_IBUS }, + { 0x40000000, NVKM_SUBDEV_PRIVRING }, { 0x10000000, NVKM_SUBDEV_BUS }, { 0x08000000, NVKM_SUBDEV_FB }, { 0x02000000, NVKM_SUBDEV_LTC }, @@ -106,13 +106,13 @@ gp100_mc = { int gp100_mc_new_(const struct nvkm_mc_func *func, struct nvkm_device *device, - int index, struct nvkm_mc **pmc) + enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { struct gp100_mc *mc; if (!(mc = kzalloc(sizeof(*mc), GFP_KERNEL))) return -ENOMEM; - nvkm_mc_ctor(func, device, index, &mc->base); + nvkm_mc_ctor(func, device, type, inst, &mc->base); *pmc = &mc->base; spin_lock_init(&mc->lock); @@ -122,7 +122,7 @@ gp100_mc_new_(const struct nvkm_mc_func *func, struct nvkm_device *device, } int -gp100_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +gp100_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return gp100_mc_new_(&gp100_mc, device, index, pmc); + return gp100_mc_new_(&gp100_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.c index 45c62f5ef782..dd581d030ced 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.c @@ -43,7 +43,7 @@ gp10b_mc = { }; int -gp10b_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +gp10b_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return gp100_mc_new_(&gp10b_mc, device, index, pmc); + return gp100_mc_new_(&gp10b_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gt215.c index 99d50a3d956f..1b4d43531dba 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gt215.c @@ -27,7 +27,7 @@ static const struct nvkm_mc_map gt215_mc_reset[] = { { 0x04008000, NVKM_ENGINE_MSVLD }, { 0x01020000, NVKM_ENGINE_MSPDEC }, - { 0x00802000, NVKM_ENGINE_CE0 }, + { 0x00802000, NVKM_ENGINE_CE, 0 }, { 0x00400002, NVKM_ENGINE_MSPPP }, { 0x00201000, NVKM_ENGINE_GR }, { 0x00000100, NVKM_ENGINE_FIFO }, @@ -37,7 +37,7 @@ gt215_mc_reset[] = { static const struct nvkm_mc_map gt215_mc_intr[] = { { 0x04000000, NVKM_ENGINE_DISP }, - { 0x00400000, NVKM_ENGINE_CE0 }, + { 0x00400000, NVKM_ENGINE_CE, 0 }, { 0x00020000, NVKM_ENGINE_MSPDEC }, { 0x00008000, NVKM_ENGINE_MSVLD }, { 0x00001000, NVKM_ENGINE_GR }, @@ -71,7 +71,7 @@ gt215_mc = { }; int -gt215_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +gt215_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return nvkm_mc_new_(>215_mc, device, index, pmc); + return nvkm_mc_new_(>215_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c index 6509defd1460..bc0d09bafa99 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c @@ -80,7 +80,7 @@ nv04_mc = { }; int -nv04_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +nv04_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return nvkm_mc_new_(&nv04_mc, device, index, pmc); + return nvkm_mc_new_(&nv04_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv11.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv11.c index 9213107901e6..ab59ca1ee068 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv11.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv11.c @@ -44,7 +44,7 @@ nv11_mc = { }; int -nv11_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +nv11_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return nvkm_mc_new_(&nv11_mc, device, index, pmc); + return nvkm_mc_new_(&nv11_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv17.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv17.c index 64bf5bbf8146..03d756e26e57 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv17.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv17.c @@ -53,7 +53,7 @@ nv17_mc = { }; int -nv17_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +nv17_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return nvkm_mc_new_(&nv17_mc, device, index, pmc); + return nvkm_mc_new_(&nv17_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c index 65fa44a64b98..95f65766e8b0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c @@ -48,7 +48,7 @@ nv44_mc = { }; int -nv44_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +nv44_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return nvkm_mc_new_(&nv44_mc, device, index, pmc); + return nvkm_mc_new_(&nv44_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c index fe93b4fd7100..fce3613cdfa5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c @@ -55,7 +55,7 @@ nv50_mc = { }; int -nv50_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +nv50_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return nvkm_mc_new_(&nv50_mc, device, index, pmc); + return nvkm_mc_new_(&nv50_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h index 0d01b2c419ff..c8bcabb98f99 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h @@ -4,14 +4,15 @@ #define nvkm_mc(p) container_of((p), struct nvkm_mc, subdev) #include <subdev/mc.h> -void nvkm_mc_ctor(const struct nvkm_mc_func *, struct nvkm_device *, - int index, struct nvkm_mc *); -int nvkm_mc_new_(const struct nvkm_mc_func *, struct nvkm_device *, - int index, struct nvkm_mc **); +void nvkm_mc_ctor(const struct nvkm_mc_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_mc *); +int nvkm_mc_new_(const struct nvkm_mc_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_mc **); struct nvkm_mc_map { u32 stat; - u32 unit; + enum nvkm_subdev_type type; + int inst; bool noauto; }; @@ -52,7 +53,7 @@ void gf100_mc_unk260(struct nvkm_mc *, u32); void gp100_mc_intr_unarm(struct nvkm_mc *); void gp100_mc_intr_rearm(struct nvkm_mc *); void gp100_mc_intr_mask(struct nvkm_mc *, u32, u32); -int gp100_mc_new_(const struct nvkm_mc_func *, struct nvkm_device *, int, +int gp100_mc_new_(const struct nvkm_mc_func *, struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_mc **); extern const struct nvkm_mc_map gk104_mc_intr[]; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/tu102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/tu102.c index af0afd1ad6ee..58db83ebadc5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/tu102.c @@ -112,15 +112,15 @@ tu102_mc = { .reset = gk104_mc_reset, }; -int +static int tu102_mc_new_(const struct nvkm_mc_func *func, struct nvkm_device *device, - int index, struct nvkm_mc **pmc) + enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { struct tu102_mc *mc; if (!(mc = kzalloc(sizeof(*mc), GFP_KERNEL))) return -ENOMEM; - nvkm_mc_ctor(func, device, index, &mc->base); + nvkm_mc_ctor(func, device, type, inst, &mc->base); *pmc = &mc->base; spin_lock_init(&mc->lock); @@ -130,7 +130,7 @@ tu102_mc_new_(const struct nvkm_mc_func *func, struct nvkm_device *device, } int -tu102_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +tu102_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc) { - return tu102_mc_new_(&tu102_mc, device, index, pmc); + return tu102_mc_new_(&tu102_mc, device, type, inst, pmc); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c index 6d5212ae2fd5..ad3b44a9e0e7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c @@ -402,6 +402,7 @@ nvkm_mmu_dtor(struct nvkm_subdev *subdev) nvkm_vmm_unref(&mmu->vmm); nvkm_mmu_ptc_fini(mmu); + mutex_destroy(&mmu->mutex); return mmu; } @@ -414,22 +415,23 @@ nvkm_mmu = { void nvkm_mmu_ctor(const struct nvkm_mmu_func *func, struct nvkm_device *device, - int index, struct nvkm_mmu *mmu) + enum nvkm_subdev_type type, int inst, struct nvkm_mmu *mmu) { - nvkm_subdev_ctor(&nvkm_mmu, device, index, &mmu->subdev); + nvkm_subdev_ctor(&nvkm_mmu, device, type, inst, &mmu->subdev); mmu->func = func; mmu->dma_bits = func->dma_bits; nvkm_mmu_ptc_init(mmu); + mutex_init(&mmu->mutex); mmu->user.ctor = nvkm_ummu_new; mmu->user.base = func->mmu.user; } int nvkm_mmu_new_(const struct nvkm_mmu_func *func, struct nvkm_device *device, - int index, struct nvkm_mmu **pmmu) + enum nvkm_subdev_type type, int inst, struct nvkm_mmu **pmmu) { if (!(*pmmu = kzalloc(sizeof(**pmmu), GFP_KERNEL))) return -ENOMEM; - nvkm_mmu_ctor(func, device, index, *pmmu); + nvkm_mmu_ctor(func, device, type, inst, *pmmu); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/g84.c index 8accda5a772b..ce47a3b97be9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/g84.c @@ -35,7 +35,8 @@ g84_mmu = { }; int -g84_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +g84_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { - return nvkm_mmu_new_(&g84_mmu, device, index, pmmu); + return nvkm_mmu_new_(&g84_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c index 2cd5ec81c0d0..7a28b1d49f7c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c @@ -84,7 +84,8 @@ gf100_mmu = { }; int -gf100_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +gf100_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { - return nvkm_mmu_new_(&gf100_mmu, device, index, pmmu); + return nvkm_mmu_new_(&gf100_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk104.c index 3d7d1eb1cff9..34c9b2b821f6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk104.c @@ -35,7 +35,8 @@ gk104_mmu = { }; int -gk104_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +gk104_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { - return nvkm_mmu_new_(&gk104_mmu, device, index, pmmu); + return nvkm_mmu_new_(&gk104_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.c index ac74965a60d4..a7db29c429ee 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.c @@ -35,7 +35,8 @@ gk20a_mmu = { }; int -gk20a_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +gk20a_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { - return nvkm_mmu_new_(&gk20a_mmu, device, index, pmmu); + return nvkm_mmu_new_(&gk20a_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm200.c index 83990c83f9f8..e1696f637a68 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm200.c @@ -90,9 +90,10 @@ gm200_mmu_fixed = { }; int -gm200_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +gm200_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { if (device->fb->page) - return nvkm_mmu_new_(&gm200_mmu_fixed, device, index, pmmu); - return nvkm_mmu_new_(&gm200_mmu, device, index, pmmu); + return nvkm_mmu_new_(&gm200_mmu_fixed, device, type, inst, pmmu); + return nvkm_mmu_new_(&gm200_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm20b.c index 7353a94b4091..e6e1a8ad701e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm20b.c @@ -47,9 +47,10 @@ gm20b_mmu_fixed = { }; int -gm20b_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +gm20b_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { if (device->fb->page) - return nvkm_mmu_new_(&gm20b_mmu_fixed, device, index, pmmu); - return nvkm_mmu_new_(&gm20b_mmu, device, index, pmmu); + return nvkm_mmu_new_(&gm20b_mmu_fixed, device, type, inst, pmmu); + return nvkm_mmu_new_(&gm20b_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp100.c index 65cb9d28e60e..daa5ab0f8711 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp100.c @@ -37,9 +37,10 @@ gp100_mmu = { }; int -gp100_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +gp100_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { if (!nvkm_boolopt(device->cfgopt, "GP100MmuLayout", true)) - return gm200_mmu_new(device, index, pmmu); - return nvkm_mmu_new_(&gp100_mmu, device, index, pmmu); + return gm200_mmu_new(device, type, inst, pmmu); + return nvkm_mmu_new_(&gp100_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp10b.c index 0a50be9a785a..edd0bf9a5cd8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp10b.c @@ -37,9 +37,10 @@ gp10b_mmu = { }; int -gp10b_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +gp10b_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { if (!nvkm_boolopt(device->cfgopt, "GP100MmuLayout", true)) - return gm20b_mmu_new(device, index, pmmu); - return nvkm_mmu_new_(&gp10b_mmu, device, index, pmmu); + return gm20b_mmu_new(device, type, inst, pmmu); + return nvkm_mmu_new_(&gp10b_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gv100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gv100.c index e0997eedd6d9..fb8bdc88d566 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gv100.c @@ -37,7 +37,8 @@ gv100_mmu = { }; int -gv100_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +gv100_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { - return nvkm_mmu_new_(&gv100_mmu, device, index, pmmu); + return nvkm_mmu_new_(&gv100_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mcp77.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mcp77.c index 0527b50730d9..514876d6411b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mcp77.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mcp77.c @@ -35,7 +35,8 @@ mcp77_mmu = { }; int -mcp77_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +mcp77_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { - return nvkm_mmu_new_(&mcp77_mmu, device, index, pmmu); + return nvkm_mmu_new_(&mcp77_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c index d201c887c2cd..0674aa8f68c8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c @@ -35,7 +35,8 @@ nv04_mmu = { }; int -nv04_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +nv04_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { - return nvkm_mmu_new_(&nv04_mmu, device, index, pmmu); + return nvkm_mmu_new_(&nv04_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c index adca81895c09..909f92b72847 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c @@ -47,11 +47,12 @@ nv41_mmu = { }; int -nv41_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +nv41_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { if (device->type == NVKM_DEVICE_AGP || !nvkm_boolopt(device->cfgopt, "NvPCIE", true)) - return nv04_mmu_new(device, index, pmmu); + return nv04_mmu_new(device, type, inst, pmmu); - return nvkm_mmu_new_(&nv41_mmu, device, index, pmmu); + return nvkm_mmu_new_(&nv41_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c index 598c53a27bde..dd2a8d461da3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c @@ -62,11 +62,12 @@ nv44_mmu = { }; int -nv44_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +nv44_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { if (device->type == NVKM_DEVICE_AGP || !nvkm_boolopt(device->cfgopt, "NvPCIE", true)) - return nv04_mmu_new(device, index, pmmu); + return nv04_mmu_new(device, type, inst, pmmu); - return nvkm_mmu_new_(&nv44_mmu, device, index, pmmu); + return nvkm_mmu_new_(&nv44_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c index c0083ddda65a..78d46e35d0a9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c @@ -71,7 +71,8 @@ nv50_mmu = { }; int -nv50_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +nv50_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { - return nvkm_mmu_new_(&nv50_mmu, device, index, pmmu); + return nvkm_mmu_new_(&nv50_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/priv.h index 479b02344271..5265bf4d8366 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/priv.h @@ -4,10 +4,10 @@ #define nvkm_mmu(p) container_of((p), struct nvkm_mmu, subdev) #include <subdev/mmu.h> -void nvkm_mmu_ctor(const struct nvkm_mmu_func *, struct nvkm_device *, - int index, struct nvkm_mmu *); -int nvkm_mmu_new_(const struct nvkm_mmu_func *, struct nvkm_device *, - int index, struct nvkm_mmu **); +void nvkm_mmu_ctor(const struct nvkm_mmu_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_mmu *); +int nvkm_mmu_new_(const struct nvkm_mmu_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_mmu **); struct nvkm_mmu_func { void (*init)(struct nvkm_mmu *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.c index 94081f35f967..8d060ce47f86 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.c @@ -51,7 +51,8 @@ tu102_mmu = { }; int -tu102_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) +tu102_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mmu **pmmu) { - return nvkm_mmu_new_(&tu102_mmu, device, index, pmmu); + return nvkm_mmu_new_(&tu102_mmu, device, type, inst, pmmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c index 6a2d9eb8e1ea..5438384d9a67 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c @@ -187,12 +187,11 @@ gf100_vmm_invalidate_pdb(struct nvkm_vmm *vmm, u64 addr) void gf100_vmm_invalidate(struct nvkm_vmm *vmm, u32 type) { - struct nvkm_subdev *subdev = &vmm->mmu->subdev; - struct nvkm_device *device = subdev->device; + struct nvkm_device *device = vmm->mmu->subdev.device; struct nvkm_mmu_pt *pd = vmm->pd->pt[0]; u64 addr = 0; - mutex_lock(&subdev->mutex); + mutex_lock(&vmm->mmu->mutex); /* Looks like maybe a "free flush slots" counter, the * faster you write to 0x100cbc to more it decreases. */ @@ -222,7 +221,7 @@ gf100_vmm_invalidate(struct nvkm_vmm *vmm, u32 type) if (nvkm_rd32(device, 0x100c80) & 0x00008000) break; ); - mutex_unlock(&subdev->mutex); + mutex_unlock(&vmm->mmu->mutex); } void diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.c index 1d3369683a21..31984671daf8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.c @@ -80,17 +80,16 @@ nv41_vmm_desc_12[] = { static void nv41_vmm_flush(struct nvkm_vmm *vmm, int level) { - struct nvkm_subdev *subdev = &vmm->mmu->subdev; - struct nvkm_device *device = subdev->device; + struct nvkm_device *device = vmm->mmu->subdev.device; - mutex_lock(&subdev->mutex); + mutex_lock(&vmm->mmu->mutex); nvkm_wr32(device, 0x100810, 0x00000022); nvkm_msec(device, 2000, if (nvkm_rd32(device, 0x100810) & 0x00000020) break; ); nvkm_wr32(device, 0x100810, 0x00000000); - mutex_unlock(&subdev->mutex); + mutex_unlock(&vmm->mmu->mutex); } static const struct nvkm_vmm_func diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c index 2d89e27e8e9e..b7548dcd72c7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c @@ -184,7 +184,7 @@ nv50_vmm_flush(struct nvkm_vmm *vmm, int level) struct nvkm_device *device = subdev->device; int i, id; - mutex_lock(&subdev->mutex); + mutex_lock(&vmm->mmu->mutex); for (i = 0; i < NVKM_SUBDEV_NR; i++) { if (!atomic_read(&vmm->engref[i])) continue; @@ -207,7 +207,7 @@ nv50_vmm_flush(struct nvkm_vmm *vmm, int level) case NVKM_ENGINE_MSVLD : id = 0x09; break; case NVKM_ENGINE_CIPHER: case NVKM_ENGINE_SEC : id = 0x0a; break; - case NVKM_ENGINE_CE0 : id = 0x0d; break; + case NVKM_ENGINE_CE : id = 0x0d; break; default: continue; } @@ -217,10 +217,9 @@ nv50_vmm_flush(struct nvkm_vmm *vmm, int level) if (!(nvkm_rd32(device, 0x100c80) & 0x00000001)) break; ) < 0) - nvkm_error(subdev, "%s mmu invalidate timeout\n", - nvkm_subdev_name[i]); + nvkm_error(subdev, "%s mmu invalidate timeout\n", nvkm_subdev_type[i]); } - mutex_unlock(&subdev->mutex); + mutex_unlock(&vmm->mmu->mutex); } int diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c index b1294d0076c0..6cb5eefa45e9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c @@ -26,15 +26,14 @@ static void tu102_vmm_flush(struct nvkm_vmm *vmm, int depth) { - struct nvkm_subdev *subdev = &vmm->mmu->subdev; - struct nvkm_device *device = subdev->device; + struct nvkm_device *device = vmm->mmu->subdev.device; u32 type = (5 /* CACHE_LEVEL_UP_TO_PDE3 */ - depth) << 24; type |= 0x00000001; /* PAGE_ALL */ if (atomic_read(&vmm->engref[NVKM_SUBDEV_BAR])) type |= 0x00000004; /* HUB_ONLY */ - mutex_lock(&subdev->mutex); + mutex_lock(&vmm->mmu->mutex); nvkm_wr32(device, 0xb830a0, vmm->pd->pt[0]->addr >> 8); nvkm_wr32(device, 0xb830a4, 0x00000000); @@ -46,7 +45,7 @@ tu102_vmm_flush(struct nvkm_vmm *vmm, int depth) break; ); - mutex_unlock(&subdev->mutex); + mutex_unlock(&vmm->mmu->mutex); } static const struct nvkm_vmm_func diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c index f44682d62f75..c1acfe642da3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c @@ -230,7 +230,8 @@ nvkm_mxm = { }; int -nvkm_mxm_new_(struct nvkm_device *device, int index, struct nvkm_mxm **pmxm) +nvkm_mxm_new_(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_mxm **pmxm) { struct nvkm_bios *bios = device->bios; struct nvkm_mxm *mxm; @@ -240,7 +241,7 @@ nvkm_mxm_new_(struct nvkm_device *device, int index, struct nvkm_mxm **pmxm) if (!(mxm = *pmxm = kzalloc(sizeof(*mxm), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_mxm, device, index, &mxm->subdev); + nvkm_subdev_ctor(&nvkm_mxm, device, type, inst, &mxm->subdev); data = mxm_table(bios, &ver, &len); if (!data || !(ver = nvbios_rd08(bios, data))) { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c index 70e2c414bb7b..f3167904dcb0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c @@ -201,12 +201,13 @@ mxm_dcb_sanitise(struct nvkm_mxm *mxm) } int -nv50_mxm_new(struct nvkm_device *device, int index, struct nvkm_subdev **pmxm) +nv50_mxm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_subdev **pmxm) { struct nvkm_mxm *mxm; int ret; - ret = nvkm_mxm_new_(device, index, &mxm); + ret = nvkm_mxm_new_(device, type, inst, &mxm); if (mxm) *pmxm = &mxm->subdev; if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/priv.h index fc8f69e6fc64..fcacb6c6a7f7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/priv.h @@ -12,5 +12,5 @@ struct nvkm_mxm { u8 *mxms; }; -int nvkm_mxm_new_(struct nvkm_device *, int index, struct nvkm_mxm **); +int nvkm_mxm_new_(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_mxm **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c index ee2431a7804e..a7d42ea8ba28 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c @@ -183,13 +183,13 @@ nvkm_pci_func = { int nvkm_pci_new_(const struct nvkm_pci_func *func, struct nvkm_device *device, - int index, struct nvkm_pci **ppci) + enum nvkm_subdev_type type, int inst, struct nvkm_pci **ppci) { struct nvkm_pci *pci; if (!(pci = *ppci = kzalloc(sizeof(**ppci), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_pci_func, device, index, &pci->subdev); + nvkm_subdev_ctor(&nvkm_pci_func, device, type, inst, &pci->subdev); pci->func = func; pci->pdev = device->func->pci(device)->pdev; pci->irq = -1; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c index 62438d892f42..5b29aacedef3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c @@ -150,7 +150,8 @@ g84_pci_func = { }; int -g84_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +g84_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pci **ppci) { - return nvkm_pci_new_(&g84_pci_func, device, index, ppci); + return nvkm_pci_new_(&g84_pci_func, device, type, inst, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.c index 48874359d5f6..a9e0674009c6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.c @@ -51,7 +51,8 @@ g92_pci_func = { }; int -g92_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +g92_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pci **ppci) { - return nvkm_pci_new_(&g92_pci_func, device, index, ppci); + return nvkm_pci_new_(&g92_pci_func, device, type, inst, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c index 09adb37a5664..7bacd0693283 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c @@ -43,7 +43,8 @@ g94_pci_func = { }; int -g94_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +g94_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pci **ppci) { - return nvkm_pci_new_(&g94_pci_func, device, index, ppci); + return nvkm_pci_new_(&g94_pci_func, device, type, inst, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c index 00a5e7d3ee9d..099906092fe1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c @@ -96,7 +96,8 @@ gf100_pci_func = { }; int -gf100_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +gf100_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pci **ppci) { - return nvkm_pci_new_(&gf100_pci_func, device, index, ppci); + return nvkm_pci_new_(&gf100_pci_func, device, type, inst, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.c index 11bf419afe3f..bcde609ba866 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.c @@ -43,7 +43,8 @@ gf106_pci_func = { }; int -gf106_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +gf106_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pci **ppci) { - return nvkm_pci_new_(&gf106_pci_func, device, index, ppci); + return nvkm_pci_new_(&gf106_pci_func, device, type, inst, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.c index e68030507d88..6be87ecffc89 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.c @@ -222,7 +222,8 @@ gk104_pci_func = { }; int -gk104_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +gk104_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pci **ppci) { - return nvkm_pci_new_(&gk104_pci_func, device, index, ppci); + return nvkm_pci_new_(&gk104_pci_func, device, type, inst, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gp100.c index 82c5234a06ff..a5fafda0014d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gp100.c @@ -38,7 +38,8 @@ gp100_pci_func = { }; int -gp100_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +gp100_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pci **ppci) { - return nvkm_pci_new_(&gp100_pci_func, device, index, ppci); + return nvkm_pci_new_(&gp100_pci_func, device, type, inst, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv04.c index 5b1ed42cb90b..9ab64194b185 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv04.c @@ -52,7 +52,8 @@ nv04_pci_func = { }; int -nv04_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +nv04_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pci **ppci) { - return nvkm_pci_new_(&nv04_pci_func, device, index, ppci); + return nvkm_pci_new_(&nv04_pci_func, device, type, inst, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.c index 6eb417765802..6a3c31cf0200 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.c @@ -59,7 +59,8 @@ nv40_pci_func = { }; int -nv40_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +nv40_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pci **ppci) { - return nvkm_pci_new_(&nv40_pci_func, device, index, ppci); + return nvkm_pci_new_(&nv40_pci_func, device, type, inst, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.c index fc617e4c0ab6..9cad17f178ec 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.c @@ -45,7 +45,8 @@ nv46_pci_func = { }; int -nv46_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +nv46_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pci **ppci) { - return nvkm_pci_new_(&nv46_pci_func, device, index, ppci); + return nvkm_pci_new_(&nv46_pci_func, device, type, inst, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv4c.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv4c.c index 1f1b26b5fa72..741e34bf307c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv4c.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv4c.c @@ -31,7 +31,8 @@ nv4c_pci_func = { }; int -nv4c_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +nv4c_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pci **ppci) { - return nvkm_pci_new_(&nv4c_pci_func, device, index, ppci); + return nvkm_pci_new_(&nv4c_pci_func, device, type, inst, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h index 7009aad86b6e..9b7583532962 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h @@ -4,8 +4,8 @@ #define nvkm_pci(p) container_of((p), struct nvkm_pci, subdev) #include <subdev/pci.h> -int nvkm_pci_new_(const struct nvkm_pci_func *, struct nvkm_device *, - int index, struct nvkm_pci **); +int nvkm_pci_new_(const struct nvkm_pci_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_pci **); struct nvkm_pci_func { void (*init)(struct nvkm_pci *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c index a0fe607c9c07..24382875fb4f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c @@ -148,6 +148,7 @@ nvkm_pmu_dtor(struct nvkm_subdev *subdev) nvkm_falcon_cmdq_del(&pmu->hpq); nvkm_falcon_qmgr_del(&pmu->qmgr); nvkm_falcon_dtor(&pmu->falcon); + mutex_destroy(&pmu->send.mutex); return nvkm_pmu(subdev); } @@ -162,11 +163,13 @@ nvkm_pmu = { int nvkm_pmu_ctor(const struct nvkm_pmu_fwif *fwif, struct nvkm_device *device, - int index, struct nvkm_pmu *pmu) + enum nvkm_subdev_type type, int inst, struct nvkm_pmu *pmu) { int ret; - nvkm_subdev_ctor(&nvkm_pmu, device, index, &pmu->subdev); + nvkm_subdev_ctor(&nvkm_pmu, device, type, inst, &pmu->subdev); + + mutex_init(&pmu->send.mutex); INIT_WORK(&pmu->recv.work, nvkm_pmu_recv); init_waitqueue_head(&pmu->recv.wait); @@ -177,9 +180,8 @@ nvkm_pmu_ctor(const struct nvkm_pmu_fwif *fwif, struct nvkm_device *device, pmu->func = fwif->func; - ret = nvkm_falcon_ctor(pmu->func->flcn, &pmu->subdev, - nvkm_subdev_name[pmu->subdev.index], 0x10a000, - &pmu->falcon); + ret = nvkm_falcon_ctor(pmu->func->flcn, &pmu->subdev, pmu->subdev.name, + 0x10a000, &pmu->falcon); if (ret) return ret; @@ -195,10 +197,10 @@ nvkm_pmu_ctor(const struct nvkm_pmu_fwif *fwif, struct nvkm_device *device, int nvkm_pmu_new_(const struct nvkm_pmu_fwif *fwif, struct nvkm_device *device, - int index, struct nvkm_pmu **ppmu) + enum nvkm_subdev_type type, int inst, struct nvkm_pmu **ppmu) { struct nvkm_pmu *pmu; if (!(pmu = *ppmu = kzalloc(sizeof(*pmu), GFP_KERNEL))) return -ENOMEM; - return nvkm_pmu_ctor(fwif, device, index, *ppmu); + return nvkm_pmu_ctor(fwif, device, type, inst, *ppmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c index 3ecb3d9cbcf2..f725a3ec5479 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c @@ -30,14 +30,14 @@ void gf100_pmu_reset(struct nvkm_pmu *pmu) { struct nvkm_device *device = pmu->subdev.device; - nvkm_mc_disable(device, NVKM_SUBDEV_PMU); - nvkm_mc_enable(device, NVKM_SUBDEV_PMU); + nvkm_mc_disable(device, NVKM_SUBDEV_PMU, 0); + nvkm_mc_enable(device, NVKM_SUBDEV_PMU, 0); } bool gf100_pmu_enabled(struct nvkm_pmu *pmu) { - return nvkm_mc_enabled(pmu->subdev.device, NVKM_SUBDEV_PMU); + return nvkm_mc_enabled(pmu->subdev.device, NVKM_SUBDEV_PMU, 0); } static const struct nvkm_pmu_func @@ -69,7 +69,8 @@ gf100_pmu_fwif[] = { }; int -gf100_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +gf100_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) { - return nvkm_pmu_new_(gf100_pmu_fwif, device, index, ppmu); + return nvkm_pmu_new_(gf100_pmu_fwif, device, type, inst, ppmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c index 8dd0271aaaee..0f4b6697a4e4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c @@ -47,7 +47,8 @@ gf119_pmu_fwif[] = { }; int -gf119_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +gf119_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) { - return nvkm_pmu_new_(gf119_pmu_fwif, device, index, ppmu); + return nvkm_pmu_new_(gf119_pmu_fwif, device, type, inst, ppmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c index 8b70cc17a634..9e7631d7aa41 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c @@ -127,7 +127,8 @@ gk104_pmu_fwif[] = { }; int -gk104_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +gk104_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) { - return nvkm_pmu_new_(gk104_pmu_fwif, device, index, ppmu); + return nvkm_pmu_new_(gk104_pmu_fwif, device, type, inst, ppmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c index 0081f2141b10..dbaefee53e1f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c @@ -106,7 +106,8 @@ gk110_pmu_fwif[] = { }; int -gk110_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +gk110_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) { - return nvkm_pmu_new_(gk110_pmu_fwif, device, index, ppmu); + return nvkm_pmu_new_(gk110_pmu_fwif, device, type, inst, ppmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c index b227c701a5e7..a08fb049e6d6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c @@ -48,7 +48,8 @@ gk208_pmu_fwif[] = { }; int -gk208_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +gk208_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) { - return nvkm_pmu_new_(gk208_pmu_fwif, device, index, ppmu); + return nvkm_pmu_new_(gk208_pmu_fwif, device, type, inst, ppmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c index 26c1adf8f44c..a67a42e73f08 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c @@ -210,7 +210,8 @@ gk20a_pmu_fwif[] = { }; int -gk20a_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +gk20a_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) { struct gk20a_pmu *pmu; int ret; @@ -219,7 +220,7 @@ gk20a_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) return -ENOMEM; *ppmu = &pmu->base; - ret = nvkm_pmu_ctor(gk20a_pmu_fwif, device, index, &pmu->base); + ret = nvkm_pmu_ctor(gk20a_pmu_fwif, device, type, inst, &pmu->base); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c index 5afb55e58b51..622ee637f97b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c @@ -49,7 +49,8 @@ gm107_pmu_fwif[] = { }; int -gm107_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +gm107_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) { - return nvkm_pmu_new_(gm107_pmu_fwif, device, index, ppmu); + return nvkm_pmu_new_(gm107_pmu_fwif, device, type, inst, ppmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c index 383376addb41..5968c7696596 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c @@ -45,7 +45,8 @@ gm200_pmu_fwif[] = { }; int -gm200_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +gm200_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) { - return nvkm_pmu_new_(gm200_pmu_fwif, device, index, ppmu); + return nvkm_pmu_new_(gm200_pmu_fwif, device, type, inst, ppmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c index 8f6ed5373ea1..148706977eec 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c @@ -240,7 +240,8 @@ gm20b_pmu_fwif[] = { }; int -gm20b_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +gm20b_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) { - return nvkm_pmu_new_(gm20b_pmu_fwif, device, index, ppmu); + return nvkm_pmu_new_(gm20b_pmu_fwif, device, type, inst, ppmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c index 3d8ce14dba7b..00da1b873ce8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c @@ -51,7 +51,8 @@ gp102_pmu_fwif[] = { }; int -gp102_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +gp102_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) { - return nvkm_pmu_new_(gp102_pmu_fwif, device, index, ppmu); + return nvkm_pmu_new_(gp102_pmu_fwif, device, type, inst, ppmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c index 9c237c426599..461f722656e2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c @@ -99,7 +99,8 @@ gp10b_pmu_fwif[] = { }; int -gp10b_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +gp10b_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) { - return nvkm_pmu_new_(gp10b_pmu_fwif, device, index, ppmu); + return nvkm_pmu_new_(gp10b_pmu_fwif, device, type, inst, ppmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c index 88b909913ff9..b0407b86bc10 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c @@ -34,7 +34,7 @@ gt215_pmu_send(struct nvkm_pmu *pmu, u32 reply[2], struct nvkm_device *device = subdev->device; u32 addr; - mutex_lock(&subdev->mutex); + mutex_lock(&pmu->send.mutex); /* wait for a free slot in the fifo */ addr = nvkm_rd32(device, 0x10a4a0); if (nvkm_msec(device, 2000, @@ -42,7 +42,7 @@ gt215_pmu_send(struct nvkm_pmu *pmu, u32 reply[2], if (tmp != (addr ^ 8)) break; ) < 0) { - mutex_unlock(&subdev->mutex); + mutex_unlock(&pmu->send.mutex); return -EBUSY; } @@ -79,7 +79,7 @@ gt215_pmu_send(struct nvkm_pmu *pmu, u32 reply[2], reply[1] = pmu->recv.data[1]; } - mutex_unlock(&subdev->mutex); + mutex_unlock(&pmu->send.mutex); return 0; } @@ -282,7 +282,8 @@ gt215_pmu_fwif[] = { }; int -gt215_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +gt215_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_pmu **ppmu) { - return nvkm_pmu_new_(gt215_pmu_fwif, device, index, ppmu); + return nvkm_pmu_new_(gt215_pmu_fwif, device, type, inst, ppmu); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h index 276b6d778e53..e7860d177353 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h @@ -62,8 +62,8 @@ int gf100_pmu_nofw(struct nvkm_pmu *, int, const struct nvkm_pmu_fwif *); int gm200_pmu_nofw(struct nvkm_pmu *, int, const struct nvkm_pmu_fwif *); int gm20b_pmu_load(struct nvkm_pmu *, int, const struct nvkm_pmu_fwif *); -int nvkm_pmu_ctor(const struct nvkm_pmu_fwif *, struct nvkm_device *, - int index, struct nvkm_pmu *); -int nvkm_pmu_new_(const struct nvkm_pmu_fwif *, struct nvkm_device *, - int index, struct nvkm_pmu **); +int nvkm_pmu_ctor(const struct nvkm_pmu_fwif *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_pmu *); +int nvkm_pmu_new_(const struct nvkm_pmu_fwif *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_pmu **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/privring/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/Kbuild new file mode 100644 index 000000000000..d47d1bdd0f2b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/Kbuild @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: MIT +nvkm-y += nvkm/subdev/privring/gf100.o +nvkm-y += nvkm/subdev/privring/gf117.o +nvkm-y += nvkm/subdev/privring/gk104.o +nvkm-y += nvkm/subdev/privring/gk20a.o +nvkm-y += nvkm/subdev/privring/gm200.o +nvkm-y += nvkm/subdev/privring/gp10b.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf100.c index 1115376bc85f..ef7caca70372 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf100.c @@ -25,39 +25,39 @@ #include <subdev/timer.h> static void -gf100_ibus_intr_hub(struct nvkm_subdev *ibus, int i) +gf100_privring_intr_hub(struct nvkm_subdev *privring, int i) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; u32 addr = nvkm_rd32(device, 0x122120 + (i * 0x0400)); u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0400)); u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0400)); - nvkm_debug(ibus, "HUB%d: %06x %08x (%08x)\n", i, addr, data, stat); + nvkm_debug(privring, "HUB%d: %06x %08x (%08x)\n", i, addr, data, stat); } static void -gf100_ibus_intr_rop(struct nvkm_subdev *ibus, int i) +gf100_privring_intr_rop(struct nvkm_subdev *privring, int i) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; u32 addr = nvkm_rd32(device, 0x124120 + (i * 0x0400)); u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0400)); u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0400)); - nvkm_debug(ibus, "ROP%d: %06x %08x (%08x)\n", i, addr, data, stat); + nvkm_debug(privring, "ROP%d: %06x %08x (%08x)\n", i, addr, data, stat); } static void -gf100_ibus_intr_gpc(struct nvkm_subdev *ibus, int i) +gf100_privring_intr_gpc(struct nvkm_subdev *privring, int i) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; u32 addr = nvkm_rd32(device, 0x128120 + (i * 0x0400)); u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0400)); u32 stat = nvkm_rd32(device, 0x128128 + (i * 0x0400)); - nvkm_debug(ibus, "GPC%d: %06x %08x (%08x)\n", i, addr, data, stat); + nvkm_debug(privring, "GPC%d: %06x %08x (%08x)\n", i, addr, data, stat); } void -gf100_ibus_intr(struct nvkm_subdev *ibus) +gf100_privring_intr(struct nvkm_subdev *privring) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; u32 intr0 = nvkm_rd32(device, 0x121c58); u32 intr1 = nvkm_rd32(device, 0x121c5c); u32 hubnr = nvkm_rd32(device, 0x121c70); @@ -68,7 +68,7 @@ gf100_ibus_intr(struct nvkm_subdev *ibus) for (i = 0; (intr0 & 0x0000ff00) && i < hubnr; i++) { u32 stat = 0x00000100 << i; if (intr0 & stat) { - gf100_ibus_intr_hub(ibus, i); + gf100_privring_intr_hub(privring, i); intr0 &= ~stat; } } @@ -76,7 +76,7 @@ gf100_ibus_intr(struct nvkm_subdev *ibus) for (i = 0; (intr0 & 0xffff0000) && i < ropnr; i++) { u32 stat = 0x00010000 << i; if (intr0 & stat) { - gf100_ibus_intr_rop(ibus, i); + gf100_privring_intr_rop(privring, i); intr0 &= ~stat; } } @@ -84,7 +84,7 @@ gf100_ibus_intr(struct nvkm_subdev *ibus) for (i = 0; intr1 && i < gpcnr; i++) { u32 stat = 0x00000001 << i; if (intr1 & stat) { - gf100_ibus_intr_gpc(ibus, i); + gf100_privring_intr_gpc(privring, i); intr1 &= ~stat; } } @@ -97,9 +97,9 @@ gf100_ibus_intr(struct nvkm_subdev *ibus) } static int -gf100_ibus_init(struct nvkm_subdev *ibus) +gf100_privring_init(struct nvkm_subdev *privring) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; nvkm_mask(device, 0x122310, 0x0003ffff, 0x00000800); nvkm_wr32(device, 0x12232c, 0x00100064); nvkm_wr32(device, 0x122330, 0x00100064); @@ -109,14 +109,14 @@ gf100_ibus_init(struct nvkm_subdev *ibus) } static const struct nvkm_subdev_func -gf100_ibus = { - .init = gf100_ibus_init, - .intr = gf100_ibus_intr, +gf100_privring = { + .init = gf100_privring_init, + .intr = gf100_privring_intr, }; int -gf100_ibus_new(struct nvkm_device *device, int index, - struct nvkm_subdev **pibus) +gf100_privring_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_subdev **pprivring) { - return nvkm_subdev_new_(&gf100_ibus, device, index, pibus); + return nvkm_subdev_new_(&gf100_privring, device, type, inst, pprivring); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf117.c b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf117.c index 1124dadac145..c78721fcd729 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf117.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf117.c @@ -24,9 +24,9 @@ #include "priv.h" static int -gf117_ibus_init(struct nvkm_subdev *ibus) +gf117_privring_init(struct nvkm_subdev *privring) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; nvkm_mask(device, 0x122310, 0x0003ffff, 0x00000800); nvkm_mask(device, 0x122348, 0x0003ffff, 0x00000100); nvkm_mask(device, 0x1223b0, 0x0003ffff, 0x00000fff); @@ -34,14 +34,14 @@ gf117_ibus_init(struct nvkm_subdev *ibus) } static const struct nvkm_subdev_func -gf117_ibus = { - .init = gf117_ibus_init, - .intr = gf100_ibus_intr, +gf117_privring = { + .init = gf117_privring_init, + .intr = gf100_privring_intr, }; int -gf117_ibus_new(struct nvkm_device *device, int index, - struct nvkm_subdev **pibus) +gf117_privring_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_subdev **pprivring) { - return nvkm_subdev_new_(&gf117_ibus, device, index, pibus); + return nvkm_subdev_new_(&gf117_privring, device, type, inst, pprivring); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk104.c index 22e487b493ad..568a4c0997bd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk104.c @@ -25,39 +25,39 @@ #include <subdev/timer.h> static void -gk104_ibus_intr_hub(struct nvkm_subdev *ibus, int i) +gk104_privring_intr_hub(struct nvkm_subdev *privring, int i) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; u32 addr = nvkm_rd32(device, 0x122120 + (i * 0x0800)); u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0800)); u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0800)); - nvkm_debug(ibus, "HUB%d: %06x %08x (%08x)\n", i, addr, data, stat); + nvkm_debug(privring, "HUB%d: %06x %08x (%08x)\n", i, addr, data, stat); } static void -gk104_ibus_intr_rop(struct nvkm_subdev *ibus, int i) +gk104_privring_intr_rop(struct nvkm_subdev *privring, int i) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; u32 addr = nvkm_rd32(device, 0x124120 + (i * 0x0800)); u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0800)); u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0800)); - nvkm_debug(ibus, "ROP%d: %06x %08x (%08x)\n", i, addr, data, stat); + nvkm_debug(privring, "ROP%d: %06x %08x (%08x)\n", i, addr, data, stat); } static void -gk104_ibus_intr_gpc(struct nvkm_subdev *ibus, int i) +gk104_privring_intr_gpc(struct nvkm_subdev *privring, int i) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; u32 addr = nvkm_rd32(device, 0x128120 + (i * 0x0800)); u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0800)); u32 stat = nvkm_rd32(device, 0x128128 + (i * 0x0800)); - nvkm_debug(ibus, "GPC%d: %06x %08x (%08x)\n", i, addr, data, stat); + nvkm_debug(privring, "GPC%d: %06x %08x (%08x)\n", i, addr, data, stat); } void -gk104_ibus_intr(struct nvkm_subdev *ibus) +gk104_privring_intr(struct nvkm_subdev *privring) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; u32 intr0 = nvkm_rd32(device, 0x120058); u32 intr1 = nvkm_rd32(device, 0x12005c); u32 hubnr = nvkm_rd32(device, 0x120070); @@ -68,7 +68,7 @@ gk104_ibus_intr(struct nvkm_subdev *ibus) for (i = 0; (intr0 & 0x0000ff00) && i < hubnr; i++) { u32 stat = 0x00000100 << i; if (intr0 & stat) { - gk104_ibus_intr_hub(ibus, i); + gk104_privring_intr_hub(privring, i); intr0 &= ~stat; } } @@ -76,7 +76,7 @@ gk104_ibus_intr(struct nvkm_subdev *ibus) for (i = 0; (intr0 & 0xffff0000) && i < ropnr; i++) { u32 stat = 0x00010000 << i; if (intr0 & stat) { - gk104_ibus_intr_rop(ibus, i); + gk104_privring_intr_rop(privring, i); intr0 &= ~stat; } } @@ -84,7 +84,7 @@ gk104_ibus_intr(struct nvkm_subdev *ibus) for (i = 0; intr1 && i < gpcnr; i++) { u32 stat = 0x00000001 << i; if (intr1 & stat) { - gk104_ibus_intr_gpc(ibus, i); + gk104_privring_intr_gpc(privring, i); intr1 &= ~stat; } } @@ -97,9 +97,9 @@ gk104_ibus_intr(struct nvkm_subdev *ibus) } static int -gk104_ibus_init(struct nvkm_subdev *ibus) +gk104_privring_init(struct nvkm_subdev *privring) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; nvkm_mask(device, 0x122318, 0x0003ffff, 0x00001000); nvkm_mask(device, 0x12231c, 0x0003ffff, 0x00000200); nvkm_mask(device, 0x122310, 0x0003ffff, 0x00000800); @@ -111,15 +111,15 @@ gk104_ibus_init(struct nvkm_subdev *ibus) } static const struct nvkm_subdev_func -gk104_ibus = { - .preinit = gk104_ibus_init, - .init = gk104_ibus_init, - .intr = gk104_ibus_intr, +gk104_privring = { + .preinit = gk104_privring_init, + .init = gk104_privring_init, + .intr = gk104_privring_intr, }; int -gk104_ibus_new(struct nvkm_device *device, int index, - struct nvkm_subdev **pibus) +gk104_privring_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_subdev **pprivring) { - return nvkm_subdev_new_(&gk104_ibus, device, index, pibus); + return nvkm_subdev_new_(&gk104_privring, device, type, inst, pprivring); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk20a.c index 187d544378b0..55e4a60d8770 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk20a.c @@ -19,13 +19,13 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ -#include <subdev/ibus.h> +#include <subdev/privring.h> #include <subdev/timer.h> static void -gk20a_ibus_init_ibus_ring(struct nvkm_subdev *ibus) +gk20a_privring_init_privring_ring(struct nvkm_subdev *privring) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; nvkm_mask(device, 0x137250, 0x3f, 0); nvkm_mask(device, 0x000200, 0x20, 0); @@ -46,14 +46,14 @@ gk20a_ibus_init_ibus_ring(struct nvkm_subdev *ibus) } static void -gk20a_ibus_intr(struct nvkm_subdev *ibus) +gk20a_privring_intr(struct nvkm_subdev *privring) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; u32 status0 = nvkm_rd32(device, 0x120058); if (status0 & 0x7) { - nvkm_debug(ibus, "resetting ibus ring\n"); - gk20a_ibus_init_ibus_ring(ibus); + nvkm_debug(privring, "resetting privring ring\n"); + gk20a_privring_init_privring_ring(privring); } /* Acknowledge interrupt */ @@ -65,21 +65,21 @@ gk20a_ibus_intr(struct nvkm_subdev *ibus) } static int -gk20a_ibus_init(struct nvkm_subdev *ibus) +gk20a_privring_init(struct nvkm_subdev *privring) { - gk20a_ibus_init_ibus_ring(ibus); + gk20a_privring_init_privring_ring(privring); return 0; } static const struct nvkm_subdev_func -gk20a_ibus = { - .init = gk20a_ibus_init, - .intr = gk20a_ibus_intr, +gk20a_privring = { + .init = gk20a_privring_init, + .intr = gk20a_privring_intr, }; int -gk20a_ibus_new(struct nvkm_device *device, int index, - struct nvkm_subdev **pibus) +gk20a_privring_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_subdev **pprivring) { - return nvkm_subdev_new_(&gk20a_ibus, device, index, pibus); + return nvkm_subdev_new_(&gk20a_privring, device, type, inst, pprivring); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gm200.c index 0f1f0ad6377e..b4eaf6db36d7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gm200.c @@ -24,13 +24,13 @@ #include "priv.h" static const struct nvkm_subdev_func -gm200_ibus = { - .intr = gk104_ibus_intr, +gm200_privring = { + .intr = gk104_privring_intr, }; int -gm200_ibus_new(struct nvkm_device *device, int index, - struct nvkm_subdev **pibus) +gm200_privring_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_subdev **pprivring) { - return nvkm_subdev_new_(&gm200_ibus, device, index, pibus); + return nvkm_subdev_new_(&gm200_privring, device, type, inst, pprivring); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gp10b.c index 0347b367cefe..4534111cf907 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/gp10b.c @@ -19,14 +19,14 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ -#include <subdev/ibus.h> +#include <subdev/privring.h> #include "priv.h" static int -gp10b_ibus_init(struct nvkm_subdev *ibus) +gp10b_privring_init(struct nvkm_subdev *privring) { - struct nvkm_device *device = ibus->device; + struct nvkm_device *device = privring->device; nvkm_wr32(device, 0x1200a8, 0x0); @@ -42,14 +42,14 @@ gp10b_ibus_init(struct nvkm_subdev *ibus) } static const struct nvkm_subdev_func -gp10b_ibus = { - .init = gp10b_ibus_init, - .intr = gk104_ibus_intr, +gp10b_privring = { + .init = gp10b_privring_init, + .intr = gk104_privring_intr, }; int -gp10b_ibus_new(struct nvkm_device *device, int index, - struct nvkm_subdev **pibus) +gp10b_privring_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_subdev **pprivring) { - return nvkm_subdev_new_(&gp10b_ibus, device, index, pibus); + return nvkm_subdev_new_(&gp10b_privring, device, type, inst, pprivring); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/privring/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/priv.h new file mode 100644 index 000000000000..b378c14bc8dc --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/privring/priv.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef __NVKM_PRIVRING_PRIV_H__ +#define __NVKM_PRIVRING_PRIV_H__ +#include <subdev/privring.h> + +void gf100_privring_intr(struct nvkm_subdev *); +void gk104_privring_intr(struct nvkm_subdev *); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c index 4a4d1e224126..fc5ee118e910 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c @@ -421,10 +421,10 @@ nvkm_therm = { }; void -nvkm_therm_ctor(struct nvkm_therm *therm, struct nvkm_device *device, - int index, const struct nvkm_therm_func *func) +nvkm_therm_ctor(struct nvkm_therm *therm, struct nvkm_device *device, enum nvkm_subdev_type type, + int inst, const struct nvkm_therm_func *func) { - nvkm_subdev_ctor(&nvkm_therm, device, index, &therm->subdev); + nvkm_subdev_ctor(&nvkm_therm, device, type, inst, &therm->subdev); therm->func = func; nvkm_alarm_init(&therm->alarm, nvkm_therm_alarm); @@ -443,13 +443,13 @@ nvkm_therm_ctor(struct nvkm_therm *therm, struct nvkm_device *device, int nvkm_therm_new_(const struct nvkm_therm_func *func, struct nvkm_device *device, - int index, struct nvkm_therm **ptherm) + enum nvkm_subdev_type type, int inst, struct nvkm_therm **ptherm) { struct nvkm_therm *therm; if (!(therm = *ptherm = kzalloc(sizeof(*therm), GFP_KERNEL))) return -ENOMEM; - nvkm_therm_ctor(therm, device, index, func); + nvkm_therm_ctor(therm, device, type, inst, func); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c index 96f8da40ac82..4af86f2d3e7e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c @@ -223,12 +223,13 @@ g84_therm = { }; int -g84_therm_new(struct nvkm_device *device, int index, struct nvkm_therm **ptherm) +g84_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_therm **ptherm) { struct nvkm_therm *therm; int ret; - ret = nvkm_therm_new_(&g84_therm, device, index, &therm); + ret = nvkm_therm_new_(&g84_therm, device, type, inst, &therm); *ptherm = therm; if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c index 0981b02790e2..2b031d4eaeb6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c @@ -146,8 +146,8 @@ gf119_therm = { }; int -gf119_therm_new(struct nvkm_device *device, int index, - struct nvkm_therm **ptherm) +gf119_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_therm **ptherm) { - return nvkm_therm_new_(&gf119_therm, device, index, ptherm); + return nvkm_therm_new_(&gf119_therm, device, type, inst, ptherm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c index 4e03971d2e3d..45e295c271fb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c @@ -35,8 +35,8 @@ gk104_clkgate_enable(struct nvkm_therm *base) int i; /* Program ENG_MANT, ENG_FILTER */ - for (i = 0; order[i].engine != NVKM_SUBDEV_NR; i++) { - if (!nvkm_device_subdev(dev, order[i].engine)) + for (i = 0; order[i].type != NVKM_SUBDEV_NR; i++) { + if (!nvkm_device_subdev(dev, order[i].type, order[i].inst)) continue; nvkm_mask(dev, 0x20200 + order[i].offset, 0xff00, 0x4500); @@ -47,8 +47,8 @@ gk104_clkgate_enable(struct nvkm_therm *base) nvkm_wr32(dev, 0x02028c, therm->idle_filter->hubmmu); /* Enable clockgating (ENG_CLK = RUN->AUTO) */ - for (i = 0; order[i].engine != NVKM_SUBDEV_NR; i++) { - if (!nvkm_device_subdev(dev, order[i].engine)) + for (i = 0; order[i].type != NVKM_SUBDEV_NR; i++) { + if (!nvkm_device_subdev(dev, order[i].type, order[i].inst)) continue; nvkm_mask(dev, 0x20200 + order[i].offset, 0x00ff, 0x0045); @@ -64,8 +64,8 @@ gk104_clkgate_fini(struct nvkm_therm *base, bool suspend) int i; /* ENG_CLK = AUTO->RUN, ENG_PWR = RUN->AUTO */ - for (i = 0; order[i].engine != NVKM_SUBDEV_NR; i++) { - if (!nvkm_device_subdev(dev, order[i].engine)) + for (i = 0; order[i].type != NVKM_SUBDEV_NR; i++) { + if (!nvkm_device_subdev(dev, order[i].type, order[i].inst)) continue; nvkm_mask(dev, 0x20200 + order[i].offset, 0xff, 0x54); @@ -73,15 +73,15 @@ gk104_clkgate_fini(struct nvkm_therm *base, bool suspend) } const struct gk104_clkgate_engine_info gk104_clkgate_engine_info[] = { - { NVKM_ENGINE_GR, 0x00 }, - { NVKM_ENGINE_MSPDEC, 0x04 }, - { NVKM_ENGINE_MSPPP, 0x08 }, - { NVKM_ENGINE_MSVLD, 0x0c }, - { NVKM_ENGINE_CE0, 0x10 }, - { NVKM_ENGINE_CE1, 0x14 }, - { NVKM_ENGINE_MSENC, 0x18 }, - { NVKM_ENGINE_CE2, 0x1c }, - { NVKM_SUBDEV_NR, 0 }, + { NVKM_ENGINE_GR, 0, 0x00 }, + { NVKM_ENGINE_MSPDEC, 0, 0x04 }, + { NVKM_ENGINE_MSPPP, 0, 0x08 }, + { NVKM_ENGINE_MSVLD, 0, 0x0c }, + { NVKM_ENGINE_CE, 0, 0x10 }, + { NVKM_ENGINE_CE, 1, 0x14 }, + { NVKM_ENGINE_MSENC, 0, 0x18 }, + { NVKM_ENGINE_CE, 2, 0x1c }, + { NVKM_SUBDEV_NR }, }; const struct gf100_idle_filter gk104_idle_filter = { @@ -106,9 +106,8 @@ gk104_therm_func = { }; static int -gk104_therm_new_(const struct nvkm_therm_func *func, - struct nvkm_device *device, - int index, +gk104_therm_new_(const struct nvkm_therm_func *func, struct nvkm_device *device, + enum nvkm_subdev_type type, int inst, const struct gk104_clkgate_engine_info *clkgate_order, const struct gf100_idle_filter *idle_filter, struct nvkm_therm **ptherm) @@ -118,19 +117,17 @@ gk104_therm_new_(const struct nvkm_therm_func *func, if (!therm) return -ENOMEM; - nvkm_therm_ctor(&therm->base, device, index, func); + nvkm_therm_ctor(&therm->base, device, type, inst, func); *ptherm = &therm->base; therm->clkgate_order = clkgate_order; therm->idle_filter = idle_filter; - return 0; } int -gk104_therm_new(struct nvkm_device *device, - int index, struct nvkm_therm **ptherm) +gk104_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_therm **ptherm) { - return gk104_therm_new_(&gk104_therm_func, device, index, + return gk104_therm_new_(&gk104_therm_func, device, type, inst, gk104_clkgate_engine_info, &gk104_idle_filter, ptherm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.h b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.h index 293e7743b19b..9a8641421038 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.h @@ -31,7 +31,8 @@ #include "gf100.h" struct gk104_clkgate_engine_info { - enum nvkm_devidx engine; + enum nvkm_subdev_type type; + int inst; u8 offset; }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c index 86848ece4d89..c845fd392f58 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c @@ -68,8 +68,8 @@ gm107_therm = { }; int -gm107_therm_new(struct nvkm_device *device, int index, +gm107_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_therm **ptherm) { - return nvkm_therm_new_(&gm107_therm, device, index, ptherm); + return nvkm_therm_new_(&gm107_therm, device, type, inst, ptherm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm200.c index 73dc78093d5d..e0cdd12463ec 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm200.c @@ -32,8 +32,8 @@ gm200_therm = { }; int -gm200_therm_new(struct nvkm_device *device, int index, +gm200_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_therm **ptherm) { - return nvkm_therm_new_(&gm200_therm, device, index, ptherm); + return nvkm_therm_new_(&gm200_therm, device, type, inst, ptherm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gp100.c index 9f0dea3f61dc..44f021392b95 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gp100.c @@ -49,8 +49,8 @@ gp100_therm = { }; int -gp100_therm_new(struct nvkm_device *device, int index, +gp100_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_therm **ptherm) { - return nvkm_therm_new_(&gp100_therm, device, index, ptherm); + return nvkm_therm_new_(&gp100_therm, device, type, inst, ptherm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c index c08097f2aff5..9e451bd9395c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c @@ -68,8 +68,8 @@ gt215_therm = { }; int -gt215_therm_new(struct nvkm_device *device, int index, - struct nvkm_therm **ptherm) +gt215_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_therm **ptherm) { - return nvkm_therm_new_(>215_therm, device, index, ptherm); + return nvkm_therm_new_(>215_therm, device, type, inst, ptherm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c index 2c92ffb5f9d0..c13fee9734df 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c @@ -197,8 +197,8 @@ nv40_therm = { }; int -nv40_therm_new(struct nvkm_device *device, int index, +nv40_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_therm **ptherm) { - return nvkm_therm_new_(&nv40_therm, device, index, ptherm); + return nvkm_therm_new_(&nv40_therm, device, type, inst, ptherm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c index 9b57b433d4cf..9cf16a75a3cd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c @@ -169,8 +169,8 @@ nv50_therm = { }; int -nv50_therm_new(struct nvkm_device *device, int index, +nv50_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_therm **ptherm) { - return nvkm_therm_new_(&nv50_therm, device, index, ptherm); + return nvkm_therm_new_(&nv50_therm, device, type, inst, ptherm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h index 21659daf1864..54e960589411 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h @@ -30,10 +30,10 @@ #include <subdev/bios/gpio.h> #include <subdev/bios/perf.h> -int nvkm_therm_new_(const struct nvkm_therm_func *, struct nvkm_device *, - int index, struct nvkm_therm **); -void nvkm_therm_ctor(struct nvkm_therm *therm, struct nvkm_device *device, - int index, const struct nvkm_therm_func *func); +int nvkm_therm_new_(const struct nvkm_therm_func *, struct nvkm_device *, enum nvkm_subdev_type, + int, struct nvkm_therm **); +void nvkm_therm_ctor(struct nvkm_therm *, struct nvkm_device *, enum nvkm_subdev_type, int, + const struct nvkm_therm_func *); struct nvkm_fan { struct nvkm_therm *parent; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c index dd922033628c..8b0da0c06268 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c @@ -183,14 +183,14 @@ nvkm_timer = { int nvkm_timer_new_(const struct nvkm_timer_func *func, struct nvkm_device *device, - int index, struct nvkm_timer **ptmr) + enum nvkm_subdev_type type, int inst, struct nvkm_timer **ptmr) { struct nvkm_timer *tmr; if (!(tmr = *ptmr = kzalloc(sizeof(*tmr), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_timer, device, index, &tmr->subdev); + nvkm_subdev_ctor(&nvkm_timer, device, type, inst, &tmr->subdev); tmr->func = func; INIT_LIST_HEAD(&tmr->alarms); spin_lock_init(&tmr->lock); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c index 9ed5f64912d0..73c3776b6b83 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c @@ -33,7 +33,8 @@ gk20a_timer = { }; int -gk20a_timer_new(struct nvkm_device *device, int index, struct nvkm_timer **ptmr) +gk20a_timer_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_timer **ptmr) { - return nvkm_timer_new_(&gk20a_timer, device, index, ptmr); + return nvkm_timer_new_(&gk20a_timer, device, type, inst, ptmr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c index 7f48249f41de..0058e856b378 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c @@ -145,7 +145,8 @@ nv04_timer = { }; int -nv04_timer_new(struct nvkm_device *device, int index, struct nvkm_timer **ptmr) +nv04_timer_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_timer **ptmr) { - return nvkm_timer_new_(&nv04_timer, device, index, ptmr); + return nvkm_timer_new_(&nv04_timer, device, type, inst, ptmr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c index bb99a152f26e..7e1f8c22f2a8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c @@ -82,7 +82,8 @@ nv40_timer = { }; int -nv40_timer_new(struct nvkm_device *device, int index, struct nvkm_timer **ptmr) +nv40_timer_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_timer **ptmr) { - return nvkm_timer_new_(&nv40_timer, device, index, ptmr); + return nvkm_timer_new_(&nv40_timer, device, type, inst, ptmr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c index 3cf9ec1b1b57..c2b263721f10 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c @@ -79,7 +79,8 @@ nv41_timer = { }; int -nv41_timer_new(struct nvkm_device *device, int index, struct nvkm_timer **ptmr) +nv41_timer_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_timer **ptmr) { - return nvkm_timer_new_(&nv41_timer, device, index, ptmr); + return nvkm_timer_new_(&nv41_timer, device, type, inst, ptmr); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h index 89e97294b182..e6debe7e2fa9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h @@ -4,8 +4,8 @@ #define nvkm_timer(p) container_of((p), struct nvkm_timer, subdev) #include <subdev/timer.h> -int nvkm_timer_new_(const struct nvkm_timer_func *, struct nvkm_device *, - int index, struct nvkm_timer **); +int nvkm_timer_new_(const struct nvkm_timer_func *, struct nvkm_device *, enum nvkm_subdev_type, + int, struct nvkm_timer **); struct nvkm_timer_func { void (*init)(struct nvkm_timer *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/top/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/top/Kbuild index 438d9d78ab52..d5db845195dc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/top/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/top/Kbuild @@ -1,3 +1,4 @@ # SPDX-License-Identifier: MIT nvkm-y += nvkm/subdev/top/base.o nvkm-y += nvkm/subdev/top/gk104.o +nvkm-y += nvkm/subdev/top/ga100.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c index cce6e4e90ebf..28d0789f50fe 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c @@ -28,7 +28,8 @@ nvkm_top_device_new(struct nvkm_top *top) { struct nvkm_top_device *info = kmalloc(sizeof(*info), GFP_KERNEL); if (info) { - info->index = NVKM_SUBDEV_NR; + info->type = NVKM_SUBDEV_NR; + info->inst = -1; info->addr = 0; info->fault = -1; info->engine = -1; @@ -41,14 +42,14 @@ nvkm_top_device_new(struct nvkm_top *top) } u32 -nvkm_top_addr(struct nvkm_device *device, enum nvkm_devidx index) +nvkm_top_addr(struct nvkm_device *device, enum nvkm_subdev_type type, int inst) { struct nvkm_top *top = device->top; struct nvkm_top_device *info; if (top) { list_for_each_entry(info, &top->device, head) { - if (info->index == index) + if (info->type == type && info->inst == inst) return info->addr; } } @@ -57,14 +58,14 @@ nvkm_top_addr(struct nvkm_device *device, enum nvkm_devidx index) } u32 -nvkm_top_reset(struct nvkm_device *device, enum nvkm_devidx index) +nvkm_top_reset(struct nvkm_device *device, enum nvkm_subdev_type type, int inst) { struct nvkm_top *top = device->top; struct nvkm_top_device *info; if (top) { list_for_each_entry(info, &top->device, head) { - if (info->index == index && info->reset >= 0) + if (info->type == type && info->inst == inst && info->reset >= 0) return BIT(info->reset); } } @@ -73,14 +74,14 @@ nvkm_top_reset(struct nvkm_device *device, enum nvkm_devidx index) } u32 -nvkm_top_intr_mask(struct nvkm_device *device, enum nvkm_devidx devidx) +nvkm_top_intr_mask(struct nvkm_device *device, enum nvkm_subdev_type type, int inst) { struct nvkm_top *top = device->top; struct nvkm_top_device *info; if (top) { list_for_each_entry(info, &top->device, head) { - if (info->index == devidx && info->intr >= 0) + if (info->type == type && info->inst == inst && info->intr >= 0) return BIT(info->intr); } } @@ -88,44 +89,21 @@ nvkm_top_intr_mask(struct nvkm_device *device, enum nvkm_devidx devidx) return 0; } -u32 -nvkm_top_intr(struct nvkm_device *device, u32 intr, u64 *psubdevs) -{ - struct nvkm_top *top = device->top; - struct nvkm_top_device *info; - u64 subdevs = 0; - u32 handled = 0; - - if (top) { - list_for_each_entry(info, &top->device, head) { - if (info->index != NVKM_SUBDEV_NR && info->intr >= 0) { - if (intr & BIT(info->intr)) { - subdevs |= BIT_ULL(info->index); - handled |= BIT(info->intr); - } - } - } - } - - *psubdevs = subdevs; - return intr & ~handled; -} - int -nvkm_top_fault_id(struct nvkm_device *device, enum nvkm_devidx devidx) +nvkm_top_fault_id(struct nvkm_device *device, enum nvkm_subdev_type type, int inst) { struct nvkm_top *top = device->top; struct nvkm_top_device *info; list_for_each_entry(info, &top->device, head) { - if (info->index == devidx && info->fault >= 0) + if (info->type == type && info->inst == inst && info->fault >= 0) return info->fault; } return -ENOENT; } -enum nvkm_devidx +struct nvkm_subdev * nvkm_top_fault(struct nvkm_device *device, int fault) { struct nvkm_top *top = device->top; @@ -133,28 +111,10 @@ nvkm_top_fault(struct nvkm_device *device, int fault) list_for_each_entry(info, &top->device, head) { if (info->fault == fault) - return info->index; - } - - return NVKM_SUBDEV_NR; -} - -enum nvkm_devidx -nvkm_top_engine(struct nvkm_device *device, int index, int *runl, int *engn) -{ - struct nvkm_top *top = device->top; - struct nvkm_top_device *info; - int n = 0; - - list_for_each_entry(info, &top->device, head) { - if (info->engine >= 0 && info->runlist >= 0 && n++ == index) { - *runl = info->runlist; - *engn = info->engine; - return info->index; - } + return nvkm_device_subdev(device, info->type, info->inst); } - return -ENODEV; + return NULL; } static int @@ -186,12 +146,12 @@ nvkm_top = { int nvkm_top_new_(const struct nvkm_top_func *func, struct nvkm_device *device, - int index, struct nvkm_top **ptop) + enum nvkm_subdev_type type, int inst, struct nvkm_top **ptop) { struct nvkm_top *top; if (!(top = *ptop = kzalloc(sizeof(*top), GFP_KERNEL))) return -ENOMEM; - nvkm_subdev_ctor(&nvkm_top, device, index, &top->subdev); + nvkm_subdev_ctor(&nvkm_top, device, type, inst, &top->subdev); top->func = func; INIT_LIST_HEAD(&top->device); return 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.c new file mode 100644 index 000000000000..31933f3e5a07 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.c @@ -0,0 +1,107 @@ +/* + * Copyright 2021 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "priv.h" + +static int +ga100_top_oneinit(struct nvkm_top *top) +{ + struct nvkm_subdev *subdev = &top->subdev; + struct nvkm_device *device = subdev->device; + struct nvkm_top_device *info = NULL; + u32 data, type, inst; + int i, n, size = nvkm_rd32(device, 0x0224fc) >> 20; + + for (i = 0, n = 0; i < size; i++) { + if (!info) { + if (!(info = nvkm_top_device_new(top))) + return -ENOMEM; + type = ~0; + inst = 0; + } + + data = nvkm_rd32(device, 0x022800 + (i * 0x04)); + nvkm_trace(subdev, "%02x: %08x\n", i, data); + if (!data && n == 0) + continue; + + switch (n++) { + case 0: + type = (data & 0x3f000000) >> 24; + inst = (data & 0x000f0000) >> 16; + info->fault = (data & 0x0000007f); + break; + case 1: + info->addr = (data & 0x00fff000); + info->reset = (data & 0x0000001f); + break; + case 2: + info->runlist = (data & 0x0000fc00) >> 10; + info->engine = (data & 0x00000003); + break; + default: + break; + } + + if (data & 0x80000000) + continue; + n = 0; + + /* Translate engine type to NVKM engine identifier. */ +#define I_(T,I) do { info->type = (T); info->inst = (I); } while(0) +#define O_(T,I) do { WARN_ON(inst); I_(T, I); } while (0) + switch (type) { + case 0x00000000: O_(NVKM_ENGINE_GR , 0); break; + case 0x0000000d: O_(NVKM_ENGINE_SEC2 , 0); break; + case 0x0000000e: I_(NVKM_ENGINE_NVENC , inst); break; + case 0x00000010: I_(NVKM_ENGINE_NVDEC , inst); break; + case 0x00000012: I_(NVKM_SUBDEV_IOCTRL, inst); break; + case 0x00000013: I_(NVKM_ENGINE_CE , inst); break; + case 0x00000014: O_(NVKM_SUBDEV_GSP , 0); break; + case 0x00000015: O_(NVKM_ENGINE_NVJPG , 0); break; + case 0x00000016: O_(NVKM_ENGINE_OFA , 0); break; + case 0x00000017: O_(NVKM_SUBDEV_FLA , 0); break; + break; + default: + break; + } + + nvkm_debug(subdev, "%02x.%d (%8s): addr %06x fault %2d " + "runlist %2d engine %2d reset %2d\n", type, inst, + info->type == NVKM_SUBDEV_NR ? "????????" : nvkm_subdev_type[info->type], + info->addr, info->fault, info->runlist, info->engine, info->reset); + info = NULL; + } + + return 0; +} + +static const struct nvkm_top_func +ga100_top = { + .oneinit = ga100_top_oneinit, +}; + +int +ga100_top_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_top **ptop) +{ + return nvkm_top_new_(&ga100_top, device, type, inst, ptop); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c index 1156634533f9..4dcad97bd505 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c @@ -70,26 +70,26 @@ gk104_top_oneinit(struct nvkm_top *top) continue; /* Translate engine type to NVKM engine identifier. */ -#define A_(A) if (inst == 0) info->index = NVKM_ENGINE_##A -#define B_(A) if (inst + NVKM_ENGINE_##A##0 < NVKM_ENGINE_##A##_LAST + 1) \ - info->index = NVKM_ENGINE_##A##0 + inst -#define C_(A) if (inst == 0) info->index = NVKM_SUBDEV_##A +#define I_(T,I) do { info->type = (T); info->inst = (I); } while(0) +#define O_(T,I) do { WARN_ON(inst); I_(T, I); } while (0) switch (type) { - case 0x00000000: A_(GR ); break; - case 0x00000001: A_(CE0 ); break; - case 0x00000002: A_(CE1 ); break; - case 0x00000003: A_(CE2 ); break; - case 0x00000008: A_(MSPDEC); break; - case 0x00000009: A_(MSPPP ); break; - case 0x0000000a: A_(MSVLD ); break; - case 0x0000000b: A_(MSENC ); break; - case 0x0000000c: A_(VIC ); break; - case 0x0000000d: A_(SEC2 ); break; - case 0x0000000e: B_(NVENC ); break; - case 0x0000000f: A_(NVENC1); break; - case 0x00000010: B_(NVDEC ); break; - case 0x00000013: B_(CE ); break; - case 0x00000014: C_(GSP ); break; + case 0x00000000: O_(NVKM_ENGINE_GR , 0); break; + case 0x00000001: O_(NVKM_ENGINE_CE , 0); break; + case 0x00000002: O_(NVKM_ENGINE_CE , 1); break; + case 0x00000003: O_(NVKM_ENGINE_CE , 2); break; + case 0x00000008: O_(NVKM_ENGINE_MSPDEC, 0); break; + case 0x00000009: O_(NVKM_ENGINE_MSPPP , 0); break; + case 0x0000000a: O_(NVKM_ENGINE_MSVLD , 0); break; + case 0x0000000b: O_(NVKM_ENGINE_MSENC , 0); break; + case 0x0000000c: O_(NVKM_ENGINE_VIC , 0); break; + case 0x0000000d: O_(NVKM_ENGINE_SEC2 , 0); break; + case 0x0000000e: I_(NVKM_ENGINE_NVENC , inst); break; + case 0x0000000f: O_(NVKM_ENGINE_NVENC , 1); break; + case 0x00000010: I_(NVKM_ENGINE_NVDEC , inst); break; + case 0x00000012: I_(NVKM_SUBDEV_IOCTRL, inst); break; + case 0x00000013: I_(NVKM_ENGINE_CE , inst); break; + case 0x00000014: O_(NVKM_SUBDEV_GSP , 0); break; + case 0x00000015: O_(NVKM_ENGINE_NVJPG , 0); break; default: break; } @@ -97,8 +97,7 @@ gk104_top_oneinit(struct nvkm_top *top) nvkm_debug(subdev, "%02x.%d (%8s): addr %06x fault %2d " "engine %2d runlist %2d intr %2d " "reset %2d\n", type, inst, - info->index == NVKM_SUBDEV_NR ? NULL : - nvkm_subdev_name[info->index], + info->type == NVKM_SUBDEV_NR ? "????????" : nvkm_subdev_type[info->type], info->addr, info->fault, info->engine, info->runlist, info->intr, info->reset); info = NULL; @@ -113,7 +112,8 @@ gk104_top = { }; int -gk104_top_new(struct nvkm_device *device, int index, struct nvkm_top **ptop) +gk104_top_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_top **ptop) { - return nvkm_top_new_(&gk104_top, device, index, ptop); + return nvkm_top_new_(&gk104_top, device, type, inst, ptop); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/top/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/top/priv.h index a16baa2941cf..8e103a836705 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/top/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/top/priv.h @@ -8,19 +8,8 @@ struct nvkm_top_func { int (*oneinit)(struct nvkm_top *); }; -int nvkm_top_new_(const struct nvkm_top_func *, struct nvkm_device *, - int, struct nvkm_top **); - -struct nvkm_top_device { - enum nvkm_devidx index; - u32 addr; - int fault; - int engine; - int runlist; - int reset; - int intr; - struct list_head head; -}; +int nvkm_top_new_(const struct nvkm_top_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_top **); struct nvkm_top_device *nvkm_top_device_new(struct nvkm_top *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c index e344901cfdc7..a17a6dd8d3de 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c @@ -281,12 +281,12 @@ nvkm_volt = { void nvkm_volt_ctor(const struct nvkm_volt_func *func, struct nvkm_device *device, - int index, struct nvkm_volt *volt) + enum nvkm_subdev_type type, int inst, struct nvkm_volt *volt) { struct nvkm_bios *bios = device->bios; int i; - nvkm_subdev_ctor(&nvkm_volt, device, index, &volt->subdev); + nvkm_subdev_ctor(&nvkm_volt, device, type, inst, &volt->subdev); volt->func = func; /* Assuming the non-bios device should build the voltage table later */ @@ -319,10 +319,10 @@ nvkm_volt_ctor(const struct nvkm_volt_func *func, struct nvkm_device *device, int nvkm_volt_new_(const struct nvkm_volt_func *func, struct nvkm_device *device, - int index, struct nvkm_volt **pvolt) + enum nvkm_subdev_type type, int inst, struct nvkm_volt **pvolt) { if (!(*pvolt = kzalloc(sizeof(**pvolt), GFP_KERNEL))) return -ENOMEM; - nvkm_volt_ctor(func, device, index, *pvolt); + nvkm_volt_ctor(func, device, type, inst, *pvolt); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf100.c index d9ed6925ca64..b47a1c0817be 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf100.c @@ -56,12 +56,13 @@ gf100_volt = { }; int -gf100_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) +gf100_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_volt **pvolt) { struct nvkm_volt *volt; int ret; - ret = nvkm_volt_new_(&gf100_volt, device, index, &volt); + ret = nvkm_volt_new_(&gf100_volt, device, type, inst, &volt); *pvolt = volt; if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf117.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf117.c index 547a58f0aeac..03c8a2c2916c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf117.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf117.c @@ -46,12 +46,13 @@ gf117_volt = { }; int -gf117_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) +gf117_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_volt **pvolt) { struct nvkm_volt *volt; int ret; - ret = nvkm_volt_new_(&gf117_volt, device, index, &volt); + ret = nvkm_volt_new_(&gf117_volt, device, type, inst, &volt); *pvolt = volt; if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c index 1c744e029454..d1ce4309cfb8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c @@ -95,7 +95,8 @@ gk104_volt_pwm = { }; int -gk104_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) +gk104_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_volt **pvolt) { const struct nvkm_volt_func *volt_func = &gk104_volt_gpio; struct dcb_gpio_func gpio; @@ -114,7 +115,7 @@ gk104_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) if (!(volt = kzalloc(sizeof(*volt), GFP_KERNEL))) return -ENOMEM; - nvkm_volt_ctor(volt_func, device, index, &volt->base); + nvkm_volt_ctor(volt_func, device, type, inst, &volt->base); *pvolt = &volt->base; volt->bios = bios; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c index ce5d83cdc7cf..8c2faa964511 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c @@ -144,14 +144,14 @@ gk20a_volt = { }; int -gk20a_volt_ctor(struct nvkm_device *device, int index, +gk20a_volt_ctor(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, const struct cvb_coef *coefs, int nb_coefs, int vmin, struct gk20a_volt *volt) { struct nvkm_device_tegra *tdev = device->func->tegra(device); int i, uv; - nvkm_volt_ctor(&gk20a_volt, device, index, &volt->base); + nvkm_volt_ctor(&gk20a_volt, device, type, inst, &volt->base); uv = regulator_get_voltage(tdev->vdd); nvkm_debug(&volt->base.subdev, "the default voltage is %duV\n", uv); @@ -172,7 +172,7 @@ gk20a_volt_ctor(struct nvkm_device *device, int index, } int -gk20a_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) +gk20a_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_volt **pvolt) { struct gk20a_volt *volt; @@ -181,6 +181,6 @@ gk20a_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) return -ENOMEM; *pvolt = &volt->base; - return gk20a_volt_ctor(device, index, gk20a_cvb_coef, + return gk20a_volt_ctor(device, type, inst, gk20a_cvb_coef, ARRAY_SIZE(gk20a_cvb_coef), 0, volt); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.h b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.h index 6a6c97f9684e..01f8a5fcf496 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.h @@ -37,7 +37,7 @@ struct gk20a_volt { struct regulator *vdd; }; -int gk20a_volt_ctor(struct nvkm_device *device, int index, +int gk20a_volt_ctor(struct nvkm_device *device, enum nvkm_subdev_type, int, const struct cvb_coef *coefs, int nb_coefs, int vmin, struct gk20a_volt *volt); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gm20b.c index 2925b9cae681..c2e9694d333f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gm20b.c @@ -64,7 +64,8 @@ static const u32 speedo_to_vmin[] = { }; int -gm20b_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) +gm20b_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_volt **pvolt) { struct nvkm_device_tegra *tdev = device->func->tegra(device); struct gk20a_volt *volt; @@ -84,9 +85,9 @@ gm20b_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) vmin = speedo_to_vmin[tdev->gpu_speedo_id]; if (tdev->gpu_speedo_id >= 1) - return gk20a_volt_ctor(device, index, gm20b_na_cvb_coef, - ARRAY_SIZE(gm20b_na_cvb_coef), vmin, volt); + return gk20a_volt_ctor(device, type, inst, gm20b_na_cvb_coef, + ARRAY_SIZE(gm20b_na_cvb_coef), vmin, volt); else - return gk20a_volt_ctor(device, index, gm20b_cvb_coef, - ARRAY_SIZE(gm20b_cvb_coef), vmin, volt); + return gk20a_volt_ctor(device, type, inst, gm20b_cvb_coef, + ARRAY_SIZE(gm20b_cvb_coef), vmin, volt); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.c index 23409387abb5..d6a587d6082d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.c @@ -30,12 +30,13 @@ nv40_volt = { }; int -nv40_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) +nv40_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, + struct nvkm_volt **pvolt) { struct nvkm_volt *volt; int ret; - ret = nvkm_volt_new_(&nv40_volt, device, index, &volt); + ret = nvkm_volt_new_(&nv40_volt, device, type, inst, &volt); *pvolt = volt; if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/priv.h index 75f13a34671f..24e2d16d1913 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/priv.h @@ -4,10 +4,10 @@ #define nvkm_volt(p) container_of((p), struct nvkm_volt, subdev) #include <subdev/volt.h> -void nvkm_volt_ctor(const struct nvkm_volt_func *, struct nvkm_device *, - int index, struct nvkm_volt *); -int nvkm_volt_new_(const struct nvkm_volt_func *, struct nvkm_device *, - int index, struct nvkm_volt **); +void nvkm_volt_ctor(const struct nvkm_volt_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_volt *); +int nvkm_volt_new_(const struct nvkm_volt_func *, struct nvkm_device *, enum nvkm_subdev_type, int, + struct nvkm_volt **); struct nvkm_volt_func { int (*oneinit)(struct nvkm_volt *); diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 8becbe09af2f..bfacf8fe5cc1 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -2478,6 +2478,9 @@ int radeon_asic_init(struct radeon_device *rdev) if (rdev->family == CHIP_HAINAN) { rdev->has_uvd = false; rdev->has_vce = false; + } else if (rdev->family == CHIP_OLAND) { + rdev->has_uvd = true; + rdev->has_vce = false; } else { rdev->has_uvd = true; rdev->has_vce = true; diff --git a/drivers/gpu/drm/radeon/radeon_vce.c b/drivers/gpu/drm/radeon/radeon_vce.c index a450497368b2..511a942e851d 100644 --- a/drivers/gpu/drm/radeon/radeon_vce.c +++ b/drivers/gpu/drm/radeon/radeon_vce.c @@ -68,7 +68,6 @@ int radeon_vce_init(struct radeon_device *rdev) case CHIP_TAHITI: case CHIP_PITCAIRN: case CHIP_VERDE: - case CHIP_OLAND: case CHIP_ARUBA: fw_name = FIRMWARE_TAHITI; break; diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c index c296f94f9700..7bc302a89232 100644 --- a/drivers/gpu/drm/radeon/rs690.c +++ b/drivers/gpu/drm/radeon/rs690.c @@ -187,7 +187,7 @@ static void rs690_mc_init(struct radeon_device *rdev) /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport * memory is present. */ - if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { + if (!rdev->mc.igp_sideport_enabled && radeon_fastfb == 1) { DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n", (unsigned long long)rdev->mc.aper_base, k8_addr); rdev->mc.aper_base = (resource_size_t)k8_addr; diff --git a/drivers/gpu/drm/radeon/vce_v1_0.c b/drivers/gpu/drm/radeon/vce_v1_0.c index 70c5da2141d7..bdfbcf14b864 100644 --- a/drivers/gpu/drm/radeon/vce_v1_0.c +++ b/drivers/gpu/drm/radeon/vce_v1_0.c @@ -169,7 +169,6 @@ int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data) chip_id = 0x01000015; break; case CHIP_PITCAIRN: - case CHIP_OLAND: chip_id = 0x01000016; break; case CHIP_ARUBA: |