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2022-07-08ARM: dts: colibri-imx6ull: fix snvs pinmux groupMax Krummenacher
A pin controlled by the iomuxc-snvs pin controller must be specified under the dtb's iomuxc-snvs node. Move the one and only pin of that category from the iomuxc node and set the pinctrl-0 using it accordingly. Fixes: 2aa9d6201949 ("ARM: dts: imx6ull-colibri: add touchscreen device nodes") Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-07-08Merge tag 'zynq-dt-for-v5.20' of https://github.com/Xilinx/linux-xlnx into ↵Arnd Bergmann
arm/dt ARM: Zynq DT changes for v5.20 - Align gpio-keys node names with dtschema * tag 'zynq-dt-for-v5.20' of https://github.com/Xilinx/linux-xlnx: ARM: dts: xilinx: align gpio-key node names with dtschema Link: https://lore.kernel.org/r/87d2bd4a-b90d-6396-17c5-c95ac64d17d0@monstr.eu Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-07arm64: dts: renesas: Prepare AA1024XD12 panel .dtsi for overlay supportLaurent Pinchart
The Mitsubishi AA1024XD12 panel can be used for R-Car Gen2 and Gen3 boards as an optional external panel. It is described in the arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi file as a direct child of the DT root node. This allows including r8a77xx-aa104xd12-panel.dtsi in board device trees, with other minor modifications, to enable the panel. This is however not how external components should be modelled. Instead of modifying the board device tree to enable the panel, it should be compiled as a DT overlay, to be loaded by the boot loader. Prepare the r8a77xx-aa104xd12-panel.dtsi file for this usage by declaring a panel node only, without hardcoding its path. Overlay sources can then include r8a77xx-aa104xd12-panel.dtsi where appropriate. This change doesn't cause any regression as r8a77xx-aa104xd12-panel.dtsi is currently unused. As overlay support for this panel has only been tested with Gen3 hardware, and Gen2 support will require more development, move the file to arch/arm64/boot/dts/renesas/. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Link: https://lore.kernel.org/r/20211229193135.28767-2-laurent.pinchart+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-07Merge tag 'samsung-dt-5.20-2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Samsung DTS ARM changes for v5.20, part two 1. Cleanups: align SDHCI node names. 2. DT bindings: Document preferred compatible naming schema. 3. DT bindings: fixes and improvements to Exynos PMU bindings. * tag 'samsung-dt-5.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: dt-bindings: soc: samsung: exynos-pmu: add reboot-mode dt-bindings: soc: samsung: exynos-pmu: use abolute ref paths dt-bindings: soc: samsung: exynos-pmu: cleanup assigned clocks dt-bindings: samsung: document preferred compatible naming ARM: dts: s5pv210: align SDHCI node name with dtschema ARM: dts: s3c64xx: align SDHCI node name with dtschema ARM: dts: s3c24xx: align SDHCI node name with dtschema ARM: dts: exynos: align SDHCI node name with dtschema Link: https://lore.kernel.org/r/20220707080408.69251-1-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-06ARM: dts: qcom: msm8974: rename GPU's OPP table nodeDmitry Baryshkov
Rename the GPU's opp table node to make it follow the display/msm/gpu.yaml schema. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706145412.1566011-6-dmitry.baryshkov@linaro.org
2022-07-06ARM: dts: qcom: apq8064: disable DSI and DSI PHY by defaultDmitry Baryshkov
Disable DSI and DSI PHY devices by default. The only actual user, Nexus 7, already contains `status = "okay"` property in the respective devices nodes. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706145412.1566011-5-dmitry.baryshkov@linaro.org
2022-07-06ARM: dts: qcom: apq8064: rename DSI PHY iface clockDmitry Baryshkov
Follow the usual scheme and use name 'iface' rather than 'iface_clk' for the interface clock. The DSI PHY driver can cope with both of them, so there is no breakage. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706145412.1566011-4-dmitry.baryshkov@linaro.org
2022-07-06ARM: dts: qcom: extend scm compatible to match dt-schemaDavid Heidelberg
First device specific compatible, then general one. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220626183247.142776-1-david@ixit.cz
2022-07-06Merge tag 'dt-cleanup-5.20-2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Cleanup of ARM DTS for v5.20, part two Series of cleanups for ARM DTS - white-spaces, gpio-key subnode names and gpio-key properties for more boards: TI, Marvell, AT91 and Aspeed. * tag 'dt-cleanup-5.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: aspeed: correct gpio-keys properties ARM: dts: aspeed: align gpio-key node names with dtschema ARM: dts: at91: drop unneeded status from gpio-keys ARM: dts: at91: correct gpio-keys properties ARM: dts: at91: align gpio-key node names with dtschema ARM: dts: omap: correct gpio-keys properties ARM: dts: omap: align gpio-key node names with dtschema ARM: dts: marvell: correct gpio-keys properties ARM: dts: marvell: align gpio-key node names with dtschema ARM: dts: omap: adjust whitespace around '=' ARM: dts: ti: adjust whitespace around '=' Link: https://lore.kernel.org/r/20220706163754.33064-2-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-06Merge tag 'stm32-dt-for-v5.20-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt STM32 DT for v5.20, round 1 Highlights: ---------- - MCU: -Fix whitespace coding style. No functional changes. - MPU: - General: - Remove specific IPCC wakeup interrupt on STM32MP15. - Enable OPTEE firmware and scmi support (clock/reset) on STM32MP13. It allows to enable RCC clock driver. - Add new pins configurations groups. - DH boards: - Add DHCOR based DRC Compact board. It embeds: 2xETH, 1xCAN, uSD, USB, eMMC and SDIO wifi. - Add ST MIPID02 bindings to AV96 (not enabled by default) - OSD32: - Correct vcc-supply for eeprom. - fix missing internally connected voltage regulator (ldo3 supplied by vdd_ddr). * tag 'stm32-dt-for-v5.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (25 commits) ARM: dts: stm32: Add ST MIPID02 bindings to AV96 ARM: dts: stm32: Add alternate pinmux for RCC pin ARM: dts: stm32: Add alternate pinmux for DCMI pins ARM: dts: stm32: Add DHCOR based DRC Compact board ARM: dts: stm32: Add alternate pinmux for UART5 pins ARM: dts: stm32: Add alternate pinmux for UART4 pins ARM: dts: stm32: Add alternate pinmux for UART3 pins ARM: dts: stm32: Add alternate pinmux for SPI2 pins ARM: dts: stm32: Add alternate pinmux for CAN1 pins dt-bindings: arm: stm32: Add compatible string for DH electronics DHCOR DRC Compact ARM: dts: stm32: Fix SPI2 pinmux pin comments on stm32mp15 ARM: dts: stm32: add optee reserved memory on stm32mp135f-dk ARM: dts: stm32: add RCC on STM32MP13x SoC family ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP13 dt-bindings: rcc: stm32: select the "secure" path for stm32mp13 ARM: dts: stm32: correct vcc-supply for eeprom on stm32mp15xx-osd32 ARM: dts: stm32: fix missing internally connected voltage regulator for OSD32MP1 ARM: dts: stm32: adjust whitespace around '=' on MCU boards ARM: dts: stm32: Move DHCOR BUCK3 VDD 2V9 adjustment to 1V8 DTSI ARM: dts: stm32: remove the IPCC "wakeup" IRQ on stm32mp151 ... Link: https://lore.kernel.org/r/a250f32b-f67c-2922-0748-e39dc791e95c@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-06Merge tag 'at91-dt-5.20' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt AT91 DT for v5.20 It contains: - compilation warning fixes for SAMA5D2 - updates for all AT91 device tree to use generic name for reset controller - reset controller node for SAMA7G5 - MCAN1 and UDPHS nodes for LAN966 SoCs - Flexcom3 bindings were updated for lan966x-pcb8291.dts board to cope with reality * tag 'at91-dt-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: dts: lan966x: Add UDPHS support dt-bindings: usb: atmel: Add Microchip LAN9662 compatible string ARM: dts: lan966x: Cleanup flexcom3 usart pinctrl settings. ARM: dts: lan966x: Add mcan1 node. ARM: dts: at91: sama7g5: add reset-controller node ARM: dts: at91: use generic name for reset controller ARM: dts: at91: sama5d2: fix compilation warning ARM: dts: at91: sama5d2: fix compilation warning Link: https://lore.kernel.org/r/20220705084637.818216-1-claudiu.beznea@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-06Merge tag 'ux500-dts-v5.20' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into arm/dt Ux500 DTS updates for the v5.20 kernel: - Fix orientation matrices on a few U8500 mobile phones. - Drop unused i2c power supply handled by the power domain. * tag 'ux500-dts-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik: ARM: dts: ux500: Drop unused i2c power domain supply ARM: dts: ux500: Fix Gavini accelerometer mounting matrix ARM: dts: ux500: Fix Codina accelerometer mounting matrix ARM: dts: ux500: Fix Janice accelerometer mounting matrix Link: https://lore.kernel.org/r/CACRpkdY1MG=HG+tOCmD1_LEAStV1-ycCLkwShMRD4R=4jGDYHQ@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-06Merge tag 'v5.20-rockchip-dts32-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt NFC flash node on rk3066a-mk808 and some dts styling fixes (alignment and node names). * tag 'v5.20-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: correct gpio-keys properties on rk3288-tinker ARM: dts: rockchip: align gpio-key node names with dtschema ARM: dts: rockchip: adjust whitespace around '=' ARM: dts: rockchip: enable nfc node in rk3066a-mk808.dts Link: https://lore.kernel.org/r/14795241.VsHLxoZxqI@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-05ARM: dts: sun8i-r40: Add thermal trip points/cooling mapsqianfan Zhao
For the trip points, I used values from the BSP code. The critical trip point value is 30°C above the maximum recommended ambient temperature (85°C) for the SoC from the datasheet, so there's some headroom even at such a high ambient temperature. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Tested-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220517013607.2252-4-qianfanguijin@163.com
2022-07-05ARM: dts: sun8i-r40: add opp table for cpuqianfan Zhao
OPP table value is get from allwinner lichee linux-3.10 kernel driver Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Tested-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220517013607.2252-3-qianfanguijin@163.com
2022-07-05ARM: dts: sun8i-r40: Add "cpu-supply" node for sun8i-r40 based boardqianfan Zhao
The CPU of sun8i-r40 is powered by PMIC, let's add "cpu-supply" node. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Tested-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220517013607.2252-2-qianfanguijin@163.com
2022-07-05Merge branch 'for-v5.20/aspeed-dts-cleanup' into for-v5.20/dts-cleanupKrzysztof Kozlowski
2022-07-05ARM: dts: aspeed: correct gpio-keys propertiesKrzysztof Kozlowski
gpio-keys children do not use unit addresses. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220616005333.18491-37-krzysztof.kozlowski@linaro.org
2022-07-05ARM: dts: aspeed: align gpio-key node names with dtschemaKrzysztof Kozlowski
The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220616005333.18491-36-krzysztof.kozlowski@linaro.org
2022-07-05ARM: dts: stm32: Add ST MIPID02 bindings to AV96Marek Vasut
Add DT bindings for ST MIPID02 and DCMI to Avenger96 base DT. Both the ST MIPID02 and DCMI are disabled by default, as the AV96 camera module is optional. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add alternate pinmux for RCC pinMarek Vasut
Add another mux option for RCC pin, this is used on AV96 board for e.g. sensor clock supply. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add alternate pinmux for DCMI pinsMarek Vasut
Add another mux option for DCMI pins, this is used on AV96 board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add DHCOR based DRC Compact boardMarek Vasut
Add DT for DH DRC Compact unit, which is a universal controller device. The system has two ethernet ports, one CAN, RS485 and RS232, USB, uSD card slot, eMMC and SDIO Wi-Fi. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add alternate pinmux for UART5 pinsMarek Vasut
Add another mux option for UART5 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add alternate pinmux for UART4 pinsMarek Vasut
Add another mux option for UART4 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add alternate pinmux for UART3 pinsMarek Vasut
Add another mux option for UART3 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add alternate pinmux for SPI2 pinsMarek Vasut
Add another mux option for SPI2 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add alternate pinmux for CAN1 pinsMarek Vasut
Add another mux option for CAN1 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Fix SPI2 pinmux pin comments on stm32mp15Marek Vasut
Those pin comments refer to SPI2 pins, not SPI1 pins, update the comments. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: lan966x: Add UDPHS supportHerve Codina
Add UDPHS (the USB High Speed Device Port controller) support. The both lan966x SOCs (LAN9662 and LAN9668) have the same UDPHS IP. This IP is also the same as the one present in the SAMA5D3 SOC. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220704102845.168438-4-herve.codina@bootlin.com
2022-07-05ARM: dts: stm32: add optee reserved memory on stm32mp135f-dkGabriel Fernandez
Add the static OP-TEE reserved memory regions. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: add RCC on STM32MP13x SoC familyGabriel Fernandez
Enables Reset and Clocks Controller on STM32MP13 Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP13Gabriel Fernandez
Enable optee and SCMI clocks support. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: correct vcc-supply for eeprom on stm32mp15xx-osd32Leonard Göhrs
According to the OSD32MP1 Power System overview[1] the EEPROM is connected to the VDD line and not to some single-purpose fixed regulator. Set the EEPROM supply according to the diagram to eliminate this parent-less regulator. [1]: https://octavosystems.com/app_notes/osd32mp1-power-system-overview/#connections Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de> Acked-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: fix missing internally connected voltage regulator for OSD32MP1Leonard Göhrs
According to the OSD32MP1 Power System overview[1] ldo3's input is always internally connected to vdd_ddr. [1]: https://octavosystems.com/app_notes/osd32mp1-power-system-overview/#connections Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: adjust whitespace around '=' on MCU boardsKrzysztof Kozlowski
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Move DHCOR BUCK3 VDD 2V9 adjustment to 1V8 DTSIMarek Vasut
The Buck3 on DHCOR is used to supply IO voltage. It can output either 3V3 in the default DHCOR configuration, or 2V9 in case of AV96 DHCOR variant which has extra Empirion DCDC converter in front of the 1V8 IO supply, or outright 1V8 in case of 1V8 IO DHCOR without the Empirion DCDC converter. The 2V9 mode in case of AV96 DHCOR variant is used to reduce unnecessarily high input voltage to the Empirion DCDC converter, so move it into matching DTSI to stop confusing users. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: remove the IPCC "wakeup" IRQ on stm32mp151Fabien Dessenne
The stm32 ipcc mailbox driver supports only two interrupts (rx and tx), so remove the unsupported "wakeup" one. Note that the EXTI interrupt 61 has two roles : it is hierarchically linked to the GIC IPCC "rx" interrupt, and it acts as a wakeup source. Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: lan966x: Cleanup flexcom3 usart pinctrl settings.Kavyasree Kotagiri
On pcb8291, Flexcom3 usart has only tx and rx pins. Cleaningup usart3 pinctrl settings. Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220704135809.6952-1-kavyasree.kotagiri@microchip.com
2022-07-05ARM: dts: imx6qdl-ts7970: Fix ngpio typo and countKris Bahnsen
Device-tree incorrectly used "ngpio" which caused the driver to fallback to 32 ngpios. This platform has 62 GPIO registers. Fixes: 9ff8e9fccef9 ("ARM: dts: TS-7970: add basic device tree") Signed-off-by: Kris Bahnsen <kris@embeddedTS.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-07-05ARM: dts: layerscape: Add SFP node for TA 2.1 devicesSean Anderson
This adds an appropriate SFP node for Trust Architecture 2.1 devices. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-07-05ARM: dts: ux500: Drop unused i2c power domain supplyLinus Walleij
This regulator supply is replaced by the proper power domain. Reported-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220701225339.814962-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-04Merge tag 'omap-for-v5.20/dt-signed' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt Devicetree changes omaps for v5.20 merge window Just one devicetree change to add EEPROM regulator for BeagleBone Black. * tag 'omap-for-v5.20/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: am33xx: Map baseboard EEPROM on BeagleBone Black Link: https://lore.kernel.org/r/pull-1656918942-515224@atomide.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-04Merge tag 'stm32-dt-for-v5.19-fixes-2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/fixes STM32 DT fixes for v5.19, round 2 Highlights: ----------- -Fixes STM32MP15: - Add missing usbh clock and fix clk order for usbh to avoid PLL issue. - Fix SCMI version: use scmi regulator and update missing SCMI clocks to be able to correcly boot. * tag 'stm32-dt-for-v5.19-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: ARM: dts: stm32: add missing usbh clock and fix clk order on stm32mp15 ARM: dts: stm32: delete fixed clock node on STM32MP15-SCMI ARM: dts: stm32: DSI should use LSE SCMI clock on DK1/ED1 STM32 board ARM: dts: stm32: use the correct clock source for CEC on stm32mp151 ARM: dts: stm32: fix pwr regulators references to use scmi Link: https://lore.kernel.org/r/1259e082-a3a4-96a5-ec9c-05dbb893a746@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-04ARM: dts: stm32: add missing usbh clock and fix clk order on stm32mp15Fabrice Gasnier
The USBH composed of EHCI and OHCI controllers needs the PHY clock to be initialized first, before enabling (gating) them. The reverse is also required when going to suspend. So, add USBPHY clock as 1st entry in both controllers, so the USBPHY PLL gets enabled 1st upon controller init. Upon suspend/resume, this also makes the clock to be disabled/re-enabled in the correct order. This fixes some IRQ storm conditions seen when going to low-power, due to PHY PLL being disabled before all clocks are cleanly gated. Fixes: 949a0c0dec85 ("ARM: dts: stm32: add USB Host (USBH) support to stm32mp157c") Fixes: db7be2cb87ae ("ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151") Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-04ARM: dts: stm32: delete fixed clock node on STM32MP15-SCMIGabriel Fernandez
Delete the node fixed clock managed by secure world with SCMI. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-04ARM: dts: stm32: DSI should use LSE SCMI clock on DK1/ED1 STM32 boardGabriel Fernandez
LSE clock is provided by SCMI. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-04ARM: dts: stm32: use the correct clock source for CEC on stm32mp151Gabriel Fernandez
The peripheral clock of CEC is not LSE but CEC. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-04ARM: dts: stm32: fix pwr regulators references to use scmiEtienne Carriere
Fixes stm32mp15*-scmi DTS files introduced in [1] to also access PWR regulators through SCMI service. This is needed since enabling secure only access to RCC clock and reset controllers also enables secure access only on PWR voltage regulators reg11, reg18 and usb33 hence these must also be accessed through SCMI Voltage Domain protocol. This change applies on commit [2] that already corrects issues from commit [1]. Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Link: [1] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-7-alexandre.torgue@foss.st.com Link: [2] https://lore.kernel.org/linux-arm-kernel/20220613071920.5463-1-alexandre.torgue@foss.st.com Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-04ARM: dts: lan966x: Add mcan1 node.Kavyasree Kotagiri
Add the mcan1 node. By default, keep it disabled. Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220627110552.26315-1-kavyasree.kotagiri@microchip.com
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