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path: root/drivers/clk/socfpga/clk-gate.c
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2022-01-05clk: socfpga: remove redundant assignment after a mask operationColin Ian King
The assignment operation after a & mask operation is redundant, the variables being assigned are not used afterwards. Replace the &= operator with just & operator. Cleans up two clang-scan warnings: drivers/clk/socfpga/clk-gate.c:37:10: warning: Although the value stored to 'l4_src' is used in the enclosing expression, the value is never actually read from 'l4_src' [deadcode.DeadStores] return l4_src &= 0x1; ^ ~~~ drivers/clk/socfpga/clk-gate.c:46:10: warning: Although the value stored to 'perpll_src' is used in the enclosing expression, the value is never actually read from 'perpll_src' [deadcode.DeadStores] return perpll_src &= 0x3; Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Link: https://lore.kernel.org/r/20211230150321.167576-1-colin.i.king@gmail.com Acked-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-04-27Merge branches 'clk-cleanup', 'clk-renesas', 'clk-socfpga', 'clk-allwinner' ↵Stephen Boyd
and 'clk-qcom' into clk-next - Use clk_hw pointers in socfpga driver - Cleanup parent data in qcom clk drivers * clk-cleanup: clk: Drop double "if" in clk_core_determine_round_nolock() comment clk: at91: Trivial typo fixes in the file sama7g5.c clk: use clk_core_enable_lock() a bit more * clk-renesas: clk: renesas: Zero init clk_init_data clk: renesas: Couple of spelling fixes clk: renesas: r8a779a0: Add CMT clocks clk: renesas: r8a7795: Add TMU clocks clk: renesas: r8a779a0: Add TSC clock clk: renesas: r8a779a0: Add TMU clocks clk: renesas: r8a77965: Add DAB clock clk: renesas: r8a77990: Add DAB clock * clk-socfpga: clk: socfpga: remove redundant initialization of variable div clk: socfpga: arria10: Fix memory leak of socfpga_clk on error return clk: socfpga: Fix code formatting clk: socfpga: Convert to s10/agilex/n5x to use clk_hw clk: socfpga: arria10: convert to use clk_hw clk: socfpga: use clk_hw_register for a5/c5 * clk-allwinner: clk: sunxi: Demote non-conformant kernel-doc headers clk: sunxi-ng: v3s: use sigma-delta modulation for audio-pll * clk-qcom: (45 commits) clk: qcom: rpmh: add support for SDX55 rpmh IPA clock clk: qcom: gcc-sdm845: get rid of the test clock clk: qcom: convert SDM845 Global Clock Controller to parent_data dt-bindings: clock: separate SDM845 GCC clock bindings clk: qcom: apss-ipq-pll: Add missing MODULE_DEVICE_TABLE clk: qcom: a53-pll: Add missing MODULE_DEVICE_TABLE clk: qcom: a7-pll: Add missing MODULE_DEVICE_TABLE clk: qcom: gcc-sm8350: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-sm8250: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-sm8150: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-sc8180x: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-sc7180: use ARRAY_SIZE instead of specifying num_parents clk: qcom: videocc-sm8250: use parent_hws where possible clk: qcom: videocc-sm8150: use parent_hws where possible clk: qcom: gpucc-sm8250: use parent_hws where possible clk: qcom: gpucc-sm8150: use parent_hws where possible clk: qcom: gcc-sm8350: use parent_hws where possible clk: qcom: gcc-sm8250: use parent_hws where possible clk: qcom: gcc-sm8150: use parent_hws where possible clk: qcom: gcc-sdx55: use parent_hws where possible ...
2021-03-30clk: socfpga: use clk_hw_register for a5/c5Dinh Nguyen
As recommended by Stephen Boyd, convert the cyclone5/arria5 clock driver to use the clk_hw registration method. Suggested-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210302214151.1333447-1-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-03-29clk: socfpga: fix iomem pointer cast on 64-bitKrzysztof Kozlowski
Pointers should be cast with uintptr_t instead of integer. This fixes warning when compile testing on ARM64: drivers/clk/socfpga/clk-gate.c: In function ‘socfpga_clk_recalc_rate’: drivers/clk/socfpga/clk-gate.c:102:7: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] Fixes: b7cec13f082f ("clk: socfpga: Look for the GPIO_DB_CLK by its offset") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210314110709.32599-1-krzysztof.kozlowski@canonical.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-16clk: socfpga: deindent code to proper indentationStephen Boyd
This code is indented oddly, causing checkpatch to complain. Indent it properly. Cc: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190814002402.18154-1-sboyd@kernel.org Acked-by: Dinh Nguyen <dinguyen@kernel.org>
2019-08-16clk: socfpga: Don't reference clk_init_data after registrationStephen Boyd
A future patch is going to change semantics of clk_register() so that clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid referencing this member here so that we don't run into NULL pointer exceptions. Cc: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190731193517.237136-7-sboyd@kernel.org Acked-by: Dinh Nguyen <dinguyen@kernel.org>
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner
Based on 3 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version [author] [kishon] [vijay] [abraham] [i] [kishon]@[ti] [com] this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version [author] [graeme] [gregory] [gg]@[slimlogic] [co] [uk] [author] [kishon] [vijay] [abraham] [i] [kishon]@[ti] [com] [based] [on] [twl6030]_[usb] [c] [author] [hema] [hk] [hemahk]@[ti] [com] this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 1105 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.202006027@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-01-24clk: socfpga: Don't have get_parent for single parent opsStephen Boyd
This driver creates a gate clk with the possibility to have multiple parents. That can cause problems if the common clk framework tries to call the get_parent() op and gets back a number that's larger than the number of parents the clk says it supports in clk_init_data::num_parents. Let's duplicate the clk_ops structure each time this function is called and drop the get/set parent ops when there is only one parent. This allows the framework to consider a number larger than clk_init_data::num_parents as an error condition of the get_parent() clk op, clearing the way for proper code. Cc: Jerome Brunet <jbrunet@baylibre.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Tested-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2015-07-28clk: socfpga: switch to GENMASK()Andy Shevchenko
Convert the code to use GENMASK() helper instead of div_mask() macro. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-20clk: socfpga: Remove clk.h and clkdev.h includesStephen Boyd
Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Remove the include here because this is a provider driver. The clkdev.h include isn't used either, remove it and add in slab.h to make sure things keep compiling. Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-05clk: socfpga: make use of of_clk_parent_fill helper functionDinh Nguyen
Use of_clk_parent_fill to fill in the parent clock's array. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-21clk: socfpga: update clk.h so for Arria10 platform to useDinh Nguyen
There are 5 possible parent clocks for the SoCFPGA Arria10. Move the define SYSMGR_SDMMC_CTRL_SET and streq() to clk.h so that the Arria clock driver can use. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-14clk: socfpga: Silence sparse warningStephen Boyd
drivers/clk/socfpga/clk-gate.c:227:40: warning: Using plain integer as NULL pointer Cc: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-05-12clk: socfpga: add divider registers to the main pll outputsDinh Nguyen
The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main PLL go through a pre-divider before coming into the system. These registers were hidden for the CycloneV platform, but are now used for the ArriaV platform. This patch updates the clock driver to read the div-reg property for the socfpga-periph-clk clocks. Also moves the div_mask define to clk.h for re-use. Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-02-18clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk"Dinh Nguyen
The clk-phase property is used to represent the 2 clock phase values that is needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will use the syscon driver to set sdmmc_clk's phase shift that is located in the system manager. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> --- v9: none v8: Use degrees in the clk-phase binding property v7: Add dts property to represent the clk phase of the sdmmc_clk. Add a prepare function to the gate clk that will toggle clock phase setting. Remove the "altr,socfpga-sdmmc-sdr-clk" clock type. v6: Add a new clock type "altr,socfpga-sdmmc-sdr-clk" that will be used to set the phase shift settings. v5: Use the "snps,dw-mshc" binding v4: Use the sdmmc_clk prepare function to set the phase shift settings v3: Not use the syscon driver because as of 3.13-rc1, the syscon driver is loaded after the clock driver. v2: Use the syscon driver
2014-02-18clk: socfpga: split clk codeSteffen Trumtrar
Move the different kinds of clocks into their own files. The reason is to aid readability of the code. This also goes along with the other SoC-specific clock drivers. The split introduces new structs for the three types of clocks and uses them. Other changes are not done to the code. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
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