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path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
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2021-09-07drm/amdgpu: Create common PSP TA load functionCandice Li
Creat common PSP TA load function and update PSP ta_mem_context with size information. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-01drm/amd/amdgpu: consolidate PSP TA unload functionCandice Li
Create common PSP TA unload function and replace all common TA unloading sequences. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-30drm/amdgpu: show both cmd id and name when psp cmd failedLang Yu
To cover the corner case that people want to know the ID of an UNKNOWN CMD. Suggested-by: John Clements <john.clements@amd.com> Signed-off-by: Lang Yu <lang.yu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-24drm/amd/amdgpu: consolidate PSP TA init shared buf functionsCandice Li
Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-18drm/amd: consolidate TA shared memory structuresCandice Li
Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-18drm/amdgpu: get extended xgmi topology dataJonathan Kim
The TA has a limit to the amount of data that can be retrieved from GET_TOPOLOGY. For setups that exceed this limit, the xGMI topology needs to be re-initialized and data needs to be re-fetched from the extended link records by setting a flag in the shared command buffer. The number of hops and the number of links must be accumulated by the driver. Other data points are all fetched from the first request. Because the TA has already exceeded its link record limit, it cannot hold bidirectional information. Otherwise the driver would have to do more than two fetches so the driver has to reflect the topology information in the opposite direction. v2: squashed with internal reviewed fix Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Hawking Zhang <hawking.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-16drm/amd/amdgpu: consolidate PSP TA contextCandice Li
Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-05drm/amdgpu: added synchronization for psp cmd buf accessJohn Clements
resolved race condition accessing psp cmd submission memory Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-05drm/amd/amdgpu: remove redundant host to psp cmd buf allocationsCandice Li
Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-05gpu/drm/amd: Remove duplicated include of drm_drv.hzhouchuangao
Duplicate include header file <drm/drm_drv.h> line 28: #include <drm/drm_drv.h> line 44: #include <drm/drm_drv.h> Signed-off-by: zhouchuangao <zhouchuangao@vivo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-28drm/amdgpu: Added support for added psp driver binaries FWJohn Clements
Detect psp driver binaries packed into FW and try to load the FW Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-28drm/amdgpu: Added latest PSP FW headerJohn Clements
Improved handling for scalling PSP FW binaries Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-23drm/amdgpu: enable psp v11.0.8 for cyan_skillfishLang Yu
Add psp v11.0.8 to ip block initialization. v2: use APU flags (Alex) Signed-off-by: Lang Yu <lang.yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-23drm/amdgpu: init psp v11.0.8 function for cyan_skillfishLang Yu
Add psp v11.0.8 function into psp driver. Signed-off-by: Lang Yu <lang.yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-23drm/amdgpu: adjust fw_name string length for tocLang Yu
Adjust toc fw_name string length to PSP_FW_NAME_LEN. Signed-off-by: Lang Yu <lang.yu@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-23drm/amd/amdgpu: add consistent PSP FW loading size checkingCandice Li
Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-23drm/amdgpu: Change a few function namesOak Zeng
Function name "psp_np_fw_load" is not proper as people don't know _np_fw_ means "non psp firmware". Change the function name to psp_load_non_psp_fw for better understanding. Same thing for function psp_execute_np_fw_load. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-23drm/amdgpu: add psp command to get num xgmi links between direct peersJonathan Kim
The TA can now be invoked to provide the number of xgmi links connecting a direct source and destination peer. Non-direct peers will report zero links. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-16drm/amdgpu: Switch to VRAM buffer for USBC PD FW.Andrey Grodzovsky
System memory-based implementation for updating the USBCPD is deprecated for so switching to LFB based implementation for all the ASICs. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alexander Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-01drm/amdgpu: show explicit name instead of id in psp_cmd_submit_bufLang Yu
Use amdgpu_ucode_name to show ucode name and psp_gfx_cmd_name to show psp_gfx_cmd name in psp_cmd_submit_buf. v2: adjust function name Signed-off-by: Lang Yu <Lang.Yu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-01drm/amdgpu: add function to show psp_gfx_cmd name via idLang Yu
Implement function psp_gfx_cmd_name to show cmd name via cmd id. v2: rename it to psp_gfx_cmd_name Signed-off-by: Lang Yu <Lang.Yu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-15drm/amdgpu: correct psp ucode arrary start addressHawking Zhang
For ASICs that need to load sys_drv_aux and sos_aux, the sys_start_addr is not the start address of psp ucode array because the sys_drv_aux and sos_aux actaully located at the end of the ucode array, instead, the psp ucode arrary start address should be sos_hdr + sos_hdr_offset. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-11drm/amdgpu: disable DRAM memory training when GECC is enabledHawking Zhang
GECC and G6 mem training are mutually exclusive functionalities. VBIOS/PSP will set the flag (BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) in runtime database to indicate whether dram memory training need to be disabled or not. For Navi1x families, two stage mem training is always enabled. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-11drm/amdgpu: cache psp runtime boot_cfg_bitmask in sw_intHawking Zhang
PSP runtime boot_cfg_bitmask carries various psp bl feature bit mask that can be used by driver. Cache it in sw_init for further usage. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-11drm/amdgpu: add helper function to query psp runtime db entry (v2)Hawking Zhang
PSP will dump various boot up information into a portion of local frame buffer, called runtime database. The helper function is used for driver to query those shared information. v2: init ret and check !ret to exit loop as soon as found the entry Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-11drm/amdgpu: enable dynamic GECC support (v2)Hawking Zhang
Dynamic GECC allows user to specify GECC enablement status, which will take effect in next boot cycle. v2: initialize boot_cfg to 0xFF Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-11drm/amdgpu: add helper function to query gecc status in boot configHawking Zhang
Query GECC enablement status in boot config Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-11drm/amdgpu: allow different boot configsHawking Zhang
More boot configs need to be supported via BOOTCFG_CMD_SET Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-11drm/amd/pm: drop the incomplete fix for Navi14 runpm issueEvan Quan
As the fix by adding PPSMC_MSG_PrepareMp1ForUnload is proved to be incomplete. Another fix(see link below) has been sent out. Link: https://lore.kernel.org/linux-pci/20210602021255.939090-1-evan.quan@amd.com/ Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-10drm/amdgpu: Added support for loading auxiliary PSP FWJohn Clements
In the case with xgmi connected to cpu load alternate psp fw Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-10drm/amdgpu: Updated fw header structure sourceJohn Clements
synchronized fw header with latest source Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-08drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOVRohit Khaire
This is similar to IH_RB_CNTL programming in navi10_ih_toggle_ring_interrupts Signed-off-by: Rohit Khaire <rohit.khaire@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Horace Chen <horace.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-08drm/amdgpu: allocate psp fw private buffer from VRAM for sriov vfZhigang Luo
psp added new feature to check fw buffer address for sriov vf. the address range must be in vf fb. Signed-off-by: Zhigang Luo <zhigang.luo@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-By : Shaoyun.liu <shaoyunl@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-08drm/amdgpu: add psp ta microcode init for aldebaran sriov vfZhigang Luo
need to load xgmi ta for aldebaran sriov vf. Signed-off-by: Zhigang Luo <zhigang.luo@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-By : Shaoyun.liu <shaoyunl@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04drm/amdgpu: enable psp_v13 for yellow carpAaron Liu
This patch enables psp_v13 for yellow carp. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04drm/amdgpu: Don't flush/invalidate HDP for APUs and A+AEric Huang
Integrate two generic functions to determine if HDP flush is needed for all Asics. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-25drm/amdgpu: Rename flag which prevents HW accessAndrey Grodzovsky
Make it's name not feature but function descriptive. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210521204122.762288-1-andrey.grodzovsky@amd.com
2021-05-22Merge drm/drm-next into drm-misc-nextThomas Zimmermann
Backmerging from drm/drm-next to the patches for AMD devices for v5.14. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
2021-05-19drm/amdgpu: Guard against write accesses after device removalAndrey Grodzovsky
This should prevent writing to memory or IO ranges possibly already allocated for other uses after our device is removed. v5: Protect more places wher memcopy_to/form_io takes place Protect IB submissions v6: Switch to !drm_dev_enter instead of scoping entire code with brackets. v7: Drop guard of HW ring commands emission protection since they are in GART and not in MMIO. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210512142648.666476-10-andrey.grodzovsky@amd.com
2021-05-19drm/amd/amdgpu: add psp support for beige_gobyChengming Gui
add general PSP support for beige_goby Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-19drm/amdgpu: query boot config cap before issue psp cmdHawking Zhang
Only send boot_config cmd to ASICs that support dynamic boot config. Otherwise, the boot_config cmd will fail. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-10drm/amdgpu: covert ras status to kernel errnoDennis Li
The original codes use ras status and kernl errno together in the same function, which is a wrong code style. Signed-off-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-10drm/amdgpu: Rename to ras_*_enabledLuben Tuikov
Rename, ras_hw_supported --> ras_hw_enabled, and ras_features --> ras_enabled, to show that ras_enabled is a subset of ras_hw_enabled, which itself is a subset of the ASIC capability. Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: John Clements <john.clements@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-10drm/amdgpu: Remove redundant ras->supportedLuben Tuikov
Remove redundant ras->supported, as this value is also stored in adev->ras_features. Use adev->ras_features, as that supercedes "ras", since the latter is its member. The dependency goes like this: ras <== adev->ras_features <== hw_supported, and is read as "ras depends on ras_features, which depends on hw_supported." The arrows show the flow of information, i.e. the dependency update. "hw_supported" should also live in "adev". Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: John Clements <john.clements@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-10drm/amdgpu: Add Aldebaran virtualization supportZhigang Luo
1. add Aldebaran in virtualization detection list. 2. disable Aldebaran virtual display support as there is no GFX engine in Aldebaran. 3. skip TMR loading if Aldebaran is in virtualizatin mode as it shares the one host loaded. Signed-off-by: Zhigang Luo <zhigang.luo@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-28drm/amdgpu/sriov: Remove clear vf fw supportVictor Zhao
PSP clear_vf_fw feature is outdated and has been removed. Remove the related functions. Signed-off-by: Victor Zhao <Victor.Zhao@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-23drm/amdgpu: add support for ras init flagsJohn Clements
conditionally configure ras for dgpu mode or poison propogation mode Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20Revert "drm/amdgpu: workaround the TMR MC address issue (v2)"Oak Zeng
This reverts commit 2f055097daef498da57552f422f49de50a1573e6. 2f055097daef498da57552f422f49de50a1573e6 was a driver workaround when PSP firmware was not ready. Now the PSP fw is ready so we revert this driver workaround. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-15drm/amd/sriov no need to config GECC for sriovJack Zhang
No need to config GECC feature here for sriov Leave the host drvier to do the configuration job. Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-15drm/amdgpu: Introduce new SETUP_TMR interfaceOak Zeng
This new interface passes both virtual and physical address to PSP. It is backward compatible with old interface. v2: use a function to simplify tmr physical address calc (Lijo) Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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