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path: root/drivers/gpu/drm/amd/amdgpu
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2019-07-30drm/amdgpu: add reset_method asic callback for viAlex Deucher
VI always uses the legacy pci based reset. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: add reset_method asic callback for cikAlex Deucher
CIK always uses the legacy pci based reset. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: add reset_method asic callback for siAlex Deucher
SI always uses the legacy pci based reset. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: add an asic callback to determine the reset methodAlex Deucher
Sometimes the driver may have to behave differently depending on the method we are using to reset the GPU. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/powerplay: fix null pointer dereference around dpm state relatesEvan Quan
DPM state relates are not supported on the new SW SMU ASICs. But still it's not OK to trigger null pointer dereference on accessing them. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/powerplay: minor fixes around SW SMU power and fan settingEvan Quan
Add checking for possible invalid input and null pointer. And drop redundant code. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/display: enable S/G for RAVEN chipShirish S
enables gpu_vm_support in dm and adds AMDGPU_GEM_DOMAIN_GTT as supported domain v2: Move BO placement logic into amdgpu_display_supported_domains v3: Use amdgpu_bo_validate_uswc in amdgpu_display_supported_domains. v4: amdgpu_bo_validate_uswc moved to sepperate patch. Signed-off-by: Shirish S <shirish.s@amd.com> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: Add check for USWC support for amdgpu_display_supported_domainsAndrey Grodzovsky
This verifies we don't add GTT as allowed domain for APUs when USWC is disabled. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: Create helper to clear AMDGPU_GEM_CREATE_CPU_GTT_USWCAndrey Grodzovsky
Move the logic to clear AMDGPU_GEM_CREATE_CPU_GTT_USWC in amdgpu_bo_do_create into standalone helper so it can be reused in other functions. v4: Switch to return bool. v5: Fix typos. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: Fix hard hang for S/G display BOs.Andrey Grodzovsky
HW requires for caching to be unset for scanout BO mappings when the BO placement is in GTT memory. Usually the flag to unset is passed from user mode but for FB mode this was missing. v2: Keep all BO placement logic in amdgpu_display_supported_domains Suggested-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Tested-by: Shirish S <shirish.s@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: adding xgmi error monitoringJonathan Kim
monitor xgmi errors via mc pie status through fica registers. Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com> Reviewed-by: Kent Russell <Kent.Russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: add perfmon and fica atomics for dfJonathan Kim
adding perfmon and fica atomic operations to adhere to data fabrics finite state machine requirements for indirect register access. Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com> Reviewed-by: Kent Russell <Kent.Russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu/gmc10: fix pte mytpe field error for navi14tiancyin
navi14 share same PTE format with navi10. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: tiancyin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: use VCN firmware offset for cache windowJames Zhu
Since we are using the signed FW now, and also using PSP firmware loading, but it's still potential to break driver when loading FW directly instead of PSP, so we should add offset. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/powerplay: some cosmetic fixesEvan Quan
Drop redundant check, duplicate check, duplicate setting and fix the return value. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: Use dev_get_drvdata where possibleChuhong Yuan
Instead of using to_pci_dev + pci_get_drvdata, use dev_get_drvdata to make code simpler. Signed-off-by: Chuhong Yuan <hslester96@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdkfd: Fix byte align on VegaMKent Russell
This was missed during the addition of VegaM support Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-27Merge tag 'Wimplicit-fallthrough-5.3-rc2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/gustavoars/linux Pull Wimplicit-fallthrough enablement from Gustavo A. R. Silva: "This marks switch cases where we are expecting to fall through, and globally enables the -Wimplicit-fallthrough option in the main Makefile. Finally, some missing-break fixes that have been tagged for -stable: - drm/amdkfd: Fix missing break in switch statement - drm/amdgpu/gfx10: Fix missing break in switch statement With these changes, we completely get rid of all the fall-through warnings in the kernel" * tag 'Wimplicit-fallthrough-5.3-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/gustavoars/linux: Makefile: Globally enable fall-through warning drm/i915: Mark expected switch fall-throughs drm/amd/display: Mark expected switch fall-throughs drm/amdkfd/kfd_mqd_manager_v10: Avoid fall-through warning drm/amdgpu/gfx10: Fix missing break in switch statement drm/amdkfd: Fix missing break in switch statement perf/x86/intel: Mark expected switch fall-throughs mtd: onenand_base: Mark expected switch fall-through afs: fsclient: Mark expected switch fall-throughs afs: yfsclient: Mark expected switch fall-throughs can: mark expected switch fall-throughs firewire: mark expected switch fall-throughs
2019-07-26Merge tag 'drm-fixes-5.3-2019-07-24' of ↵Dave Airlie
git://people.freedesktop.org/~agd5f/linux into drm-fixes drm-fixes-5.3-2019-07-24: amdgpu: - RAS fixes for vega20 - Navi VCN fix - DC audio fixes - DC DSC fixes - DC dongle fixes - DC clk mgr fixes - Fix DDC lines on some RV2 boards - GDS fixes for compute - Navi SMU fixes ttm: - Use the same attributes when freeing d_page->vaddr Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190724210527.3415-1-alexander.deucher@amd.com
2019-07-25drm/amdgpu/gfx10: Fix missing break in switch statementGustavo A. R. Silva
Add missing break statement in order to prevent the code from falling through to case AMDGPU_IRQ_STATE_ENABLE. This bug was found thanks to the ongoing efforts to enable -Wimplicit-fallthrough. Fixes: a644d85a5cd4 ("drm/amdgpu: add gfx v10 implementation (v10)") Cc: stable@vger.kernel.org Reviewed-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
2019-07-22drm/amdgpu/smu: move fan rpm query into the asic specific codeAlex Deucher
On vega20, there is an SMU message to query it. On navi, it's fetched from the metrics table. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-22drm/amdgpu/smu: move fan rpm query into the asic specific codeAlex Deucher
On vega20, there is an SMU message to query it. On navi, it's fetched from the metrics table. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-22drm/amdgpu: set sdma irq src num according to sdma instancesHawking Zhang
Otherwise, it will cause driver access non-existing sdma registers in gpu reset code path Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-22Merge v5.3-rc1 into drm-misc-nextMaxime Ripard
Noralf needs some SPI patches in 5.3 to merge some work on tinydrm. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-07-19Merge tag 'drm-next-2019-07-19' of git://anongit.freedesktop.org/drm/drmLinus Torvalds
Pull drm fixes from Daniel Vetter: "Dave is back in shape, but now family got it so I'm doing the pull. Two things worthy of note: - nouveau feature pull was way too late, Dave&me decided to not take that, so Ben spun up a pull with just the fixes. - after some chatting with the arm display maintainers we decided to change a bit how that's maintained, for more oversight/review and cross vendor collab. More details below: nouveau: - bugfixes - TU116 enabling (minor iteration) :w amdgpu: - large pile of fixes for new hw support this release (navi, vega20) - audio hotplug fix - bunch of corner cases and small fixes all over for amdgpu/kfd komeda: - back out some new properties (from this merge window) that needs more pondering. bochs: - fb pitch setup core: - a new panel quirk - misc fixes" * tag 'drm-next-2019-07-19' of git://anongit.freedesktop.org/drm/drm: (73 commits) drm/nouveau/secboot/gp102-: remove WAR for SEC2 RTOS start bug drm/nouveau/flcn/gp102-: improve implementation of bind_context() on SEC2/GSP drm/nouveau: fix memory leak in nouveau_conn_reset() drm/nouveau/dmem: missing mutex_lock in error path drm/nouveau/hwmon: return EINVAL if the GPU is powered down for sensors reads drm/nouveau: fix bogus GPL-2 license header drm/nouveau: fix bogus GPL-2 license header drm/nouveau/i2c: Enable i2c pads & busses during preinit drm/nouveau/disp/tu102-: wire up scdc parameter setter drm/nouveau/core: recognise TU116 chipset drm/nouveau/kms: disallow dual-link harder if hdmi connection detected drm/nouveau/disp/nv50-: fix center/aspect-corrected scaling drm/nouveau/disp/nv50-: force scaler for any non-default LVDS/eDP modes drm/nouveau/mcp89/mmu: Use mcp77_mmu_new instead of g84_mmu_new on MCP89. drm/amd/display: init res_pool dccg_ref, dchub_ref with xtalin_freq drm/amdgpu/pm: remove check for pp funcs in freq sysfs handlers drm/amd/display: Force uclk to max for every state drm/amdkfd: Remove GWS from process during uninit drm/amd/amdgpu: Fix offset for vmid selection in debugfs interface drm/amd/powerplay: update vega20 driver if to fit latest SMU firmware ...
2019-07-18drm/amdgpu: use VCN firmware offset for cache windowLeo Liu
Since we are using the signed FW now, and also using PSP firmware loading, but it's still potential to break driver when loading FW directly instead of PSP, so we should add offset. Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: drop ras self testHawking Zhang
this function is not needed any more. error injection is the only way to validate ras but it can't be executed in amdgpu_ras_init, where gpu is even not initialized Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: only allow error injection to UMC IP blockHawking Zhang
error injection to other IP blocks (except UMC) will be enabled until RAS feature stablize on those IP blocks Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: disable GFX RAS by defaultHawking Zhang
GFX RAS has not been stablized yet. disable GFX ras until it is fully funcitonal. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: do not create ras debugfs/sysfs node for ASICs that don't have ↵Hawking Zhang
ras ability driver shouldn't init any ras debugfs/sysfs node for ASICs that don't have ras hardware ability Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: Default disable GDS for compute VMIDsJoseph Greathouse
The GDS and GWS blocks default to allowing all VMIDs to access all entries. Graphics VMIDs can handle setting these limits when the driver launches work. However, compute workloads under HWS control don't go through the kernel driver. Instead, HWS firmware should set these limits when a process is put into a VMID slot. Disable access to these devices by default by turning off all mask bits (for OA) and setting BASE=SIZE=0 (for GDS and GWS) for all compute VMIDs. If a process wants to use these resources, they can request this from the HWS firmware (when such capabilities are enabled). HWS will then handle setting the base and limit for the process when it is assigned to a VMID. This will also prevent user kernels from getting 'stuck' in GWS by accident if they write GWS-using code but HWS firmware is not set up to handle GWS reset. Until HWS is enabled to handle GWS properly, all GWS accesses will MEM_VIOL fault the kernel. v2: Move initialization outside of SRBM mutex Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: flag arcturus as experimental for nowAlex Deucher
Current support will only work in internal engineering boards. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: drop unused function definitionsAlex Deucher
These were dropped and the headers never got cleaned up. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu:add all VCN rings into schedule request queueJames Zhu
Add all VCN instances' decode/encode/jpeg decode rings into drm_sched_rq list. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: enable all 8 sdma instances for Arcturus siliconLe Ma
The more 6 sdma instances work fine now with DF fix in vbios: * mmDF_PIE_AON_MiscClientsEnable(0x1c728)=0x3fe(DF_ALL_INSTANCE) [9:4]MmhubsEnable=3f (change from 0) Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: Add more detail to the VM fault printingYong Zhao
With the printing, we don't need to parse the value on our own any more. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: limit sdma instances to 2 for Arcturus in BU phaseLe Ma
Another 6 sdma instances do not work at present. Disable them to unblock KFD for silicon bringup as a workaround Signed-off-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: skip gfx 9 common golden settings for arctHawking Zhang
They are not needed by arct Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18amd/powerplay: No SW XGMI dpm for Arcturus rev 2Yong Zhao
xgmi dpm is handled by the SMU. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: clean up nonexistent firmware declaration for ArcturusLe Ma
CPG firmwares are not used. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: init gds config for arctHawking Zhang
arct has 4KB gds (4 banks inside) so the max_wave_id should be 0xfff Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: keep stolen memory for arctHawking Zhang
Any dce register read back from arct is invalid. use hard code stolen memory for arct until we validate the s3. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: init arct external rev idHawking Zhang
Properly set the external silicon revision id. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: add arct gc golden settingsHawking Zhang
Golden GC register settings from the hw team. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: add arct sdma golden settingsHawking Zhang
Golden SDMA register settings from the hw team. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: add pci DID for Arcturus GL-XL.Feifei Xu
Add device ids for Arcturus. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: assign fb_start/end in mmhub v9.4 interfaceLe Ma
Align with mmhub v1.0. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: add harvest support for ArcturusJames Zhu
Add VCN harvest support for Arcturus Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: add multiple instances support for ArcturusJames Zhu
Arcturus has dual-VCN. Need add multiple instances support for Arcturus. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amdgpu: modify amdgpu_vcn to support multiple instancesJames Zhu
Arcturus has dual-VCN. Need Restruct amdgpu_device::vcn to support multiple vcns. There are no any logical changes here Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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