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path: root/drivers/net/dsa
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2022-02-05net: dsa: realtek: don't default Kconfigs to yJakub Kicinski
We generally default the vendor to y and the drivers itself to n. NET_DSA_REALTEK, however, selects a whole bunch of things, so it's not a pure "vendor selection" knob. Let's default it all to n. Signed-off-by: Jakub Kicinski <kuba@kernel.org> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-05net: dsa: qca8k: check correct variable in qca8k_phy_eth_command()Dan Carpenter
This is a copy and paste bug. It was supposed to check "clear_skb" instead of "write_skb". Fixes: 2cd548566384 ("net: dsa: qca8k: add support for phy read/write with mgmt Ethernet") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-04net: dsa: realtek: convert to phylink_generic_validate()Russell King (Oracle)
Populate the supported interfaces and MAC capabilities for the Realtek rtl8365 DSA switch and remove the old validate implementation to allow DSA to use phylink_generic_validate() for this switch driver. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-03Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski
No conflicts. Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-02-03net: dsa: mv88e6xxx: improve 88e6352 serdes statistics detectionRussell King (Oracle)
The decision whether to report serdes statistics currently depends on the cached C_Mode value for the port, read at probe time or updated by configuration. However, port 4 can be in "automedia" mode when it is used as a serdes port, meaning it switches between the internal PHY and the serdes, changing the read-only C_Mode value depending on which first gains link. Consequently, the C_Mode value read at probe does not accurately reflect whether the port has the serdes associated with it. In "net: dsa: mv88e6xxx: add mv88e6352_g2_scratch_port_has_serdes()", we added a way to read the hardware configuration to determine which port has the serdes associated with it. Use this to determine which port reports the serdes statistics. Reviewed-by: Marek Behún <kabel@kernel.org> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-03net: dsa: mv88e6xxx: convert to phylink_generic_validate()Russell King (Oracle)
Now that the mv88e6xxx chip drivers are supplying the supported interfaces and MAC capabilities, switch the driver to use the generic phylink validation implementation by removing our own validation implementations. This causes DSA to call phylink_generic_validate() on our behalf. Reviewed-by: Marek Behún <kabel@kernel.org> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-03net: dsa: mv88e6xxx: populate supported_interfaces and mac_capabilitiesRussell King (Oracle)
Populate the supported interfaces and MAC capabilities for the Marvell MV88E6xxx DSA switches in preparation to using these for the validation functionality. Patch co-authored by Marek. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: Marek Behún <kabel@kernel.org> [ fixed 6341 and 6393x ] Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-03net: dsa: mv88e6xxx: add mv88e6352_g2_scratch_port_has_serdes()Russell King (Oracle)
Read the hardware configuration to determine which port is attached to the serdes. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-03net: dsa: mv88e6xxx: Improve multichip isolation of standalone portsTobias Waldekranz
Given that standalone ports are now configured to bypass the ATU and forward all frames towards the upstream port, extend the ATU bypass to multichip systems. Load VID 0 (standalone) into the VTU with the policy bit set. Since VID 4095 (bridged) is already loaded, we now know that all VIDs in use are always available in all VTUs. Therefore, we can safely enable 802.1Q on DSA ports. Setting the DSA ports' VTU policy to TRAP means that all incoming frames on VID 0 will be classified as MGMT - as a result, the ATU is bypassed on all subsequent switches. With this isolation in place, we are able to support configurations that are simultaneously very quirky and very useful. Quirky because it involves looping cables between local switchports like in this example: CPU | .------. .---0---. | .----0----. | sw0 | | | sw1 | '-1-2-3-' | '-1-2-3-4-' $ @ '---' $ @ % % We have three physically looped pairs ($, @, and %). This is very useful because it allows us to run the kernel's kselftests for the bridge on mv88e6xxx hardware. Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-03net: dsa: mv88e6xxx: Enable port policy support on 6097Tobias Waldekranz
This chip has support for the same per-port policy actions found in later versions of LinkStreet devices. Fixes: f3a2cd326e44 ("net: dsa: mv88e6xxx: introduce .port_set_policy") Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-03net: dsa: mv88e6xxx: Support policy entries in the VTUTobias Waldekranz
A VTU entry with policy enabled is used in combination with a port's VTU policy setting to override normal switching behavior for frames assigned to the entry's VID. A typical example is to Treat all frames in a particular VLAN as control traffic, and trap them to the CPU. In which case the relevant user port's VTU policy would be set to TRAP. Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-03net: dsa: mv88e6xxx: Improve isolation of standalone portsTobias Waldekranz
Clear MapDA on standalone ports to bypass any ATU lookup that might point the packet in the wrong direction. This means that all packets are flooded using the PVT config. So make sure that standalone ports are only allowed to communicate with the local upstream port. Here is a scenario in which this is needed: CPU | .----. .---0---. | .--0--. | sw0 | | | sw1 | '-1-2-3-' | '-1-2-' '---' - sw0p1 and sw1p1 are bridged - sw0p2 and sw1p2 are in standalone mode - Learning must be enabled on sw0p3 in order for hardware forwarding to work properly between bridged ports 1. A packet with SA :aa comes in on sw1p2 1a. Egresses sw1p0 1b. Ingresses sw0p3, ATU adds an entry for :aa towards port 3 1c. Egresses sw0p0 2. A packet with DA :aa comes in on sw0p2 2a. If an ATU lookup is done at this point, the packet will be incorrectly forwarded towards sw0p3. With this change in place, the ATU is bypassed and the packet is forwarded in accordance with the PVT, which only contains the CPU port. Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-03net: dsa: xrs700x: convert to phylink_generic_validate()Russell King (Oracle)
Populate the supported interfaces and MAC capabilities for the xrs700x family of DSA switches and remove the old validate implementation to allow DSA to use phylink_generic_validate() for this switch driver. According to commit ee00b24f32eb ("net: dsa: add Arrow SpeedChips XRS700x driver") the switch supports one RMII port and up to three RGMII ports. This commit assumes that port 0 is the RMII port and the remainder are RGMII. This commit also results in the Autoneg bit being set in the ethtool link modes, which wasn't in the original; if this switch supports RGMII to a 10/100/1G PHY, then surely we want to allow Autoneg on the PHY. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-03net: dsa: qca8k: convert to phylink_generic_validate()Russell King (Oracle)
Populate the supported interfaces and MAC capabilities for the QCA8K DSA switch and remove the old validate implementation to allow DSA to use phylink_generic_validate() for this switch driver. In making this change, we bring consistency to the ethtool linkmodes that phylink's validate step produces, thereby following the expected behaviour as the phylink documentation has explained. Specifically, the ethtool 1000baseX_Full capability is now permitted for all interface modes, as it is a property of the PHY driver whether 1000baseX fiber connections can be supported. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-03net: dsa: ksz8795: convert to phylink_generic_validate()Russell King (Oracle)
Populate the supported interfaces and MAC capabilities for the Microchip KSZ8795 DSA switch and remove the old validate implementation to allow DSA to use phylink_generic_validate() for this switch driver. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-03net: dsa: bcm_sf2: convert to phylink_generic_validate()Russell King (Oracle)
Populate the supported interfaces and MAC capabilities for the bcm_sf2 DSA switch and remove the old validate implementation to allow DSA to use phylink_generic_validate() for this switch driver. The exclusion of Gigabit linkmodes for MII and Reverse MII links is handled within phylink_generic_validate() in phylink, so there is no need to make them conditional on the interface mode in the driver. Thanks to Florian Fainelli for suggesting how to populate the supported interfaces. Link: https://lore.kernel.org/r/3b3fed98-0c82-99e9-dc72-09fe01c2bcf3@gmail.com Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-03net: dsa: ar9331: convert to phylink_generic_validate()Russell King (Oracle)
Populate the supported interfaces and MAC capabilities for the AR9331 DSA switch and remove the old validate implementation to allow DSA to use phylink_generic_validate() for this switch driver. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-02net: dsa: qca8k: introduce qca8k_bulk_read/write functionAnsuel Smith
Introduce qca8k_bulk_read/write() function to use mgmt Ethernet way to read/write packet in bulk. Make use of this new function in the fdb function and while at it reduce the reg for fdb_read from 4 to 3 as the max bit for the ARL(fdb) table is 83 bits. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-02net: dsa: qca8k: add support for larger read/write size with mgmt EthernetAnsuel Smith
mgmt Ethernet packet can read/write up to 16byte at times. The len reg is limited to 15 (0xf). The switch actually sends and accepts data in 4 different steps of len values. Len steps: - 0: nothing - 1-4: first 4 byte - 5-6: first 12 byte - 7-15: all 16 byte In the alloc skb function we check if the len is 16 and we fix it to a len of 15. It the read/write function interest to extract the real asked data. The tagger handler will always copy the fully 16byte with a READ command. This is useful for some big regs like the fdb reg that are more than 4byte of data. This permits to introduce a bulk function that will send and request the entire entry in one go. Write function is changed and it does now require to pass the pointer to val to also handle array val. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-02net: dsa: qca8k: cache lo and hi for mdio writeAnsuel Smith
From Documentation, we can cache lo and hi the same way we do with the page. This massively reduce the mdio write as 3/4 of the time as we only require to write the lo or hi part for a mdio write. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-02net: dsa: qca8k: move page cache to driver privAnsuel Smith
There can be multiple qca8k switch on the same system. Move the static qca8k_current_page to qca8k_priv and make it specific for each switch. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-02net: dsa: qca8k: add support for phy read/write with mgmt EthernetAnsuel Smith
Use mgmt Ethernet also for phy read/write if availabale. Use a different seq number to make sure we receive the correct packet. On any error, we fallback to the legacy mdio read/write. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-02net: dsa: qca8k: add support for mib autocast in Ethernet packetAnsuel Smith
The switch can autocast MIB counter using Ethernet packet. Add support for this and provide a handler for the tagger. The switch will send packet with MIB counter for each port, the switch will use completion API to wait for the correct packet to be received and will complete the task only when each packet is received. Although the handler will drop all the other packet, we still have to consume each MIB packet to complete the request. This is done to prevent mixed data with concurrent ethtool request. connect_tag_protocol() is used to add the handler to the tag_qca tagger, master_state_change() use the MIB lock to make sure no MIB Ethernet is in progress. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-02net: dsa: qca8k: add support for mgmt read/write in Ethernet packetAnsuel Smith
Add qca8k side support for mgmt read/write in Ethernet packet. qca8k supports some specially crafted Ethernet packet that can be used for mgmt read/write instead of the legacy method uart/internal mdio. This add support for the qca8k side to craft the packet and enqueue it. Each port and the qca8k_priv have a special struct to put data in it. The completion API is used to wait for the packet to be received back with the requested data. The various steps are: 1. Craft the special packet with the qca hdr set to mgmt read/write mode. 2. Set the lock in the dedicated mgmt struct. 3. Increment the seq number and set it in the mgmt pkt 4. Reinit the completion. 5. Enqueue the packet. 6. Wait the packet to be received. 7. Use the data set by the tagger to complete the mdio operation. If the completion timeouts or the ack value is not true, the legacy mdio way is used. It has to be considered that in the initial setup mdio is still used and mdio is still used until DSA is ready to accept and tag packet. tag_proto_connect() is used to fill the required handler for the tagger to correctly parse and elaborate the special Ethernet mdio packet. Locking is added to qca8k_master_change() to make sure no mgmt Ethernet are in progress. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-02net: dsa: qca8k: add tracking state of master portAnsuel Smith
MDIO/MIB Ethernet require the master port and the tagger availabale to correctly work. Use the new api master_state_change to track when master is operational or not and set a bool in qca8k_priv. We cache the first cached master available and we check if other cpu port are operational when the cached one goes down. This cached master will later be used by mdio read/write and mib request to correctly use the working function. qca8k implementation for MDIO/MIB Ethernet is bad. CPU port0 is the only one that answers with the ack packet or sends MIB Ethernet packets. For this reason the master_state_change ignore CPU port6 and only checks CPU port0 if it's operational and enables this mode. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-31net: dsa: mt7530: make NET_DSA_MT7530 select MEDIATEK_GE_PHYArınç ÜNAL
Make MediaTek MT753x DSA driver enable MediaTek Gigabit PHYs driver to properly control MT7530 and MT7531 switch PHYs. A noticeable change is that the behaviour of switchport interfaces going up-down-up-down is no longer there. Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch") Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20220129062703.595-1-arinc.unal@arinc9.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-01-31net: dsa: mv88e6xxx: Improve indirect addressing performanceTobias Waldekranz
Before this change, both the read and write callback would start out by asserting that the chip's busy flag was cleared. However, both callbacks also made sure to wait for the clearing of the busy bit before returning - making the initial check superfluous. The only time that would ever have an effect was if the busy bit was initially set for some reason. With that in mind, make sure to perform an initial check of the busy bit, after which both read and write can rely the previous operation to have waited for the bit to clear. This cuts the number of operations on the underlying MDIO bus by 25% Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-31net: dsa: mv88e6xxx: Improve performance of busy bit pollingTobias Waldekranz
Avoid a long delay when a busy bit is still set and has to be polled again. Measurements on a system with 2 Opals (6097F) and one Agate (6352) show that even with this much tighter loop, we have about a 50% chance of the bit being cleared on the first poll, all other accesses see the bit being cleared on the second poll. On a standard MDIO bus running MDC at 2.5MHz, a single access with 32 bits of preamble plus 32 bits of data takes 64*(1/2.5MHz) = 25.6us. This means that mv88e6xxx_smi_direct_wait took 26us + CPU overhead in the fast scenario, but 26us + 1500us + 26us + CPU overhead in the slow case - bringing the average close to 1ms. With this change in place, the slow case is closer to 2*26us + CPU overhead, with the average well below 100us - a 10x improvement. This translates to real-world winnings. On a 3-chip 20-port system, the modprobe time drops by 88%: Before: root@coronet:~# time modprobe mv88e6xxx real 0m 15.99s user 0m 0.00s sys 0m 1.52s After: root@coronet:~# time modprobe mv88e6xxx real 0m 2.21s user 0m 0.00s sys 0m 1.54s Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-28net: dsa: realtek: rtl8365mb: fix trap_door > 7Luiz Angelo Daros de Luca
Trap door number is a 4-bit number divided in two regions (3 and 1-bit). Both values were not masked properly. This bug does not affect supported devices as they use up to port 7 (ext2). It would only be a problem if the driver becomes compatible with 10-port switches like RTL8370MB and RTL8310SR. Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-28net: dsa: realtek: rtl8365mb: allow non-cpu extint portsLuiz Angelo Daros de Luca
External interfaces can be configured, even if they are not CPU ports. The first CPU port will also be the trap port (for receiving trapped frames from the switch). The CPU information was dropped from chip data as it was not used outside setup. The only other place it was used is when it wrongly checks for CPU port when it should check for extint. The supported modes check now uses port type and not port usage. As a byproduct, more than one CPU can be configured. although this might not work well with DSA setups. Also, this driver is still only blindly forwarding all traffic to CPU port(s). This change was not tested in a device with multiple active external interfaces ports. realtek_priv->cpu_port is now only used by rtl8366rb.c Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-28net: dsa: realtek: rtl8365mb: add RTL8367RB-VB supportLuiz Angelo Daros de Luca
RTL8367RB-VB is a 5+2 port 10/100/1000M Ethernet switch. It is similar to RTL8367S but in this version, both external interfaces are RGMII. Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-28net: dsa: realtek: rtl8365mb: add RTL8367S supportLuiz Angelo Daros de Luca
Realtek's RTL8367S, a 5+2 port 10/100/1000M Ethernet switch. It shares the same driver family (RTL8367C) with other models as the RTL8365MB-VC. Its compatible string is "realtek,rtl8367s". It was tested only with MDIO interface (realtek-mdio), although it might work out-of-the-box with SMI interface (using realtek-smi). This patch was based on an unpublished patch from Alvin Šipraga <alsi@bang-olufsen.dk>. Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Alvin Šipraga <alsi@bang-olufsen.dk> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-28net: dsa: realtek: rtl8365mb: use DSA CPU portLuiz Angelo Daros de Luca
Instead of a fixed CPU port, assume that DSA is correct. Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Alvin Šipraga <alsi@bang-olufsen.dk> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-28net: dsa: realtek: rtl8365mb: use GENMASK(n-1,0) instead of BIT(n)-1Luiz Angelo Daros de Luca
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Alvin Šipraga <alsi@bang-olufsen.dk> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-28net: dsa: realtek: rtl8365mb: rename extport to extintLuiz Angelo Daros de Luca
"extport" 0, 1, 2 was used to reference external ports id (ext0, ext1, ext2). Meanwhile, port 0..9 is used as switch ports, including external ports. "extport" was renamed to extint to make it clear it does not mean the port number but the external interface number id. The macros that map extint numbers to registers addresses now use inline ifs instead of binary arithmetic. Realtek uses in docs and drivers EXT_PORT0 (GMAC1) and EXT_PORT1 (GMAC2), with EXT_PORT0 being converted to ext_id == 1 and so on. It might introduce some confusing while reading datasheets but it will not be exposed to users. "extint" was hardcoded to 1. However, some chips have multiple external interfaces. It's not right to assume the CPU port uses extint 1 nor that all extint are CPU ports. Now it came from a map between port number and external interface id number. This patch still does not allow multiple CPU ports nor extint as a non CPU port. Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-28net: dsa: realtek: add new mdio interface for driversLuiz Angelo Daros de Luca
This driver is a mdio_driver instead of a platform driver (like realtek-smi). ds_ops was duplicated for smi and mdio usage as mdio interfaces uses phy_{read,write} in ds_ops and the presence of phy_read is incompatible with external slave_mii_bus allocation. Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-28net: dsa: realtek: convert subdrivers into modulesLuiz Angelo Daros de Luca
Preparing for multiple interfaces support, the drivers must be independent of realtek-smi. Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Alvin Šipraga <alsi@bang-olufsen.dk> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-28net: dsa: realtek: remove direct calls to realtek-smiLuiz Angelo Daros de Luca
Remove the only two direct calls from subdrivers to realtek-smi. Now they are called from realtek_priv. Subdrivers can now be linked independently from realtek-smi. Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> Reviewed-by: Alvin Šipraga <alsi@bang-olufsen.dk> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-28net: dsa: realtek: rename realtek_smi to realtek_privLuiz Angelo Daros de Luca
In preparation to adding other interfaces, the private data structure was renamed to priv. Also, realtek_smi_variant and realtek_smi_ops were renamed to realtek_variant and realtek_ops as those structs are not SMI specific. Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Alvin Šipraga <alsi@bang-olufsen.dk> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-28net: dsa: realtek-smi: move to subdirectoryLuiz Angelo Daros de Luca
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by: Alvin Šipraga <alsi@bang-olufsen.dk> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-28net: dsa: realtek-smi: fix kdoc warningsLuiz Angelo Daros de Luca
Removed kdoc mark for incomplete struct description. Added a return description for rtl8366rb_drop_untagged. Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-28net: dsa: microchip: Add property to disable reference clockRobert Hancock
Add a new microchip,synclko-disable property which can be specified to disable the reference clock output from the device if not required by the board design. Signed-off-by: Robert Hancock <robert.hancock@calian.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-24net: use bool values to pass bool param of phy_init_eee()Jisheng Zhang
The 2nd param of phy_init_eee(): clk_stop_enable is a bool param, use true or false instead of 1/0. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20220123152241.1480-1-jszhang@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-01-07net: dsa: felix: add port fast age supportVladimir Oltean
Add support for flushing the MAC table on a given port in the ocelot switch library, and use this functionality in the felix DSA driver. This operation is needed when a port leaves a bridge to become standalone, and when the learning is disabled, and when the STP state changes to a state where no FDB entry should be present. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20220107144229.244584-1-vladimir.oltean@nxp.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-01-02net: dsa: seville: name change for clarity from pcs to mdio_deviceColin Foster
A simple variable update from "pcs" to "mdio_device" for the mdio device will make things a little cleaner. Signed-off-by: Colin Foster <colin.foster@in-advantage.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-02net: dsa: felix: name change for clarity from pcs to mdio_deviceColin Foster
Simple rename of a variable to make things more logical. Signed-off-by: Colin Foster <colin.foster@in-advantage.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-02net: phy: lynx: refactor Lynx PCS module to use generic phylink_pcsColin Foster
Remove references to lynx_pcs structures so drivers like the Felix DSA can reference alternate PCS drivers. Signed-off-by: Colin Foster <colin.foster@in-advantage.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31Merge git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-nextDavid S. Miller
Alexei Starovoitov says: ==================== pull-request: bpf-next 2021-12-30 The following pull-request contains BPF updates for your *net-next* tree. We've added 72 non-merge commits during the last 20 day(s) which contain a total of 223 files changed, 3510 insertions(+), 1591 deletions(-). The main changes are: 1) Automatic setrlimit in libbpf when bpf is memcg's in the kernel, from Andrii. 2) Beautify and de-verbose verifier logs, from Christy. 3) Composable verifier types, from Hao. 4) bpf_strncmp helper, from Hou. 5) bpf.h header dependency cleanup, from Jakub. 6) get_func_[arg|ret|arg_cnt] helpers, from Jiri. 7) Sleepable local storage, from KP. 8) Extend kfunc with PTR_TO_CTX, PTR_TO_MEM argument support, from Kumar. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-30net: dsa: bcm_sf2: refactor LED regs accessRafał Miłecki
1. Define more regs. Some switches (e.g. BCM4908) have up to 6 regs. 2. Add helper for handling non-lineral port <-> reg mappings. 3. Add support for 12 B LED reg blocks on BCM4908 (different layout) Complete support for LEDs setup will be implemented once Linux receives a proper design & implementation for "hardware" LEDs. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20211229171642.22942-1-zajec5@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-12-29net: Don't include filter.h from net/sock.hJakub Kicinski
sock.h is pretty heavily used (5k objects rebuilt on x86 after it's touched). We can drop the include of filter.h from it and add a forward declaration of struct sk_filter instead. This decreases the number of rebuilt objects when bpf.h is touched from ~5k to ~1k. There's a lot of missing includes this was masking. Primarily in networking tho, this time. Signed-off-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: Alexei Starovoitov <ast@kernel.org> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Nikolay Aleksandrov <nikolay@nvidia.com> Acked-by: Stefano Garzarella <sgarzare@redhat.com> Link: https://lore.kernel.org/bpf/20211229004913.513372-1-kuba@kernel.org