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AFI_INTR is unmasked in tegra_pcie_enable_controller(), mask it to avoid
unwanted interrupts raised by AFI after pex_rst is asserted.
The following sequence triggers such scenario:
- tegra_pcie_remove() triggers runtime suspend
- pex_rst is asserted in runtime suspend
- PRSNT_MAP bit field in RP_PRIV_MISC register changes from EP_PRSNT to
EP_ABSNT
- This is sensed by AFI and triggers "Slot present pin change" interrupt
- tegra_pcie_isr() function accesses AFI register when runtime suspend
is going through power off sequence
Resulting faulty backtrace:
rmmod pci-tegra
pci_generic_config_write32: 108 callbacks suppressed
pci_bus 0002:00: 2-byte config write to 0002:00:02.0 offset 0x4c may corrupt adjacent RW1C bits
pci_bus 0002:00: 2-byte config write to 0002:00:02.0 offset 0x9c may corrupt adjacent RW1C bits
pci_bus 0002:00: 2-byte config write to 0002:00:02.0 offset 0x88 may corrupt adjacent RW1C bits
pci_bus 0002:00: 2-byte config write to 0002:00:02.0 offset 0x90 may corrupt adjacent RW1C bits
pci_bus 0002:00: 2-byte config write to 0002:00:02.0 offset 0x4 may corrupt adjacent RW1C bits
igb 0002:04:00.1: removed PHC on enP2p4s0f1
igb 0002:04:00.0: removed PHC on enP2p4s0f0
pci_bus 0002:00: 2-byte config write to 0002:00:01.0 offset 0x4c may corrupt adjacent RW1C bits
pci_bus 0002:00: 2-byte config write to 0002:00:01.0 offset 0x9c may corrupt adjacent RW1C bits
pci_bus 0002:00: 2-byte config write to 0002:00:01.0 offset 0x88 may corrupt adjacent RW1C bits
pci_bus 0002:00: 2-byte config write to 0002:00:01.0 offset 0x90 may corrupt adjacent RW1C bits
pci_bus 0002:00: 2-byte config write to 0002:00:01.0 offset 0x4 may corrupt adjacent RW1C bits
rcu: INFO: rcu_preempt self-detected stall on CPU
SError Interrupt on CPU0, code 0xbf000002 -- SError
CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 5.1.0-rc3-next-20190405-00027-gcd8110499e6f-dirty #42
Hardware name: NVIDIA Jetson TX1 Developer Kit (DT)
pstate: 20000085 (nzCv daIf -PAN -UAO)
pc : tegra_pcie_isr+0x58/0x178 [pci_tegra]
lr : tegra_pcie_isr+0x40/0x178 [pci_tegra]
sp : ffff000010003da0
x29: ffff000010003da0 x28: 0000000000000000
x27: ffff8000f9e61000 x26: ffff000010fbf420
x25: ffff000011427f93 x24: ffff8000fa600410
x23: ffff00001129d000 x22: ffff00001129d000
x21: ffff8000f18bf3c0 x20: 0000000000000070
x19: 00000000ffffffff x18: 0000000000000000
x17: 0000000000000000 x16: 0000000000000000
x15: 0000000000000000 x14: ffff000008d40a48
x13: ffff000008d40a30 x12: ffff000008d40a20
x11: ffff000008d40a10 x10: ffff000008d40a00
x9 : ffff000008d409e8 x8 : ffff000008d40ae8
x7 : ffff000008d40ad0 x6 : ffff000010003e58
x5 : ffff8000fac00248 x4 : 0000000000000000
x3 : ffff000008d40b08 x2 : fffffffffffffff8
x1 : ffff000008d3f4e8 x0 : 00000000ffffffff
Kernel panic - not syncing: Asynchronous SError Interrupt
CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 5.1.0-rc3-next-20190405-00027-gcd8110499e6f-dirty #42
Hardware name: NVIDIA Jetson TX1 Developer Kit (DT)
Call trace:
dump_backtrace+0x0/0x158
show_stack+0x14/0x20
dump_stack+0xa8/0xcc
panic+0x140/0x2f4
nmi_panic+0x6c/0x70
arm64_serror_panic+0x74/0x80
__pte_error+0x0/0x28
el1_error+0x84/0xf8
tegra_pcie_isr+0x58/0x178 [pci_tegra]
__handle_irq_event_percpu+0x70/0x198
handle_irq_event_percpu+0x34/0x88
handle_irq_event+0x48/0x78
handle_fasteoi_irq+0xb4/0x190
generic_handle_irq+0x24/0x38
__handle_domain_irq+0x5c/0xb8
gic_handle_irq+0x58/0xa8
el1_irq+0xb8/0x180
cpuidle_enter_state+0x138/0x358
cpuidle_enter+0x18/0x20
call_cpuidle+0x1c/0x48
do_idle+0x230/0x2d0
cpu_startup_entry+0x20/0x28
rest_init+0xd4/0xe0
arch_call_rest_init+0xc/0x14
start_kernel+0x444/0x470
AFI_INTR is re-enabled on resume in tegra_pcie_pm_resume() through
tegra_pcie_enable_controller().
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
[lorenzo.pieralisi@arm.com: updated log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
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Tegra PCIe has register specifications for:
- AXI to FPCI(AFI) bridge
- Multiple PCIe root ports
- PCIe PHY
- PCIe pad control
Rearrange Tegra PCIe driver functions so that each function programs
the required module only.
- tegra_pcie_enable_controller(): Program AFI module and enable PCIe
controller
- tegra_pcie_phy_power_on(): Bring up PCIe PHY
- tegra_pcie_apply_pad_settings(): Program PCIe REFCLK pad settings
- tegra_pcie_enable_ports(): Program each root port and bring up PCIe
link
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
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Unroll the PCIe power on sequence if any one of the steps fails in
tegra_pcie_power_on().
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
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Since the upstream MSI memory writes are generated by downstream
devices, it is logically correct to have MSI target memory coming from
the DMA pool reserved for PCIe than from the general memory pool
reserved for CPU access to avoid PCIe DMA addresses coinciding with
MSI target address thereby raising unwanted MSI interrupts.
Enforce this behaviour by retrieving the MSI address through the DMA
API.
Limit the MSI target address to 32-bits to make it work for PCIe
endpoints that support only 32-bit MSI target address; endpoints that
support 64-bit MSI target address work with 32-bit MSI target
address too.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
[lorenzo.pieralisi@arm.com: updated commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
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Native PCI drivers for root complex devices were originally all in
drivers/pci/host/. Some of these devices can also be operated in endpoint
mode. Drivers for endpoint mode didn't seem to fit in the "host"
directory, so we put both the root complex and endpoint drivers in
per-device directories, e.g., drivers/pci/dwc/, drivers/pci/cadence/, etc.
These per-device directories contain trivial Kconfig and Makefiles and
clutter drivers/pci/. Make a new drivers/pci/controllers/ directory and
collect all the device-specific drivers there.
No functional change intended.
Link: https://lkml.kernel.org/r/1520304202-232891-1-git-send-email-shawn.lin@rock-chips.com
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
[bhelgaas: changelog]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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