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path: root/drivers/spi
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2022-06-13spi: s3c64xx: set pointers to null using NULL rather than 0Colin Ian King
There are pointers being set to null using use. Use NULL instead. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20220612203428.2754823-1-colin.i.king@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-13spi: micro: fix unreasonable clk_prepare_enable() on error in ↵Peng Wu
mchp_corespi_probe() Fix the unreasonable clk_prepare_enable() with clk_disable_unprepare() before return from mchp_corespi_probe() in the error handling case. Signed-off-by: Peng Wu <wupeng58@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220611021117.40494-1-wupeng58@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-13spi: tegra210-quad: Multi-cs supportKrishna Yarlagadda
Tegra Grace and later chips can support upto 4 chip select lines for QUAD SPI. Added new compatible for Tegra Grace. Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Link: https://lore.kernel.org/r/20220607114659.54314-2-kyarlagadda@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-10spi: atmel-quadspi: add runtime pm supportMark Brown
Merge series from Claudiu Beznea <claudiu.beznea@microchip.com>: The following series adds runtime PM support for atmel-quadspi driver. clk_disable()/clk_enable() is called on proper runtime_suspend()/runtime_resume() ops. Along with it 2 minor cleanups were added (patches 2/3, 3/3).
2022-06-10spi: Use device_find_any_child() instead of custom approachAndy Shevchenko
We have already a helper to get the first child device, use it and drop custom approach. Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-by: Mark Brown <broonie@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220610120219.18988-2-andriy.shevchenko@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-06-10spi: Fix per-cpu stats access on 32 bit systemsDavid Jander
On 32 bit systems, the following kernel BUG is hit: BUG: using smp_processor_id() in preemptible [00000000] code: swapper/0/1 caller is debug_smp_processor_id+0x18/0x24 CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.19.0-rc1-00001-g6ae0aec8a366 #181 Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree) Backtrace: dump_backtrace from show_stack+0x20/0x24 r7:81024ffd r6:00000000 r5:81024ffd r4:60000013 show_stack from dump_stack_lvl+0x60/0x78 dump_stack_lvl from dump_stack+0x14/0x1c r7:81024ffd r6:80f652de r5:80bec180 r4:819a2500 dump_stack from check_preemption_disabled+0xc8/0xf0 check_preemption_disabled from debug_smp_processor_id+0x18/0x24 r8:8119b7e0 r7:81205534 r6:819f5c00 r5:819f4c00 r4:c083d724 debug_smp_processor_id from __spi_sync+0x78/0x220 __spi_sync from spi_sync+0x34/0x4c r10:bb7bf4e0 r9:c083d724 r8:00000007 r7:81a068c0 r6:822a83c0 r5:c083d724 r4:819f4c00 spi_sync from spi_mem_exec_op+0x338/0x370 r5:000000b4 r4:c083d910 spi_mem_exec_op from spi_nor_read_id+0x98/0xdc r10:bb7bf4e0 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:82358040 r4:819f7c40 spi_nor_read_id from spi_nor_detect+0x38/0x114 r7:82358040 r6:00000000 r5:819f7c40 r4:819f7c40 spi_nor_detect from spi_nor_scan+0x11c/0xbec r10:bb7bf4e0 r9:00000000 r8:00000000 r7:c083da4c r6:00000000 r5:00010101 r4:819f7c40 spi_nor_scan from spi_nor_probe+0x10c/0x2d0 r10:bb7bf4e0 r9:bb7bf4d0 r8:00000000 r7:819f4c00 r6:00000000 r5:00000000 r4:819f7c40 per-cpu access needs to be guarded against preemption. Fixes: 6598b91b5ac3 ("spi: spi.c: Convert statistics to per-cpu u64_stats_t") Reported-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: David Jander <david@protonic.nl> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220609121334.2984808-1-david@protonic.nl Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-10spi: sifive: add PM callbacks to support suspend/resumeAndy Chiu
The patch has been tested on Unmatched using pm_test. The Unmatched board uses SD over SPI and it was tested by initiating S2RAM cycles for all devices while reading/writing files at the same time. We found no dropped connection to the card or corrupted filesystem during test cycles. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Reviewed-by: Greentime Hu <greentime.hu@sifive.com> Link: https://lore.kernel.org/r/20220610074459.3261383-2-andy.chiu@sifive.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-09spi: atmel-quadspi: align condition to parenthesisClaudiu Beznea
Align condition to parenthesis. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220609084246.1795419-4-claudiu.beznea@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-09spi: atmel-quadspi: use pm_ptr()Claudiu Beznea
Use pm_ptr() for atmel_quadspi_pm_ops. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220609084246.1795419-3-claudiu.beznea@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-09spi: atmel-quadspi: add runtime pm supportClaudiu Beznea
Add runtime PM support for atmel-quadspi which will disable/enable QSPI clocks on proper runtime_suspend/runtime_resume ops. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220609084246.1795419-2-claudiu.beznea@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-09spi: Return true/false (not 1/0) from bool functionYang Li
Return boolean values ("true" or "false") instead of 1 or 0 from bool function. As reported by coccicheck: ./drivers/spi/spi-s3c64xx.c:385:9-10: WARNING: return of 0/1 in function 's3c64xx_spi_can_dma' with return type bool Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220609071250.59509-1-yang.lee@linux.alibaba.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-09spi: fix platform_no_drv_owner.cocci warningYang Li
Remove .owner field if calls are used which set it automatically. Eliminate the following coccicheck warning: ./drivers/spi/spi-microchip-core.c:624:3-8: No need to set .owner here. The core will do it. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/20220609055533.95866-1-yang.lee@linux.alibaba.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-08spi: s3c64xx: Fix spelling mistake "hannel" -> "channel"Colin Ian King
There is a spelling mistake in a dev_err message. Fix it. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20220608081912.2083086-1-colin.i.king@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-07spi: add support for microchip fpga spi controllersConor Dooley
Add a driver for Microchip FPGA SPI controllers, specifically supporting the "hard" controllers on PolarFire SoC. Co-developed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220607073833.2331539-2-conor.dooley@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-07spi: stm32-qspi: Remove unused parametersMark Brown
Merge series from patrice.chotard@foss.st.com <patrice.chotard@foss.st.com>: This series cleans up spi-stm32-qspi driver by removing unused parameters
2022-06-06spi: spi-ti-qspi: Support per-transfer and per-slave speed_hz settingsAtsushi Nemoto
The spi-ti-qspi driver initializes its spi clock by the spi-max-frequency property from the controller node, and ignores per-transfer (and per-slave) speed_hz settings. Isolate clock settings out from ti_qspi_setup() and call it from ti_qspi_start_transfer_one() and ti_qspi_exec_mem_op(), using per-transfer speed_hz and per-slave max_speed_hz settings. Also drop spi_max_frequency from struct ti_qspi and use spi_master's max_speed_hz. Signed-off-by: Atsushi Nemoto <atsushi.nemoto@sord.co.jp> Link: https://lore.kernel.org/r/20220519.084604.966119051165023533.atsushi.nemoto@sord.co.jp Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-06spi: spi.c: Convert statistics to per-cpu u64_stats_tDavid Jander
This change gives a dramatic performance improvement in the hot path, since many costly spin_lock_irqsave() calls can be avoided. On an i.MX8MM system with a MCP2518FD CAN controller connected via SPI, the time the driver takes to handle interrupts, or in other words the time the IRQ line of the CAN controller stays low is mainly dominated by the time it takes to do 3 relatively short sync SPI transfers. The effect of this patch is a reduction of this time from 136us down to only 98us. Suggested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David Jander <david@protonic.nl> Link: https://lore.kernel.org/r/20220524091808.2269898-1-david@protonic.nl Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-06spi: intel: Use correct order for the parameters of devm_kcalloc()Christophe JAILLET
We should have 'n', then 'size', not the opposite. This is harmless because the 2 values are just multiplied, but having the correct order silence a (unpublished yet) smatch warning. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/d114558dd0351b863ced8cc01b31754a5a4b960d.1653116362.git.christophe.jaillet@wanadoo.fr Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-06spi: spi-zynqmp-gqspi: Add two chip select supportAmit Kumar Mahapatra
ZynqMP GQSPI controller can support up to two chip selects but the current GQSPI driver only support CS0. With this update and num-cs DT property set to 2 GQSPI driver can now support two slave devices each connected to one chip select. GQSPI driver configures the Lower CS and Upper CS based on the reg DT property. Changes tested on ZynqMP board with two SPI-NOR flashes each connected to a different CS. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Link: https://lore.kernel.org/r/20220512145820.20425-1-amit.kumar-mahapatra@xilinx.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-06spi: cadence-quadspi: Remove spi_master_put() in probe failure pathVaishnav Achath
Currently the spi_master is allocated by devm_spi_alloc_master() and devres core manages the deallocation, but in probe failure path spi_master_put() is being handled manually which causes "refcount underflow use-after-free" warning when probe failure happens after allocating spi_master. Trimmed backtrace during failure: refcount_t: underflow; use-after-free. pc : refcount_warn_saturate+0xf4/0x144 Call trace: refcount_warn_saturate kobject_put put_device devm_spi_release_controller devres_release_all This commit makes relevant changes to remove spi_master_put() from probe failure path. Fixes: 606e5d408184 ("spi: cadence-quadspi: Handle spi_unregister_master() in remove()") Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Link: https://lore.kernel.org/r/20220601071611.11853-1-vaishnav.a@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-06spi: s3c64xx: requests spi-dma channel only during data transferAdithya K V
Current s3c64xx SPI driver acquires DMA channel during driver probe and holds on it even when channels are not used (no DMA transfer). This is a problem especially when all the DMA channels are exhausted (as other IPs on the same DMA controller also acquires DMA channel) and if a new IP/Device requests for a DMA channel (on the same DMA controller), it won’t get DMA channel allocated. The said issue can be avoided if s3c64xx driver request and release DMA channel before and after data transfer. Let’s modify the driver to request and release DMA channel before and after DMA mode data transfer. Signed-off-by: Adithya K V <adithya.kv@samsung.com> Link: https://lore.kernel.org/r/20220524140132.59300-1-adithya.kv@samsung.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-06spi: spi-altera-dfl: Fix an error handling pathChristophe JAILLET
The spi_alloc_master() call is not undone in all error handling paths. Moreover, there is no .remove function to release the allocated memory. In order to fix both this issues, switch to devm_spi_alloc_master(). This allows further simplification of the probe. Fixes: ba2fc167e944 ("spi: altera: Add DFL bus driver for Altera API Controller") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/0607bb59f4073f86abe5c585d35245aef0b045c6.1653805901.git.christophe.jaillet@wanadoo.fr Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-06spi: stm32-qspi: Remove stm32_qspi_wait_poll_status() unused parameterPatrice Chotard
op parameter is not used, remove it. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20220602092540.369604-4-patrice.chotard@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-06spi: stm32-qspi: Remove stm32_qspi_wait_cmd() unused parameterPatrice Chotard
struct spi_mem_op *op parameter is no more used, remove it. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20220602092540.369604-3-patrice.chotard@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-06spi: stm32-qspi: Remove stm32_qspi_get_mode() unused parameterPatrice Chotard
struct stm32_qspi *qsp is no more used remove it. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20220602092540.369604-2-patrice.chotard@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-06spi: spi-mem: Fix spi_mem_poll_status()Patrice Chotard
In spi_mem_exec_op(), in case cs_gpiod descriptor is set, exec_op() callback can't be used. The same must be applied in spi_mem_poll_status(), poll_status() callback can't be used, we must use the legacy path using read_poll_timeout(). Tested on STM32mp257c-ev1 specific evaluation board on which a spi-nand was mounted instead of a spi-nor. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20220602091022.358127-1-patrice.chotard@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-06spi: cadence: Detect transmit FIFO depthLars-Peter Clausen
The depth of the transmit FIFO for the Cadence SPI controller is currently hardcoded to 128. But the depth is a synthesis configuration parameter of the core and can vary between different SoCs. If the configured FIFO size is less than 128 the driver will busy loop in the cdns_spi_fill_tx_fifo() function waiting for FIFO space to become available. Depending on the length and speed of the transfer it can spin for a significant amount of time. The cdns_spi_fill_tx_fifo() function is called from the drivers interrupt handler, so it can leave interrupts disabled for a prolonged amount of time. In addition the read FIFO will also overflow and data will be discarded. To avoid this detect the actual size of the FIFO and use that rather than the hardcoded value. To detect the FIFO size the FIFO threshold register is used. The register is sized so that it can hold FIFO size - 1 as its maximum value. Bits that are not needed to hold the threshold value will always read 0. By writing 0xffff to the register and then reading back the value in the register we get the FIFO size. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20220527091143.3780378-1-lars@metafoo.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-06spi: spi-cadence: Fix SPI CS gets toggling sporadicallySai Krishna Potthuri
As part of unprepare_transfer_hardware, SPI controller will be disabled which will indirectly deassert the CS line. This will create a problem in some of the devices where message will be transferred with cs_change flag set(CS should not be deasserted). As per SPI controller implementation, if SPI controller is disabled then all output enables are inactive and all pins are set to input mode which means CS will go to default state high(deassert). This leads to an issue when core explicitly ask not to deassert the CS (cs_change = 1). This patch fix the above issue by checking the Slave select status bits from configuration register before disabling the SPI. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Link: https://lore.kernel.org/r/20220606062525.18447-1-amit.kumar-mahapatra@xilinx.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-03Merge tag 'driver-core-5.19-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core updates from Greg KH: "Here is the set of driver core changes for 5.19-rc1. Lots of tiny driver core changes and cleanups happened this cycle, but the two major things are: - firmware_loader reorganization and additions including the ability to have XZ compressed firmware images and the ability for userspace to initiate the firmware load when it needs to, instead of being always initiated by the kernel. FPGA devices specifically want this ability to have their firmware changed over the lifetime of the system boot, and this allows them to work without having to come up with yet-another-custom-uapi interface for loading firmware for them. - physical location support added to sysfs so that devices that know this information, can tell userspace where they are located in a common way. Some ACPI devices already support this today, and more bus types should support this in the future. Smaller changes include: - driver_override api cleanups and fixes - error path cleanups and fixes - get_abi script fixes - deferred probe timeout changes. It's that last change that I'm the most worried about. It has been reported to cause boot problems for a number of systems, and I have a tested patch series that resolves this issue. But I didn't get it merged into my tree before 5.18-final came out, so it has not gotten any linux-next testing. I'll send the fixup patches (there are 2) as a follow-on series to this pull request. All have been tested in linux-next for weeks, with no reported issues other than the above-mentioned boot time-outs" * tag 'driver-core-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (55 commits) driver core: fix deadlock in __device_attach kernfs: Separate kernfs_pr_cont_buf and rename_lock. topology: Remove unused cpu_cluster_mask() driver core: Extend deferred probe timeout on driver registration MAINTAINERS: add Russ Weight as a firmware loader maintainer driver: base: fix UAF when driver_attach failed test_firmware: fix end of loop test in upload_read_show() driver core: location: Add "back" as a possible output for panel driver core: location: Free struct acpi_pld_info *pld driver core: Add "*" wildcard support to driver_async_probe cmdline param driver core: location: Check for allocations failure arch_topology: Trace the update thermal pressure kernfs: Rename kernfs_put_open_node to kernfs_unlink_open_file. export: fix string handling of namespace in EXPORT_SYMBOL_NS rpmsg: use local 'dev' variable rpmsg: Fix calling device_lock() on non-initialized device firmware_loader: describe 'module' parameter of firmware_upload_register() firmware_loader: Move definitions from sysfs_upload.h to sysfs.h firmware_loader: Fix configs for sysfs split selftests: firmware: Add firmware upload selftests ...
2022-06-01Merge tag 'spi-fix-v5.19-rc0' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "A couple of fixes that came in during the merge window: a driver fix for spurious timeouts in the fsi driver and an improvement to make the core display error messages for transfer_one_message() to help people debug things" * tag 'spi-fix-v5.19-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: core: Display return code when failing to transfer message spi: fsi: Fix spurious timeout
2022-05-26Merge tag 'arm-multiplatform-5.19-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARMv4T/v5 multiplatform support from Arnd Bergmann: "This series has been 12 years in the making, it mostly finishes the work that was started with the founding of Linaro to clean up platform support in the kernel. The largest change here is a cleanup of the omap1 platform, which is the final ARM machine type to get converted to the common-clk subsystem. All the omap1 specific drivers are now made independent of the mach/*.h headers to allow the platform to be part of a generic ARMv4/v5 multiplatform kernel. The last bit that enables this support is still missing here while we wait for some last dependencies to make it into the mainline kernel through other subsystems. The s3c24xx, ixp4xx, iop32x, ep93xx and dove platforms were all almost at the point of allowing multiplatform kernels, this work gets completed here along with a few additional cleanup. At the same time, the s3c24xx and s3c64xx are now deprecated and expected to get removed in the future. The PXA and OMAP1 bits are in a separate branch because of dependencies. Once both branches are merged, only the three Intel StrongARM platforms (RiscPC, Footbridge/NetWinder and StrongARM1100) need separate kernels, and there are no plans to include these" * tag 'arm-multiplatform-5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (61 commits) ARM: ixp4xx: Consolidate Kconfig fixing issue ARM: versatile: Add missing of_node_put in dcscb_init ARM: config: Refresh IXP4xx config after multiplatform ARM: omap1: add back omap_set_dma_priority() stub ARM: omap: fix missing declaration warnings ARM: omap: fix address space warnings from sparse ARM: spear: remove include/mach/ subdirectory ARM: davinci: remove include/mach/ subdirectory ARM: omap2: remove include/mach/ subdirectory integrator: remove empty ap_init_early() ARM: s3c: fix include path MAINTAINERS: omap1: Add Janusz as an additional maintainer ARM: omap1: htc_herald: fix typos in comments ARM: OMAP1: fix typos in comments ARM: OMAP1: clock: Remove noop code ARM: OMAP1: clock: Remove unused code ARM: OMAP1: clock: Fix UART rate reporting algorithm ARM: OMAP1: clock: Fix early UART rate issues ARM: OMAP1: Prepare for conversion of OMAP1 clocks to CCF ARM: omap1: fix build with no SoC selected ...
2022-05-26spi: core: Display return code when failing to transfer messageEddie James
All the other calls to the controller driver display the error return code. The return code is helpful to understand what went wrong, so include it when failing to transfer one message. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20220525165852.33167-3-eajames@linux.ibm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-05-26spi: fsi: Fix spurious timeoutEddie James
The driver may return a timeout error even if the status register indicates that the transfer may proceed. Fix this by restructuring the polling loop. Fixes: 89b35e3f2851 ("spi: fsi: Implement a timeout for polling status") Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20220525165852.33167-2-eajames@linux.ibm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-05-25Merge tag 'sound-5.19-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound Pull sound updates from Takashi Iwai: "Not much dramatic changes at this time, but we've received quite a lot of changes for ASoC, while there are still a few fixes and quirks for usual HD- and USB-auido. Here are some highlights. ASoC: - Overhaul of endianness specification for data formats, avoiding needless restrictions due to CODECs - Initial stages of Intel AVS driver merge - Introduction of v4 IPC mechanism for SOF - TDM mode support for AK4613 - Support for Analog Devices ADAU1361, Cirrus Logic CS35L45, Maxim MAX98396, MediaTek MT8186, NXP i.MX8 micfil and SAI interfaces, nVidia Tegra186 ASRC, and Texas Instruments TAS2764 and TAS2780 Others: - A few regression fixes after the USB-audio endpoint management refactoring - More enhancements for Cirrus HD-audio codec support (still ongoing) - Addition of generic serial MIDI driver" * tag 'sound-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (504 commits) ALSA: hda/realtek - Add new type for ALC245 ALSA: usb-audio: Configure sync endpoints before data ALSA: ctxfi: fix typo in comment ALSA: cs5535audio: fix typo in comment ALSA: ctxfi: Add SB046x PCI ID ALSA: usb-audio: Add missing ep_idx in fixed EP quirks ALSA: usb-audio: Workaround for clock setup on TEAC devices ALSA: lola: Bounds check loop iterator against streams array size ASoC: max98090: Move check for invalid values before casting in max98090_put_enab_tlv() ASoC: rt1308-sdw: add the default value of register 0xc320 ASoC: rt9120: Use pm_runtime and regcache to optimize 'pwdnn' logic ASoC: rt9120: Fix 3byte read, valule offset typo ASoC: amd: acp: Set Speaker enable/disable pin through rt1019 codec driver. ASoC: amd: acp: Set Speaker enable/disable pin through rt1019 codec driver ASoC: wm2000: fix missing clk_disable_unprepare() on error in wm2000_anc_transition() ASoC: codecs: lpass: Fix passing zero to 'PTR_ERR' ASoC: SOF: sof-client-ipc-flood-test: use pm_runtime_resume_and_get() ASoC: SOF: mediatek: remove duplicate include in mt8195.c ASoC: SOF: mediatek: Add mt8195 debug dump ASoC: SOF: mediatek: Add mediatek common debug dump ...
2022-05-24Merge tag 'spi-v5.19' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi updates from Mark Brown: "This is quite a quiet release but some new drivers mean that the diffstat is fairly large. The new drivers include the aspeed driver which is migrated from MTD as part of the ongoing move of controllers with specialised support for SPI flashes into the SPI subsystem. - Support for devices which flip CPHA during recieve only transfers (eg, if MOSI and MISO have inverted polarity). - Overhaul of the i.MX driver, including the addition of PIO support for better performance on small transfers. - Migration of the Aspeed driver from MTD. - Support for Aspeed AST2400, Ingenic JZ4775 and X1/2000 and MediaTek IPM and SFI" * tag 'spi-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (84 commits) spi: spi-au1550: replace ternary operator with min() mtd: spi-nor: aspeed: set the decoding size to at least 2MB for AST2600 spi: aspeed: Calibrate read timings spi: aspeed: Add support for the AST2400 SPI controller spi: aspeed: Workaround AST2500 limitations spi: aspeed: Adjust direct mapping to device size spi: aspeed: Add support for direct mapping spi: spi-mem: Convert Aspeed SMC driver to spi-mem spi: Convert the Aspeed SMC controllers device tree binding spi: spi-cadence: Update ISR status variable type to irqreturn_t spi: Doc fix - Describe add_lock and dma_map_dev in spi_controller spi: cadence-quadspi: Handle spi_unregister_master() in remove() spi: stm32-qspi: Remove SR_BUSY bit check before sending command spi: stm32-qspi: Always check SR_TCF flags in stm32_qspi_wait_cmd() spi: stm32-qspi: Fix wait_cmd timeout in APM mode spi: cadence-quadspi: remove unnecessary (void *) casts spi: cadence-quadspi: Add missing blank line in cqspi_request_mmap_dma() spi: spi-imx: mx51_ecspi_prepare_message(): skip writing MX51_ECSPI_CONFIG register if unchanged spi: spi-imx: add PIO polling support spi: spi-imx: replace struct spi_imx_data::bitbang by pointer to struct spi_controller ...
2022-05-23Merge tag 'asoc-v5.19' of ↵Takashi Iwai
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus ASoC: Updates for v5.19 This is quite a big update, partly due to the addition of some larger drivers (more of which is to follow since at least the AVS driver is still a work in progress) and partly due to Charles' work sorting out our handling of endianness. As has been the case recently it's much more about drivers than the core. - Overhaul of endianness specification for data formats, avoiding needless restrictions due to CODECs. - Initial stages of Intel AVS driver merge. - Introduction of v4 IPC mechanism for SOF. - TDM mode support for AK4613. - Support for Analog Devices ADAU1361, Cirrus Logic CS35L45, Maxim MAX98396, MediaTek MT8186, NXP i.MX8 micfil and SAI interfaces, nVidia Tegra186 ASRC, and Texas Instruments TAS2764 and TAS2780
2022-05-16spi: spi-mem: Convert Aspeed SMC driver to spi-memMark Brown
Merge series from Cédric Le Goater <clg@kaod.org>: This series adds a new SPI driver using the spi-mem interface for the Aspeed static memory controllers of the AST2600, AST2500 and AST2400 SoCs. * AST2600 Firmware SPI Memory Controller (FMC) * AST2600 SPI Flash Controller (SPI1 and SPI2) * AST2500 Firmware SPI Memory Controller (FMC) * AST2500 SPI Flash Controller (SPI1 and SPI2) * AST2400 New Static Memory Controller (also referred as FMC) * AST2400 SPI Flash Controller (SPI) It is based on the current OpenBMC kernel driver [1], using directly the MTD SPI-NOR interface and on a patchset [2] previously proposed adding support for the AST2600 only. This driver takes a slightly different approach to cover all 6 controllers. It does not make use of the controller register disabling Address and Data byte lanes because is not available on the AST2400 SoC. We could introduce a specific handler for new features available on recent SoCs if needed. As there is not much difference on performance, the driver chooses the common denominator: "User mode" which has been heavily tested in [1]. "User mode" is also used as a fall back method when flash device mapping window is too small. Problems to address with spi-mem were the configuration of the mapping windows and the calibration of the read timings. The driver handles them in the direct mapping handler when some knowledge on the size of the flash device is know. It is not perfect but not incorrect either. The algorithm is one from [1] because it doesn't require the DMA registers which are not available on all controllers. Direct mapping for writes is not supported (yet). I have seen some corruption with writes and I preferred to use the safer and proven method of the initial driver [1]. We can improve that later. The driver supports Quad SPI RX transfers on the AST2600 SoC but it didn't have the expected results. Therefore it is not activated yet. There are some issues on the pinctrl to investigate first. Tested on: * OpenPOWER Palmetto (AST2400) * Facebook Wedge 100 BMC (AST2400) by Tao Ren <rentao.bupt@gmail.com> * Evaluation board (AST2500) * Inspur FP5280G2 BMC (AST2500) by John Wang <wangzq.jn@gmail.com> * Facebook Backpack CMM BMC (AST2500) by Tao Ren <rentao.bupt@gmail.com> * OpenPOWER Witherspoon (AST2500) * Evaluation board (AST2600 A0 and A3) * Rainier board (AST2600) [1] https://github.com/openbmc/linux/blob/dev-5.15/drivers/mtd/spi-nor/controllers/aspeed-smc.c [2] https://patchwork.ozlabs.org/project/linux-aspeed/list/?series=212394
2022-05-16spi: spi-au1550: replace ternary operator with min()Guo Zhengkui
Fix the following coccicheck warnings: drivers/spi/spi-au1550.c:408:21-22: WARNING opportunity for min() drivers/spi/spi-au1550.c:542:21-22: WARNING opportunity for min() min() macro is defined in include/linux/minmax.h. It avoids multiple evaluations of the arguments when non-constant and performs strict type-checking. Signed-off-by: Guo Zhengkui <guozhengkui@vivo.com> Link: https://lore.kernel.org/r/20220513130333.58379-1-guozhengkui@vivo.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-05-16mtd: spi-nor: aspeed: set the decoding size to at least 2MB for AST2600Potin Lai
In AST2600, the unit of SPI CEx decoding range register is 1MB, and end address offset is set to the acctual offset - 1MB. If the flash only has 1MB, the end address will has same value as start address, which will causing unexpected errors. This patch set the decoding size to at least 2MB to avoid decoding errors. Tested: root@bletchley:~# dmesg | grep "aspeed-smc 1e631000.spi: CE0 window" [ 59.328134] aspeed-smc 1e631000.spi: CE0 window resized to 2MB (AST2600 Decoding) [ 59.343001] aspeed-smc 1e631000.spi: CE0 window [ 0x50000000 - 0x50200000 ] 2MB root@bletchley:~# devmem 0x1e631030 0x00100000 Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Signed-off-by: Potin Lai <potin.lai@quantatw.com> [ clg : Ported on new spi-mem driver ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Link: https://lore.kernel.org/r/20220509175616.1089346-12-clg@kaod.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-05-16spi: aspeed: Calibrate read timingsCédric Le Goater
To accommodate the different response time of SPI transfers on different boards and different SPI NOR devices, the Aspeed controllers provide a set of Read Timing Compensation registers to tune the timing delays depending on the frequency being used. The AST2600 SoC has one of these registers per device. On the AST2500 and AST2400 SoCs, the timing register is shared by all devices which is problematic to get good results other than for one device. The algorithm first reads a golden buffer at low speed and then performs reads with different clocks and delay cycle settings to find a breaking point. This selects a default good frequency for the CEx control register. The current settings are a bit optimistic as we pick the first delay giving good results. A safer approach would be to determine an interval and choose the middle value. Calibration is performed when the direct mapping for reads is created. Since the underlying spi-nor object needs to be initialized to create the spi_mem operation for direct mapping, we should be fine. Having a specific API would clarify the requirements though. Cc: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Joel Stanley <joel@jms.id.au> Tested-by: Tao Ren <rentao.bupt@gmail.com> Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Link: https://lore.kernel.org/r/20220509175616.1089346-9-clg@kaod.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-05-16spi: aspeed: Add support for the AST2400 SPI controllerCédric Le Goater
Extend the driver for the AST2400 SPI Flash Controller (SPI). This controller has a slightly different interface which requires adaptation of the 4B handling. Summary of features : . host Firmware . 1 chip select pin (CE0) . slightly different register set, between AST2500 and the legacy controller . no segment registers . single, dual mode. Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Joel Stanley <joel@jms.id.au> Tested-by: Tao Ren <rentao.bupt@gmail.com> Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Link: https://lore.kernel.org/r/20220509175616.1089346-8-clg@kaod.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-05-16spi: aspeed: Workaround AST2500 limitationsCédric Le Goater
It is not possible to configure a full 128MB window for a chip of the same size on the AST2500 SPI controller. For this case, the maximum window size is restricted to 120MB for CE0. Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Joel Stanley <joel@jms.id.au> Tested-by: Tao Ren <rentao.bupt@gmail.com> Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Link: https://lore.kernel.org/r/20220509175616.1089346-7-clg@kaod.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-05-16spi: aspeed: Adjust direct mapping to device sizeCédric Le Goater
The segment registers of the FMC/SPI controllers provide a way to configure the mapping window of the flash device contents on the AHB bus. Adjust this window to the size of the spi-mem mapping. Things get more complex with multiple devices. The driver needs to also adjust the window of the next device to make sure that there is no overlap, even if there is no available device. The proposal below is not perfect but it is covering all the cases we have seen on different boards with one and two devices on the same bus. Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Joel Stanley <joel@jms.id.au> Tested-by: Tao Ren <rentao.bupt@gmail.com> Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Link: https://lore.kernel.org/r/20220509175616.1089346-6-clg@kaod.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-05-16spi: aspeed: Add support for direct mappingCédric Le Goater
Use direct mapping to read the flash device contents. This operation mode is called "Command mode" on Aspeed SoC SMC controllers. It uses a Control Register for the settings to apply when a memory operation is performed on the flash device mapping window. If the window is not big enough, fall back to the "User mode" to perform the read. Direct mapping for writes will come later when validated. Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Joel Stanley <joel@jms.id.au> Tested-by: Tao Ren <rentao.bupt@gmail.com> Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Link: https://lore.kernel.org/r/20220509175616.1089346-5-clg@kaod.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-05-16spi: spi-mem: Convert Aspeed SMC driver to spi-memCédric Le Goater
This SPI driver adds support for the Aspeed static memory controllers of the AST2600, AST2500 and AST2400 SoCs using the spi-mem interface. * AST2600 Firmware SPI Memory Controller (FMC) . BMC firmware . 3 chip select pins (CE0 ~ CE2) . Only supports SPI type flash memory . different segment register interface . single, dual and quad mode. * AST2600 SPI Flash Controller (SPI1 and SPI2) . host firmware . 2 chip select pins (CE0 ~ CE1) . different segment register interface . single, dual and quad mode. * AST2500 Firmware SPI Memory Controller (FMC) . BMC firmware . 3 chip select pins (CE0 ~ CE2) . supports SPI type flash memory (CE0-CE1) . CE2 can be of NOR type flash but this is not supported by the driver . single, dual mode. * AST2500 SPI Flash Controller (SPI1 and SPI2) . host firmware . 2 chip select pins (CE0 ~ CE1) . single, dual mode. * AST2400 New Static Memory Controller (also referred as FMC) . BMC firmware . New register set . 5 chip select pins (CE0 ∼ CE4) . supports NOR flash, NAND flash and SPI flash memory. . single, dual and quad mode. Each controller has a memory range on which flash devices contents are mapped. Each device is assigned a window that can be changed at bootime with the Segment Address Registers. Each SPI flash device can then be accessed in two modes: Command and User. When in User mode, SPI transfers are initiated with accesses to the memory segment of a device. When in Command mode, memory operations on the memory segment of a device generate SPI commands automatically using a Control Register for the settings. This initial patch adds support for User mode. Command mode needs a little more work to check that the memory window on the AHB bus fits the device size. It will come later when support for direct mapping is added. Single and dual mode RX transfers are supported. Other types than SPI are not supported. Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Joel Stanley <joel@jms.id.au> Tested-by: Tao Ren <rentao.bupt@gmail.com> Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Link: https://lore.kernel.org/r/20220509175616.1089346-4-clg@kaod.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-05-13spi: spi-cadence: Update ISR status variable type to irqreturn_tAmit Kumar Mahapatra
Data type of status variable, that hold the return value of the ISR, should be irqreturn_t & not u32. This patch updates status variable type to irqreturn_t. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Link: https://lore.kernel.org/r/20220512145025.20205-1-amit.kumar-mahapatra@xilinx.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-05-12spi: cadence-quadspi: Handle spi_unregister_master() in remove()Vaishnav Achath
Currently devres managed removal of the spi_controller happens after removing the power domain of the host platform_device.While this does not affect the clean removal of the controller, but affects graceful removal of the child devices if the child device removal requires issuing commands over SPI. Eg. flash device being soft reset to 1S-1S-1S mode before removal so that on next probe operations in 1S-1S-1S mode is successful. Failure is seen when `rmmod spi-cadence-quadspi` is performed: root@j7-evm:~# rmmod spi_cadence_quadspi [ 49.230996] cadence-qspi 47050000.spi: QSPI is still busy after 500ms timeout. [ 49.238209] spi-nor spi1.0: operation failed with -110 [ 49.244457] spi-nor spi1.0: Software reset failed: -110 and on subsequent modprobe the OSPI flash probe fails as it is in 8D-8D-8D mode since the previous soft reset did not happen. root@j7-evm:~# modprobe spi_cadence_quadspi [ 73.253536] spi-nor spi0.0: unrecognized JEDEC id bytes: ff ff ff ff ff ff [ 73.260476] spi-nor: probe of spi0.0 failed with error -2 This commit adds necessary changes to perform spi_unregister_master() in the host device remove() so that the child devices are gracefully removed before the power domain is removed. changes tested on J721E with mt35xu512aba flash. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Link: https://lore.kernel.org/r/20220511115516.14894-1-vaishnav.a@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-05-11spi: stm32-qspi: flags management fixesMark Brown
Merge series from patrice.chotard@foss.st.com <patrice.chotard@foss.st.com> Patrice Chotard <patrice.chotard@foss.st.com>: From: Patrice Chotard <patrice.chotard@foss.st.com> This series update flags management in the following cases: - In APM mode, don't take care of TCF and TEF flags - Always check TCF flag in stm32_qspi_wait_cmd() - Don't check BUSY flag when sending new command
2022-05-11spi: stm32-qspi: Remove SR_BUSY bit check before sending commandPatrice Chotard
Waiting for SR_BUSY bit when receiving a new command is not needed. SR_BUSY bit is already managed in the previous command treatment. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20220511074644.558874-4-patrice.chotard@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-05-11spi: stm32-qspi: Always check SR_TCF flags in stm32_qspi_wait_cmd()Patrice Chotard
Currently, SR_TCF flag is checked in case there is data, this criteria is not correct. SR_TCF flags is set when programmed number of bytes has been transferred to the memory device ("bytes" comprised command and data send to the SPI device). So even if there is no data, we must check SR_TCF flag. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20220511074644.558874-3-patrice.chotard@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
generated by cgit v1.2.3 (git 2.46.0) at 2025-07-31 06:46:23 +0000