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path: root/drivers/spi
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2022-08-29spi: sh-msiof: add generic Gen4 bindingWolfram Sang
No further changes in this generation discovered yet. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220824094327.33685-3-wsa+renesas@sang-engineering.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-28spi: stm32-qspi: Fix stm32_qspi_transfer_one_message() error pathPatrice Chotard
The patch a557fca630cc: "spi: stm32_qspi: Add transfer_one_message() spi callback" from Aug 23, 2022, leads to the following Smatch static checker warning: drivers/spi/spi-stm32-qspi.c:627 stm32_qspi_transfer_one_message() error: uninitialized symbol 'ret'.Fix the following Smatch static checker warning: Fixes: a557fca630cc ("spi: stm32_qspi: Add transfer_one_message() spi callback") Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20220826092031.1393430-1-patrice.chotard@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-25spi: amd: Configure device speedLucas Tanure
Number of clock frequencies are supported by AMD controller which are mentioned in the amd_spi_freq structure table. Create mechanism to configure device clock frequency such that it is strictly less than the requested frequency. Give priority to the device transfer speed and in case it is not set then use the max clock speed supported by the device. Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Co-developed-by: Shreeya Patel <shreeya.patel@collabora.com> Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com> Link: https://lore.kernel.org/r/20220825143132.253224-1-shreeya.patel@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-25spi: pxa2xx: Remove the unneeded result variableye xingchen
Return the value clk_prepare_enable() directly instead of storing it in another redundant variable. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn> Link: https://lore.kernel.org/r/20220825072828.229294-1-ye.xingchen@zte.com.cn Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-24ACPI: Drop parent field from struct acpi_deviceRafael J. Wysocki
The parent field in struct acpi_device is, in fact, redundant, because the dev.parent field in it effectively points to the same object and it is used by the driver core. Accordingly, the parent field can be dropped from struct acpi_device and for this purpose define acpi_dev_parent() to retrieve a parent struct acpi_device pointer from the dev.parent field in struct acpi_device. Next, update all of the users of the parent field in struct acpi_device to use acpi_dev_parent() instead of it and drop it. While at it, drop the ACPI_IS_ROOT_DEVICE() macro that is only used in one place in a confusing way. No intentional functional impact. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Wei Liu <wei.liu@kernel.org> Reviewed-by: Punit Agrawal <punit.agrawal@bytedance.com>
2022-08-23spi: stm32_qspi: use QSPI bus as 8 lines communication channelMark Brown
Merge series from patrice.chotard@foss.st.com <patrice.chotard@foss.st.com>: The goal of this series is to allow to use QSPI bus as a 8 lines communication channel for specific purpose. The QSPI block offers the possibility to communicate with 2 flashes in parrallel using the dual flash mode, 8 data lines are then used. Usage of cs-gpios populated and spi-tx-bus-width / spi-rx-bus-width both set to 8, is needed to enable dual flash mode. The addition of the legacy transfer_one_message() spi callback is also needed as currently the stm32-qspi driver only supports spi_controller_mem_ops API.
2022-08-23spi: dw: Quite logging on deferred controller registrationSerge Semin
It's pretty possible to have the spi_register_controller() method returning -EPROBE_DEFER status in case, for instance, if the GPIOs used for the CS implementation aren't ready to be requested due to the corresponding platform devices still pending to be probed. Let's make sure the DW SSI driver won't print error message in that case by calling the dev_err_probe() function if the SPI-registration procedure exited with a non-zero status. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20220822181853.23063-1-Sergey.Semin@baikalelectronics.ru Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-23spi: stm32_qspi: Add transfer_one_message() spi callbackPatrice Chotard
Add transfer_one_message() spi callback in order to use the QSPI interface as a communication channel using up to 8 qspi lines (QSPI configured in dual flash mode). To enable this mode, both spi-rx-bus-width and spi-tx-bus-width must be set to 8 and cs-qpios must be populated. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20220823075850.575043-3-patrice.chotard@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-22spi: intel: 64k erase is supported from Canon Lake and beyondMika Westerberg
The hardware sequencer in Intel Canon Lake and beyond supports also 64k erase command. The SPI-NOR core uses SFDP (Serial Flash Discovery Parameter) to figure out what the chip actually supports and only issues 64k erase if it is supported. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20220816125537.89389-1-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-22spi: intel: Add support for second flash chipMika Westerberg
Intel SPI flash controller has been supporting two chip selects long time already even if the most common configuration is to have a single flash chip for the BIOS and related data. This adds support for the second chip select if we find out that there are two flash components (this information is available in the mandatory flash descriptor on the first chip). The second chip is exposed as is without any partition information. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20220816130818.89600-1-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-22spi: cadence-quadspi: Disable irqs during indirect readsNiravkumar L Rabara
On architecture where reading the SRAM is slower than the pace at controller fills it, with interrupt enabled while reading from SRAM FIFO causes unwanted interrupt storm to CPU. The inner "bytes to read" loop never exits and waits for the completion so it is enough to only enable the watermark interrupt when we are out of bytes to read, which only happens when we start the transfer (waiting for the FIFO to fill up initially) if the SRAM is slow. So only using read watermark interrupt, as the current implementation doesn't utilize the SRAM full and indirect complete read interrupt. And disable all the read interrupts while reading from SRAM. Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> Link: https://lore.kernel.org/r/20220813042616.1372110-1-niravkumar.l.rabara@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-19spi: move from strlcpy with unused retval to strscpyWolfram Sang
Follow the advice of the below link and prefer 'strscpy' in this subsystem. Conversion is 1:1 because the return value is not used. Generated by a coccinelle script. Link: https://lore.kernel.org/r/CAHk-=wgfRnXz0W3D37d01q3JFkr_i_uTL=V6A6G1oUZcprmknw@mail.gmail.com/ Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220818210107.7373-1-wsa+renesas@sang-engineering.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-18spi: amd: Setup all xfers before opcode executionCristian Ciocaltea
The AMD SPI controller hardware seems to expect the FIFO buffer to be fully setup with the details of all transfers in the SPI message before it is able to start processing the data in a reliable way. Furthermore, it imposes a strict ordering restriction, in the sense that all TX transfers must be handled prior any RX transfer. Hence, let's ensure amd_spi_execute_opcode() is called only once, after all TX transfers have been setup, and process any remaining RX transfers afterwards, in a second iteration. Additionally, get rid of the unnecessary AMD_SPI_XFER_TX/RX defines and improve error handling. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220818010059.403776-1-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-16Merge tag 'spi-fix-v6.0-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "A few fixes that came in since my pull request, the Meson fix is a little large since it's fixing all possible cases of the problem that was observed with the driver and clock API trying to share configuration by integrating the device clocking fully with the clock API rather than spot fixing the one instance that was observed" * tag 'spi-fix-v6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: dt-bindings: Drop Pratyush Yadav spi: meson-spicc: add local pow2 clock ops to preserve rate between messages MAINTAINERS: rectify entry for ARM/HPE GXP ARCHITECTURE spi: spi.c: Add missing __percpu annotations in users of spi_statistics
2022-08-15spi: npcm-pspi: add Arbel NPCM8XX supportMark Brown
Merge series from Tomer Maimon <tmaimon77@gmail.com>: This patch set adds Arbel NPCM8XX Peripheral SPI (PSPI) support to PSPI NPCM driver.
2022-08-15Add support for Microchip QSPI controllerMark Brown
Merge series from Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>: This patch enables the Microchip's FPGA QSPI and Polarfire SoC QSPI controller support. Tested spi-nand (W25N01GV) and spi-nor (MT25QL256A) on Microchip's ICICLE kit. tested using both FPGA QSPI and Polarfie SoC QSPI.
2022-08-15spi: lpspi: Simplify some error messageChristophe JAILLET
dev_err_probe() already prints the error code in a human readable way, so there is no need to duplicate it as a numerical value at the end of the message. Fixes: 12f62a857c83 ("spi: lpspi: Silence error message upon deferred probe") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-By: Alexander Stein <alexander.stein@ew.tq-group.com> Link: https://lore.kernel.org/r/253543c462b765eca40ba54c66f4e3fdf4acdeb7.1659735546.git.christophe.jaillet@wanadoo.fr Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-15spi: microchip-core: Simplify some error messageChristophe JAILLET
dev_err_probe() already prints the error code in a human readable way, so there is no need to duplicate it as a numerical value at the end of the message. Moreover, in the case of devm_clk_get() it would only display '0' because 'ret' is know to be 0 at this point. Fixes: cdeaf3a99a02 ("spi: microchip-core: switch to use dev_err_probe()") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/fb894ecec68e03fb7fc9353027c8b1a2610833d7.1659735153.git.christophe.jaillet@wanadoo.fr Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-15spi: s3c64xx: correct dma_chan pointer initializationChanho Park
Use NULL for dma channel pointer initialization instead of plain integer. sparse warnings: (new ones prefixed by >>) >> drivers/spi/spi-s3c64xx.c:387:34: sparse: sparse: Using plain integer as NULL pointer drivers/spi/spi-s3c64xx.c:388:34: sparse: sparse: Using plain integer as NULL pointer Reported-by: kernel test robot <lkp@intel.com> Fixes: 82295bc0d192 ("spi: s3c64xx: move dma_release_channel to unprepare") Fixes: f52b03c70744 ("spi: s3c64xx: requests spi-dma channel only during data transfer") Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Andi Shyti <andi@etezian.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220808004851.25122-1-chanho61.park@samsung.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-15spi: microchip-core-qspi: Add support for microchip fpga qspi controllersNaga Sureshkumar Relli
Add a driver for Microchip FPGA QSPI controllers. This driver also supports "hard" QSPI controllers on Polarfire SoC. Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220808064603.1174906-4-nagasuresh.relli@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-15spi: npcm-pspi: Add NPCM845 peripheral SPI supportTomer Maimon
Add Nuvoton BMC NPCM845 NPCM Peripheral SPI (PSPI) support. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20220722114136.251415-3-tmaimon77@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-15spi: bitbang: Fix lsb-first RxRobin Murphy
Shifting the recieved bit by "bits" inserts it at the top of the *currently remaining* Tx data, so we end up accumulating the whole transfer into bit 0 of the output word. Oops. For the algorithm to work as intended, we need to remember where the top of the *original* word was, and shift Rx to there. Fixes: 1847e3046c52 ("spi: gpio: Implement LSB First bitbang support") Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/28324d8622da80461cce35a82859b003d6f6c4b0.1659538737.git.robin.murphy@arm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-15Merge remote-tracking branch 'spi/for-5.20' into spi-6.0Mark Brown
2022-08-11spi: meson-spicc: add local pow2 clock ops to preserve rate between messagesNeil Armstrong
At the end of a message, the HW gets a reset in meson_spicc_unprepare_transfer(), this resets the SPICC_CONREG register and notably the value set by the Common Clock Framework. This is problematic because: - the register value CCF can be different from the corresponding CCF cached rate - CCF is allowed to change the clock rate whenever the HW state This introduces: - local pow2 clock ops checking the HW state before allowing a clock operation - separation of legacy pow2 clock patch and new enhanced clock path - SPICC_CONREG datarate value is now value kepts across messages It has been checked that: - SPICC_CONREG datarate value is kept across messages - CCF is only allowed to change the SPICC_CONREG datarate value when busy - SPICC_CONREG datarate value is correct for each transfer This didn't appear before commit 3e0cf4d3fc29 ("spi: meson-spicc: add a linear clock divider support") because we recalculated and wrote the rate for each xfer. Fixes: 3e0cf4d3fc29 ("spi: meson-spicc: add a linear clock divider support") Reported-by: Da Xue <da@libre.computer> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220811134445.678446-1-narmstrong@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-06Merge tag 'powerpc-6.0-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull powerpc updates from Michael Ellerman: - Add support for syscall stack randomization - Add support for atomic operations to the 32 & 64-bit BPF JIT - Full support for KASAN on 64-bit Book3E - Add a watchdog driver for the new PowerVM hypervisor watchdog - Add a number of new selftests for the Power10 PMU support - Add a driver for the PowerVM Platform KeyStore - Increase the NMI watchdog timeout during live partition migration, to avoid timeouts due to increased memory access latency - Add support for using the 'linux,pci-domain' device tree property for PCI domain assignment - Many other small features and fixes Thanks to Alexey Kardashevskiy, Andy Shevchenko, Arnd Bergmann, Athira Rajeev, Bagas Sanjaya, Christophe Leroy, Erhard Furtner, Fabiano Rosas, Greg Kroah-Hartman, Greg Kurz, Haowen Bai, Hari Bathini, Jason A. Donenfeld, Jason Wang, Jiang Jian, Joel Stanley, Juerg Haefliger, Kajol Jain, Kees Cook, Laurent Dufour, Madhavan Srinivasan, Masahiro Yamada, Maxime Bizon, Miaoqian Lin, Murilo Opsfelder Araújo, Nathan Lynch, Naveen N. Rao, Nayna Jain, Nicholas Piggin, Ning Qiang, Pali Rohár, Petr Mladek, Rashmica Gupta, Sachin Sant, Scott Cheloha, Segher Boessenkool, Stephen Rothwell, Uwe Kleine-König, Wolfram Sang, Xiu Jianfeng, and Zhouyi Zhou. * tag 'powerpc-6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (191 commits) powerpc/64e: Fix kexec build error EDAC/ppc_4xx: Include required of_irq header directly powerpc/pci: Fix PHB numbering when using opal-phbid powerpc/64: Init jump labels before parse_early_param() selftests/powerpc: Avoid GCC 12 uninitialised variable warning powerpc/cell/axon_msi: Fix refcount leak in setup_msi_msg_address powerpc/xive: Fix refcount leak in xive_get_max_prio powerpc/spufs: Fix refcount leak in spufs_init_isolated_loader powerpc/perf: Include caps feature for power10 DD1 version powerpc: add support for syscall stack randomization powerpc: Move system_call_exception() to syscall.c powerpc/powernv: rename remaining rng powernv_ functions to pnv_ powerpc/powernv/kvm: Use darn for H_RANDOM on Power9 powerpc/powernv: Avoid crashing if rng is NULL selftests/powerpc: Fix matrix multiply assist test powerpc/signal: Update comment for clarity powerpc: make facility_unavailable_exception 64s powerpc/platforms/83xx/suspend: Remove write-only global variable powerpc/platforms/83xx/suspend: Prevent unloading the driver powerpc/platforms/83xx/suspend: Reorder to get rid of a forward declaration ...
2022-08-05spi: spi.c: Add missing __percpu annotations in users of spi_statisticsDavid Jander
Fixes sparse warnings of this kind: drivers/spi/spi.c:117:16: sparse: expected struct spi_statistics * drivers/spi/spi.c:117:16: sparse: got struct spi_statistics [noderef] __percpu *[assigned] pcpu_stats Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: David Jander <david@protonic.nl> Link: https://lore.kernel.org/r/20220805084458.1602277-1-david@protonic.nl Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-04Merge tag 'driver-core-6.0-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core / kernfs updates from Greg KH: "Here is the set of driver core and kernfs changes for 6.0-rc1. The "biggest" thing in here is some scalability improvements for kernfs for large systems. Other than that, included in here are: - arch topology and cache info changes that have been reviewed and discussed a lot. - potential error path cleanup fixes - deferred driver probe cleanups - firmware loader cleanups and tweaks - documentation updates - other small things All of these have been in the linux-next tree for a while with no reported problems" * tag 'driver-core-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (63 commits) docs: embargoed-hardware-issues: fix invalid AMD contact email firmware_loader: Replace kmap() with kmap_local_page() sysfs docs: ABI: Fix typo in comment kobject: fix Kconfig.debug "its" grammar kernfs: Fix typo 'the the' in comment docs: driver-api: firmware: add driver firmware guidelines. (v3) arch_topology: Fix cache attributes detection in the CPU hotplug path ACPI: PPTT: Leave the table mapped for the runtime usage cacheinfo: Use atomic allocation for percpu cache attributes drivers/base: fix userspace break from using bin_attributes for cpumap and cpulist MAINTAINERS: Change mentions of mpm to olivia docs: ABI: sysfs-devices-soc: Update Lee Jones' email address docs: ABI: sysfs-class-pwm: Update Lee Jones' email address Documentation/process: Add embargoed HW contact for LLVM Revert "kernfs: Change kernfs_notify_list to llist." ACPI: Remove the unused find_acpi_cpu_cache_topology() arch_topology: Warn that topology for nested clusters is not supported arch_topology: Add support for parsing sockets in /cpu-map arch_topology: Set cluster identifier in each core/thread from /cpu-map arch_topology: Limit span of cpu_clustergroup_mask() ...
2022-08-02Merge tag 'spi-v5.20' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi updates from Mark Brown: "The big update this time around is some excellent work from David Jander who went through the fast path and really eliminated overheads, meaning that we are seeing a huge reduction in the time spent between transfers for single threaded clients. Benchmarking has been coming out at about a halving of overhead which is clearly visible in system level usage that stresses SPI like some CAN and IIO applications, especially with small transfers. Thanks to David for taking the time to drill down into this and push the work upstream. Otherwise there's been a bunch of new device support and the usual updates. - Optimisation of the fast path, particularly around the number and types of locking operations, from David Jander. - Support for Arbel NPCM845, HP GXP, Intel Meteor Lake and Thunder Bay, MediaTek MT8188 and MT8365, Microchip FPGAs, nVidia Tegra 241 and Samsung Exynos Auto v9 and 4210" * tag 'spi-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (97 commits) MAINTAINERS: add spi support to GXP spi: dt-bindings: add documentation for hpe,gxp-spifi spi: spi-gxp: Add support for HPE GXP SoCs spi: a3700: support BE for AC5 SPI driver spi/panel: dt-bindings: drop CPHA and CPOL from common properties spi: bcm2835: enable shared interrupt support spi: dt-bindings: spi-controller: correct example indentation spi: dt-bindings: qcom,spi-geni-qcom: allow three interconnects spi: npcm-fiu: Add NPCM8XX support dt-binding: spi: Add npcm845 compatible to npcm-fiu document spi: npcm-fiu: Modify direct read dummy configuration spi: atmel: remove #ifdef CONFIG_{PM, SLEEP} spi: dt-bindings: Add compatible for MediaTek MT8188 spi: dt-bindings: mediatek,spi-mtk-nor: Update bindings for nor flash spi: dt-bindings: atmel,at91rm9200-spi: convert to json-schema spi: tegra20-slink: fix UAF in tegra_slink_remove() spi: Fix simplification of devm_spi_register_controller spi: microchip-core: switch to use dev_err_probe() spi: microchip-core: switch to use devm_spi_alloc_master() spi: microchip-core: fix UAF in mchp_corespi_remove() ...
2022-08-02Merge tag 'arm-drivers-6.0' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC drivers from Arnd Bergmann: "The SoC driver updates contain changes to improve support for additional SoC variants, as well as cleanups an minor bugfixes in a number of existing drivers. Notable updates this time include: - Support for Qualcomm MSM8909 (Snapdragon 210) in various drivers - Updates for interconnect drivers on Qualcomm Snapdragon - A new driver support for NMI interrupts on Fujitsu A64fx - A rework of Broadcom BCMBCA Kconfig dependencies - Improved support for BCM2711 (Raspberry Pi 4) power management to allow the use of the V3D GPU - Cleanups to the NXP guts driver - Arm SCMI firmware driver updates to add tracing support, and use the firmware interfaces for system power control and for power capping" * tag 'arm-drivers-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (125 commits) soc: a64fx-diag: disable modular build dt-bindings: soc: qcom: qcom,smd-rpm: add power-controller dt-bindings: soc: qcom: aoss: document qcom,sm8450-aoss-qmp dt-bindings: soc: qcom,rpmh-rsc: simplify qcom,tcs-config ARM: mach-qcom: Add support for MSM8909 dt-bindings: arm: cpus: Document "qcom,msm8909-smp" enable-method soc: qcom: spm: Add CPU data for MSM8909 dt-bindings: soc: qcom: spm: Add MSM8909 CPU compatible soc: qcom: rpmpd: Add compatible for MSM8909 dt-bindings: power: qcom-rpmpd: Add MSM8909 power domains soc: qcom: smd-rpm: Add compatible for MSM8909 dt-bindings: soc: qcom: smd-rpm: Add MSM8909 soc: qcom: icc-bwmon: Remove unnecessary print function dev_err() soc: fujitsu: Add A64FX diagnostic interrupt driver soc: qcom: socinfo: Fix the id of SA8540P SoC soc: qcom: Make QCOM_RPMPD depend on PM tty: serial: bcm63xx: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA spi: bcm63xx-hsspi: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA clk: bcm: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA hwrng: bcm2835: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA ...
2022-07-29Add SPI Driver to HPE GXP ArchitectureMark Brown
Merge series from nick.hawkins@hpe.com <nick.hawkins@hpe.com>: The GXP supports 3 separate SPI interfaces to accommodate the system flash, core flash, and other functions. The SPI engine supports variable clock frequency, selectable 3-byte or 4-byte addressing and a configurable x1, x2, and x4 command/address/data modes. The memory buffer for reading and writing ranges between 256 bytes and 8KB. This driver supports access to the core flash and bios part.
2022-07-29spi: spi-gxp: Add support for HPE GXP SoCsNick Hawkins
The GXP supports 3 separate SPI interfaces to accommodate the system flash, core flash, and other functions. The SPI engine supports variable clock frequency, selectable 3-byte or 4-byte addressing and a configurable x1, x2, and x4 command/address/data modes. The memory buffer for reading and writing ranges between 256 bytes and 8KB. This driver supports access to the core flash and bios part. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> Link: https://lore.kernel.org/r/20220728161459.7738-2-nick.hawkins@hpe.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-26spi: a3700: support BE for AC5 SPI driverNoam
Signed-off-by: Noam <lnoam@marvell.com> Tested-by: Raz Adashi <raza@marvell.com> Reviewed-by: Raz Adashi <raza@marvell.com> Signed-off-by: Vadym Kochan <vadym.kochan@plvision.eu> Link: https://lore.kernel.org/r/20220726130038.20995-1-vadym.kochan@plvision.eu Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-25spi: bcm2835: enable shared interrupt supportMartin Sperl
BCM2711 shares an interrupt betweem 5 SPI interfaces (0, 3, 4, 5 & 6). Another interrupt is shared between SPI1, SPI2 and UART1, which also affects BCM2835/6/7. Acting on an interrupt intended for another interface ought to be harmless (although potentially inefficient), but it can cause this driver to crash - presumably because some critical state is not ready. Add a test to the spi-bcm2835 interrupt service routine that interrupts are enabled on this interface to avoid the crash and improve efficiency. Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Link: https://github.com/raspberrypi/linux/issues/5048 Suggested-by: https://github.com/boe-pi Co-developed-by: Phil Elwell <phil@raspberrypi.com> Signed-off-by: Phil Elwell <phil@raspberrypi.com> Cc: Mark Brown <broonie@kernel.org> Cc: Lukas Wunner <lukas@wunner.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/r/20220719105305.3076354-1-mkl@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-21spi: spi-rspi: Fix PIO fallback on RZ platformsBiju Das
RSPI IP on RZ/{A, G2L} SoC's has the same signal for both interrupt and DMA transfer request. Setting DMARS register for DMA transfer makes the signal to work as a DMA transfer request signal and subsequent interrupt requests to the interrupt controller are masked. PIO fallback does not work as interrupt signal is disabled. This patch fixes this issue by re-enabling the interrupts by calling dmaengine_synchronize(). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20220721143449.879257-1-biju.das.jz@bp.renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-20spi: spi-cadence: Fix SPI NO Slave Select macro definitionSai Krishna Potthuri
Fix SPI NO Slave Select macro definition, when all the SPI CS bits are high which means no slave is selected. Fixes: 21b511ddee09 ("spi: spi-cadence: Fix SPI CS gets toggling sporadically") Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Link: https://lore.kernel.org/r/20220713164529.28444-1-amit.kumar-mahapatra@xilinx.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-20spi: npcm-fiu: Add NPCM8XX supportTomer Maimon
Adding FIU NPCM8XX support to NPCM FIU driver. NPCM8XX FIU supports four controllers. As part of adding NPCM8XX support: - Add NPCM8XX specific compatible string. - Using an internal burst configuration register instead of a GCR register. - Support FIU1 controller. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20220718081146.256070-4-tmaimon77@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-20spi: npcm-fiu: Modify direct read dummy configurationTomer Maimon
Modify NPCM BMC FIU direct read dummy configuration that according spi-mem direct read function. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20220718081146.256070-2-tmaimon77@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-20spi: bcm2835: bcm2835_spi_handle_err(): fix NULL pointer deref for non DMA ↵Marc Kleine-Budde
transfers In case a IRQ based transfer times out the bcm2835_spi_handle_err() function is called. Since commit 1513ceee70f2 ("spi: bcm2835: Drop dma_pending flag") the TX and RX DMA transfers are unconditionally canceled, leading to NULL pointer derefs if ctlr->dma_tx or ctlr->dma_rx are not set. Fix the NULL pointer deref by checking that ctlr->dma_tx and ctlr->dma_rx are valid pointers before accessing them. Fixes: 1513ceee70f2 ("spi: bcm2835: Drop dma_pending flag") Cc: Lukas Wunner <lukas@wunner.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/r/20220719072234.2782764-1-mkl@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-18spi: atmel: remove #ifdef CONFIG_{PM, SLEEP}Claudiu Beznea
Remove #ifdef CONFIG_PM, #ifdef CONFIG_PM_SLEEP and use SYSTEM_SLEEP_PM_OPS() and RUNTIME_PM_OPS() macros instead which allows getting also rid of __maybe_unused in the code. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220718071052.1707858-1-claudiu.beznea@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-14spi: cadence-quadspi: Remove spi_master_put() in probe failure pathVaishnav Achath
Currently the spi_master is allocated by devm_spi_alloc_master() and devres core manages the deallocation, but in probe failure path spi_master_put() is being handled manually which causes "refcount underflow use-after-free" warning when probe failure happens after allocating spi_master. Trimmed backtrace during failure: refcount_t: underflow; use-after-free. pc : refcount_warn_saturate+0xf4/0x144 Call trace: refcount_warn_saturate kobject_put put_device devm_spi_release_controller devres_release_all This commit makes relevant changes to remove spi_master_put() from probe failure path. Fixes: 606e5d408184 ("spi: cadence-quadspi: Handle spi_unregister_master() in remove()") Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Link: https://lore.kernel.org/r/20220601071611.11853-1-vaishnav.a@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13Add support for Intel Thunder Bay SPI controllerMark Brown
Merge series from nandhini.srikandan@intel.com <nandhini.srikandan@intel.com>: This patch enables support for DW SPI on Intel Thunder Bay. This patch set also enables master mode for latest Designware SPI versions. The driver is tested on Keem Bay and Thunder Bay evaluation board.
2022-07-13spi: microchip-core: fix and cleanupsMark Brown
Merge series from Yang Yingliang <yangyingliang@huawei.com>: Patch #1 fix a UAF in mchp_corespi_remove(). Patch #2 and #3 some cleanups to simpify code.
2022-07-13spi: tegra20-slink: fix UAF in tegra_slink_remove()Yang Yingliang
After calling spi_unregister_master(), the refcount of master will be decrease to 0, and it will be freed in spi_controller_release(), the device data also will be freed, so it will lead a UAF when using 'tspi'. To fix this, get the master before unregister and put it when finish using it. Fixes: 26c863418221 ("spi: tegra20-slink: Don't use resource-managed spi_register helper") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220713094024.1508869-1-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13spi: Fix simplification of devm_spi_register_controllerYang Yingliang
This reverts commit 59ebbe40fb51 ("spi: simplify devm_spi_register_controller"). If devm_add_action() fails in devm_add_action_or_reset(), devm_spi_unregister() will be called, it decreases the refcount of 'ctlr->dev' to 0, then it will cause uaf in the drivers that calling spi_put_controller() in error path. Fixes: 59ebbe40fb51 ("spi: simplify devm_spi_register_controller") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220712135504.1055688-1-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13spi: microchip-core: switch to use dev_err_probe()Yang Yingliang
Switch to use dev_err_probe() to simpify error path. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220713025657.3524506-4-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13spi: microchip-core: switch to use devm_spi_alloc_master()Yang Yingliang
Switch to use devm_spi_alloc_master() to simpify error path. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220713025657.3524506-3-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13spi: microchip-core: fix UAF in mchp_corespi_remove()Yang Yingliang
When using devm_spi_register_master(), the unregister function will be called in devres_release_all() which is called after ->remove(), so remove spi_unregister_master() andspi_master_put(). Fixes: 9ac8d17694b6 ("spi: add support for microchip fpga spi controllers") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220713025657.3524506-2-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13spi: dw: Add support for Intel Thunder Bay SPI controllerNandhini Srikandan
Add support for Intel Thunder Bay SPI controller, which uses DesignWare DWC_ssi core and also add common init function for both Keem Bay and Thunder Bay. Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com> Acked-by: Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20220713042223.1458-5-nandhini.srikandan@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13spi: dw: Add support for master mode selection for DWC SSI controllerNandhini Srikandan
Add support to select the controller mode as master mode by setting Bit 31 of CTRLR0 register. This feature is supported for controller versions above v1.02. Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com> Acked-by: Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20220713042223.1458-4-nandhini.srikandan@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13spi: dw: Fix IP-core versions macroNandhini Srikandan
Add the missing underscore in IP version macro to avoid compilation issue. The macro is used for IP version comparison in the current patchset. Fixes: 2cc8d9227bbb ("spi: dw: Introduce Synopsys IP-core versions interface") Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com> Acked-by: Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20220713042223.1458-2-nandhini.srikandan@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
generated by cgit v1.2.3 (git 2.46.0) at 2025-07-31 01:59:18 +0000