From 9530dcf1082da23438ee557291c07d475128f63a Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 4 May 2020 21:51:05 +0200 Subject: ARM: dts: meson: add the gadget mode properties to the USB0 controller Testing with a USB RNDIS connection and iperf3 gives the following results: - From the host computer to the device at ~250Mbit/s - From the device to the host computer at ~76Mbit/s Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20200504195105.2909711-1-martin.blumenstingl@googlemail.com --- arch/arm/boot/dts/meson.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index 5d198309058a..ae89deaa8c9c 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -229,6 +229,9 @@ interrupts = ; phys = <&usb0_phy>; phy-names = "usb2-phy"; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <500>; + g-tx-fifo-size = <256 192 128 128 128>; dr_mode = "host"; status = "disabled"; }; -- cgit v1.2.3 From f5a7382d6f176e29e4fd9d733b93d5b93771a7e4 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 15 May 2020 22:25:20 +0200 Subject: ARM: dts: meson8m2: Use the Meson8m2 specific USB2 PHY compatible Use the Meson8m2 specific USB2 PHY compatible string. The 3.10 vendor kernel has at least one known difference between Meson8 and Meson8m2: Meson8m2 sets the ACA_ENABLE bit while Meson8 doesn't. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20200515202520.1487514-1-martin.blumenstingl@googlemail.com --- arch/arm/boot/dts/meson8m2.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi index 5bde7f502007..ca749cc3cc65 100644 --- a/arch/arm/boot/dts/meson8m2.dtsi +++ b/arch/arm/boot/dts/meson8m2.dtsi @@ -64,6 +64,14 @@ compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc"; }; +&usb0_phy { + compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy"; +}; + +&usb1_phy { + compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy"; +}; + &wdt { compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt"; }; -- cgit v1.2.3 From b632506c5af22a9a7c63674fc605d24cf94d585b Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Tue, 12 May 2020 23:51:47 +0200 Subject: ARM: dts: meson: Add the Ethernet "timing-adjustment" clock Add the "timing-adjusment" clock now that we now that this is connected to the PRG_ETHERNET registers. It is used internally to generate the RGMII RX delay no the MAC side (if needed). Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20200512215148.540322-2-martin.blumenstingl@googlemail.com --- arch/arm/boot/dts/meson8b.dtsi | 5 +++-- arch/arm/boot/dts/meson8m2.dtsi | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index e34b039b9357..ba36168b9c1b 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -425,8 +425,9 @@ clocks = <&clkc CLKID_ETH>, <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; + <&clkc CLKID_MPLL2>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; rx-fifo-depth = <4096>; tx-fifo-depth = <2048>; diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi index ca749cc3cc65..2397ba06d608 100644 --- a/arch/arm/boot/dts/meson8m2.dtsi +++ b/arch/arm/boot/dts/meson8m2.dtsi @@ -30,8 +30,9 @@ 0xc1108140 0x8>; clocks = <&clkc CLKID_ETH>, <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; + <&clkc CLKID_MPLL2>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; resets = <&reset RESET_ETHERNET>; reset-names = "stmmaceth"; }; -- cgit v1.2.3 From 005231128e9e97461e81fa32421957a7664317ca Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Tue, 12 May 2020 23:51:48 +0200 Subject: ARM: dts: meson: Switch existing boards with RGMII PHY to "rgmii-id" Let the PHY generate the RX and TX delay on the Odroid-C1 and MXIII Plus. Previously we did not know that these boards used an RX delay. We assumed that setting the TX delay on the MAC side It turns out that these boards also require an RX delay of 2ns (verified on Odroid-C1, but the u-boot code uses the same setup on both boards). Ethernet only worked because u-boot added this RX delay on the MAC side. The 4ns TX delay was also wrong and the result of using an unsupported RGMII TX clock divider setting. This has been fixed in the driver with commit bd6f48546b9cb7 ("net: stmmac: dwmac-meson8b: Fix the RGMII TX delay on Meson8b/8m2 SoCs"). Switch to phy-mode "rgmii-id" to let the PHY side handle all the delays, (as recommended by the Ethernet maintainers anyways) to correctly describe the need for a 2ns RX as well as 2ns TX delay on these boards. This fixes the Ethernet performance on Odroid-C1 where there was a huge amount of packet loss when transmitting data due to the incorrect TX delay. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20200512215148.540322-3-martin.blumenstingl@googlemail.com --- arch/arm/boot/dts/meson8b-odroidc1.dts | 3 +-- arch/arm/boot/dts/meson8m2-mxiii-plus.dts | 4 +--- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index a2a47804fc4a..cb21ac9f517c 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -202,9 +202,8 @@ pinctrl-0 = <ð_rgmii_pins>; pinctrl-names = "default"; - phy-mode = "rgmii"; phy-handle = <ð_phy>; - amlogic,tx-delay-ns = <4>; + phy-mode = "rgmii-id"; nvmem-cells = <ðernet_mac_address>; nvmem-cell-names = "mac-address"; diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts index d54477b1001c..cc498191ddd1 100644 --- a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts +++ b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts @@ -69,9 +69,7 @@ pinctrl-names = "default"; phy-handle = <ð_phy0>; - phy-mode = "rgmii"; - - amlogic,tx-delay-ns = <4>; + phy-mode = "rgmii-id"; mdio { compatible = "snps,dwmac-mdio"; -- cgit v1.2.3