A set of fixes for X86:

 - Ensure that the PIT is set up when the local APIC is disable or
   configured in legacy mode. This is caused by an ordering issue
   introduced in the recent changes which skip PIT initialization when the
   TSC and APIC frequencies are already known.

 - Handle malformed SRAT tables during early ACPI parsing which caused an
   infinite loop anda boot hang.

 - Fix a long standing race in the affinity setting code which affects PCI
   devices with non-maskable MSI interrupts. The problem is caused by the
   non-atomic writes of the MSI address (destination APIC id) and data
   (vector) fields which the device uses to construct the MSI message. The
   non-atomic writes are mandated by PCI.

   If both fields change and the device raises an interrupt after writing
   address and before writing data, then the MSI block constructs a
   inconsistent message which causes interrupts to be lost and subsequent
   malfunction of the device.

   The fix is to redirect the interrupt to the new vector on the current
   CPU first and then switch it over to the new target CPU. This allows to
   observe an eventually raised interrupt in the transitional stage (old
   CPU, new vector) to be observed in the APIC IRR and retriggered on the
   new target CPU and the new vector. The potential spurious interrupts
   caused by this are harmless and can in the worst case expose a buggy
   driver (all handlers have to be able to deal with spurious interrupts as
   they can and do happen for various reasons).

 - Add the missing suspend/resume mechanism for the HYPERV hypercall page
   which prevents resume hibernation on HYPERV guests. This change got
   lost before the merge window.

 - Mask the IOAPIC before disabling the local APIC to prevent potentially
   stale IOAPIC remote IRR bits which cause stale interrupt lines after
   resume.
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