diff options
Diffstat (limited to 'drivers/gpu/drm/amd/include/atomfirmware.h')
| -rw-r--r-- | drivers/gpu/drm/amd/include/atomfirmware.h | 80 |
1 files changed, 79 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h index 58364a8eb1f3..2aa6d27ed68f 100644 --- a/drivers/gpu/drm/amd/include/atomfirmware.h +++ b/drivers/gpu/drm/amd/include/atomfirmware.h @@ -501,6 +501,7 @@ enum atombios_firmware_capability ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200, ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING = 0x00000400, ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT = 0x0008000, + ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE = 0x0020000, }; enum atom_cooling_solution_id{ @@ -981,6 +982,40 @@ struct atom_display_controller_info_v4_2 uint8_t reserved3[8]; }; +struct atom_display_controller_info_v4_3 +{ + struct atom_common_table_header table_header; + uint32_t display_caps; + uint32_t bootup_dispclk_10khz; + uint16_t dce_refclk_10khz; + uint16_t i2c_engine_refclk_10khz; + uint16_t dvi_ss_percentage; // in unit of 0.001% + uint16_t dvi_ss_rate_10hz; + uint16_t hdmi_ss_percentage; // in unit of 0.001% + uint16_t hdmi_ss_rate_10hz; + uint16_t dp_ss_percentage; // in unit of 0.001% + uint16_t dp_ss_rate_10hz; + uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode + uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode + uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode + uint8_t ss_reserved; + uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available + uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available + uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable + uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable + uint16_t dpphy_refclk_10khz; + uint16_t reserved2; + uint8_t dcnip_min_ver; + uint8_t dcnip_max_ver; + uint8_t max_disp_pipe_num; + uint8_t max_vbios_active_disp_pipe_num; + uint8_t max_ppll_num; + uint8_t max_disp_phy_num; + uint8_t max_aux_pairs; + uint8_t remotedisplayconfig; + uint8_t reserved3[8]; +}; + struct atom_display_controller_info_v4_4 { struct atom_common_table_header table_header; uint32_t display_caps; @@ -1043,7 +1078,9 @@ enum dce_info_caps_def DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 =0x04, // only for VBIOS DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08, - + // only for VBIOS + DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE =0x20, + DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE = 0x40, }; /* @@ -3300,6 +3337,47 @@ enum atom_smu11_syspll3_1_clock_id { SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK }; +enum atom_smu12_syspll_id { + SMU12_SYSPLL0_ID = 0, + SMU12_SYSPLL1_ID = 1, + SMU12_SYSPLL2_ID = 2, + SMU12_SYSPLL3_0_ID = 3, + SMU12_SYSPLL3_1_ID = 4, +}; + +enum atom_smu12_syspll0_clock_id { + SMU12_SYSPLL0_SMNCLK_ID = 0, // SOCCLK + SMU12_SYSPLL0_SOCCLK_ID = 1, // SOCCLK + SMU12_SYSPLL0_MP0CLK_ID = 2, // MP0CLK + SMU12_SYSPLL0_MP1CLK_ID = 3, // MP1CLK + SMU12_SYSPLL0_MP2CLK_ID = 4, // MP2CLK + SMU12_SYSPLL0_VCLK_ID = 5, // VCLK + SMU12_SYSPLL0_LCLK_ID = 6, // LCLK + SMU12_SYSPLL0_DCLK_ID = 7, // DCLK + SMU12_SYSPLL0_ACLK_ID = 8, // ACLK + SMU12_SYSPLL0_ISPCLK_ID = 9, // ISPCLK + SMU12_SYSPLL0_SHUBCLK_ID = 10, // SHUBCLK +}; + +enum atom_smu12_syspll1_clock_id { + SMU12_SYSPLL1_DISPCLK_ID = 0, // DISPCLK + SMU12_SYSPLL1_DPPCLK_ID = 1, // DPPCLK + SMU12_SYSPLL1_DPREFCLK_ID = 2, // DPREFCLK + SMU12_SYSPLL1_DCFCLK_ID = 3, // DCFCLK +}; + +enum atom_smu12_syspll2_clock_id { + SMU12_SYSPLL2_Pre_GFXCLK_ID = 0, // Pre_GFXCLK +}; + +enum atom_smu12_syspll3_0_clock_id { + SMU12_SYSPLL3_0_FCLK_ID = 0, // FCLK +}; + +enum atom_smu12_syspll3_1_clock_id { + SMU12_SYSPLL3_1_UMCCLK_ID = 0, // UMCCLK +}; + struct atom_get_smu_clock_info_output_parameters_v3_1 { union { |