From 4562236b3bc0a28aeb6ee93b2d8a849a4c4e1c7c Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 12 Sep 2017 15:58:20 -0400 Subject: drm/amd/dc: Add dc display driver (v2) Supported DCE versions: 8.0, 10.0, 11.0, 11.2 v2: rebase against 4.11 Signed-off-by: Harry Wentland Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/include/logger_interface.h | 140 +++++++++++++++++++++ 1 file changed, 140 insertions(+) create mode 100644 drivers/gpu/drm/amd/display/include/logger_interface.h (limited to 'drivers/gpu/drm/amd/display/include/logger_interface.h') diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h new file mode 100644 index 000000000000..b58d30de8293 --- /dev/null +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -0,0 +1,140 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_LOGGER_INTERFACE_H__ +#define __DAL_LOGGER_INTERFACE_H__ + +#include "logger_types.h" + +struct dc_context; +struct dc_link; +struct dc_surface_update; + +/* + * + * DAL logger functionality + * + */ + +struct dal_logger *dal_logger_create(struct dc_context *ctx); + +uint32_t dal_logger_destroy(struct dal_logger **logger); + +void dm_logger_write( + struct dal_logger *logger, + enum dc_log_type log_type, + const char *msg, + ...); + +void dm_logger_append( + struct log_entry *entry, + const char *msg, + ...); + +void dm_logger_open( + struct dal_logger *logger, + struct log_entry *entry, + enum dc_log_type log_type); + +void dm_logger_close(struct log_entry *entry); + +void dc_conn_log(struct dc_context *ctx, + const struct dc_link *link, + uint8_t *hex_data, + int hex_data_count, + enum dc_log_type event, + const char *msg, + ...); + +void logger_write(struct dal_logger *logger, + enum dc_log_type log_type, + const char *msg, + void *paralist); + +void pre_surface_trace( + const struct dc *dc, + const struct dc_surface *const *surfaces, + int surface_count); + +void update_surface_trace( + const struct dc *dc, + const struct dc_surface_update *updates, + int surface_count); + +void post_surface_trace(const struct dc *dc); + + +/* Any function which is empty or have incomplete implementation should be + * marked by this macro. + * Note that the message will be printed exactly once for every function + * it is used in order to avoid repeating of the same message. */ +#define DAL_LOGGER_NOT_IMPL(fmt, ...) \ +{ \ + static bool print_not_impl = true; \ +\ + if (print_not_impl == true) { \ + print_not_impl = false; \ + dm_logger_write(ctx->logger, LOG_WARNING, \ + "DAL_NOT_IMPL: " fmt, ##__VA_ARGS__); \ + } \ +} + +/****************************************************************************** + * Convenience macros to save on typing. + *****************************************************************************/ + +#define DC_ERROR(...) \ + dm_logger_write(dc_ctx->logger, LOG_ERROR, \ + __VA_ARGS__); + +#define DC_SYNC_INFO(...) \ + dm_logger_write(dc_ctx->logger, LOG_SYNC, \ + __VA_ARGS__); + + +/* Connectivity log format: + * [time stamp] [drm] [Major_minor] [connector name] message..... + * eg: + * [ 26.590965] [drm] [Conn_LKTN] [DP-1] HBRx4 pass VS=0, PE=0^ + * [ 26.881060] [drm] [Conn_Mode] [DP-1] {2560x1080, 2784x1111@185580Khz}^ + */ + +#define CONN_DATA_DETECT(link, hex_data, hex_len, ...) \ + dc_conn_log(link->ctx, &link->public, hex_data, hex_len, \ + LOG_EVENT_DETECTION, ##__VA_ARGS__) + +#define CONN_DATA_LINK_LOSS(link, hex_data, hex_len, ...) \ + dc_conn_log(link->ctx, &link->public, hex_data, hex_len, \ + LOG_EVENT_LINK_LOSS, ##__VA_ARGS__) + +#define CONN_MSG_LT(link, ...) \ + dc_conn_log(link->ctx, &link->public, NULL, 0, \ + LOG_EVENT_LINK_TRAINING, ##__VA_ARGS__) + +#define CONN_MSG_MODE(link, ...) \ + dc_conn_log(link->ctx, &link->public, NULL, 0, \ + LOG_EVENT_MODE_SET, ##__VA_ARGS__) + +#endif /* __DAL_LOGGER_INTERFACE_H__ */ -- cgit v1.2.3 From 9474980ac470a20d244318db9a7c12be01437805 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Thu, 8 Dec 2016 09:47:11 -0500 Subject: drm/amd/display: Added timing sync trace. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 32 ++++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dc.h | 1 + .../amd/display/dc/dce110/dce110_hw_sequencer.c | 1 - .../gpu/drm/amd/display/include/logger_interface.h | 5 ++++ 5 files changed, 41 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/include/logger_interface.h') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 8e1d695fcb77..de99d71f9042 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1488,8 +1488,10 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda core_dc->hwss.prepare_pipe_for_context( core_dc, pipe_ctx, context); } - if (apply_ctx) + if (apply_ctx) { core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context); + context_timing_trace(dc, &context->res_ctx); + } } for (i = context->res_ctx.pool->pipe_count - 1; i >= 0; i--) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index 8ca0f1e0369a..78b8e0c5b4e7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -22,6 +22,13 @@ ##__VA_ARGS__); \ } while (0) +#define TIMING_TRACE(...) do {\ + if (dc->debug.timing_trace) \ + dm_logger_write(logger, \ + LOG_SYNC, \ + ##__VA_ARGS__); \ +} while (0) + void pre_surface_trace( const struct dc *dc, const struct dc_surface *const *surfaces, @@ -268,3 +275,28 @@ void post_surface_trace(const struct dc *dc) SURFACE_TRACE("post surface process.\n"); } + +void context_timing_trace( + const struct dc *dc, + struct resource_context *res_ctx) +{ + int i; + struct core_dc *core_dc = DC_TO_CORE(dc); + struct dal_logger *logger = core_dc->ctx->logger; + + for (i = 0; i < core_dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; + int h_pos = 0; + int v_pos = 0; + + if (pipe_ctx->stream == NULL) + continue; + + pipe_ctx->tg->funcs->get_position(pipe_ctx->tg, &h_pos, &v_pos); + TIMING_TRACE("Pipe_%d H_tot:%d V_tot:%d H_pos:%d V_pos:%d\n", + pipe_ctx->pipe_idx, + pipe_ctx->stream->public.timing.h_total, + pipe_ctx->stream->public.timing.v_total, + h_pos, v_pos); + } +} diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e1f2434ee95e..bb7cdde3e37b 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -140,6 +140,7 @@ struct dc_debug { bool max_disp_clk; bool target_trace; bool surface_trace; + bool timing_trace; bool validation_trace; bool disable_stutter; bool disable_dcc; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 6ad23f327631..99937facf645 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1892,7 +1892,6 @@ static void dce110_apply_ctx_for_surface( program_blender(dc, pipe_ctx); } - } static void dce110_power_down_fe(struct core_dc *dc, struct pipe_ctx *pipe) diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index b58d30de8293..08a6911d3a3a 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -31,6 +31,7 @@ struct dc_context; struct dc_link; struct dc_surface_update; +struct resource_context; /* * @@ -85,6 +86,10 @@ void update_surface_trace( void post_surface_trace(const struct dc *dc); +void context_timing_trace( + const struct dc *dc, + struct resource_context *res_ctx); + /* Any function which is empty or have incomplete implementation should be * marked by this macro. -- cgit v1.2.3 From c9742685c24acd6d71cdda3067bfc2f512fe2b7c Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Wed, 7 Jun 2017 13:53:30 -0400 Subject: drm/amd/display: add bw logging for dcn Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 138 +++++++++++ drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 38 +++ drivers/gpu/drm/amd/display/dc/dc.h | 1 + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 260 +++++++++++++++++---- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 + .../gpu/drm/amd/display/include/logger_interface.h | 4 + 7 files changed, 398 insertions(+), 49 deletions(-) (limited to 'drivers/gpu/drm/amd/display/include/logger_interface.h') diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 6d8bc6c74a73..f0f688b99d37 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -1312,6 +1312,144 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc) void dcn_bw_sync_calcs_and_dml(struct core_dc *dc) { kernel_fpu_begin(); + dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, + "sr_exit_time: %d ns\n" + "sr_enter_plus_exit_time: %d ns\n" + "urgent_latency: %d ns\n" + "write_back_latency: %d ns\n" + "percent_of_ideal_drambw_received_after_urg_latency: %d %\n" + "max_request_size: %d bytes\n" + "dcfclkv_max0p9: %d kHz\n" + "dcfclkv_nom0p8: %d kHz\n" + "dcfclkv_mid0p72: %d kHz\n" + "dcfclkv_min0p65: %d kHz\n" + "max_dispclk_vmax0p9: %d kHz\n" + "max_dispclk_vnom0p8: %d kHz\n" + "max_dispclk_vmid0p72: %d kHz\n" + "max_dispclk_vmin0p65: %d kHz\n" + "max_dppclk_vmax0p9: %d kHz\n" + "max_dppclk_vnom0p8: %d kHz\n" + "max_dppclk_vmid0p72: %d kHz\n" + "max_dppclk_vmin0p65: %d kHz\n" + "socclk: %d kHz\n" + "fabric_and_dram_bandwidth_vmax0p9: %d MB/s\n" + "fabric_and_dram_bandwidth_vnom0p8: %d MB/s\n" + "fabric_and_dram_bandwidth_vmid0p72: %d MB/s\n" + "fabric_and_dram_bandwidth_vmin0p65: %d MB/s\n" + "phyclkv_max0p9: %d kHz\n" + "phyclkv_nom0p8: %d kHz\n" + "phyclkv_mid0p72: %d kHz\n" + "phyclkv_min0p65: %d kHz\n" + "downspreading: %d %\n" + "round_trip_ping_latency_cycles: %d DCFCLK Cycles\n" + "urgent_out_of_order_return_per_channel: %d Bytes\n" + "number_of_channels: %d\n" + "vmm_page_size: %d Bytes\n" + "dram_clock_change_latency: %d ns\n" + "return_bus_width: %d Bytes\n", + dc->dcn_soc.sr_exit_time * 1000, + dc->dcn_soc.sr_enter_plus_exit_time * 1000, + dc->dcn_soc.urgent_latency * 1000, + dc->dcn_soc.write_back_latency * 1000, + dc->dcn_soc.percent_of_ideal_drambw_received_after_urg_latency, + dc->dcn_soc.max_request_size, + dc->dcn_soc.dcfclkv_max0p9 * 1000, + dc->dcn_soc.dcfclkv_nom0p8 * 1000, + dc->dcn_soc.dcfclkv_mid0p72 * 1000, + dc->dcn_soc.dcfclkv_min0p65 * 1000, + dc->dcn_soc.max_dispclk_vmax0p9 * 1000, + dc->dcn_soc.max_dispclk_vnom0p8 * 1000, + dc->dcn_soc.max_dispclk_vmid0p72 * 1000, + dc->dcn_soc.max_dispclk_vmin0p65 * 1000, + dc->dcn_soc.max_dppclk_vmax0p9 * 1000, + dc->dcn_soc.max_dppclk_vnom0p8 * 1000, + dc->dcn_soc.max_dppclk_vmid0p72 * 1000, + dc->dcn_soc.max_dppclk_vmin0p65 * 1000, + dc->dcn_soc.socclk * 1000, + dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9 * 1000, + dc->dcn_soc.fabric_and_dram_bandwidth_vnom0p8 * 1000, + dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72 * 1000, + dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 * 1000, + dc->dcn_soc.phyclkv_max0p9 * 1000, + dc->dcn_soc.phyclkv_nom0p8 * 1000, + dc->dcn_soc.phyclkv_mid0p72 * 1000, + dc->dcn_soc.phyclkv_min0p65 * 1000, + dc->dcn_soc.downspreading * 100, + dc->dcn_soc.round_trip_ping_latency_cycles, + dc->dcn_soc.urgent_out_of_order_return_per_channel, + dc->dcn_soc.number_of_channels, + dc->dcn_soc.vmm_page_size, + dc->dcn_soc.dram_clock_change_latency * 1000, + dc->dcn_soc.return_bus_width); + dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, + "rob_buffer_size_in_kbyte: %d\n" + "det_buffer_size_in_kbyte: %d\n" + "dpp_output_buffer_pixels: %d\n" + "opp_output_buffer_lines: %d\n" + "pixel_chunk_size_in_kbyte: %d\n" + "pte_enable: %d\n" + "pte_chunk_size: %d kbytes\n" + "meta_chunk_size: %d kbytes\n" + "writeback_chunk_size: %d kbytes\n" + "odm_capability: %d\n" + "dsc_capability: %d\n" + "line_buffer_size: %d bits\n" + "max_line_buffer_lines: %d\n" + "is_line_buffer_bpp_fixed: %d\n" + "line_buffer_fixed_bpp: %d\n" + "writeback_luma_buffer_size: %d kbytes\n" + "writeback_chroma_buffer_size: %d kbytes\n" + "max_num_dpp: %d\n" + "max_num_writeback: %d\n" + "max_dchub_topscl_throughput: %d pixels/dppclk\n" + "max_pscl_tolb_throughput: %d pixels/dppclk\n" + "max_lb_tovscl_throughput: %d pixels/dppclk\n" + "max_vscl_tohscl_throughput: %d pixels/dppclk\n" + "max_hscl_ratio: %d\n" + "max_vscl_ratio: %d\n" + "max_hscl_taps: %d\n" + "max_vscl_taps: %d\n" + "pte_buffer_size_in_requests: %d\n" + "dispclk_ramping_margin: %d %\n" + "under_scan_factor: %d %\n" + "max_inter_dcn_tile_repeaters: %d\n" + "can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one: %d\n" + "bug_forcing_luma_and_chroma_request_to_same_size_fixed: %d\n" + "dcfclk_cstate_latency: %d\n", + dc->dcn_ip.rob_buffer_size_in_kbyte, + dc->dcn_ip.det_buffer_size_in_kbyte, + dc->dcn_ip.dpp_output_buffer_pixels, + dc->dcn_ip.opp_output_buffer_lines, + dc->dcn_ip.pixel_chunk_size_in_kbyte, + dc->dcn_ip.pte_enable, + dc->dcn_ip.pte_chunk_size, + dc->dcn_ip.meta_chunk_size, + dc->dcn_ip.writeback_chunk_size, + dc->dcn_ip.odm_capability, + dc->dcn_ip.dsc_capability, + dc->dcn_ip.line_buffer_size, + dc->dcn_ip.max_line_buffer_lines, + dc->dcn_ip.is_line_buffer_bpp_fixed, + dc->dcn_ip.line_buffer_fixed_bpp, + dc->dcn_ip.writeback_luma_buffer_size, + dc->dcn_ip.writeback_chroma_buffer_size, + dc->dcn_ip.max_num_dpp, + dc->dcn_ip.max_num_writeback, + dc->dcn_ip.max_dchub_topscl_throughput, + dc->dcn_ip.max_pscl_tolb_throughput, + dc->dcn_ip.max_lb_tovscl_throughput, + dc->dcn_ip.max_vscl_tohscl_throughput, + dc->dcn_ip.max_hscl_ratio, + dc->dcn_ip.max_vscl_ratio, + dc->dcn_ip.max_hscl_taps, + dc->dcn_ip.max_vscl_taps, + dc->dcn_ip.pte_buffer_size_in_requests, + dc->dcn_ip.dispclk_ramping_margin, + dc->dcn_ip.under_scan_factor * 100, + dc->dcn_ip.max_inter_dcn_tile_repeaters, + dc->dcn_ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one, + dc->dcn_ip.bug_forcing_luma_and_chroma_request_to_same_size_fixed, + dc->dcn_ip.dcfclk_cstate_latency); dc->dml.soc.vmin.socclk_mhz = dc->dcn_soc.socclk; dc->dml.soc.vmid.socclk_mhz = dc->dcn_soc.socclk; dc->dml.soc.vnom.socclk_mhz = dc->dcn_soc.socclk; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index fb5bacb50ebc..47870a640f37 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1379,8 +1379,10 @@ void dc_update_surfaces_and_stream(struct dc *dc, if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) { BREAK_TO_DEBUGGER(); goto fail; - } else + } else { core_dc->hwss.set_bandwidth(core_dc, context, false); + context_clock_trace(dc, context); + } } if (!surface_count) /* reset */ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index c60b59f41693..ad556e9b0754 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -29,6 +29,13 @@ ##__VA_ARGS__); \ } while (0) +#define CLOCK_TRACE(...) do {\ + if (dc->debug.clock_trace) \ + dm_logger_write(logger, \ + LOG_BANDWIDTH_CALCS, \ + ##__VA_ARGS__); \ +} while (0) + void pre_surface_trace( const struct dc *dc, const struct dc_surface *const *surfaces, @@ -314,3 +321,34 @@ void context_timing_trace( h_pos[i], v_pos[i]); } } + +void context_clock_trace( + const struct dc *dc, + struct validate_context *context) +{ +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + struct core_dc *core_dc = DC_TO_CORE(dc); + struct dal_logger *logger = core_dc->ctx->logger; + + CLOCK_TRACE("Current: dispclk_khz:%d dppclk_div:%d dcfclk_khz:%d\n" + "dcfclk_deep_sleep_khz:%d fclk_khz:%d\n" + "dram_ccm_us:%d min_active_dram_ccm_us:%d\n", + context->bw.dcn.calc_clk.dispclk_khz, + context->bw.dcn.calc_clk.dppclk_div, + context->bw.dcn.calc_clk.dcfclk_khz, + context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz, + context->bw.dcn.calc_clk.fclk_khz, + context->bw.dcn.calc_clk.dram_ccm_us, + context->bw.dcn.calc_clk.min_active_dram_ccm_us); + CLOCK_TRACE("Calculated: dispclk_khz:%d dppclk_div:%d dcfclk_khz:%d\n" + "dcfclk_deep_sleep_khz:%d fclk_khz:%d\n" + "dram_ccm_us:%d min_active_dram_ccm_us:%d\n", + context->bw.dcn.calc_clk.dispclk_khz, + context->bw.dcn.calc_clk.dppclk_div, + context->bw.dcn.calc_clk.dcfclk_khz, + context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz, + context->bw.dcn.calc_clk.fclk_khz, + context->bw.dcn.calc_clk.dram_ccm_us, + context->bw.dcn.calc_clk.min_active_dram_ccm_us); +#endif +} diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 7191b2519334..e08e532cafb8 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -160,6 +160,7 @@ struct dc_debug { bool max_disp_clk; bool surface_trace; bool timing_trace; + bool clock_trace; bool validation_trace; bool disable_stutter; bool disable_dcc; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 0a346aafacce..93a34e2ef175 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1412,6 +1412,128 @@ static void dcn10_enable_timing_synchronization( DC_SYNC_INFO("Sync complete\n"); } +static void print_rq_dlg_ttu( + struct core_dc *core_dc, + struct pipe_ctx *pipe_ctx) +{ + dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS, + "\n============== DML TTU Output parameters [%d] ==============\n" + "qos_level_low_wm: %d, \n" + "qos_level_high_wm: %d, \n" + "min_ttu_vblank: %d, \n" + "qos_level_flip: %d, \n" + "refcyc_per_req_delivery_l: %d, \n" + "qos_level_fixed_l: %d, \n" + "qos_ramp_disable_l: %d, \n" + "refcyc_per_req_delivery_pre_l: %d, \n" + "refcyc_per_req_delivery_c: %d, \n" + "qos_level_fixed_c: %d, \n" + "qos_ramp_disable_c: %d, \n" + "refcyc_per_req_delivery_pre_c: %d\n" + "=============================================================\n", + pipe_ctx->pipe_idx, + pipe_ctx->ttu_regs.qos_level_low_wm, + pipe_ctx->ttu_regs.qos_level_high_wm, + pipe_ctx->ttu_regs.min_ttu_vblank, + pipe_ctx->ttu_regs.qos_level_flip, + pipe_ctx->ttu_regs.refcyc_per_req_delivery_l, + pipe_ctx->ttu_regs.qos_level_fixed_l, + pipe_ctx->ttu_regs.qos_ramp_disable_l, + pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l, + pipe_ctx->ttu_regs.refcyc_per_req_delivery_c, + pipe_ctx->ttu_regs.qos_level_fixed_c, + pipe_ctx->ttu_regs.qos_ramp_disable_c, + pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c + ); + + dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS, + "\n============== DML DLG Output parameters [%d] ==============\n" + "refcyc_h_blank_end: %d, \n" + "dlg_vblank_end: %d, \n" + "min_dst_y_next_start: %d, \n" + "refcyc_per_htotal: %d, \n" + "refcyc_x_after_scaler: %d, \n" + "dst_y_after_scaler: %d, \n" + "dst_y_prefetch: %d, \n" + "dst_y_per_vm_vblank: %d, \n" + "dst_y_per_row_vblank: %d, \n" + "ref_freq_to_pix_freq: %d, \n" + "vratio_prefetch: %d, \n" + "refcyc_per_pte_group_vblank_l: %d, \n" + "refcyc_per_meta_chunk_vblank_l: %d, \n" + "dst_y_per_pte_row_nom_l: %d, \n" + "refcyc_per_pte_group_nom_l: %d, \n", + pipe_ctx->pipe_idx, + pipe_ctx->dlg_regs.refcyc_h_blank_end, + pipe_ctx->dlg_regs.dlg_vblank_end, + pipe_ctx->dlg_regs.min_dst_y_next_start, + pipe_ctx->dlg_regs.refcyc_per_htotal, + pipe_ctx->dlg_regs.refcyc_x_after_scaler, + pipe_ctx->dlg_regs.dst_y_after_scaler, + pipe_ctx->dlg_regs.dst_y_prefetch, + pipe_ctx->dlg_regs.dst_y_per_vm_vblank, + pipe_ctx->dlg_regs.dst_y_per_row_vblank, + pipe_ctx->dlg_regs.ref_freq_to_pix_freq, + pipe_ctx->dlg_regs.vratio_prefetch, + pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l, + pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l, + pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l, + pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l + ); + + dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS, + "\ndst_y_per_meta_row_nom_l: %d, \n" + "refcyc_per_meta_chunk_nom_l: %d, \n" + "refcyc_per_line_delivery_pre_l: %d, \n" + "refcyc_per_line_delivery_l: %d, \n" + "vratio_prefetch_c: %d, \n" + "refcyc_per_pte_group_vblank_c: %d, \n" + "refcyc_per_meta_chunk_vblank_c: %d, \n" + "dst_y_per_pte_row_nom_c: %d, \n" + "refcyc_per_pte_group_nom_c: %d, \n" + "dst_y_per_meta_row_nom_c: %d, \n" + "refcyc_per_meta_chunk_nom_c: %d, \n" + "refcyc_per_line_delivery_pre_c: %d, \n" + "refcyc_per_line_delivery_c: %d \n" + "========================================================\n", + pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l, + pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l, + pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l, + pipe_ctx->dlg_regs.refcyc_per_line_delivery_l, + pipe_ctx->dlg_regs.vratio_prefetch_c, + pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c, + pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c, + pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c, + pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c, + pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c, + pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c, + pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c, + pipe_ctx->dlg_regs.refcyc_per_line_delivery_c + ); + + dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS, + "\n============== DML RQ Output parameters [%d] ==============\n" + "chunk_size: %d \n" + "min_chunk_size: %d \n" + "meta_chunk_size: %d \n" + "min_meta_chunk_size: %d \n" + "dpte_group_size: %d \n" + "mpte_group_size: %d \n" + "swath_height: %d \n" + "pte_row_height_linear: %d \n" + "========================================================\n", + pipe_ctx->pipe_idx, + pipe_ctx->rq_regs.rq_regs_l.chunk_size, + pipe_ctx->rq_regs.rq_regs_l.min_chunk_size, + pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size, + pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size, + pipe_ctx->rq_regs.rq_regs_l.dpte_group_size, + pipe_ctx->rq_regs.rq_regs_l.mpte_group_size, + pipe_ctx->rq_regs.rq_regs_l.swath_height, + pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear + ); +} + static void dcn10_power_on_fe( struct core_dc *dc, struct pipe_ctx *pipe_ctx, @@ -1419,57 +1541,52 @@ static void dcn10_power_on_fe( { struct dc_surface *dc_surface = &pipe_ctx->surface->public; - /* power up DCHUP and DPP from pseudo code pipe_move.c */ - /*TODO: function: power_on_plane. If already power up, skip - */ - { - power_on_plane(dc->ctx, - pipe_ctx->pipe_idx, pipe_ctx->tg->inst); + power_on_plane(dc->ctx, + pipe_ctx->pipe_idx, pipe_ctx->tg->inst); - /* enable DCFCLK current DCHUB */ - enable_dcfclk(dc->ctx, + /* enable DCFCLK current DCHUB */ + enable_dcfclk(dc->ctx, + pipe_ctx->pipe_idx, + pipe_ctx->pix_clk_params.requested_pix_clk, + context->bw.dcn.calc_clk.dppclk_div); + dc->current_context->bw.dcn.cur_clk.dppclk_div = + context->bw.dcn.calc_clk.dppclk_div; + context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div; + + if (dc_surface) { + dm_logger_write(dc->ctx->logger, LOG_DC, + "Pipe:%d 0x%x: addr hi:0x%x, " + "addr low:0x%x, " + "src: %d, %d, %d," + " %d; dst: %d, %d, %d, %d;\n", pipe_ctx->pipe_idx, - pipe_ctx->pix_clk_params.requested_pix_clk, - context->bw.dcn.calc_clk.dppclk_div); - dc->current_context->bw.dcn.cur_clk.dppclk_div = - context->bw.dcn.calc_clk.dppclk_div; - context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div; - - if (dc_surface) { - dm_logger_write(dc->ctx->logger, LOG_DC, - "Pipe:%d 0x%x: addr hi:0x%x, " - "addr low:0x%x, " - "src: %d, %d, %d," - " %d; dst: %d, %d, %d, %d;\n", - pipe_ctx->pipe_idx, - dc_surface, - dc_surface->address.grph.addr.high_part, - dc_surface->address.grph.addr.low_part, - dc_surface->src_rect.x, - dc_surface->src_rect.y, - dc_surface->src_rect.width, - dc_surface->src_rect.height, - dc_surface->dst_rect.x, - dc_surface->dst_rect.y, - dc_surface->dst_rect.width, - dc_surface->dst_rect.height); - - dm_logger_write(dc->ctx->logger, LOG_HW_SET_MODE, - "Pipe %d: width, height, x, y\n" - "viewport:%d, %d, %d, %d\n" - "recout: %d, %d, %d, %d\n", - pipe_ctx->pipe_idx, - pipe_ctx->scl_data.viewport.width, - pipe_ctx->scl_data.viewport.height, - pipe_ctx->scl_data.viewport.x, - pipe_ctx->scl_data.viewport.y, - pipe_ctx->scl_data.recout.width, - pipe_ctx->scl_data.recout.height, - pipe_ctx->scl_data.recout.x, - pipe_ctx->scl_data.recout.y); - } + dc_surface, + dc_surface->address.grph.addr.high_part, + dc_surface->address.grph.addr.low_part, + dc_surface->src_rect.x, + dc_surface->src_rect.y, + dc_surface->src_rect.width, + dc_surface->src_rect.height, + dc_surface->dst_rect.x, + dc_surface->dst_rect.y, + dc_surface->dst_rect.width, + dc_surface->dst_rect.height); + + dm_logger_write(dc->ctx->logger, LOG_HW_SET_MODE, + "Pipe %d: width, height, x, y\n" + "viewport:%d, %d, %d, %d\n" + "recout: %d, %d, %d, %d\n", + pipe_ctx->pipe_idx, + pipe_ctx->scl_data.viewport.width, + pipe_ctx->scl_data.viewport.height, + pipe_ctx->scl_data.viewport.x, + pipe_ctx->scl_data.viewport.y, + pipe_ctx->scl_data.recout.width, + pipe_ctx->scl_data.recout.height, + pipe_ctx->scl_data.recout.x, + pipe_ctx->scl_data.recout.y); + print_rq_dlg_ttu(dc, pipe_ctx); } - } static void program_gamut_remap(struct pipe_ctx *pipe_ctx) @@ -1743,6 +1860,53 @@ static void dcn10_apply_ctx_for_surface( } } + dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, + "\n============== Watermark parameters ==============\n" + "a.urgent_ns: %d \n" + "a.cstate_enter_plus_exit: %d \n" + "a.cstate_exit: %d \n" + "a.pstate_change: %d \n" + "a.pte_meta_urgent: %d \n" + "b.urgent_ns: %d \n" + "b.cstate_enter_plus_exit: %d \n" + "b.cstate_exit: %d \n" + "b.pstate_change: %d \n" + "b.pte_meta_urgent: %d \n", + context->bw.dcn.watermarks.a.urgent_ns, + context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns, + context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns, + context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns, + context->bw.dcn.watermarks.a.pte_meta_urgent_ns, + context->bw.dcn.watermarks.b.urgent_ns, + context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns, + context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns, + context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns, + context->bw.dcn.watermarks.b.pte_meta_urgent_ns + ); + dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, + "\nc.urgent_ns: %d \n" + "c.cstate_enter_plus_exit: %d \n" + "c.cstate_exit: %d \n" + "c.pstate_change: %d \n" + "c.pte_meta_urgent: %d \n" + "d.urgent_ns: %d \n" + "d.cstate_enter_plus_exit: %d \n" + "d.cstate_exit: %d \n" + "d.pstate_change: %d \n" + "d.pte_meta_urgent: %d \n" + "========================================================\n", + context->bw.dcn.watermarks.c.urgent_ns, + context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns, + context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns, + context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns, + context->bw.dcn.watermarks.c.pte_meta_urgent_ns, + context->bw.dcn.watermarks.d.urgent_ns, + context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns, + context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns, + context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns, + context->bw.dcn.watermarks.d.pte_meta_urgent_ns + ); + for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index e527d10b3e1f..6ada9a262721 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -429,6 +429,7 @@ static const struct dc_debug debug_defaults_drv = { .disable_dmcu = true, .force_abm_enable = false, .timing_trace = false, + .clock_trace = true, .disable_pplib_clock_request = true, .disable_pplib_wm_range = false, #if defined(CONFIG_DRM_AMD_DC_DCN1_0) @@ -441,6 +442,7 @@ static const struct dc_debug debug_defaults_diags = { .disable_dmcu = true, .force_abm_enable = false, .timing_trace = true, + .clock_trace = true, #if defined(CONFIG_DRM_AMD_DC_DCN1_0) .disable_pplib_clock_request = true, .disable_pplib_wm_range = true, diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index 08a6911d3a3a..b75c343f8680 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -32,6 +32,7 @@ struct dc_context; struct dc_link; struct dc_surface_update; struct resource_context; +struct validate_context; /* * @@ -90,6 +91,9 @@ void context_timing_trace( const struct dc *dc, struct resource_context *res_ctx); +void context_clock_trace( + const struct dc *dc, + struct validate_context *context); /* Any function which is empty or have incomplete implementation should be * marked by this macro. -- cgit v1.2.3 From 9ff1bb090b40949cddfbb904e613395ad2633fc7 Mon Sep 17 00:00:00 2001 From: Corbin McElhanney Date: Fri, 23 Jun 2017 17:45:50 -0400 Subject: drm/amd/display: Add extra mode and clock info to DTN logs Adds some additional information to logs in dc_commit_streams to better match Dal2. Also adds a new function, dc_raw_log, that has the same functionality as dc_conn_log, but does not attach display specific prefixes to the log output. Finally, adds a new DC log type, LOG_DTN, that logs to LogMinor_DispConnect_dtn in DM. This new log type and dc_raw_log are used to generate clock info in the logs to match Dal2. Signed-off-by: Corbin McElhanney Reviewed-by: Aric Cyr Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 +- .../gpu/drm/amd/display/dc/basics/log_helpers.c | 30 +++++++++++++++++++++- drivers/gpu/drm/amd/display/dc/basics/logger.c | 6 +++-- drivers/gpu/drm/amd/display/dc/core/dc.c | 7 ++++- drivers/gpu/drm/amd/display/dc/dm_helpers.h | 3 ++- .../gpu/drm/amd/display/include/logger_interface.h | 5 ++++ drivers/gpu/drm/amd/display/include/logger_types.h | 1 + 7 files changed, 48 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/amd/display/include/logger_interface.h') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 64db62e609eb..df4d221e46c1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -322,7 +322,7 @@ bool dm_helpers_dp_mst_send_payload_allocation( return true; } -bool dm_helpers_dc_conn_log(struct dc_context*ctx, const char *msg) +bool dm_helpers_dc_conn_log(struct dc_context *ctx, struct log_entry *entry, enum dc_log_type event) { return true; } diff --git a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c index 1268be9ebaf3..070ae6f680e1 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c @@ -95,7 +95,35 @@ void dc_conn_log(struct dc_context *ctx, dm_logger_append(&entry, "%2.2X ", hex_data[i]); dm_logger_append(&entry, "^\n"); - dm_helpers_dc_conn_log(ctx, entry.buf); + dm_helpers_dc_conn_log(ctx, &entry, event); + dm_logger_close(&entry); + + va_end(args); +} + +void dc_raw_log(struct dc_context *ctx, + enum dc_log_type event, + const char *msg, + ...) +{ + va_list args; + struct log_entry entry = { 0 }; + + dm_logger_open(ctx->logger, &entry, event); + + va_start(args, msg); + entry.buf_offset += dm_log_to_buffer( + &entry.buf[entry.buf_offset], + LOG_MAX_LINE_SIZE - entry.buf_offset, + msg, args); + + if (entry.buf[strlen(entry.buf) - 1] == '\n') { + entry.buf[strlen(entry.buf) - 1] = '\0'; + entry.buf_offset--; + } + + dm_logger_append(&entry, "^\n"); + dm_helpers_dc_conn_log(ctx, &entry, event); dm_logger_close(&entry); va_end(args); diff --git a/drivers/gpu/drm/amd/display/dc/basics/logger.c b/drivers/gpu/drm/amd/display/dc/basics/logger.c index 4be83703b809..0b17374b1535 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/logger.c +++ b/drivers/gpu/drm/amd/display/dc/basics/logger.c @@ -59,7 +59,8 @@ static const struct dc_log_type_info log_type_info_tbl[] = { {LOG_EVENT_LINK_TRAINING, "LKTN"}, {LOG_EVENT_LINK_LOSS, "LinkLoss"}, {LOG_EVENT_UNDERFLOW, "Underflow"}, - {LOG_IF_TRACE, "InterfaceTrace"} + {LOG_IF_TRACE, "InterfaceTrace"}, + {LOG_DTN, "DTN"} }; @@ -84,7 +85,8 @@ static const struct dc_log_type_info log_type_info_tbl[] = { (1 << LOG_DETECTION_DP_CAPS) | \ (1 << LOG_BACKLIGHT)) | \ (1 << LOG_I2C_AUX) | \ - (1 << LOG_IF_TRACE) /* | \ + (1 << LOG_IF_TRACE) | \ + (1 << LOG_DTN) /* | \ (1 << LOG_DEBUG) | \ (1 << LOG_BIOS) | \ (1 << LOG_SURFACE) | \ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 51e4cb30f858..c113c1a259d4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -944,9 +944,14 @@ bool dc_commit_streams( dc_enable_stereo(dc, context, streams, stream_count); } - CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}", + CONN_MSG_MODE(sink->link, "{%ux%u, %ux%u@%u, %ux%u@%uKhz}", + context->streams[i]->public.src.width, + context->streams[i]->public.src.height, context->streams[i]->public.timing.h_addressable, context->streams[i]->public.timing.v_addressable, + context->streams[i]->public.timing.pix_clk_khz * 1000 / + context->streams[i]->public.timing.h_total / + context->streams[i]->public.timing.v_total, // Refresh rate context->streams[i]->public.timing.h_total, context->streams[i]->public.timing.v_total, context->streams[i]->public.timing.pix_clk_khz); diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h index 9fb606c49217..a831421c7ea0 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h +++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h @@ -70,7 +70,8 @@ bool dm_helpers_dp_mst_start_top_mgr( bool dm_helpers_dc_conn_log( struct dc_context*ctx, - const char *msg); + struct log_entry *entry, + enum dc_log_type event); void dm_helpers_dp_mst_stop_top_mgr( struct dc_context *ctx, diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index b75c343f8680..ce5fef243b09 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -70,6 +70,11 @@ void dc_conn_log(struct dc_context *ctx, const char *msg, ...); +void dc_raw_log(struct dc_context *ctx, + enum dc_log_type event, + const char *msg, + ...); + void logger_write(struct dal_logger *logger, enum dc_log_type log_type, const char *msg, diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h b/drivers/gpu/drm/amd/display/include/logger_types.h index dfc0f102b33d..42ffb93e3172 100644 --- a/drivers/gpu/drm/amd/display/include/logger_types.h +++ b/drivers/gpu/drm/amd/display/include/logger_types.h @@ -37,6 +37,7 @@ enum dc_log_type { LOG_WARNING, LOG_DEBUG, LOG_DC, + LOG_DTN, LOG_SURFACE, LOG_HW_HOTPLUG, LOG_HW_LINK_TRAINING, -- cgit v1.2.3 From 6d244be884d20b1e9c912291a242dccedd6d9040 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Thu, 20 Jul 2017 00:12:20 -0400 Subject: drm/amd/display: plumbing to allow easy print of HW state for DTN Signed-off-by: Tony Cheng Reviewed-by: Wesley Chalmers Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 7 +++++++ drivers/gpu/drm/amd/display/dc/dc.h | 2 ++ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 12 ++++++++++++ drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 ++ drivers/gpu/drm/amd/display/include/logger_interface.h | 4 ++++ 5 files changed, 27 insertions(+) (limited to 'drivers/gpu/drm/amd/display/include/logger_interface.h') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index eda36c7a5c57..ad1b90563eb6 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2035,3 +2035,10 @@ bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) } +void dc_log_hw_state(struct dc *dc) +{ + struct core_dc *core_dc = DC_TO_CORE(dc); + + if (core_dc->hwss.log_hw_state) + core_dc->hwss.log_hw_state(core_dc); +} diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 7ecbff792e66..7b8e11c28c62 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -236,6 +236,8 @@ void dc_destroy(struct dc **dc); bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data); +void dc_log_hw_state(struct dc *dc); + /******************************************************************************* * Surface Interfaces ******************************************************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 6543027469af..c0aa32b71ad1 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1851,6 +1851,17 @@ static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc) return; } +static void dcn10_log_hw_state(struct core_dc *dc) +{ + struct dc_context *dc_ctx = dc->ctx; + + DTN_INFO("%s: Hello World", __func__); + + /* todo: add meaningful register reads and print out HW state + * + */ +} + static bool dcn10_dummy_display_power_gating( struct core_dc *dc, uint8_t controller_id, @@ -1887,6 +1898,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { .set_static_screen_control = set_static_screen_control, .setup_stereo = dcn10_setup_stereo, .set_avmute = dce110_set_avmute, + .log_hw_state = dcn10_log_hw_state, }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index d94e8e446ce5..4c027a98cfd3 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -154,6 +154,8 @@ struct hw_sequencer_funcs { struct core_dc *dc); void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); + + void (*log_hw_state)(struct core_dc *dc); }; void color_space_to_black_color( diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index ce5fef243b09..c861e726cd8f 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -123,6 +123,10 @@ void context_clock_trace( dm_logger_write(dc_ctx->logger, LOG_ERROR, \ __VA_ARGS__); +#define DTN_INFO(...) \ + dm_logger_write(dc_ctx->logger, LOG_DTN, \ + __VA_ARGS__) + #define DC_SYNC_INFO(...) \ dm_logger_write(dc_ctx->logger, LOG_SYNC, \ __VA_ARGS__); -- cgit v1.2.3 From f811fd5a66a3e69cdc184accfe189de5a1f6dba4 Mon Sep 17 00:00:00 2001 From: Wesley Chalmers Date: Thu, 20 Jul 2017 17:13:12 -0400 Subject: drm/amd/display: Change DTN_INFO macro Signed-off-by: Wesley Chalmers Reviewed-by: Wesley Chalmers Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/include/logger_interface.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/include/logger_interface.h') diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index c861e726cd8f..6e6fd4e8fc00 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -124,7 +124,7 @@ void context_clock_trace( __VA_ARGS__); #define DTN_INFO(...) \ - dm_logger_write(dc_ctx->logger, LOG_DTN, \ + dc_raw_log(dc_ctx, LOG_DTN, \ __VA_ARGS__) #define DC_SYNC_INFO(...) \ -- cgit v1.2.3 From d0778ebfd58f5650de17531296ee5ecdde39ba68 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Sat, 22 Jul 2017 20:05:20 -0400 Subject: drm/amd/display: Roll core_link into dc_link Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 4 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h | 2 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 100 ++++---- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 229 +++++++++--------- drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 6 +- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 264 ++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 40 ++-- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 8 +- drivers/gpu/drm/amd/display/dc/core/dc_sink.c | 9 +- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 +- drivers/gpu/drm/amd/display/dc/dc.h | 112 ++++++--- drivers/gpu/drm/amd/display/dc/dc_ddc_types.h | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 4 +- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 2 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 2 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 16 +- .../drm/amd/display/dc/dce110/dce110_resource.c | 2 +- .../drm/amd/display/dc/dce112/dce112_resource.c | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 2 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 58 +---- drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 16 +- drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/link_hwss.h | 22 +- .../gpu/drm/amd/display/include/logger_interface.h | 8 +- 29 files changed, 444 insertions(+), 484 deletions(-) (limited to 'drivers/gpu/drm/amd/display/include/logger_interface.h') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 2bb2fc2a6566..c558f700df35 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -563,7 +563,7 @@ struct amdgpu_connector { /* The 'old' sink - before an HPD. * The 'current' sink is in dc_link->sink. */ const struct dc_sink *dc_sink; - const struct dc_link *dc_link; + struct dc_link *dc_link; const struct dc_sink *dc_em_sink; const struct dc_stream *stream; void *con_priv; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index b247904206ba..4885403f5cec 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -1874,7 +1874,7 @@ void amdgpu_dm_connector_init_helper( struct amdgpu_display_manager *dm, struct amdgpu_connector *aconnector, int connector_type, - const struct dc_link *link, + struct dc_link *link, int link_index) { struct amdgpu_device *adev = dm->ddev->dev_private; @@ -1997,7 +1997,7 @@ int amdgpu_dm_connector_init( int res = 0; int connector_type; struct dc *dc = dm->dc; - const struct dc_link *link = dc_get_link_at_index(dc, link_index); + struct dc_link *link = dc_get_link_at_index(dc, link_index); struct amdgpu_i2c_adapter *i2c; ((struct dc_link *)link)->priv = aconnector; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h index 115d9081d964..c565787cd782 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h @@ -114,7 +114,7 @@ void amdgpu_dm_connector_init_helper( struct amdgpu_display_manager *dm, struct amdgpu_connector *aconnector, int connector_type, - const struct dc_link *link, + struct dc_link *link, int link_index); int amdgpu_dm_connector_mode_valid( diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 569310ab116d..73740e2a5819 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -94,7 +94,7 @@ static bool create_links( for (i = 0; i < connectors_num; i++) { struct link_init_data link_init_params = {0}; - struct core_link *link; + struct dc_link *link; link_init_params.ctx = dc->ctx; /* next BIOS object table connector */ @@ -111,7 +111,7 @@ static bool create_links( } for (i = 0; i < num_virtual_links; i++) { - struct core_link *link = dm_alloc(sizeof(*link)); + struct dc_link *link = dm_alloc(sizeof(*link)); struct encoder_init_data enc_init = {0}; if (link == NULL) { @@ -121,7 +121,7 @@ static bool create_links( link->ctx = dc->ctx; link->dc = dc; - link->public.connector_signal = SIGNAL_TYPE_VIRTUAL; + link->connector_signal = SIGNAL_TYPE_VIRTUAL; link->link_id.type = OBJECT_TYPE_CONNECTOR; link->link_id.id = CONNECTOR_ID_VIRTUAL; link->link_id.enum_id = ENUM_ID_1; @@ -137,7 +137,7 @@ static bool create_links( enc_init.encoder.enum_id = ENUM_ID_1; virtual_link_encoder_construct(link->link_enc, &enc_init); - link->public.link_index = dc->link_count; + link->link_index = dc->link_count; dc->links[dc->link_count] = link; dc->link_count++; } @@ -278,14 +278,14 @@ static void set_drive_settings(struct dc *dc, int i; for (i = 0; i < core_dc->link_count; i++) { - if (&core_dc->links[i]->public == link) + if (core_dc->links[i] == link) break; } if (i >= core_dc->link_count) ASSERT_CRITICAL(false); - dc_link_dp_set_drive_settings(&core_dc->links[i]->public, lt_settings); + dc_link_dp_set_drive_settings(core_dc->links[i], lt_settings); } static void perform_link_training(struct dc *dc, @@ -297,20 +297,17 @@ static void perform_link_training(struct dc *dc, for (i = 0; i < core_dc->link_count; i++) dc_link_dp_perform_link_training( - &core_dc->links[i]->public, + core_dc->links[i], link_setting, skip_video_pattern); } static void set_preferred_link_settings(struct dc *dc, struct dc_link_settings *link_setting, - const struct dc_link *link) + struct dc_link *link) { - struct core_link *core_link = DC_LINK_TO_CORE(link); - - core_link->public.preferred_link_setting = - *link_setting; - dp_retrain_link_dp_test(core_link, link_setting, false); + link->preferred_link_setting = *link_setting; + dp_retrain_link_dp_test(link, link_setting, false); } static void enable_hpd(const struct dc_link *link) @@ -325,7 +322,7 @@ static void disable_hpd(const struct dc_link *link) static void set_test_pattern( - const struct dc_link *link, + struct dc_link *link, enum dp_test_pattern test_pattern, const struct link_training_settings *p_link_settings, const unsigned char *p_custom_pattern, @@ -345,9 +342,8 @@ void set_dither_option(const struct dc_stream *dc_stream, { struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct bit_depth_reduction_params params; - struct core_link *core_link = DC_LINK_TO_CORE(stream->status.link); - struct pipe_ctx *pipes = - core_link->dc->current_context->res_ctx.pipe_ctx; + struct dc_link *link = stream->status.link; + struct pipe_ctx *pipes = link->dc->current_context->res_ctx.pipe_ctx; memset(¶ms, 0, sizeof(params)); if (!stream) @@ -1693,10 +1689,10 @@ struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i) return NULL; } -const struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index) +struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index) { struct core_dc *core_dc = DC_TO_CORE(dc); - return &core_dc->links[link_index]->public; + return core_dc->links[link_index]; } const struct graphics_object_id dc_get_link_id_at_index( @@ -1710,7 +1706,7 @@ enum dc_irq_source dc_get_hpd_irq_source_at_index( struct dc *dc, uint32_t link_index) { struct core_dc *core_dc = DC_TO_CORE(dc); - return core_dc->links[link_index]->public.irq_source_hpd; + return core_dc->links[link_index]->irq_source_hpd; } const struct audio **dc_get_audios(struct dc *dc) @@ -1796,9 +1792,9 @@ bool dc_read_aux_dpcd( { struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_link *link = core_dc->links[link_index]; + struct dc_link *link = core_dc->links[link_index]; enum ddc_result r = dal_ddc_service_read_dpcd_data( - link->public.ddc, + link->ddc, false, I2C_MOT_UNDEF, address, @@ -1815,10 +1811,10 @@ bool dc_write_aux_dpcd( uint32_t size) { struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_link *link = core_dc->links[link_index]; + struct dc_link *link = core_dc->links[link_index]; enum ddc_result r = dal_ddc_service_write_dpcd_data( - link->public.ddc, + link->ddc, false, I2C_MOT_UNDEF, address, @@ -1837,9 +1833,9 @@ bool dc_read_aux_i2c( { struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_link *link = core_dc->links[link_index]; + struct dc_link *link = core_dc->links[link_index]; enum ddc_result r = dal_ddc_service_read_dpcd_data( - link->public.ddc, + link->ddc, true, mot, address, @@ -1857,10 +1853,10 @@ bool dc_write_aux_i2c( uint32_t size) { struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_link *link = core_dc->links[link_index]; + struct dc_link *link = core_dc->links[link_index]; enum ddc_result r = dal_ddc_service_write_dpcd_data( - link->public.ddc, + link->ddc, true, mot, address, @@ -1880,10 +1876,10 @@ bool dc_query_ddc_data( struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_link *link = core_dc->links[link_index]; + struct dc_link *link = core_dc->links[link_index]; bool result = dal_ddc_service_query_ddc_data( - link->public.ddc, + link->ddc, address, write_buf, write_size, @@ -1900,8 +1896,8 @@ bool dc_submit_i2c( { struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_link *link = core_dc->links[link_index]; - struct ddc_service *ddc = link->public.ddc; + struct dc_link *link = core_dc->links[link_index]; + struct ddc_service *ddc = link->ddc; return dal_i2caux_submit_i2c_command( ddc->ctx->i2caux, @@ -1909,10 +1905,8 @@ bool dc_submit_i2c( cmd); } -static bool link_add_remote_sink_helper(struct core_link *core_link, struct dc_sink *sink) +static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink) { - struct dc_link *dc_link = &core_link->public; - if (dc_link->sink_count >= MAX_SINKS_PER_LINK) { BREAK_TO_DEBUGGER(); return false; @@ -1927,14 +1921,13 @@ static bool link_add_remote_sink_helper(struct core_link *core_link, struct dc_s } struct dc_sink *dc_link_add_remote_sink( - const struct dc_link *link, + struct dc_link *link, const uint8_t *edid, int len, struct dc_sink_init_data *init_data) { struct dc_sink *dc_sink; enum dc_edid_status edid_status; - struct core_link *core_link = DC_LINK_TO_LINK(link); if (len > MAX_EDID_BUFFER_SIZE) { dm_error("Max EDID buffer size breached!\n"); @@ -1960,12 +1953,12 @@ struct dc_sink *dc_link_add_remote_sink( dc_sink->dc_edid.length = len; if (!link_add_remote_sink_helper( - core_link, + link, dc_sink)) goto fail_add_sink; edid_status = dm_helpers_parse_edid_caps( - core_link->ctx, + link->ctx, &dc_sink->dc_edid, &dc_sink->edid_caps); @@ -1980,43 +1973,38 @@ fail_add_sink: return NULL; } -void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink) +void dc_link_set_sink(struct dc_link *link, struct dc_sink *sink) { - struct core_link *core_link = DC_LINK_TO_LINK(link); - struct dc_link *dc_link = &core_link->public; - - dc_link->local_sink = sink; + link->local_sink = sink; if (sink == NULL) { - dc_link->type = dc_connection_none; + link->type = dc_connection_none; } else { - dc_link->type = dc_connection_single; + link->type = dc_connection_single; } } -void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink *sink) +void dc_link_remove_remote_sink(struct dc_link *link, const struct dc_sink *sink) { int i; - struct core_link *core_link = DC_LINK_TO_LINK(link); - struct dc_link *dc_link = &core_link->public; if (!link->sink_count) { BREAK_TO_DEBUGGER(); return; } - for (i = 0; i < dc_link->sink_count; i++) { - if (dc_link->remote_sinks[i] == sink) { + for (i = 0; i < link->sink_count; i++) { + if (link->remote_sinks[i] == sink) { dc_sink_release(sink); - dc_link->remote_sinks[i] = NULL; + link->remote_sinks[i] = NULL; /* shrink array to remove empty place */ - while (i < dc_link->sink_count - 1) { - dc_link->remote_sinks[i] = dc_link->remote_sinks[i+1]; + while (i < link->sink_count - 1) { + link->remote_sinks[i] = link->remote_sinks[i+1]; i++; } - dc_link->remote_sinks[i] = NULL; - dc_link->sink_count--; + link->remote_sinks[i] = NULL; + link->sink_count--; return; } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 036d22f878b8..428dbff8505b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -62,24 +62,24 @@ enum { /******************************************************************************* * Private functions ******************************************************************************/ -static void destruct(struct core_link *link) +static void destruct(struct dc_link *link) { int i; - if (link->public.ddc) - dal_ddc_service_destroy(&link->public.ddc); + if (link->ddc) + dal_ddc_service_destroy(&link->ddc); if(link->link_enc) link->link_enc->funcs->destroy(&link->link_enc); - if (link->public.local_sink) - dc_sink_release(link->public.local_sink); + if (link->local_sink) + dc_sink_release(link->local_sink); - for (i = 0; i < link->public.sink_count; ++i) - dc_sink_release(link->public.remote_sinks[i]); + for (i = 0; i < link->sink_count; ++i) + dc_sink_release(link->remote_sinks[i]); } -static struct gpio *get_hpd_gpio(const struct core_link *link) +static struct gpio *get_hpd_gpio(const struct dc_link *link) { enum bp_result bp_result; struct dc_bios *dcb = link->ctx->dc_bios; @@ -116,7 +116,7 @@ static struct gpio *get_hpd_gpio(const struct core_link *link) * true on success, false otherwise */ static bool program_hpd_filter( - const struct core_link *link) + const struct dc_link *link) { bool result = false; @@ -126,7 +126,7 @@ static bool program_hpd_filter( int delay_on_disconnect_in_ms = 0; /* Verify feature is supported */ - switch (link->public.connector_signal) { + switch (link->connector_signal) { case SIGNAL_TYPE_DVI_SINGLE_LINK: case SIGNAL_TYPE_DVI_DUAL_LINK: case SIGNAL_TYPE_HDMI_TYPE_A: @@ -181,7 +181,7 @@ static bool program_hpd_filter( return result; } -static bool detect_sink(struct core_link *link, enum dc_connection_type *type) +static bool detect_sink(struct dc_link *link, enum dc_connection_type *type) { uint32_t is_hpd_high = 0; struct gpio *hpd_pin; @@ -306,7 +306,7 @@ static enum signal_type get_basic_signal_type( * @brief * Check whether there is a dongle on DP connector */ -static bool is_dp_sink_present(struct core_link *link) +static bool is_dp_sink_present(struct dc_link *link) { enum gpio_result gpio_result; uint32_t clock_pin = 0; @@ -320,7 +320,7 @@ static bool is_dp_sink_present(struct core_link *link) ((connector_id == CONNECTOR_ID_DISPLAY_PORT) || (connector_id == CONNECTOR_ID_EDP)); - ddc = dal_ddc_service_get_ddc_pin(link->public.ddc); + ddc = dal_ddc_service_get_ddc_pin(link->ddc); if (!ddc) { BREAK_TO_DEBUGGER(); @@ -356,7 +356,7 @@ static bool is_dp_sink_present(struct core_link *link) * @brief * Detect output sink type */ -static enum signal_type link_detect_sink(struct core_link *link) +static enum signal_type link_detect_sink(struct dc_link *link) { enum signal_type result = get_basic_signal_type( link->link_enc->id, link->link_id); @@ -446,18 +446,18 @@ static enum signal_type dp_passive_dongle_detection( audio_support); } -static void link_disconnect_sink(struct core_link *link) +static void link_disconnect_sink(struct dc_link *link) { - if (link->public.local_sink) { - dc_sink_release(link->public.local_sink); - link->public.local_sink = NULL; + if (link->local_sink) { + dc_sink_release(link->local_sink); + link->local_sink = NULL; } link->dpcd_sink_count = 0; } static void detect_dp( - struct core_link *link, + struct dc_link *link, struct display_sink_capability *sink_caps, bool *converter_disable_audio, struct audio_support *audio_support, @@ -473,7 +473,7 @@ static void detect_dp( /* DP active dongles */ if (is_dp_active_dongle(link)) { - link->public.type = dc_connection_active_dongle; + link->type = dc_connection_active_dongle; if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) { /* * active dongle unplug processing for short irq @@ -517,8 +517,8 @@ static void detect_dp( if (dm_helpers_dp_mst_start_top_mgr( link->ctx, - &link->public, boot)) { - link->public.type = dc_connection_mst_branch; + link, boot)) { + link->type = dc_connection_mst_branch; } else { /* MST not supported */ sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT; @@ -526,15 +526,14 @@ static void detect_dp( } } else { /* DP passive dongles */ - sink_caps->signal = dp_passive_dongle_detection(link->public.ddc, + sink_caps->signal = dp_passive_dongle_detection(link->ddc, sink_caps, audio_support); } } -bool dc_link_detect(const struct dc_link *dc_link, bool boot) +bool dc_link_detect(struct dc_link *link, bool boot) { - struct core_link *link = DC_LINK_TO_LINK(dc_link); struct dc_sink_init_data sink_init_data = { 0 }; struct display_sink_capability sink_caps = { 0 }; uint8_t i; @@ -546,7 +545,7 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot) struct core_sink *sink = NULL; enum dc_connection_type new_connection_type = dc_connection_none; - if (link->public.connector_signal == SIGNAL_TYPE_VIRTUAL) + if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) return false; if (false == detect_sink(link, &new_connection_type)) { @@ -554,17 +553,17 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot) return false; } - if (link->public.connector_signal == SIGNAL_TYPE_EDP && - link->public.local_sink) + if (link->connector_signal == SIGNAL_TYPE_EDP && + link->local_sink) return true; link_disconnect_sink(link); if (new_connection_type != dc_connection_none) { - link->public.type = new_connection_type; + link->type = new_connection_type; /* From Disconnected-to-Connected. */ - switch (link->public.connector_signal) { + switch (link->connector_signal) { case SIGNAL_TYPE_HDMI_TYPE_A: { sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; if (aud_support->hdmi_audio_native) @@ -602,14 +601,14 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot) aud_support, boot); /* Active dongle downstream unplug */ - if (link->public.type == dc_connection_active_dongle + if (link->type == dc_connection_active_dongle && link->dpcd_caps.sink_count. bits.SINK_COUNT == 0) return true; - if (link->public.type == dc_connection_mst_branch) { + if (link->type == dc_connection_mst_branch) { LINK_INFO("link=%d, mst branch is now Connected\n", - link->public.link_index); + link->link_index); return false; } @@ -618,7 +617,7 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot) default: DC_ERROR("Invalid connector type! signal:%d\n", - link->public.connector_signal); + link->connector_signal); return false; } /* switch() */ @@ -629,13 +628,13 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot) link->dpcd_sink_count = 1; dal_ddc_service_set_transaction_type( - link->public.ddc, + link->ddc, sink_caps.transaction_type); - link->public.aux_mode = dal_ddc_service_is_in_aux_transaction_mode( - link->public.ddc); + link->aux_mode = dal_ddc_service_is_in_aux_transaction_mode( + link->ddc); - sink_init_data.link = &link->public; + sink_init_data.link = link; sink_init_data.sink_signal = sink_caps.signal; dc_sink = dc_sink_create(&sink_init_data); @@ -648,11 +647,11 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot) dc_sink->converter_disable_audio = converter_disable_audio; sink = DC_SINK_TO_CORE(dc_sink); - link->public.local_sink = &sink->public; + link->local_sink = &sink->public; edid_status = dm_helpers_read_local_edid( link->ctx, - &link->public, + link, &sink->public); switch (edid_status) { @@ -719,21 +718,21 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot) } else { /* From Connected-to-Disconnected. */ - if (link->public.type == dc_connection_mst_branch) { + if (link->type == dc_connection_mst_branch) { LINK_INFO("link=%d, mst branch is now Disconnected\n", - link->public.link_index); - dm_helpers_dp_mst_stop_top_mgr(link->ctx, &link->public); + link->link_index); + dm_helpers_dp_mst_stop_top_mgr(link->ctx, link); link->mst_stream_alloc_table.stream_count = 0; memset(link->mst_stream_alloc_table.stream_allocations, 0, sizeof(link->mst_stream_alloc_table.stream_allocations)); } - link->public.type = dc_connection_none; + link->type = dc_connection_none; sink_caps.signal = SIGNAL_TYPE_NONE; } LINK_INFO("link=%d, dc_sink_in=%p is now %s\n", - link->public.link_index, &sink->public, + link->link_index, &sink->public, (sink_caps.signal == SIGNAL_TYPE_NONE ? "Disconnected":"Connected")); @@ -741,7 +740,7 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot) } static enum hpd_source_id get_hpd_line( - struct core_link *link) + struct dc_link *link) { struct gpio *hpd; enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN; @@ -779,12 +778,12 @@ static enum hpd_source_id get_hpd_line( return hpd_id; } -static enum channel_id get_ddc_line(struct core_link *link) +static enum channel_id get_ddc_line(struct dc_link *link) { struct ddc *ddc; enum channel_id channel = CHANNEL_ID_UNKNOWN; - ddc = dal_ddc_service_get_ddc_pin(link->public.ddc); + ddc = dal_ddc_service_get_ddc_pin(link->ddc); if (ddc) { switch (dal_ddc_get_line(ddc)) { @@ -887,7 +886,7 @@ static enum transmitter translate_encoder_to_transmitter( } static bool construct( - struct core_link *link, + struct dc_link *link, const struct link_init_data *init_params) { uint8_t i; @@ -899,14 +898,14 @@ static bool construct( struct dc_bios *bios = init_params->dc->ctx->dc_bios; const struct dc_vbios_funcs *bp_funcs = bios->funcs; - link->public.irq_source_hpd = DC_IRQ_SOURCE_INVALID; - link->public.irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID; + link->irq_source_hpd = DC_IRQ_SOURCE_INVALID; + link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID; link->link_status.dpcd_caps = &link->dpcd_caps; link->dc = init_params->dc; link->ctx = dc_ctx; - link->public.link_index = init_params->link_index; + link->link_index = init_params->link_index; link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index); @@ -919,35 +918,35 @@ static bool construct( hpd_gpio = get_hpd_gpio(link); if (hpd_gpio != NULL) - link->public.irq_source_hpd = dal_irq_get_source(hpd_gpio); + link->irq_source_hpd = dal_irq_get_source(hpd_gpio); switch (link->link_id.id) { case CONNECTOR_ID_HDMI_TYPE_A: - link->public.connector_signal = SIGNAL_TYPE_HDMI_TYPE_A; + link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A; break; case CONNECTOR_ID_SINGLE_LINK_DVID: case CONNECTOR_ID_SINGLE_LINK_DVII: - link->public.connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK; + link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK; break; case CONNECTOR_ID_DUAL_LINK_DVID: case CONNECTOR_ID_DUAL_LINK_DVII: - link->public.connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK; + link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK; break; case CONNECTOR_ID_DISPLAY_PORT: - link->public.connector_signal = SIGNAL_TYPE_DISPLAY_PORT; + link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT; if (hpd_gpio != NULL) - link->public.irq_source_hpd_rx = + link->irq_source_hpd_rx = dal_irq_get_rx_source(hpd_gpio); break; case CONNECTOR_ID_EDP: - link->public.connector_signal = SIGNAL_TYPE_EDP; + link->connector_signal = SIGNAL_TYPE_EDP; if (hpd_gpio != NULL) { - link->public.irq_source_hpd = DC_IRQ_SOURCE_INVALID; - link->public.irq_source_hpd_rx = + link->irq_source_hpd = DC_IRQ_SOURCE_INVALID; + link->irq_source_hpd_rx = dal_irq_get_rx_source(hpd_gpio); } break; @@ -966,21 +965,21 @@ static bool construct( LINK_INFO("Connector[%d] description:" "signal %d\n", init_params->connector_index, - link->public.connector_signal); + link->connector_signal); ddc_service_init_data.ctx = link->ctx; ddc_service_init_data.id = link->link_id; ddc_service_init_data.link = link; - link->public.ddc = dal_ddc_service_create(&ddc_service_init_data); + link->ddc = dal_ddc_service_create(&ddc_service_init_data); - if (link->public.ddc == NULL) { + if (link->ddc == NULL) { DC_ERROR("Failed to create ddc_service!\n"); goto ddc_create_fail; } - link->public.ddc_hw_inst = + link->ddc_hw_inst = dal_ddc_get_line( - dal_ddc_service_get_ddc_pin(link->public.ddc)); + dal_ddc_service_get_ddc_pin(link->ddc)); enc_init_data.ctx = dc_ctx; bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder); @@ -988,7 +987,7 @@ static bool construct( enc_init_data.channel = get_ddc_line(link); enc_init_data.hpd_source = get_hpd_line(link); - link->public.hpd_src = enc_init_data.hpd_source; + link->hpd_src = enc_init_data.hpd_source; enc_init_data.transmitter = translate_encoder_to_transmitter(enc_init_data.encoder); @@ -1000,7 +999,7 @@ static bool construct( goto link_enc_create_fail; } - link->public.link_enc_hw_inst = link->link_enc->transmitter; + link->link_enc_hw_inst = link->link_enc->transmitter; for (i = 0; i < 4; i++) { if (BP_RESULT_OK != @@ -1015,10 +1014,10 @@ static bool construct( if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios, link->device_tag.dev_id)) continue; if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT - && link->public.connector_signal != SIGNAL_TYPE_RGB) + && link->connector_signal != SIGNAL_TYPE_RGB) continue; if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD - && link->public.connector_signal == SIGNAL_TYPE_RGB) + && link->connector_signal == SIGNAL_TYPE_RGB) continue; break; } @@ -1052,7 +1051,7 @@ static bool construct( device_tag_fail: link->link_enc->funcs->destroy(&link->link_enc); link_enc_create_fail: - dal_ddc_service_destroy(&link->public.ddc); + dal_ddc_service_destroy(&link->ddc); ddc_create_fail: create_fail: @@ -1066,9 +1065,9 @@ create_fail: /******************************************************************************* * Public functions ******************************************************************************/ -struct core_link *link_create(const struct link_init_data *init_params) +struct dc_link *link_create(const struct link_init_data *init_params) { - struct core_link *link = + struct dc_link *link = dm_alloc(sizeof(*link)); if (NULL == link) @@ -1086,7 +1085,7 @@ alloc_fail: return NULL; } -void link_destroy(struct core_link **link) +void link_destroy(struct dc_link **link) { destruct(*link); dm_free(*link); @@ -1094,7 +1093,7 @@ void link_destroy(struct core_link **link) } static void dpcd_configure_panel_mode( - struct core_link *link, + struct dc_link *link, enum dp_panel_mode panel_mode) { union dpcd_edp_config edp_config_set; @@ -1139,7 +1138,7 @@ static void dpcd_configure_panel_mode( dm_logger_write(link->ctx->logger, LOG_DETECTION_DP_CAPS, "Link: %d eDP panel mode supported: %d " "eDP panel mode enabled: %d \n", - link->public.link_index, + link->link_index, link->dpcd_caps.panel_mode_edp, panel_mode_edp); } @@ -1147,7 +1146,7 @@ static void dpcd_configure_panel_mode( static void enable_stream_features(struct pipe_ctx *pipe_ctx) { struct core_stream *stream = pipe_ctx->stream; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; union down_spread_ctrl downspread; core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, @@ -1165,7 +1164,7 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) struct core_stream *stream = pipe_ctx->stream; enum dc_status status; bool skip_video_pattern; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; struct dc_link_settings link_settings = {0}; enum dp_panel_mode panel_mode; enum dc_link_rate max_link_rate = LINK_RATE_HIGH2; @@ -1224,7 +1223,7 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) &link_settings, skip_video_pattern, LINK_TRAINING_ATTEMPTS)) { - link->public.cur_link_settings = link_settings; + link->cur_link_settings = link_settings; status = DC_OK; } else @@ -1237,12 +1236,12 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) static enum dc_status enable_link_dp_mst(struct pipe_ctx *pipe_ctx) { - struct core_link *link = pipe_ctx->stream->sink->link; + struct dc_link *link = pipe_ctx->stream->sink->link; /* sink signal type after MST branch is MST. Multiple MST sinks * share one link. Link DP PHY is enable or training only once. */ - if (link->public.cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) + if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) return DC_OK; /* set the sink to MST mode before enabling the link */ @@ -1254,16 +1253,16 @@ static enum dc_status enable_link_dp_mst(struct pipe_ctx *pipe_ctx) static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) { struct core_stream *stream = pipe_ctx->stream; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; enum dc_color_depth display_color_depth; if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) dal_ddc_service_write_scdc_data( - stream->sink->link->public.ddc, + stream->sink->link->ddc, stream->phy_pix_clk, stream->public.timing.flags.LTE_340MCSC_SCRAMBLE); - memset(&stream->sink->link->public.cur_link_settings, 0, + memset(&stream->sink->link->cur_link_settings, 0, sizeof(struct dc_link_settings)); display_color_depth = stream->public.timing.display_color_depth; @@ -1279,7 +1278,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) stream->phy_pix_clk); if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) - dal_ddc_service_read_scdc_data(link->public.ddc); + dal_ddc_service_read_scdc_data(link->ddc); } /****************************enable_link***********************************/ @@ -1321,7 +1320,7 @@ static enum dc_status enable_link(struct pipe_ctx *pipe_ctx) return status; } -static void disable_link(struct core_link *link, enum signal_type signal) +static void disable_link(struct dc_link *link, enum signal_type signal) { /* * TODO: implement call for dp_set_hw_test_pattern @@ -1345,7 +1344,7 @@ static void disable_link(struct core_link *link, enum signal_type signal) enum dc_status dc_link_validate_mode_timing( const struct core_stream *stream, - struct core_link *link, + struct dc_link *link, const struct dc_crtc_timing *timing) { uint32_t max_pix_clk = stream->sink->public.dongle_max_pix_clk; @@ -1353,7 +1352,7 @@ enum dc_status dc_link_validate_mode_timing( /* A hack to avoid failing any modes for EDID override feature on * topology change such as lower quality cable for DP or different dongle */ - if (link->public.remote_sinks[0]) + if (link->remote_sinks[0]) return DC_OK; if (0 != max_pix_clk && timing->pix_clk_khz > max_pix_clk) @@ -1376,10 +1375,9 @@ enum dc_status dc_link_validate_mode_timing( } -bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, +bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, uint32_t frame_ramp, const struct dc_stream *stream) { - struct core_link *link = DC_LINK_TO_CORE(dc_link); struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); struct core_stream *core_stream = NULL; struct abm *abm = core_dc->res_pool->abm; @@ -1392,7 +1390,7 @@ bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, dm_logger_write(link->ctx->logger, LOG_BACKLIGHT, "New Backlight level: %d (0x%X)\n", level, level); - if (dc_is_embedded_signal(dc_link->connector_signal)) { + if (dc_is_embedded_signal(link->connector_signal)) { if (stream != NULL) { core_stream = DC_STREAM_TO_CORE(stream); for (i = 0; i < MAX_PIPES; i++) { @@ -1419,9 +1417,8 @@ bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, } -bool dc_link_set_abm_disable(const struct dc_link *dc_link) +bool dc_link_set_abm_disable(const struct dc_link *link) { - struct core_link *link = DC_LINK_TO_CORE(dc_link); struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); struct abm *abm = core_dc->res_pool->abm; @@ -1434,11 +1431,9 @@ bool dc_link_set_abm_disable(const struct dc_link *dc_link) } -bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable) +bool dc_link_set_psr_enable(const struct dc_link *link, bool enable) { - struct core_link *link = DC_LINK_TO_CORE(dc_link); - struct dc_context *ctx = link->ctx; - struct core_dc *core_dc = DC_TO_CORE(ctx->dc); + struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); struct dmcu *dmcu = core_dc->res_pool->dmcu; if (dmcu != NULL && link->psr_enabled) @@ -1447,11 +1442,9 @@ bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable) return true; } -bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state) +bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state) { - struct core_link *link = DC_LINK_TO_CORE(dc_link); - struct dc_context *ctx = link->ctx; - struct core_dc *core_dc = DC_TO_CORE(ctx->dc); + struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); struct dmcu *dmcu = core_dc->res_pool->dmcu; if (dmcu != NULL && link->psr_enabled) @@ -1460,20 +1453,18 @@ bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state) return true; } -bool dc_link_setup_psr(const struct dc_link *dc_link, +bool dc_link_setup_psr(struct dc_link *link, const struct dc_stream *stream, struct psr_config *psr_config, struct psr_context *psr_context) { - struct core_link *link = DC_LINK_TO_CORE(dc_link); - struct dc_context *ctx = link->ctx; - struct core_dc *core_dc = DC_TO_CORE(ctx->dc); + struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); struct dmcu *dmcu = core_dc->res_pool->dmcu; struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); int i; psr_context->controllerId = CONTROLLER_ID_UNDEFINED; - if (dc_link != NULL && + if (link != NULL && dmcu != NULL) { /* updateSinkPsrDpcdConfig*/ union dpcd_psr_configuration psr_configuration; @@ -1501,12 +1492,12 @@ bool dc_link_setup_psr(const struct dc_link *dc_link, dm_helpers_dp_write_dpcd( link->ctx, - dc_link, + link, 368, &psr_configuration.raw, sizeof(psr_configuration.raw)); - psr_context->channel = link->public.ddc->ddc_pin->hw_info.ddc_channel; + psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel; psr_context->transmitterId = link->link_enc->transmitter; psr_context->engineId = link->link_enc->preferred_engine; @@ -1584,23 +1575,21 @@ bool dc_link_setup_psr(const struct dc_link *dc_link, } -const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link) +const struct dc_link_status *dc_link_get_status(const struct dc_link *link) { - struct core_link *link = DC_LINK_TO_CORE(dc_link); - return &link->link_status; } -void core_link_resume(struct core_link *link) +void core_link_resume(struct dc_link *link) { - if (link->public.connector_signal != SIGNAL_TYPE_VIRTUAL) + if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) program_hpd_filter(link); } static struct fixed31_32 get_pbn_per_slot(struct core_stream *stream) { struct dc_link_settings *link_settings = - &stream->sink->link->public.cur_link_settings; + &stream->sink->link->cur_link_settings; uint32_t link_rate_in_mbps = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ; struct fixed31_32 mbps = dal_fixed31_32_from_int( @@ -1653,7 +1642,7 @@ static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) } static void update_mst_stream_alloc_table( - struct core_link *link, + struct dc_link *link, struct stream_encoder *stream_enc, const struct dp_mst_stream_allocation_table *proposed_table) { @@ -1668,7 +1657,7 @@ static void update_mst_stream_alloc_table( ASSERT(proposed_table->stream_count - link->mst_stream_alloc_table.stream_count < 2); - /* copy proposed_table to core_link, add stream encoder */ + /* copy proposed_table to link, add stream encoder */ for (i = 0; i < proposed_table->stream_count; i++) { for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { @@ -1707,7 +1696,7 @@ static void update_mst_stream_alloc_table( static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) { struct core_stream *stream = pipe_ctx->stream; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; struct link_encoder *link_encoder = link->link_enc; struct stream_encoder *stream_encoder = pipe_ctx->stream_enc; struct dp_mst_stream_allocation_table proposed_table = {0}; @@ -1789,13 +1778,13 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) { struct core_stream *stream = pipe_ctx->stream; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; struct link_encoder *link_encoder = link->link_enc; struct stream_encoder *stream_encoder = pipe_ctx->stream_enc; struct dp_mst_stream_allocation_table proposed_table = {0}; struct fixed31_32 avg_time_slots_per_mtp = dal_fixed31_32_from_int(0); uint8_t i; - bool mst_mode = (link->public.type == dc_connection_mst_branch); + bool mst_mode = (link->type == dc_connection_mst_branch); /* deallocate_mst_payload is called before disable link. When mode or * disable/enable monitor, new stream is created which is not in link @@ -1875,7 +1864,7 @@ void core_link_enable_stream(struct pipe_ctx *pipe_ctx) if (status != DC_OK) { dm_logger_write(pipe_ctx->stream->ctx->logger, LOG_WARNING, "enabling link %u failed: %d\n", - pipe_ctx->stream->sink->link->public.link_index, + pipe_ctx->stream->sink->link->link_index, status); /* Abort stream enable *unless* the failure was due to diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c index 2f5a89c5b063..d09e539397ea 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c @@ -354,7 +354,7 @@ static uint32_t defer_delay_converter_wa( struct ddc_service *ddc, uint32_t defer_delay) { - struct core_link *link = ddc->link; + struct dc_link *link = ddc->link; if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_4 && !memcmp(link->dpcd_caps.branch_dev_name, @@ -423,7 +423,7 @@ static bool i2c_read( return dm_helpers_submit_i2c( ddc->ctx, - &ddc->link->public, + ddc->link, &command); } @@ -624,7 +624,7 @@ bool dal_ddc_service_query_ddc_data( ret = dm_helpers_submit_i2c( ddc->ctx, - &ddc->link->public, + ddc->link, &command); dal_ddc_i2c_payloads_destroy(&payloads); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index e90b3ebc8347..c7b400786121 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -34,7 +34,7 @@ enum { }; static void wait_for_training_aux_rd_interval( - struct core_link* link, + struct dc_link *link, uint32_t default_wait_in_micro_secs) { union training_aux_rd_interval training_rd_interval; @@ -63,7 +63,7 @@ static void wait_for_training_aux_rd_interval( } static void dpcd_set_training_pattern( - struct core_link* link, + struct dc_link *link, union dpcd_training_pattern dpcd_pattern) { core_link_write_dpcd( @@ -80,7 +80,7 @@ static void dpcd_set_training_pattern( } static void dpcd_set_link_settings( - struct core_link* link, + struct dc_link *link, const struct link_training_settings *lt_settings) { uint8_t rate = (uint8_t) @@ -123,7 +123,7 @@ static void dpcd_set_link_settings( static enum dpcd_training_patterns hw_training_pattern_to_dpcd_training_pattern( - struct core_link* link, + struct dc_link *link, enum hw_dp_training_pattern pattern) { enum dpcd_training_patterns dpcd_tr_pattern = @@ -155,7 +155,7 @@ static enum dpcd_training_patterns } static void dpcd_set_lt_pattern_and_lane_settings( - struct core_link* link, + struct dc_link *link, const struct link_training_settings *lt_settings, enum hw_dp_training_pattern pattern) { @@ -246,7 +246,7 @@ static void dpcd_set_lt_pattern_and_lane_settings( dpcd_lt_buffer, size_in_bytes + sizeof(dpcd_pattern.raw) ); - link->public.cur_lane_setting = lt_settings->lane_settings[0]; + link->cur_lane_setting = lt_settings->lane_settings[0]; } static bool is_cr_done(enum dc_lane_count ln_count, @@ -419,7 +419,7 @@ static void find_max_drive_settings( } static void get_lane_status_and_drive_settings( - struct core_link* link, + struct dc_link *link, const struct link_training_settings *link_training_setting, union lane_status *ln_status, union lane_align_status_updated *ln_status_updated, @@ -500,7 +500,7 @@ static void get_lane_status_and_drive_settings( } static void dpcd_set_lane_settings( - struct core_link* link, + struct dc_link *link, const struct link_training_settings *link_training_setting) { union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}}; @@ -560,7 +560,7 @@ static void dpcd_set_lane_settings( dpcd_lane[0].bits.MAX_SWING_REACHED, dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED); - link->public.cur_lane_setting = link_training_setting->lane_settings[0]; + link->cur_lane_setting = link_training_setting->lane_settings[0]; } @@ -580,19 +580,18 @@ static bool is_max_vs_reached( } void dc_link_dp_set_drive_settings( - const struct dc_link *link, + struct dc_link *link, struct link_training_settings *lt_settings) { - struct core_link *core_link = DC_LINK_TO_CORE(link); /* program ASIC PHY settings*/ - dp_set_hw_lane_settings(core_link, lt_settings); + dp_set_hw_lane_settings(link, lt_settings); /* Notify DP sink the PHY settings from source */ - dpcd_set_lane_settings(core_link, lt_settings); + dpcd_set_lane_settings(link, lt_settings); } static bool perform_post_lt_adj_req_sequence( - struct core_link *link, + struct dc_link *link, struct link_training_settings *lt_settings) { enum dc_lane_count lane_count = @@ -656,7 +655,7 @@ static bool perform_post_lt_adj_req_sequence( update_drive_settings( lt_settings,req_settings); - dc_link_dp_set_drive_settings(&link->public, + dc_link_dp_set_drive_settings(link, lt_settings); break; } @@ -682,7 +681,7 @@ static bool perform_post_lt_adj_req_sequence( } -static enum hw_dp_training_pattern get_supported_tp(struct core_link *link) +static enum hw_dp_training_pattern get_supported_tp(struct dc_link *link) { enum hw_dp_training_pattern highest_tp = HW_DP_TRAINING_PATTERN_2; struct encoder_feature_support *features = &link->link_enc->features; @@ -706,7 +705,7 @@ static enum hw_dp_training_pattern get_supported_tp(struct core_link *link) } static enum link_training_result perform_channel_equalization_sequence( - struct core_link *link, + struct dc_link *link, struct link_training_settings *lt_settings) { struct link_training_settings req_settings; @@ -768,7 +767,7 @@ static enum link_training_result perform_channel_equalization_sequence( } static bool perform_clock_recovery_sequence( - struct core_link *link, + struct dc_link *link, struct link_training_settings *lt_settings) { uint32_t retries_cr; @@ -877,7 +876,7 @@ static bool perform_clock_recovery_sequence( } static inline bool perform_link_training_int( - struct core_link *link, + struct dc_link *link, struct link_training_settings *lt_settings, bool status) { @@ -923,7 +922,6 @@ enum link_training_result dc_link_dp_perform_link_training( bool skip_video_pattern) { enum link_training_result status = LINK_TRAINING_SUCCESS; - struct core_link *core_link = DC_LINK_TO_CORE(link); char *link_rate = "Unknown"; struct link_training_settings lt_settings; @@ -945,19 +943,19 @@ enum link_training_result dc_link_dp_perform_link_training( lt_settings.link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ; /* 1. set link rate, lane count and spread*/ - dpcd_set_link_settings(core_link, <_settings); + dpcd_set_link_settings(link, <_settings); /* 2. perform link training (set link training done * to false is done as well)*/ - if (!perform_clock_recovery_sequence(core_link, <_settings)) { + if (!perform_clock_recovery_sequence(link, <_settings)) { status = LINK_TRAINING_CR_FAIL; } else { - status = perform_channel_equalization_sequence(core_link, + status = perform_channel_equalization_sequence(link, <_settings); } if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) { - if (!perform_link_training_int(core_link, + if (!perform_link_training_int(link, <_settings, status == LINK_TRAINING_SUCCESS)) { /* the next link training setting in this case @@ -990,7 +988,7 @@ enum link_training_result dc_link_dp_perform_link_training( } /* Connectivity log: link training */ - CONN_MSG_LT(core_link, "%sx%d %s VS=%d, PE=%d", + CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d", link_rate, lt_settings.link_settings.lane_count, (status == LINK_TRAINING_SUCCESS) ? "pass" : @@ -1004,7 +1002,7 @@ enum link_training_result dc_link_dp_perform_link_training( bool perform_link_training_with_retries( - struct core_link *link, + struct dc_link *link, const struct dc_link_settings *link_setting, bool skip_video_pattern, int attempts) @@ -1015,7 +1013,7 @@ bool perform_link_training_with_retries( for (j = 0; j < attempts; ++j) { if (dc_link_dp_perform_link_training( - &link->public, + link, link_setting, skip_video_pattern) == LINK_TRAINING_SUCCESS) return true; @@ -1027,7 +1025,7 @@ bool perform_link_training_with_retries( return false; } -static struct dc_link_settings get_max_link_cap(struct core_link *link) +static struct dc_link_settings get_max_link_cap(struct dc_link *link) { /* Set Default link settings */ struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH, @@ -1041,21 +1039,21 @@ static struct dc_link_settings get_max_link_cap(struct core_link *link) max_link_cap.link_rate = LINK_RATE_HIGH3; /* Lower link settings based on sink's link cap */ - if (link->public.reported_link_cap.lane_count < max_link_cap.lane_count) + if (link->reported_link_cap.lane_count < max_link_cap.lane_count) max_link_cap.lane_count = - link->public.reported_link_cap.lane_count; - if (link->public.reported_link_cap.link_rate < max_link_cap.link_rate) + link->reported_link_cap.lane_count; + if (link->reported_link_cap.link_rate < max_link_cap.link_rate) max_link_cap.link_rate = - link->public.reported_link_cap.link_rate; - if (link->public.reported_link_cap.link_spread < + link->reported_link_cap.link_rate; + if (link->reported_link_cap.link_spread < max_link_cap.link_spread) max_link_cap.link_spread = - link->public.reported_link_cap.link_spread; + link->reported_link_cap.link_spread; return max_link_cap; } bool dp_hbr_verify_link_cap( - struct core_link *link, + struct dc_link *link, struct dc_link_settings *known_limit_link_setting) { struct dc_link_settings max_link_cap = {0}; @@ -1080,7 +1078,7 @@ bool dp_hbr_verify_link_cap( * find the physical link capability */ /* disable PHY done possible by BIOS, will be done by driver itself */ - dp_disable_link_phy(link, link->public.connector_signal); + dp_disable_link_phy(link, link->connector_signal); dp_cs = link->dc->res_pool->dp_clock_source; @@ -1109,7 +1107,7 @@ bool dp_hbr_verify_link_cap( dp_enable_link_phy( link, - link->public.connector_signal, + link->connector_signal, dp_cs_id, cur); @@ -1117,7 +1115,7 @@ bool dp_hbr_verify_link_cap( success = true; else { status = dc_link_dp_perform_link_training( - &link->public, + link, cur, skip_video_pattern); if (status == LINK_TRAINING_SUCCESS) @@ -1125,13 +1123,13 @@ bool dp_hbr_verify_link_cap( } if (success) - link->public.verified_link_cap = *cur; + link->verified_link_cap = *cur; /* always disable the link before trying another * setting or before returning we'll enable it later * based on the actual mode we're driving */ - dp_disable_link_phy(link, link->public.connector_signal); + dp_disable_link_phy(link, link->connector_signal); } while (!success && decide_fallback_link_setting( initial_link_settings, cur, status)); @@ -1142,14 +1140,14 @@ bool dp_hbr_verify_link_cap( /* If all LT fails for all settings, * set verified = failed safe (1 lane low) */ - link->public.verified_link_cap.lane_count = LANE_COUNT_ONE; - link->public.verified_link_cap.link_rate = LINK_RATE_LOW; + link->verified_link_cap.lane_count = LANE_COUNT_ONE; + link->verified_link_cap.link_rate = LINK_RATE_LOW; - link->public.verified_link_cap.link_spread = + link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED; } - link->public.max_link_setting = link->public.verified_link_cap; + link->max_link_setting = link->verified_link_cap; return success; } @@ -1391,7 +1389,7 @@ static uint32_t bandwidth_in_kbps_from_link_settings( } bool dp_validate_mode_timing( - struct core_link *link, + struct dc_link *link, const struct dc_crtc_timing *timing) { uint32_t req_bw; @@ -1406,12 +1404,12 @@ bool dp_validate_mode_timing( return true; /* We always use verified link settings */ - link_setting = &link->public.verified_link_cap; + link_setting = &link->verified_link_cap; /* TODO: DYNAMIC_VALIDATION needs to be implemented */ /*if (flags.DYNAMIC_VALIDATION == 1 && - link->public.verified_link_cap.lane_count != LANE_COUNT_UNKNOWN) - link_setting = &link->public.verified_link_cap; + link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN) + link_setting = &link->verified_link_cap; */ req_bw = bandwidth_in_kbps_from_timing(timing); @@ -1444,7 +1442,7 @@ void decide_link_settings(struct core_stream *stream, LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED}; struct dc_link_settings current_link_setting = initial_link_setting; - struct core_link* link; + struct dc_link *link; uint32_t req_bw; uint32_t link_bw; @@ -1456,11 +1454,11 @@ void decide_link_settings(struct core_stream *stream, /* if preferred is specified through AMDDP, use it, if it's enough * to drive the mode */ - if (link->public.preferred_link_setting.lane_count != + if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN && - link->public.preferred_link_setting.link_rate != + link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) { - *link_setting = link->public.preferred_link_setting; + *link_setting = link->preferred_link_setting; return; } @@ -1469,7 +1467,7 @@ void decide_link_settings(struct core_stream *stream, * 2. could support the b/w requested by the timing */ while (current_link_setting.link_rate <= - link->public.max_link_setting.link_rate) { + link->max_link_setting.link_rate) { link_bw = bandwidth_in_kbps_from_link_settings( ¤t_link_setting); if (req_bw <= link_bw) { @@ -1478,7 +1476,7 @@ void decide_link_settings(struct core_stream *stream, } if (current_link_setting.lane_count < - link->public.max_link_setting.lane_count) { + link->max_link_setting.lane_count) { current_link_setting.lane_count = increase_lane_count( current_link_setting.lane_count); @@ -1492,16 +1490,15 @@ void decide_link_settings(struct core_stream *stream, } BREAK_TO_DEBUGGER(); - ASSERT(link->public.verified_link_cap.lane_count != - LANE_COUNT_UNKNOWN); + ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN); - *link_setting = link->public.verified_link_cap; + *link_setting = link->verified_link_cap; } /*************************Short Pulse IRQ***************************/ static bool hpd_rx_irq_check_link_loss_status( - struct core_link *link, + struct dc_link *link, union hpd_irq_data *hpd_irq_dpcd_data) { uint8_t irq_reg_rx_power_state; @@ -1514,7 +1511,7 @@ static bool hpd_rx_irq_check_link_loss_status( sink_status_changed = false; return_code = false; - if (link->public.cur_link_settings.lane_count == 0) + if (link->cur_link_settings.lane_count == 0) return return_code; /*1. Check that we can handle interrupt: Not in FS DOS, * Not in "Display Timeout" state, Link is trained. @@ -1538,7 +1535,7 @@ static bool hpd_rx_irq_check_link_loss_status( /*parse lane status*/ for (lane = 0; - lane < link->public.cur_link_settings.lane_count; + lane < link->cur_link_settings.lane_count; lane++) { /* check status of lanes 0,1 @@ -1577,7 +1574,7 @@ static bool hpd_rx_irq_check_link_loss_status( } static enum dc_status read_hpd_rx_irq_data( - struct core_link *link, + struct dc_link *link, union hpd_irq_data *irq_data) { /* The HW reads 16 bytes from 200h on HPD, @@ -1593,7 +1590,7 @@ static enum dc_status read_hpd_rx_irq_data( sizeof(union hpd_irq_data)); } -static bool allow_hpd_rx_irq(const struct core_link *link) +static bool allow_hpd_rx_irq(const struct dc_link *link) { /* * Don't handle RX IRQ unless one of following is met: @@ -1602,15 +1599,15 @@ static bool allow_hpd_rx_irq(const struct core_link *link) * 3) We know we're dealing with an active dongle */ - if ((link->public.cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || - (link->public.type == dc_connection_mst_branch) || + if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || + (link->type == dc_connection_mst_branch) || is_dp_active_dongle(link)) return true; return false; } -static bool handle_hpd_irq_psr_sink(const struct core_link *link) +static bool handle_hpd_irq_psr_sink(const struct dc_link *link) { union dpcd_psr_configuration psr_configuration; @@ -1619,7 +1616,7 @@ static bool handle_hpd_irq_psr_sink(const struct core_link *link) dm_helpers_dp_read_dpcd( link->ctx, - &link->public, + link, 368,/*DpcdAddress_PSR_Enable_Cfg*/ &psr_configuration.raw, sizeof(psr_configuration.raw)); @@ -1632,7 +1629,7 @@ static bool handle_hpd_irq_psr_sink(const struct core_link *link) dm_helpers_dp_read_dpcd( link->ctx, - &link->public, + link, 0x2006, /*DpcdAddress_PSR_Error_Status*/ (unsigned char *) dpcdbuf, sizeof(dpcdbuf)); @@ -1647,14 +1644,14 @@ static bool handle_hpd_irq_psr_sink(const struct core_link *link) /* Acknowledge and clear error bits */ dm_helpers_dp_write_dpcd( link->ctx, - &link->public, + link, 8198,/*DpcdAddress_PSR_Error_Status*/ &psr_error_status.raw, sizeof(psr_error_status.raw)); /* PSR error, disable and re-enable PSR */ - dc_link_set_psr_enable(&link->public, false); - dc_link_set_psr_enable(&link->public, true); + dc_link_set_psr_enable(link, false); + dc_link_set_psr_enable(link, true); return true; } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS == @@ -1670,7 +1667,7 @@ static bool handle_hpd_irq_psr_sink(const struct core_link *link) return false; } -static void dp_test_send_link_training(struct core_link *link) +static void dp_test_send_link_training(struct dc_link *link) { struct dc_link_settings link_settings = {0}; @@ -1686,13 +1683,13 @@ static void dp_test_send_link_training(struct core_link *link) 1); /* Set preferred link settings */ - link->public.verified_link_cap.lane_count = link_settings.lane_count; - link->public.verified_link_cap.link_rate = link_settings.link_rate; + link->verified_link_cap.lane_count = link_settings.lane_count; + link->verified_link_cap.link_rate = link_settings.link_rate; dp_retrain_link_dp_test(link, &link_settings, false); } -static void dp_test_send_phy_test_pattern(struct core_link *link) +static void dp_test_send_phy_test_pattern(struct dc_link *link) { union phy_test_pattern dpcd_test_pattern; union lane_adjust dpcd_lane_adjustment[2]; @@ -1771,10 +1768,10 @@ static void dp_test_send_phy_test_pattern(struct core_link *link) sizeof(test_80_bit_pattern)); /* prepare link training settings */ - link_settings.link = link->public.cur_link_settings; + link_settings.link = link->cur_link_settings; for (lane = 0; lane < - (unsigned int)(link->public.cur_link_settings.lane_count); + (unsigned int)(link->cur_link_settings.lane_count); lane++) { dpcd_lane_adjust.raw = get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane); @@ -1802,7 +1799,7 @@ static void dp_test_send_phy_test_pattern(struct core_link *link) * forward request to DS */ dc_link_dp_set_test_pattern( - &link->public, + link, test_pattern, &link_training_settings, test_80_bit_pattern, @@ -1810,7 +1807,7 @@ static void dp_test_send_phy_test_pattern(struct core_link *link) DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1); } -static void dp_test_send_link_test_pattern(struct core_link *link) +static void dp_test_send_link_test_pattern(struct dc_link *link) { union link_test_pattern dpcd_test_pattern; union test_misc dpcd_test_params; @@ -1850,14 +1847,14 @@ static void dp_test_send_link_test_pattern(struct core_link *link) } dc_link_dp_set_test_pattern( - &link->public, + link, test_pattern, NULL, NULL, 0); } -static void handle_automated_test(struct core_link *link) +static void handle_automated_test(struct dc_link *link) { union test_request test_request; union test_response test_response; @@ -1904,9 +1901,8 @@ static void handle_automated_test(struct core_link *link) sizeof(test_response)); } -bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link, union hpd_irq_data *out_hpd_irq_dpcd_data) +bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data) { - struct core_link *link = DC_LINK_TO_LINK(dc_link); union hpd_irq_data hpd_irq_dpcd_data = {{{{0}}}}; union device_service_irq device_service_clear = { { 0 } }; enum dc_status result = DDC_RESULT_UNKNOWN; @@ -1917,7 +1913,7 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link, union hpd_irq_data dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ, "%s: Got short pulse HPD on link %d\n", - __func__, link->public.link_index); + __func__, link->link_index); /* All the "handle_hpd_irq_xxx()" methods @@ -1951,7 +1947,7 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link, union hpd_irq_data if (!allow_hpd_rx_irq(link)) { dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ, "%s: skipping HPD handling on %d\n", - __func__, link->public.link_index); + __func__, link->link_index); return false; } @@ -1984,13 +1980,13 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link, union hpd_irq_data "Status: "); perform_link_training_with_retries(link, - &link->public.cur_link_settings, + &link->cur_link_settings, true, LINK_TRAINING_ATTEMPTS); status = false; } - if (link->public.type == dc_connection_active_dongle && + if (link->type == dc_connection_active_dongle && hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT != link->dpcd_sink_count) status = true; @@ -2010,7 +2006,7 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link, union hpd_irq_data } /*query dpcd for version and mst cap addresses*/ -bool is_mst_supported(struct core_link *link) +bool is_mst_supported(struct dc_link *link) { bool mst = false; enum dc_status st = DC_OK; @@ -2034,7 +2030,7 @@ bool is_mst_supported(struct core_link *link) } -bool is_dp_active_dongle(const struct core_link *link) +bool is_dp_active_dongle(const struct dc_link *link) { enum display_dongle_type dongle_type = link->dpcd_caps.dongle_type; @@ -2044,14 +2040,14 @@ bool is_dp_active_dongle(const struct core_link *link) } static void get_active_converter_info( - uint8_t data, struct core_link *link) + uint8_t data, struct dc_link *link) { union dp_downstream_port_present ds_port = { .byte = data }; /* decode converter info*/ if (!ds_port.fields.PORT_PRESENT) { link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; - ddc_service_set_dongle_type(link->public.ddc, + ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type); return; } @@ -2121,7 +2117,7 @@ static void get_active_converter_info( } } - ddc_service_set_dongle_type(link->public.ddc, link->dpcd_caps.dongle_type); + ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type); { struct dp_device_vendor_id dp_id; @@ -2158,7 +2154,7 @@ static void get_active_converter_info( } } -static void dp_wa_power_up_0010FA(struct core_link *link, uint8_t *dpcd_data, +static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data, int length) { int retry = 0; @@ -2199,7 +2195,7 @@ static void dp_wa_power_up_0010FA(struct core_link *link, uint8_t *dpcd_data, link->wa_flags.dp_keep_receiver_powered = false; } -static void retrieve_link_cap(struct core_link *link) +static void retrieve_link_cap(struct dc_link *link) { uint8_t dpcd_data[DP_TRAINING_AUX_RD_INTERVAL - DP_DPCD_REV + 1]; @@ -2253,11 +2249,11 @@ static void retrieve_link_cap(struct core_link *link) link->dpcd_caps.max_down_spread.raw = dpcd_data[ DP_MAX_DOWNSPREAD - DP_DPCD_REV]; - link->public.reported_link_cap.lane_count = + link->reported_link_cap.lane_count = link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT; - link->public.reported_link_cap.link_rate = dpcd_data[ + link->reported_link_cap.link_rate = dpcd_data[ DP_MAX_LINK_RATE - DP_DPCD_REV]; - link->public.reported_link_cap.link_spread = + link->reported_link_cap.link_spread = link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ? LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED; @@ -2266,8 +2262,8 @@ static void retrieve_link_cap(struct core_link *link) link->dpcd_caps.panel_mode_edp = edp_config_cap.bits.ALT_SCRAMBLER_RESET; - link->public.test_pattern_enabled = false; - link->public.compliance_test_state.raw = 0; + link->test_pattern_enabled = false; + link->compliance_test_state.raw = 0; /* read sink count */ core_link_read_dpcd(link, @@ -2279,7 +2275,7 @@ static void retrieve_link_cap(struct core_link *link) CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: "); } -void detect_dp_sink_caps(struct core_link *link) +void detect_dp_sink_caps(struct dc_link *link) { retrieve_link_cap(link); @@ -2291,18 +2287,17 @@ void detect_dp_sink_caps(struct core_link *link) */ if (is_mst_supported(link)) { - link->public.verified_link_cap = link->public.reported_link_cap; + link->verified_link_cap = link->reported_link_cap; } else { dp_hbr_verify_link_cap(link, - &link->public.reported_link_cap); + &link->reported_link_cap); } /* TODO save sink caps in link->sink */ } void dc_link_dp_enable_hpd(const struct dc_link *link) { - struct core_link *core_link = DC_LINK_TO_CORE(link); - struct link_encoder *encoder = core_link->link_enc; + struct link_encoder *encoder = link->link_enc; if (encoder != NULL && encoder->funcs->enable_hpd != NULL) encoder->funcs->enable_hpd(encoder); @@ -2310,8 +2305,7 @@ void dc_link_dp_enable_hpd(const struct dc_link *link) void dc_link_dp_disable_hpd(const struct dc_link *link) { - struct core_link *core_link = DC_LINK_TO_CORE(link); - struct link_encoder *encoder = core_link->link_enc; + struct link_encoder *encoder = link->link_enc; if (encoder != NULL && encoder->funcs->enable_hpd != NULL) encoder->funcs->disable_hpd(encoder); @@ -2327,7 +2321,7 @@ static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern) return false; } -static void set_crtc_test_pattern(struct core_link *link, +static void set_crtc_test_pattern(struct dc_link *link, struct pipe_ctx *pipe_ctx, enum dp_test_pattern test_pattern) { @@ -2402,15 +2396,13 @@ static void set_crtc_test_pattern(struct core_link *link, } bool dc_link_dp_set_test_pattern( - const struct dc_link *link, + struct dc_link *link, enum dp_test_pattern test_pattern, const struct link_training_settings *p_link_settings, const unsigned char *p_custom_pattern, unsigned int cust_pattern_size) { - struct core_link *core_link = DC_LINK_TO_CORE(link); - struct pipe_ctx *pipes = - core_link->dc->current_context->res_ctx.pipe_ctx; + struct pipe_ctx *pipes = link->dc->current_context->res_ctx.pipe_ctx; struct pipe_ctx pipe_ctx = pipes[0]; unsigned int lane; unsigned int i; @@ -2421,7 +2413,7 @@ bool dc_link_dp_set_test_pattern( memset(&training_pattern, 0, sizeof(training_pattern)); for (i = 0; i < MAX_PIPES; i++) { - if (pipes[i].stream->sink->link == core_link) { + if (pipes[i].stream->sink->link == link) { pipe_ctx = pipes[i]; break; } @@ -2431,24 +2423,24 @@ bool dc_link_dp_set_test_pattern( * is VideoMode Reset DP Phy Test Pattern if it is currently running * and request is VideoMode */ - if (core_link->public.test_pattern_enabled && test_pattern == + if (link->test_pattern_enabled && test_pattern == DP_TEST_PATTERN_VIDEO_MODE) { /* Set CRTC Test Pattern */ - set_crtc_test_pattern(core_link, &pipe_ctx, test_pattern); - dp_set_hw_test_pattern(core_link, test_pattern, + set_crtc_test_pattern(link, &pipe_ctx, test_pattern); + dp_set_hw_test_pattern(link, test_pattern, (uint8_t *)p_custom_pattern, (uint32_t)cust_pattern_size); /* Unblank Stream */ - core_link->dc->hwss.unblank_stream( + link->dc->hwss.unblank_stream( &pipe_ctx, - &core_link->public.verified_link_cap); + &link->verified_link_cap); /* TODO:m_pHwss->MuteAudioEndpoint * (pPathMode->pDisplayPath, false); */ /* Reset Test Pattern state */ - core_link->public.test_pattern_enabled = false; + link->test_pattern_enabled = false; return true; } @@ -2457,8 +2449,8 @@ bool dc_link_dp_set_test_pattern( if (is_dp_phy_pattern(test_pattern)) { /* Set DPCD Lane Settings before running test pattern */ if (p_link_settings != NULL) { - dp_set_hw_lane_settings(core_link, p_link_settings); - dpcd_set_lane_settings(core_link, p_link_settings); + dp_set_hw_lane_settings(link, p_link_settings); + dpcd_set_lane_settings(link, p_link_settings); } /* Blank stream if running test pattern */ @@ -2471,15 +2463,15 @@ bool dc_link_dp_set_test_pattern( pipes->stream_enc->funcs->dp_blank(pipe_ctx.stream_enc); } - dp_set_hw_test_pattern(core_link, test_pattern, + dp_set_hw_test_pattern(link, test_pattern, (uint8_t *)p_custom_pattern, (uint32_t)cust_pattern_size); if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { /* Set Test Pattern state */ - core_link->public.test_pattern_enabled = true; + link->test_pattern_enabled = true; if (p_link_settings != NULL) - dpcd_set_link_settings(core_link, + dpcd_set_link_settings(link, p_link_settings); } @@ -2516,7 +2508,7 @@ bool dc_link_dp_set_test_pattern( /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/) return false; - if (core_link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { + if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { /* tell receiver that we are sending qualification * pattern DP 1.2 or later - DP receiver's link quality * pattern is set using DPCD LINK_QUAL_LANEx_SET @@ -2526,12 +2518,12 @@ bool dc_link_dp_set_test_pattern( link_qual_pattern[lane] = (unsigned char)(pattern); - core_link_write_dpcd(core_link, + core_link_write_dpcd(link, DP_LINK_QUAL_LANE0_SET, link_qual_pattern, sizeof(link_qual_pattern)); - } else if (core_link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 || - core_link->dpcd_caps.dpcd_rev.raw == 0) { + } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 || + link->dpcd_caps.dpcd_rev.raw == 0) { /* tell receiver that we are sending qualification * pattern DP 1.1a or earlier - DP receiver's link * quality pattern is set using @@ -2539,27 +2531,25 @@ bool dc_link_dp_set_test_pattern( * register (0x102). We will use v_1.3 when we are * setting test pattern for DP 1.1. */ - core_link_read_dpcd(core_link, - DP_TRAINING_PATTERN_SET, - &training_pattern.raw, - sizeof(training_pattern)); + core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET, + &training_pattern.raw, + sizeof(training_pattern)); training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern; - core_link_write_dpcd(core_link, - DP_TRAINING_PATTERN_SET, - &training_pattern.raw, - sizeof(training_pattern)); + core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET, + &training_pattern.raw, + sizeof(training_pattern)); } } else { /* CRTC Patterns */ - set_crtc_test_pattern(core_link, &pipe_ctx, test_pattern); + set_crtc_test_pattern(link, &pipe_ctx, test_pattern); /* Set Test Pattern state */ - core_link->public.test_pattern_enabled = true; + link->test_pattern_enabled = true; } return true; } -void dp_enable_mst_on_sink(struct core_link *link, bool enable) +void dp_enable_mst_on_sink(struct dc_link *link, bool enable) { unsigned char mstmCntl; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index 0092e70b9efd..aac2420caefa 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -16,13 +16,13 @@ #include "dpcd_defs.h" enum dc_status core_link_read_dpcd( - struct core_link* link, + struct dc_link *link, uint32_t address, uint8_t *data, uint32_t size) { if (!dm_helpers_dp_read_dpcd(link->ctx, - &link->public, + link, address, data, size)) return DC_ERROR_UNEXPECTED; @@ -30,20 +30,20 @@ enum dc_status core_link_read_dpcd( } enum dc_status core_link_write_dpcd( - struct core_link* link, + struct dc_link *link, uint32_t address, const uint8_t *data, uint32_t size) { if (!dm_helpers_dp_write_dpcd(link->ctx, - &link->public, + link, address, data, size)) return DC_ERROR_UNEXPECTED; return DC_OK; } -void dp_receiver_power_ctrl(struct core_link *link, bool on) +void dp_receiver_power_ctrl(struct dc_link *link, bool on) { uint8_t state; @@ -54,7 +54,7 @@ void dp_receiver_power_ctrl(struct core_link *link, bool on) } void dp_enable_link_phy( - struct core_link *link, + struct dc_link *link, enum signal_type signal, enum clock_source_id clock_source, const struct dc_link_settings *link_settings) @@ -107,7 +107,7 @@ void dp_enable_link_phy( dp_receiver_power_ctrl(link, true); } -void dp_disable_link_phy(struct core_link *link, enum signal_type signal) +void dp_disable_link_phy(struct dc_link *link, enum signal_type signal) { if (!link->wa_flags.dp_keep_receiver_powered) dp_receiver_power_ctrl(link, false); @@ -120,11 +120,11 @@ void dp_disable_link_phy(struct core_link *link, enum signal_type signal) link->link_enc->funcs->disable_output(link->link_enc, signal); /* Clear current link setting.*/ - memset(&link->public.cur_link_settings, 0, - sizeof(link->public.cur_link_settings)); + memset(&link->cur_link_settings, 0, + sizeof(link->cur_link_settings)); } -void dp_disable_link_phy_mst(struct core_link *link, enum signal_type signal) +void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal) { /* MST disable link only when no stream use the link */ if (link->mst_stream_alloc_table.stream_count > 0) @@ -137,7 +137,7 @@ void dp_disable_link_phy_mst(struct core_link *link, enum signal_type signal) } bool dp_set_hw_training_pattern( - struct core_link *link, + struct dc_link *link, enum hw_dp_training_pattern pattern) { enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; @@ -165,7 +165,7 @@ bool dp_set_hw_training_pattern( } void dp_set_hw_lane_settings( - struct core_link *link, + struct dc_link *link, const struct link_training_settings *link_settings) { struct link_encoder *encoder = link->link_enc; @@ -174,13 +174,13 @@ void dp_set_hw_lane_settings( encoder->funcs->dp_set_lane_settings(encoder, link_settings); } -enum dp_panel_mode dp_get_panel_mode(struct core_link *link) +enum dp_panel_mode dp_get_panel_mode(struct dc_link *link) { /* We need to explicitly check that connector * is not DP. Some Travis_VGA get reported * by video bios as DP. */ - if (link->public.connector_signal != SIGNAL_TYPE_DISPLAY_PORT) { + if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) { switch (link->dpcd_caps.branch_dev_id) { case DP_BRANCH_DEVICE_ID_2: @@ -215,7 +215,7 @@ enum dp_panel_mode dp_get_panel_mode(struct core_link *link) } void dp_set_hw_test_pattern( - struct core_link *link, + struct dc_link *link, enum dp_test_pattern test_pattern, uint8_t *custom_pattern, uint32_t custom_pattern_size) @@ -231,7 +231,7 @@ void dp_set_hw_test_pattern( encoder->funcs->dp_set_phy_pattern(encoder, &pattern_param); } -void dp_retrain_link_dp_test(struct core_link *link, +void dp_retrain_link_dp_test(struct dc_link *link, struct dc_link_settings *link_setting, bool skip_video_pattern) { @@ -263,8 +263,8 @@ void dp_retrain_link_dp_test(struct core_link *link, SIGNAL_TYPE_DISPLAY_PORT); /* Clear current link setting. */ - memset(&link->public.cur_link_settings, 0, - sizeof(link->public.cur_link_settings)); + memset(&link->cur_link_settings, 0, + sizeof(link->cur_link_settings)); link->link_enc->funcs->enable_dp_output( link->link_enc, @@ -274,11 +274,11 @@ void dp_retrain_link_dp_test(struct core_link *link, dp_receiver_power_ctrl(link, true); dc_link_dp_perform_link_training( - &link->public, + link, link_setting, skip_video_pattern); - link->public.cur_link_settings = *link_setting; + link->cur_link_settings = *link_setting; link->dc->hwss.enable_stream(&pipes[i]); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 303c95432d5b..7a3d090f8465 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1269,7 +1269,7 @@ static struct stream_encoder *find_first_free_match_stream_enc_for_link( { int i; int j = -1; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; for (i = 0; i < pool->stream_enc_count; i++) { if (!res_ctx->is_stream_enc_acquired[i] && @@ -1322,9 +1322,7 @@ static void update_stream_signal(struct core_stream *stream) const struct dc_sink *dc_sink = stream->public.sink; if (dc_sink->sink_signal == SIGNAL_TYPE_NONE) - stream->signal = - stream->sink->link-> - public.connector_signal; + stream->signal = stream->sink->link->connector_signal; else stream->signal = dc_sink->sink_signal; } else { @@ -1380,7 +1378,7 @@ static struct core_stream *find_pll_sharable_stream( if (resource_are_streams_timing_synchronizable( stream_needs_pll, stream_has_pll) && !dc_is_dp_signal(stream_has_pll->signal) - && stream_has_pll->sink->link->public.connector_signal + && stream_has_pll->sink->link->connector_signal != SIGNAL_TYPE_VIRTUAL) return stream_has_pll; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c index da9955675fbf..7f0ba7267682 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c @@ -54,15 +54,14 @@ static void destruct(struct sink *sink) static bool construct(struct sink *sink, const struct dc_sink_init_data *init_params) { - struct core_link *core_link = DC_LINK_TO_LINK(init_params->link); + struct dc_link *link = init_params->link; - if (!core_link) { + if (!link) return false; - } sink->protected.public.sink_signal = init_params->sink_signal; - sink->protected.link = core_link; - sink->protected.ctx = core_link->ctx; + sink->protected.link = link; + sink->protected.ctx = link->ctx; sink->protected.public.dongle_max_pix_clk = init_params->dongle_max_pix_clk; sink->protected.public.converter_disable_audio = init_params->converter_disable_audio; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 73712fd6f64a..a329709de360 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -91,7 +91,7 @@ static bool construct(struct core_stream *stream, /* EDID CAP translation for HDMI 2.0 */ stream->public.timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; - stream->status.link = &stream->sink->link->public; + stream->status.link = stream->sink->link; return true; } @@ -355,5 +355,5 @@ void dc_stream_log( dm_logger_write(dm_logger, log_type, "\tlink: %d\n", - core_stream->sink->link->public.link_index); + core_stream->sink->link->link_index); } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index b14bad10db97..e15e8fb1eefe 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -31,6 +31,7 @@ #include "logger_types.h" #include "gpio_types.h" #include "link_service_types.h" +#include "grph_object_ctrl_defs.h" #define MAX_SURFACES 3 #define MAX_STREAMS 6 @@ -141,11 +142,11 @@ struct dc_link_funcs { bool skip_video_pattern); void (*set_preferred_link_settings)(struct dc *dc, struct dc_link_settings *link_setting, - const struct dc_link *link); + struct dc_link *link); void (*enable_hpd)(const struct dc_link *link); void (*disable_hpd)(const struct dc_link *link); void (*set_test_pattern)( - const struct dc_link *link, + struct dc_link *link, enum dp_test_pattern test_pattern, const struct link_training_settings *p_link_settings, const unsigned char *p_custom_pattern, @@ -641,7 +642,7 @@ struct dc_stream_status { /* * link this stream passes through */ - const struct dc_link *link; + struct dc_link *link; }; struct dc_stream_status *dc_stream_get_status( @@ -662,6 +663,50 @@ void dc_release_validate_context(struct validate_context *context); * Link Interfaces ******************************************************************************/ +struct dpcd_caps { + union dpcd_rev dpcd_rev; + union max_lane_count max_ln_count; + union max_down_spread max_down_spread; + + /* dongle type (DP converter, CV smart dongle) */ + enum display_dongle_type dongle_type; + /* Dongle's downstream count. */ + union sink_count sink_count; + /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, + indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ + struct dc_dongle_caps dongle_caps; + + uint32_t sink_dev_id; + uint32_t branch_dev_id; + int8_t branch_dev_name[6]; + int8_t branch_hw_revision; + + bool allow_invalid_MSA_timing_param; + bool panel_mode_edp; +}; + +struct dc_link_status { + struct dpcd_caps *dpcd_caps; +}; + +/* DP MST stream allocation (payload bandwidth number) */ +struct link_mst_stream_allocation { + /* DIG front */ + const struct stream_encoder *stream_enc; + /* associate DRM payload table with DC stream encoder */ + uint8_t vcp_id; + /* number of slots required for the DP stream in transport packet */ + uint8_t slot_count; +}; + +/* DP MST stream allocation table */ +struct link_mst_stream_allocation_table { + /* number of DP video streams */ + int stream_count; + /* array of stream allocations */ + struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM]; +}; + /* * A link contains one or more sinks and their connected status. * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. @@ -699,32 +744,31 @@ struct dc_link { struct ddc_service *ddc; bool aux_mode; -}; -struct dpcd_caps { - union dpcd_rev dpcd_rev; - union max_lane_count max_ln_count; - union max_down_spread max_down_spread; + /* Private to DC core */ - /* dongle type (DP converter, CV smart dongle) */ - enum display_dongle_type dongle_type; - /* Dongle's downstream count. */ - union sink_count sink_count; - /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, - indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ - struct dc_dongle_caps dongle_caps; + const struct core_dc *dc; - uint32_t sink_dev_id; - uint32_t branch_dev_id; - int8_t branch_dev_name[6]; - int8_t branch_hw_revision; + struct dc_context *ctx; - bool allow_invalid_MSA_timing_param; - bool panel_mode_edp; -}; + struct link_encoder *link_enc; + struct graphics_object_id link_id; + union ddi_channel_mapping ddi_channel_mapping; + struct connector_device_tag_info device_tag; + struct dpcd_caps dpcd_caps; + unsigned int dpcd_sink_count; + + enum edp_revision edp_revision; + bool psr_enabled; + + /* MST record stream using this link */ + struct link_flags { + bool dp_keep_receiver_powered; + } wa_flags; + struct link_mst_stream_allocation_table mst_stream_alloc_table; + + struct dc_link_status link_status; -struct dc_link_status { - struct dpcd_caps *dpcd_caps; }; const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link); @@ -734,7 +778,7 @@ const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link); * boot time. They cannot be created or destroyed. * Use dc_get_caps() to get number of links. */ -const struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index); +struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index); /* Return id of physical connector represented by a dc_link at link_index.*/ const struct graphics_object_id dc_get_link_id_at_index( @@ -750,7 +794,7 @@ bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable); bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state); -bool dc_link_setup_psr(const struct dc_link *dc_link, +bool dc_link_setup_psr(struct dc_link *dc_link, const struct dc_stream *stream, struct psr_config *psr_config, struct psr_context *psr_context); @@ -760,7 +804,7 @@ bool dc_link_setup_psr(const struct dc_link *dc_link, * true otherwise. True meaning further action is required (status update * and OS notification). */ -bool dc_link_detect(const struct dc_link *dc_link, bool boot); +bool dc_link_detect(struct dc_link *dc_link, bool boot); /* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt). * Return: @@ -768,26 +812,26 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot); * detection. * false - no change in Downstream port status. No further action required * from DM. */ -bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link, +bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, union hpd_irq_data *hpd_irq_dpcd_data); struct dc_sink_init_data; struct dc_sink *dc_link_add_remote_sink( - const struct dc_link *dc_link, + struct dc_link *dc_link, const uint8_t *edid, int len, struct dc_sink_init_data *init_data); void dc_link_remove_remote_sink( - const struct dc_link *link, + struct dc_link *link, const struct dc_sink *sink); /* Used by diagnostics for virtual link at the moment */ -void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink); +void dc_link_set_sink(struct dc_link *link, struct dc_sink *sink); void dc_link_dp_set_drive_settings( - const struct dc_link *link, + struct dc_link *link, struct link_training_settings *lt_settings); enum link_training_result dc_link_dp_perform_link_training( @@ -800,7 +844,7 @@ void dc_link_dp_enable_hpd(const struct dc_link *link); void dc_link_dp_disable_hpd(const struct dc_link *link); bool dc_link_dp_set_test_pattern( - const struct dc_link *link, + struct dc_link *link, enum dp_test_pattern test_pattern, const struct link_training_settings *p_link_settings, const unsigned char *p_custom_pattern, @@ -844,7 +888,7 @@ const struct audio **dc_get_audios(struct dc *dc); struct dc_sink_init_data { enum signal_type sink_signal; - const struct dc_link *link; + struct dc_link *link; uint32_t dongle_max_pix_clk; bool converter_disable_audio; }; diff --git a/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h b/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h index b143fe88f49f..e1affeb5cc51 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h @@ -105,7 +105,7 @@ struct ddc_service { enum ddc_transaction_type transaction_type; enum display_dongle_type dongle_type; struct dc_context *ctx; - struct core_link *link; + struct dc_link *link; uint32_t address; uint32_t edid_buf_len; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c index 0fe3ee8e29d3..aaff946a6d0a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c @@ -142,7 +142,7 @@ static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable) } static void dce_dmcu_setup_psr(struct dmcu *dmcu, - struct core_link *link, + struct dc_link *link, struct psr_context *psr_context) { struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); @@ -382,7 +382,7 @@ static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable) } static void dcn10_dmcu_setup_psr(struct dmcu *dmcu, - struct core_link *link, + struct dc_link *link, struct psr_context *psr_context) { struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index 5663d3dbd7d5..318673da189b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -1020,7 +1020,7 @@ bool dce110_link_encoder_validate_output_with_stream( case SIGNAL_TYPE_DVI_DUAL_LINK: is_valid = dce110_link_encoder_validate_dvi_output( enc110, - stream->sink->link->public.connector_signal, + stream->sink->link->connector_signal, pipe_ctx->stream->signal, &stream->public.timing); break; diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 716f664f40ce..6938158bed7f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -661,7 +661,7 @@ static enum dc_status validate_mapped_resource( for (i = 0; i < context->stream_count; i++) { struct core_stream *stream = context->streams[i]; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index cf6bf2098b7c..fe8084e290a3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -700,10 +700,10 @@ void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) void dce110_enable_stream(struct pipe_ctx *pipe_ctx) { enum dc_lane_count lane_count = - pipe_ctx->stream->sink->link->public.cur_link_settings.lane_count; + pipe_ctx->stream->sink->link->cur_link_settings.lane_count; struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing; - struct core_link *link = pipe_ctx->stream->sink->link; + struct dc_link *link = pipe_ctx->stream->sink->link; /* 1. update AVI info frame (HDMI, DP) * we always need to update info frame @@ -746,7 +746,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) void dce110_disable_stream(struct pipe_ctx *pipe_ctx) { struct core_stream *stream = pipe_ctx->stream; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; if (pipe_ctx->audio) { pipe_ctx->audio->funcs->az_disable(pipe_ctx->audio); @@ -1111,7 +1111,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( dce110_update_info_frame(pipe_ctx); if (dc_is_dp_signal(pipe_ctx->stream->signal)) dce110_unblank_stream(pipe_ctx, - &stream->sink->link->public.cur_link_settings); + &stream->sink->link->cur_link_settings); } pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; @@ -2220,7 +2220,7 @@ static void init_hw(struct core_dc *dc) /* Power up AND update implementation according to the * required signal (which may be different from the * default signal on connector). */ - struct core_link *link = dc->links[i]; + struct dc_link *link = dc->links[i]; link->link_enc->funcs->hw_init(link->link_enc); } @@ -2283,11 +2283,11 @@ void dce110_fill_display_configs( cfg->transmitter = stream->sink->link->link_enc->transmitter; cfg->link_settings.lane_count = - stream->sink->link->public.cur_link_settings.lane_count; + stream->sink->link->cur_link_settings.lane_count; cfg->link_settings.link_rate = - stream->sink->link->public.cur_link_settings.link_rate; + stream->sink->link->cur_link_settings.link_rate; cfg->link_settings.link_spread = - stream->sink->link->public.cur_link_settings.link_spread; + stream->sink->link->cur_link_settings.link_spread; cfg->sym_clock = stream->phy_pix_clk; /* Round v_refresh*/ cfg->v_refresh = stream->public.timing.pix_clk_khz * 1000; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 0fcb1cf4b4ce..015306a6ef88 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -781,7 +781,7 @@ static enum dc_status validate_mapped_resource( for (i = 0; i < context->stream_count; i++) { struct core_stream *stream = context->streams[i]; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 80f067343a91..ca1e13e2a3db 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -730,7 +730,7 @@ static enum dc_status validate_mapped_resource( for (i = 0; i < context->stream_count; i++) { struct core_stream *stream = context->streams[i]; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 5861b3fdf7d2..b2319dbf3be3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -677,7 +677,7 @@ static enum dc_status validate_mapped_resource( for (i = 0; i < context->stream_count; i++) { struct core_stream *stream = context->streams[i]; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 4390023ca6dc..c25a39214111 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -628,7 +628,7 @@ static void dcn10_init_hw(struct core_dc *dc) * required signal (which may be different from the * default signal on connector). */ - struct core_link *link = dc->links[i]; + struct dc_link *link = dc->links[i]; link->link_enc->funcs->hw_init(link->link_enc); } @@ -2259,7 +2259,7 @@ static void dcn10_config_stereo_parameters( timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA || timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) { enum display_dongle_type dongle = \ - stream->sink->link->public.ddc->dongle_type; + stream->sink->link->ddc->dongle_type; if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER || dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER || dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index eec0d5b22a9f..0110a431e289 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -845,7 +845,7 @@ static enum dc_status validate_mapped_resource( for (i = 0; i < context->stream_count; i++) { struct core_stream *stream = context->streams[i]; - struct core_link *link = stream->sink->link; + struct dc_link *link = stream->sink->link; if (old_context && resource_is_stream_unchanged(old_context, stream)) { if (stream != NULL && old_context->streams[i] != NULL) { diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h index 785236a44aee..1ecb54603e17 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h @@ -20,7 +20,7 @@ struct core_dc { struct dc_context *ctx; uint8_t link_count; - struct core_link *links[MAX_PIPES * 2]; + struct dc_link *links[MAX_PIPES * 2]; struct validate_context *current_context; struct resource_pool *res_pool; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 07a1aec5a28b..6cdfeeba0faf 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -92,13 +92,11 @@ struct core_sink { /** The 'protected' area - read/write access, for use only inside DC **/ /* not used for now */ - struct core_link *link; + struct dc_link *link; struct dc_context *ctx; }; /************ link *****************/ -#define DC_LINK_TO_CORE(dc_link) container_of(dc_link, struct core_link, public) - struct link_init_data { const struct core_dc *dc; struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ @@ -107,61 +105,15 @@ struct link_init_data { TODO: remove it when DC is complete. */ }; -/* DP MST stream allocation (payload bandwidth number) */ -struct link_mst_stream_allocation { - /* DIG front */ - const struct stream_encoder *stream_enc; - /* associate DRM payload table with DC stream encoder */ - uint8_t vcp_id; - /* number of slots required for the DP stream in transport packet */ - uint8_t slot_count; -}; - -/* DP MST stream allocation table */ -struct link_mst_stream_allocation_table { - /* number of DP video streams */ - int stream_count; - /* array of stream allocations */ - struct link_mst_stream_allocation - stream_allocations[MAX_CONTROLLER_NUM]; -}; - -struct core_link { - struct dc_link public; - const struct core_dc *dc; - - struct dc_context *ctx; /* TODO: AUTO remove 'dal' when DC is complete*/ - - struct link_encoder *link_enc; - struct graphics_object_id link_id; - union ddi_channel_mapping ddi_channel_mapping; - struct connector_device_tag_info device_tag; - struct dpcd_caps dpcd_caps; - unsigned int dpcd_sink_count; - - enum edp_revision edp_revision; - bool psr_enabled; - - /* MST record stream using this link */ - struct link_flags { - bool dp_keep_receiver_powered; - } wa_flags; - struct link_mst_stream_allocation_table mst_stream_alloc_table; - - struct dc_link_status link_status; -}; - -#define DC_LINK_TO_LINK(dc_link) container_of(dc_link, struct core_link, public) - -struct core_link *link_create(const struct link_init_data *init_params); -void link_destroy(struct core_link **link); +struct dc_link *link_create(const struct link_init_data *init_params); +void link_destroy(struct dc_link **link); enum dc_status dc_link_validate_mode_timing( const struct core_stream *stream, - struct core_link *link, + struct dc_link *link, const struct dc_crtc_timing *timing); -void core_link_resume(struct core_link *link); +void core_link_resume(struct dc_link *link); void core_link_enable_stream(struct pipe_ctx *pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h index 9c2f670c3dc3..af7ea5eaf185 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h @@ -84,7 +84,7 @@ void dal_ddc_aux_payloads_add( struct ddc_service_init_data { struct graphics_object_id id; struct dc_context *ctx; - struct core_link *link; + struct dc_link *link; }; struct ddc_service *dal_ddc_service_create( diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h index b6ef1bfd267c..d9af028a39df 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h @@ -29,12 +29,12 @@ #define LINK_TRAINING_ATTEMPTS 4 #define LINK_TRAINING_RETRY_DELAY 50 /* ms */ -struct core_link; +struct dc_link; struct core_stream; struct dc_link_settings; bool dp_hbr_verify_link_cap( - struct core_link *link, + struct dc_link *link, struct dc_link_settings *known_limit_link_setting); bool decide_fallback_link_setting(struct dc_link_settings link_setting_init, @@ -46,7 +46,7 @@ struct dc_link_settings get_common_supported_link_settings ( struct dc_link_settings link_setting_b); bool dp_validate_mode_timing( - struct core_link *link, + struct dc_link *link, const struct dc_crtc_timing *timing); void decide_link_settings( @@ -54,17 +54,17 @@ void decide_link_settings( struct dc_link_settings *link_setting); bool perform_link_training_with_retries( - struct core_link *link, + struct dc_link *link, const struct dc_link_settings *link_setting, bool skip_video_pattern, int attempts); -bool is_mst_supported(struct core_link *link); +bool is_mst_supported(struct dc_link *link); -void detect_dp_sink_caps(struct core_link *link); +void detect_dp_sink_caps(struct dc_link *link); -bool is_dp_active_dongle(const struct core_link *link); +bool is_dp_active_dongle(const struct dc_link *link); -void dp_enable_mst_on_sink(struct core_link *link, bool enable); +void dp_enable_mst_on_sink(struct dc_link *link, bool enable); #endif /* __DC_LINK_DP_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h index 6067f464d805..e34b25939a98 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h @@ -39,7 +39,7 @@ struct dmcu_funcs { unsigned int bytes); void (*set_psr_enable)(struct dmcu *dmcu, bool enable); void (*setup_psr)(struct dmcu *dmcu, - struct core_link *link, + struct dc_link *link, struct psr_context *psr_context); void (*get_psr_state)(struct dmcu *dmcu, uint32_t *psr_state); void (*set_psr_wait_loop)(struct dmcu *dmcu, diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h index 75d10e93b002..f7994cfc850d 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h +++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h @@ -29,46 +29,46 @@ #include "inc/core_status.h" enum dc_status core_link_read_dpcd( - struct core_link* link, + struct dc_link *link, uint32_t address, uint8_t *data, uint32_t size); enum dc_status core_link_write_dpcd( - struct core_link* link, + struct dc_link *link, uint32_t address, const uint8_t *data, uint32_t size); void dp_enable_link_phy( - struct core_link *link, + struct dc_link *link, enum signal_type signal, enum clock_source_id clock_source, const struct dc_link_settings *link_settings); -void dp_receiver_power_ctrl(struct core_link *link, bool on); +void dp_receiver_power_ctrl(struct dc_link *link, bool on); -void dp_disable_link_phy(struct core_link *link, enum signal_type signal); +void dp_disable_link_phy(struct dc_link *link, enum signal_type signal); -void dp_disable_link_phy_mst(struct core_link *link, enum signal_type signal); +void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal); bool dp_set_hw_training_pattern( - struct core_link *link, + struct dc_link *link, enum hw_dp_training_pattern pattern); void dp_set_hw_lane_settings( - struct core_link *link, + struct dc_link *link, const struct link_training_settings *link_settings); void dp_set_hw_test_pattern( - struct core_link *link, + struct dc_link *link, enum dp_test_pattern test_pattern, uint8_t *custom_pattern, uint32_t custom_pattern_size); -enum dp_panel_mode dp_get_panel_mode(struct core_link *link); +enum dp_panel_mode dp_get_panel_mode(struct dc_link *link); -void dp_retrain_link_dp_test(struct core_link *link, +void dp_retrain_link_dp_test(struct dc_link *link, struct dc_link_settings *link_setting, bool skip_video_pattern); diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index 6e6fd4e8fc00..3adf3cfc7aba 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -140,19 +140,19 @@ void context_clock_trace( */ #define CONN_DATA_DETECT(link, hex_data, hex_len, ...) \ - dc_conn_log(link->ctx, &link->public, hex_data, hex_len, \ + dc_conn_log(link->ctx, link, hex_data, hex_len, \ LOG_EVENT_DETECTION, ##__VA_ARGS__) #define CONN_DATA_LINK_LOSS(link, hex_data, hex_len, ...) \ - dc_conn_log(link->ctx, &link->public, hex_data, hex_len, \ + dc_conn_log(link->ctx, link, hex_data, hex_len, \ LOG_EVENT_LINK_LOSS, ##__VA_ARGS__) #define CONN_MSG_LT(link, ...) \ - dc_conn_log(link->ctx, &link->public, NULL, 0, \ + dc_conn_log(link->ctx, link, NULL, 0, \ LOG_EVENT_LINK_TRAINING, ##__VA_ARGS__) #define CONN_MSG_MODE(link, ...) \ - dc_conn_log(link->ctx, &link->public, NULL, 0, \ + dc_conn_log(link->ctx, link, NULL, 0, \ LOG_EVENT_MODE_SET, ##__VA_ARGS__) #endif /* __DAL_LOGGER_INTERFACE_H__ */ -- cgit v1.2.3 From 2248eb6b4f1fdd7aded987d178a95b021d3a1d91 Mon Sep 17 00:00:00 2001 From: Tony Cheng Date: Tue, 25 Jul 2017 22:52:45 -0400 Subject: drm/amd/display: log HUBP using DTN logging also simplify DTN INFO. all we need is a way to have DC log register states some where we can compare with golden. going through connectivity is overkill. Signed-off-by: Tony Cheng Reviewed-by: Yongqiang Sun Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 9 ++++ .../gpu/drm/amd/display/dc/basics/log_helpers.c | 28 ------------ drivers/gpu/drm/amd/display/dc/basics/logger.c | 3 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 53 +++++++++++++++++++--- .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 34 ++++++++++++++ .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 18 ++++++++ drivers/gpu/drm/amd/display/dc/dm_helpers.h | 6 --- drivers/gpu/drm/amd/display/dc/dm_services.h | 12 +++++ .../gpu/drm/amd/display/include/logger_interface.h | 24 +++++----- 9 files changed, 133 insertions(+), 54 deletions(-) (limited to 'drivers/gpu/drm/amd/display/include/logger_interface.h') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index df4d221e46c1..6c19a07709df 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -327,6 +327,15 @@ bool dm_helpers_dc_conn_log(struct dc_context *ctx, struct log_entry *entry, enu return true; } +void dm_dtn_log_begin(struct dc_context *ctx) +{} + +void dm_dtn_log_append_v(struct dc_context *ctx, + const char *pMsg, ...) +{} + +void dm_dtn_log_end(struct dc_context *ctx) +{} bool dm_helpers_dp_mst_start_top_mgr( struct dc_context *ctx, diff --git a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c index 070ae6f680e1..785b943b60ed 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c @@ -100,31 +100,3 @@ void dc_conn_log(struct dc_context *ctx, va_end(args); } - -void dc_raw_log(struct dc_context *ctx, - enum dc_log_type event, - const char *msg, - ...) -{ - va_list args; - struct log_entry entry = { 0 }; - - dm_logger_open(ctx->logger, &entry, event); - - va_start(args, msg); - entry.buf_offset += dm_log_to_buffer( - &entry.buf[entry.buf_offset], - LOG_MAX_LINE_SIZE - entry.buf_offset, - msg, args); - - if (entry.buf[strlen(entry.buf) - 1] == '\n') { - entry.buf[strlen(entry.buf) - 1] = '\0'; - entry.buf_offset--; - } - - dm_logger_append(&entry, "^\n"); - dm_helpers_dc_conn_log(ctx, &entry, event); - dm_logger_close(&entry); - - va_end(args); -} diff --git a/drivers/gpu/drm/amd/display/dc/basics/logger.c b/drivers/gpu/drm/amd/display/dc/basics/logger.c index dfd23783cc47..0b17374b1535 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/logger.c +++ b/drivers/gpu/drm/amd/display/dc/basics/logger.c @@ -428,8 +428,7 @@ void dm_logger_open( logger->open_count++; - if (log_type != LOG_DTN) - log_heading(entry); + log_heading(entry); } void dm_logger_close(struct log_entry *entry) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 03f404808a1c..e738387d8ba3 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -31,9 +31,9 @@ #include "dce110/dce110_hw_sequencer.h" #include "dce/dce_hwseq.h" #include "abm.h" +#include "dcn10/dcn10_mem_input.h" #include "dcn10/dcn10_dpp.h" #include "dcn10/dcn10_mpc.h" -#include "mem_input.h" #include "timing_generator.h" #include "opp.h" #include "ipp.h" @@ -2402,22 +2402,61 @@ static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc) return; } -static void dcn10_log_hw_state(struct core_dc *dc) + +static void log_mpc_crc(struct core_dc *dc) { struct dc_context *dc_ctx = dc->ctx; struct dce_hwseq *hws = dc->hwseq; - DTN_INFO("Hello World"); - if (REG(MPC_CRC_RESULT_GB)) DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n", REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR)); if (REG(DPP_TOP0_DPP_CRC_VAL_B_A)) DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n", REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G)); - /* todo: add meaningful register reads and print out HW state - * - */ +} + +static void dcn10_log_hw_state(struct core_dc *dc) +{ + struct dc_context *dc_ctx = dc->ctx; + struct resource_pool *pool = dc->res_pool; + int i; + + DTN_INFO_BEGIN(); + + DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t rotation \t" + "mirror \t sw_mode \t dcc_en \t blank_en \t ttu_dis \t" + "min_ttu_vblank \t qos_low_wm \t qos_high_wm \n"); + + for (i = 0; i < pool->pipe_count; i++) { + struct mem_input *mi = pool->mis[i]; + struct dcn_hubp_state s; + + dcn10_mem_input_read_state(TO_DCN10_MEM_INPUT(mi), &s); + + DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t %xh \t %xh \t " + "%d \t %d \t %d \t %d \t" + "%d \t %d \t %d \n", + i, + s.pixel_format, + s.inuse_addr_hi, + s.viewport_width, + s.viewport_height, + s.rotation_angle, + s.h_mirror_en, + s.sw_mode, + s.dcc_en, + s.blank_en, + s.ttu_disable, + s.min_ttu_vblank, + s.qos_level_low_wm, + s.qos_level_high_wm); + } + DTN_INFO("\n"); + + log_mpc_crc(dc); + + DTN_INFO_END(); } static void dcn10_wait_for_mpcc_disconnect( diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c index c56a69b5a4d7..6f01db6a51dd 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c @@ -804,6 +804,40 @@ static void min_set_viewport( PRI_VIEWPORT_Y_START_C, viewport_c->y); } +void dcn10_mem_input_read_state(struct dcn10_mem_input *mi, + struct dcn_hubp_state *s) +{ + REG_GET(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, &s->pixel_format); + + REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, + SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); + + REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, + PRI_VIEWPORT_WIDTH, &s->viewport_width, + PRI_VIEWPORT_HEIGHT, &s->viewport_height); + + REG_GET_2(DCSURF_SURFACE_CONFIG, + ROTATION_ANGLE, &s->rotation_angle, + H_MIRROR_EN, &s->h_mirror_en); + + REG_GET(DCSURF_TILING_CONFIG, + SW_MODE, &s->sw_mode); + + REG_GET(DCSURF_SURFACE_CONTROL, + PRIMARY_SURFACE_DCC_EN, &s->dcc_en); + + REG_GET_2(DCHUBP_CNTL, + HUBP_BLANK_EN, &s->blank_en, + HUBP_TTU_DISABLE, &s->ttu_disable); + + REG_GET(DCN_GLOBAL_TTU_CNTL, + MIN_TTU_VBLANK, &s->min_ttu_vblank); + + REG_GET_2(DCN_TTU_QOS_WM, + QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, + QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); +} static struct mem_input_funcs dcn10_mem_input_funcs = { .mem_input_program_display_marks = min10_program_display_marks, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h index 9130f5e0ab03..4f4e2c0708d5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h @@ -579,4 +579,22 @@ bool dcn10_mem_input_construct( const struct dcn_mi_shift *mi_shift, const struct dcn_mi_mask *mi_mask); +struct dcn_hubp_state { + uint32_t pixel_format; + uint32_t inuse_addr_hi; + uint32_t viewport_width; + uint32_t viewport_height; + uint32_t rotation_angle; + uint32_t h_mirror_en; + uint32_t sw_mode; + uint32_t dcc_en; + uint32_t blank_en; + uint32_t ttu_disable; + uint32_t min_ttu_vblank; + uint32_t qos_level_low_wm; + uint32_t qos_level_high_wm; +}; +void dcn10_mem_input_read_state(struct dcn10_mem_input *mi, + struct dcn_hubp_state *s); + #endif diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h index a831421c7ea0..e8bd501feb48 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h +++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h @@ -68,15 +68,9 @@ bool dm_helpers_dp_mst_start_top_mgr( const struct dc_link *link, bool boot); -bool dm_helpers_dc_conn_log( - struct dc_context*ctx, - struct log_entry *entry, - enum dc_log_type event); - void dm_helpers_dp_mst_stop_top_mgr( struct dc_context *ctx, const struct dc_link *link); - /** * OS specific aux read callback. */ diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index ea494a71a80b..e9bf4c417cc7 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -463,4 +463,16 @@ bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id); #define dm_log_to_buffer(buffer, size, fmt, args)\ vsnprintf(buffer, size, fmt, args) +/* + * Debug and verification hooks + */ +bool dm_helpers_dc_conn_log( + struct dc_context *ctx, + struct log_entry *entry, + enum dc_log_type event); + +void dm_dtn_log_begin(struct dc_context *ctx); +void dm_dtn_log_append_v(struct dc_context *ctx, const char *msg, ...); +void dm_dtn_log_end(struct dc_context *ctx); + #endif /* __DM_SERVICES_H__ */ diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index 3adf3cfc7aba..0a872472ecba 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -70,11 +70,6 @@ void dc_conn_log(struct dc_context *ctx, const char *msg, ...); -void dc_raw_log(struct dc_context *ctx, - enum dc_log_type event, - const char *msg, - ...); - void logger_write(struct dal_logger *logger, enum dc_log_type log_type, const char *msg, @@ -121,16 +116,11 @@ void context_clock_trace( #define DC_ERROR(...) \ dm_logger_write(dc_ctx->logger, LOG_ERROR, \ - __VA_ARGS__); - -#define DTN_INFO(...) \ - dc_raw_log(dc_ctx, LOG_DTN, \ __VA_ARGS__) #define DC_SYNC_INFO(...) \ dm_logger_write(dc_ctx->logger, LOG_SYNC, \ - __VA_ARGS__); - + __VA_ARGS__) /* Connectivity log format: * [time stamp] [drm] [Major_minor] [connector name] message..... @@ -155,4 +145,16 @@ void context_clock_trace( dc_conn_log(link->ctx, link, NULL, 0, \ LOG_EVENT_MODE_SET, ##__VA_ARGS__) +/* + * Display Test Next logging + */ +#define DTN_INFO_BEGIN() \ + dm_dtn_log_begin(dc_ctx) + +#define DTN_INFO(msg, ...) \ + dm_dtn_log_append_v(dc_ctx, msg, ##__VA_ARGS__) + +#define DTN_INFO_END() \ + dm_dtn_log_end(dc_ctx) + #endif /* __DAL_LOGGER_INTERFACE_H__ */ -- cgit v1.2.3 From c9614aeb12f80fa7a787e608d75b707175997edd Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 27 Jul 2017 09:24:04 -0400 Subject: drm/amd/display: Rename dc_surface to dc_plane_state find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_surface/struct dc_plane_state/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_plane_state_update/struct dc_surface_update/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_plane_state_status/struct dc_surface_status/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_plane_state_dcc_cap/struct dc_surface_dcc_cap/g' Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 +++++++++--------- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4 ++-- drivers/gpu/drm/amd/display/dc/core/dc.c | 18 +++++++++--------- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 4 ++-- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 22 +++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 16 ++++++++-------- drivers/gpu/drm/amd/display/dc/dc.h | 22 +++++++++++----------- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 +- drivers/gpu/drm/amd/display/dc/dc_types.h | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 2 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 6 +++--- .../drm/amd/display/dc/dce100/dce100_resource.h | 2 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 14 +++++++------- .../drm/amd/display/dc/dce112/dce112_resource.c | 2 +- .../drm/amd/display/dc/dce120/dce120_resource.c | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 2 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 14 +++++++------- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 6 +++--- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 ++-- drivers/gpu/drm/amd/display/dc/inc/resource.h | 2 +- .../gpu/drm/amd/display/include/logger_interface.h | 2 +- 22 files changed, 84 insertions(+), 84 deletions(-) (limited to 'drivers/gpu/drm/amd/display/include/logger_interface.h') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7b597a0a2ab9..af6bed907d10 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1819,7 +1819,7 @@ static int dm_crtc_cursor_move(struct drm_crtc *crtc, static bool fill_rects_from_plane_state( const struct drm_plane_state *state, - struct dc_surface *surface) + struct dc_plane_state *surface) { surface->src_rect.x = state->src_x >> 16; surface->src_rect.y = state->src_y >> 16; @@ -1894,7 +1894,7 @@ static int get_fb_info( static int fill_plane_attributes_from_fb( struct amdgpu_device *adev, - struct dc_surface *surface, + struct dc_plane_state *surface, const struct amdgpu_framebuffer *amdgpu_fb, bool addReq) { uint64_t tiling_flags; @@ -2048,7 +2048,7 @@ static int fill_plane_attributes_from_fb( static void fill_gamma_from_crtc_state( const struct drm_crtc_state *crtc_state, - struct dc_surface *dc_surface) + struct dc_plane_state *dc_surface) { int i; struct dc_gamma *gamma; @@ -2072,7 +2072,7 @@ static void fill_gamma_from_crtc_state( static int fill_plane_attributes( struct amdgpu_device *adev, - struct dc_surface *surface, + struct dc_plane_state *surface, struct drm_plane_state *plane_state, struct drm_crtc_state *crtc_state, bool addrReq) @@ -3059,7 +3059,7 @@ static int dm_plane_helper_prepare_fb( if (dm_plane_state_new->surface && dm_plane_state_old->surface != dm_plane_state_new->surface) { - struct dc_surface *surface = dm_plane_state_new->surface; + struct dc_plane_state *surface = dm_plane_state_new->surface; if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { surface->address.grph.addr.low_part = lower_32_bits(afb->address); @@ -3160,7 +3160,7 @@ int dm_plane_atomic_check(struct drm_plane *plane, if (!dm_plane_state->surface) return true; - if (dc_validate_surface(dc, dm_plane_state->surface)) + if (dc_validate_plane(dc, dm_plane_state->surface)) return 0; return -EINVAL; @@ -3926,7 +3926,7 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, struct drm_plane *plane; struct drm_plane_state *old_plane_state; struct dc_stream *dc_stream_attach; - struct dc_surface *dc_surfaces_constructed[MAX_SURFACES]; + struct dc_plane_state *dc_surfaces_constructed[MAX_SURFACES]; struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state); int planes_count = 0; @@ -4377,7 +4377,7 @@ static uint32_t add_val_sets_surface( struct dc_validation_set *val_sets, uint32_t set_count, const struct dc_stream *stream, - struct dc_surface *surface) + struct dc_plane_state *surface) { uint32_t i = 0, j = 0; @@ -4699,7 +4699,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, pflip_needed = !state->allow_modeset; if (!pflip_needed) { - struct dc_surface *surface; + struct dc_plane_state *surface; surface = dc_create_surface(dc); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index ce0223af7d5f..dcf1f77390a8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -189,14 +189,14 @@ struct amdgpu_connector *amdgpu_dm_find_first_crct_matching_connector( struct amdgpu_framebuffer; struct amdgpu_display_manager; struct dc_validation_set; -struct dc_surface; +struct dc_plane_state; /* TODO rename to dc_stream_state */ struct dc_stream; struct dm_plane_state { struct drm_plane_state base; - struct dc_surface *surface; + struct dc_plane_state *surface; }; struct dm_crtc_state { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 5acf4c697ae8..500788c35d70 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -645,7 +645,7 @@ static bool is_validation_required( return true; for (j = 0; j < set[i].surface_count; j++) { - struct dc_surface temp_surf; + struct dc_plane_state temp_surf; memset(&temp_surf, 0, sizeof(temp_surf)); temp_surf = *context->stream_status[i].surfaces[j]; @@ -684,7 +684,7 @@ static bool validate_surfaces( for (i = 0; i < set_count; i++) for (j = 0; j < set[i].surface_count; j++) - if (!dc_validate_surface(dc, set[i].surfaces[j])) + if (!dc_validate_plane(dc, set[i].surfaces[j])) return false; return true; @@ -978,7 +978,7 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c const struct dc_sink *sink = context->streams[i]->sink; for (j = 0; j < context->stream_status[i].surface_count; j++) { - const struct dc_surface *surface = + const struct dc_plane_state *surface = context->stream_status[i].surfaces[j]; core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context); @@ -1136,7 +1136,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) bool dc_commit_surfaces_to_stream( struct dc *dc, - struct dc_surface **new_surfaces, + struct dc_plane_state **new_surfaces, uint8_t new_surface_count, struct dc_stream *dc_stream) { @@ -1220,7 +1220,7 @@ void dc_release_validate_context(struct validate_context *context) static bool is_surface_in_context( const struct validate_context *context, - const struct dc_surface *surface) + const struct dc_plane_state *surface) { int j; @@ -1470,7 +1470,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, update_surface_trace(dc, srf_updates, surface_count); if (update_type >= UPDATE_TYPE_FULL) { - struct dc_surface *new_surfaces[MAX_SURFACES] = {0}; + struct dc_plane_state *new_surfaces[MAX_SURFACES] = {0}; for (i = 0; i < surface_count; i++) new_surfaces[i] = srf_updates[i].surface; @@ -1496,7 +1496,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* save update parameters into surface */ for (i = 0; i < surface_count; i++) { - struct dc_surface *surface = srf_updates[i].surface; + struct dc_plane_state *surface = srf_updates[i].surface; if (srf_updates[i].flip_addr) { surface->address = srf_updates[i].flip_addr->address; @@ -1599,7 +1599,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* Lock pipes for provided surfaces, or all active if full update*/ for (i = 0; i < surface_count; i++) { - struct dc_surface *surface = srf_updates[i].surface; + struct dc_plane_state *surface = srf_updates[i].surface; for (j = 0; j < core_dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; @@ -1649,7 +1649,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* Perform requested Updates */ for (i = 0; i < surface_count; i++) { - struct dc_surface *surface = srf_updates[i].surface; + struct dc_plane_state *surface = srf_updates[i].surface; if (update_type == UPDATE_TYPE_MED) core_dc->hwss.apply_ctx_for_surface( diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index bf127a88e533..e8d4b8c3ac2b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -38,7 +38,7 @@ void pre_surface_trace( const struct dc *dc, - const struct dc_surface *const *surfaces, + const struct dc_plane_state *const *surfaces, int surface_count) { int i; @@ -46,7 +46,7 @@ void pre_surface_trace( struct dal_logger *logger = core_dc->ctx->logger; for (i = 0; i < surface_count; i++) { - const struct dc_surface *surface = surfaces[i]; + const struct dc_plane_state *surface = surfaces[i]; SURFACE_TRACE("Surface %d:\n", i); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 005eac5fae80..fd1d6be79fee 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -430,7 +430,7 @@ static void rect_swap_helper(struct rect *rect) static void calculate_viewport(struct pipe_ctx *pipe_ctx) { - const struct dc_surface *surface = pipe_ctx->surface; + const struct dc_plane_state *surface = pipe_ctx->surface; const struct dc_stream *stream = pipe_ctx->stream; struct scaler_data *data = &pipe_ctx->scl_data; struct rect surf_src = surface->src_rect; @@ -529,7 +529,7 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip) { - const struct dc_surface *surface = pipe_ctx->surface; + const struct dc_plane_state *surface = pipe_ctx->surface; const struct dc_stream *stream = pipe_ctx->stream; struct rect surf_src = surface->src_rect; struct rect surf_clip = surface->clip_rect; @@ -607,7 +607,7 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) { - const struct dc_surface *surface = pipe_ctx->surface; + const struct dc_plane_state *surface = pipe_ctx->surface; const struct dc_stream *stream = pipe_ctx->stream; struct rect surf_src = surface->src_rect; const int in_w = stream->src.width; @@ -814,7 +814,7 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) { - const struct dc_surface *surface = pipe_ctx->surface; + const struct dc_plane_state *surface = pipe_ctx->surface; struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; struct view recout_skip = { 0 }; bool res = false; @@ -1028,7 +1028,7 @@ static int acquire_first_split_pipe( #endif bool resource_attach_surfaces_to_context( - struct dc_surface * const *surfaces, + struct dc_plane_state * const *surfaces, int surface_count, struct dc_stream *stream, struct validate_context *context, @@ -1075,7 +1075,7 @@ bool resource_attach_surfaces_to_context( tail_pipe = NULL; for (i = 0; i < surface_count; i++) { - struct dc_surface *surface = surfaces[i]; + struct dc_plane_state *surface = surfaces[i]; struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream( context, pool, stream); @@ -1351,7 +1351,7 @@ bool resource_is_stream_unchanged( static void copy_pipe_ctx( const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx) { - struct dc_surface *surface = to_pipe_ctx->surface; + struct dc_plane_state *surface = to_pipe_ctx->surface; struct dc_stream *stream = to_pipe_ctx->stream; *to_pipe_ctx = *from_pipe_ctx; @@ -2055,7 +2055,7 @@ static void set_spd_info_packet( static void set_hdr_static_info_packet( struct encoder_info_packet *info_packet, - struct dc_surface *surface, + struct dc_plane_state *surface, struct dc_stream *stream) { uint16_t i = 0; @@ -2534,13 +2534,13 @@ bool dc_validate_stream(const struct dc *dc, struct dc_stream *stream) return res == DC_OK; } -bool dc_validate_surface(const struct dc *dc, const struct dc_surface *surface) +bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_state) { struct core_dc *core_dc = DC_TO_CORE(dc); /* TODO For now validates pixel format only */ - if (core_dc->res_pool->funcs->validate_surface) - return core_dc->res_pool->funcs->validate_surface(surface) == DC_OK; + if (core_dc->res_pool->funcs->validate_plane) + return core_dc->res_pool->funcs->validate_plane(plane_state) == DC_OK; return true; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index eded6b7da97d..941b3671375d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -34,7 +34,7 @@ /******************************************************************************* * Private functions ******************************************************************************/ -static bool construct(struct dc_context *ctx, struct dc_surface *surface) +static bool construct(struct dc_context *ctx, struct dc_plane_state *surface) { surface->ctx = ctx; memset(&surface->hdr_static_ctx, @@ -42,7 +42,7 @@ static bool construct(struct dc_context *ctx, struct dc_surface *surface) return true; } -static void destruct(struct dc_surface *surface) +static void destruct(struct dc_plane_state *surface) { if (surface->gamma_correction != NULL) { dc_gamma_release(&surface->gamma_correction); @@ -57,18 +57,18 @@ static void destruct(struct dc_surface *surface) /******************************************************************************* * Public functions ******************************************************************************/ -void enable_surface_flip_reporting(struct dc_surface *surface, +void enable_surface_flip_reporting(struct dc_plane_state *surface, uint32_t controller_id) { surface->irq_source = controller_id + DC_IRQ_SOURCE_PFLIP1 - 1; /*register_flip_interrupt(surface);*/ } -struct dc_surface *dc_create_surface(const struct dc *dc) +struct dc_plane_state *dc_create_surface(const struct dc *dc) { struct core_dc *core_dc = DC_TO_CORE(dc); - struct dc_surface *surface = dm_alloc(sizeof(*surface)); + struct dc_plane_state *surface = dm_alloc(sizeof(*surface)); if (NULL == surface) goto alloc_fail; @@ -88,7 +88,7 @@ alloc_fail: } const struct dc_surface_status *dc_surface_get_status( - const struct dc_surface *dc_surface) + const struct dc_plane_state *dc_surface) { const struct dc_surface_status *surface_status; struct core_dc *core_dc; @@ -120,13 +120,13 @@ const struct dc_surface_status *dc_surface_get_status( return surface_status; } -void dc_surface_retain(struct dc_surface *surface) +void dc_surface_retain(struct dc_plane_state *surface) { ASSERT(surface->ref_count > 0); ++surface->ref_count; } -void dc_surface_release(struct dc_surface *surface) +void dc_surface_release(struct dc_plane_state *surface) { ASSERT(surface->ref_count > 0); --surface->ref_count; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d03218d6210a..d1943b9644d4 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -92,7 +92,7 @@ struct dc_static_screen_events { /* Forward declaration*/ struct dc; -struct dc_surface; +struct dc_plane_state; struct validate_context; struct dc_cap_funcs { @@ -310,7 +310,7 @@ struct dc_surface_status { bool is_right_eye; }; -struct dc_surface { +struct dc_plane_state { struct dc_plane_address address; struct scaling_taps scaling_quality; @@ -367,7 +367,7 @@ struct dc_scaling_info { }; struct dc_surface_update { - struct dc_surface *surface; + struct dc_plane_state *surface; /* isr safe update parameters. null means no updates */ struct dc_flip_addrs *flip_addr; @@ -385,12 +385,12 @@ struct dc_surface_update { /* * Create a new surface with default parameters; */ -struct dc_surface *dc_create_surface(const struct dc *dc); +struct dc_plane_state *dc_create_surface(const struct dc *dc); const struct dc_surface_status *dc_surface_get_status( - const struct dc_surface *dc_surface); + const struct dc_plane_state *dc_surface); -void dc_surface_retain(struct dc_surface *dc_surface); -void dc_surface_release(struct dc_surface *dc_surface); +void dc_surface_retain(struct dc_plane_state *dc_surface); +void dc_surface_release(struct dc_plane_state *dc_surface); void dc_gamma_retain(struct dc_gamma *dc_gamma); void dc_gamma_release(struct dc_gamma **dc_gamma); @@ -424,7 +424,7 @@ struct dc_flip_addrs { bool dc_commit_surfaces_to_stream( struct dc *dc, - struct dc_surface **dc_surfaces, + struct dc_plane_state **dc_surfaces, uint8_t surface_count, struct dc_stream *stream); @@ -470,7 +470,7 @@ enum surface_update_type { struct dc_stream_status { int primary_otg_inst; int surface_count; - struct dc_surface *surfaces[MAX_SURFACE_NUM]; + struct dc_plane_state *surfaces[MAX_SURFACE_NUM]; /* * link this stream passes through @@ -582,13 +582,13 @@ bool dc_stream_get_scanoutpos(const struct dc_stream *stream, */ struct dc_validation_set { struct dc_stream *stream; - struct dc_surface *surfaces[MAX_SURFACES]; + struct dc_plane_state *surfaces[MAX_SURFACES]; uint8_t surface_count; }; bool dc_validate_stream(const struct dc *dc, struct dc_stream *stream); -bool dc_validate_surface(const struct dc *dc, const struct dc_surface *surface); +bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_state); /* * This function takes a set of resources and checks that they are cofunctional. * diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 4c5e797da5b1..3c0b47373dfb 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -528,7 +528,7 @@ enum dc_quantization_range { /* XFM */ -/* used in struct dc_surface */ +/* used in struct dc_plane_state */ struct scaling_taps { uint32_t v_taps; uint32_t h_taps; diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index ee9e6bc88c32..4fb9584452a4 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -34,7 +34,7 @@ #include "grph_object_defs.h" /* forward declarations */ -struct dc_surface; +struct dc_plane_state; struct dc_stream; struct dc_link; struct dc_sink; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c index c46b3e82cdcc..af59ab93796a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c @@ -197,7 +197,7 @@ void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, } /* Only use LUT for 8 bit formats */ -bool dce_use_lut(const struct dc_surface *surface) +bool dce_use_lut(const struct dc_plane_state *surface) { switch (surface->format) { case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index ade7507e99c7..d5cb98a92c53 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -552,5 +552,5 @@ void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, struct clock_source *clk_src, unsigned int tg_inst); -bool dce_use_lut(const struct dc_surface *surface); +bool dce_use_lut(const struct dc_plane_state *surface); #endif /*__DCE_HWSEQ_H__*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 59f4caf057f7..2cf2fefc3d79 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -804,10 +804,10 @@ static void dce100_destroy_resource_pool(struct resource_pool **pool) *pool = NULL; } -enum dc_status dce100_validate_surface(const struct dc_surface *surface) +enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state) { - if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) + if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return DC_OK; return DC_FAIL_SURFACE_VALIDATE; @@ -819,7 +819,7 @@ static const struct resource_funcs dce100_res_pool_funcs = { .validate_with_context = dce100_validate_with_context, .validate_guaranteed = dce100_validate_guaranteed, .validate_bandwidth = dce100_validate_bandwidth, - .validate_surface = dce100_validate_surface, + .validate_plane = dce100_validate_plane, }; static bool construct( diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h index 13fc637eb731..edc50caf04d1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h @@ -16,6 +16,6 @@ struct resource_pool *dce100_create_resource_pool( uint8_t num_virtual_links, struct core_dc *dc); -enum dc_status dce100_validate_surface(const struct dc_surface *surface); +enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state); #endif /* DCE100_RESOURCE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 1f18fcf52661..84dc8916de96 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -215,7 +215,7 @@ static bool dce110_enable_display_power_gating( } static void build_prescale_params(struct ipp_prescale_params *prescale_params, - const struct dc_surface *surface) + const struct dc_plane_state *surface) { prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; @@ -240,7 +240,7 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params, static bool dce110_set_input_transfer_func( struct pipe_ctx *pipe_ctx, - const struct dc_surface *surface) + const struct dc_plane_state *surface) { struct input_pixel_processor *ipp = pipe_ctx->ipp; const struct dc_transfer_func *tf = NULL; @@ -2038,7 +2038,7 @@ static void set_plane_config( struct resource_context *res_ctx) { struct mem_input *mi = pipe_ctx->mi; - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; struct xfm_grph_csc_adjustment adjust; struct out_csc_color_matrix tbl_entry; unsigned int i; @@ -2123,7 +2123,7 @@ static void set_plane_config( static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ctx) { - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; if (surface == NULL) return; @@ -2138,7 +2138,7 @@ static void update_plane_addr(const struct core_dc *dc, void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) { - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; if (surface == NULL) return; @@ -2490,7 +2490,7 @@ static void dce110_program_front_end_for_pipe( { struct mem_input *mi = pipe_ctx->mi; struct pipe_ctx *old_pipe = NULL; - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; struct xfm_grph_csc_adjustment adjust; struct out_csc_color_matrix tbl_entry; unsigned int i; @@ -2614,7 +2614,7 @@ static void dce110_program_front_end_for_pipe( static void dce110_apply_ctx_for_surface( struct core_dc *dc, - const struct dc_surface *surface, + const struct dc_plane_state *surface, struct validate_context *context) { int i; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 495f38750ae4..c68372fa1292 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -994,7 +994,7 @@ static const struct resource_funcs dce112_res_pool_funcs = { .validate_with_context = dce112_validate_with_context, .validate_guaranteed = dce112_validate_guaranteed, .validate_bandwidth = dce112_validate_bandwidth, - .validate_surface = dce100_validate_surface + .validate_plane = dce100_validate_plane }; static void bw_calcs_data_update_from_pplib(struct core_dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index b31307b9d3e3..45f5fd63ce14 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -701,7 +701,7 @@ static const struct resource_funcs dce120_res_pool_funcs = { .validate_with_context = dce112_validate_with_context, .validate_guaranteed = dce112_validate_guaranteed, .validate_bandwidth = dce112_validate_bandwidth, - .validate_surface = dce100_validate_surface + .validate_plane = dce100_validate_plane }; static void bw_calcs_data_update_from_pplib(struct core_dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 6eeb5e9f656f..bcb66447b558 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -825,7 +825,7 @@ static const struct resource_funcs dce80_res_pool_funcs = { .validate_with_context = dce80_validate_with_context, .validate_guaranteed = dce80_validate_guaranteed, .validate_bandwidth = dce80_validate_bandwidth, - .validate_surface = dce100_validate_surface + .validate_plane = dce100_validate_plane }; static bool construct( diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index fa19c6b92f29..3979cb03cf8d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1038,7 +1038,7 @@ static void reset_hw_ctx_wrap( static bool patch_address_for_sbs_tb_stereo( struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) { - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; bool sec_split = pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface; if (sec_split && surface->address.type == PLN_ADDR_TYPE_GRPH_STEREO && @@ -1065,7 +1065,7 @@ static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ct { bool addr_patched = false; PHYSICAL_ADDRESS_LOC addr; - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; if (surface == NULL) return; @@ -1080,7 +1080,7 @@ static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ct } static bool dcn10_set_input_transfer_func( - struct pipe_ctx *pipe_ctx, const struct dc_surface *surface) + struct pipe_ctx *pipe_ctx, const struct dc_plane_state *surface) { struct input_pixel_processor *ipp = pipe_ctx->ipp; const struct dc_transfer_func *tf = NULL; @@ -1689,7 +1689,7 @@ static void dcn10_power_on_fe( struct pipe_ctx *pipe_ctx, struct validate_context *context) { - struct dc_surface *dc_surface = pipe_ctx->surface; + struct dc_plane_state *dc_surface = pipe_ctx->surface; struct dce_hwseq *hws = dc->hwseq; power_on_plane(dc->hwseq, @@ -1898,7 +1898,7 @@ static void update_dchubp_dpp( struct dce_hwseq *hws = dc->hwseq; struct mem_input *mi = pipe_ctx->mi; struct input_pixel_processor *ipp = pipe_ctx->ipp; - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; union plane_size size = surface->plane_size; struct default_adjustment ocsc = {0}; struct mpcc_cfg mpcc_cfg = {0}; @@ -2068,7 +2068,7 @@ static void dcn10_pplib_apply_display_requirements( static void dcn10_apply_ctx_for_surface( struct core_dc *dc, - const struct dc_surface *surface, + const struct dc_plane_state *surface, struct validate_context *context) { int i, be_idx; @@ -2468,7 +2468,7 @@ static bool dcn10_dummy_display_power_gating( void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) { - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; struct timing_generator *tg = pipe_ctx->tg; if (surface->ctx->dc->debug.sanity_checks) { diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index da52971d3f06..44a87c9427f7 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -36,7 +36,7 @@ #define MAX_CLOCK_SOURCES 7 -void enable_surface_flip_reporting(struct dc_surface *dc_surface, +void enable_surface_flip_reporting(struct dc_plane_state *dc_surface, uint32_t controller_id); #include "grph_object_id.h" @@ -104,7 +104,7 @@ struct resource_funcs { const struct resource_pool *pool, struct dc_stream *stream); - enum dc_status (*validate_surface)(const struct dc_surface *surface); + enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state); }; struct audio_support{ @@ -154,7 +154,7 @@ struct resource_pool { }; struct pipe_ctx { - struct dc_surface *surface; + struct dc_plane_state *surface; struct dc_stream *stream; struct mem_input *mi; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index b2f7ba2115c9..c529ddd2e0d5 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -59,7 +59,7 @@ struct hw_sequencer_funcs { void (*apply_ctx_for_surface)( struct core_dc *dc, - const struct dc_surface *surface, + const struct dc_plane_state *surface, struct validate_context *context); void (*set_plane_config)( @@ -88,7 +88,7 @@ struct hw_sequencer_funcs { bool (*set_input_transfer_func)( struct pipe_ctx *pipe_ctx, - const struct dc_surface *surface); + const struct dc_plane_state *surface); bool (*set_output_transfer_func)( struct pipe_ctx *pipe_ctx, diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index ca3f49379bea..bfd7cfc86df0 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -119,7 +119,7 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( struct dc_stream *stream); bool resource_attach_surfaces_to_context( - struct dc_surface *const *surfaces, + struct dc_plane_state *const *surfaces, int surface_count, struct dc_stream *dc_stream, struct validate_context *context, diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index 0a872472ecba..0e978d921fdf 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -77,7 +77,7 @@ void logger_write(struct dal_logger *logger, void pre_surface_trace( const struct dc *dc, - const struct dc_surface *const *surfaces, + const struct dc_plane_state *const *surfaces, int surface_count); void update_surface_trace( -- cgit v1.2.3 From 3be5262e353b8ab97c528bfc7d0dd3c820e4ba27 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 27 Jul 2017 09:55:38 -0400 Subject: drm/amd/display: Rename more dc_surface stuff to plane_state Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 288 +++++++++++---------- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +- drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 20 +- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 52 ++-- drivers/gpu/drm/amd/display/dc/core/dc.c | 130 +++++----- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 188 +++++++------- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 190 +++++++------- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 8 +- drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 74 +++--- drivers/gpu/drm/amd/display/dc/dc.h | 32 +-- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 4 +- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 2 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 8 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 125 +++++---- .../drm/amd/display/dc/dce110/dce110_resource.c | 20 +- .../drm/amd/display/dc/dce112/dce112_resource.c | 8 +- .../drm/amd/display/dc/dce120/dce120_resource.c | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 8 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 140 +++++----- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 4 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 +- drivers/gpu/drm/amd/display/dc/inc/resource.h | 2 +- .../gpu/drm/amd/display/include/logger_interface.h | 2 +- 24 files changed, 658 insertions(+), 657 deletions(-) (limited to 'drivers/gpu/drm/amd/display/include/logger_interface.h') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 497104a29d89..08567b3631cf 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -70,7 +70,7 @@ #include "i2caux_interface.h" -static enum drm_plane_type dm_surfaces_type_default[AMDGPU_MAX_PLANES] = { +static enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = { DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_PRIMARY, @@ -79,14 +79,14 @@ static enum drm_plane_type dm_surfaces_type_default[AMDGPU_MAX_PLANES] = { DRM_PLANE_TYPE_PRIMARY, }; -static enum drm_plane_type dm_surfaces_type_carizzo[AMDGPU_MAX_PLANES] = { +static enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = { DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */ }; -static enum drm_plane_type dm_surfaces_type_stoney[AMDGPU_MAX_PLANES] = { +static enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = { DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */ @@ -1285,11 +1285,11 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) return -1; } - for (i = 0; i < dm->dc->caps.max_surfaces; i++) { + for (i = 0; i < dm->dc->caps.max_planes; i++) { mode_info->planes[i] = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL); if (!mode_info->planes[i]) { - DRM_ERROR("KMS: Failed to allocate surface\n"); + DRM_ERROR("KMS: Failed to allocate plane\n"); goto fail_free_planes; } mode_info->planes[i]->base.type = mode_info->plane_type[i]; @@ -1389,7 +1389,7 @@ fail_free_encoder: fail_free_connector: kfree(aconnector); fail_free_planes: - for (i = 0; i < dm->dc->caps.max_surfaces; i++) + for (i = 0; i < dm->dc->caps.max_planes; i++) kfree(mode_info->planes[i]); return -1; } @@ -1518,52 +1518,52 @@ static int dm_early_init(void *handle) adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; - adev->mode_info.plane_type = dm_surfaces_type_default; + adev->mode_info.plane_type = dm_plane_type_default; break; case CHIP_FIJI: case CHIP_TONGA: adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 7; - adev->mode_info.plane_type = dm_surfaces_type_default; + adev->mode_info.plane_type = dm_plane_type_default; break; case CHIP_CARRIZO: adev->mode_info.num_crtc = 3; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 9; - adev->mode_info.plane_type = dm_surfaces_type_carizzo; + adev->mode_info.plane_type = dm_plane_type_carizzo; break; case CHIP_STONEY: adev->mode_info.num_crtc = 2; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 9; - adev->mode_info.plane_type = dm_surfaces_type_stoney; + adev->mode_info.plane_type = dm_plane_type_stoney; break; case CHIP_POLARIS11: case CHIP_POLARIS12: adev->mode_info.num_crtc = 5; adev->mode_info.num_hpd = 5; adev->mode_info.num_dig = 5; - adev->mode_info.plane_type = dm_surfaces_type_default; + adev->mode_info.plane_type = dm_plane_type_default; break; case CHIP_POLARIS10: adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; - adev->mode_info.plane_type = dm_surfaces_type_default; + adev->mode_info.plane_type = dm_plane_type_default; break; case CHIP_VEGA10: adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; - adev->mode_info.plane_type = dm_surfaces_type_default; + adev->mode_info.plane_type = dm_plane_type_default; break; #if defined(CONFIG_DRM_AMD_DC_DCN1_0) case CHIP_RAVEN: adev->mode_info.num_crtc = 4; adev->mode_info.num_hpd = 4; adev->mode_info.num_dig = 4; - adev->mode_info.plane_type = dm_surfaces_type_default; + adev->mode_info.plane_type = dm_plane_type_default; break; #endif default: @@ -1821,50 +1821,50 @@ static int dm_crtc_cursor_move(struct drm_crtc *crtc, static bool fill_rects_from_plane_state( const struct drm_plane_state *state, - struct dc_plane_state *surface) + struct dc_plane_state *plane_state) { - surface->src_rect.x = state->src_x >> 16; - surface->src_rect.y = state->src_y >> 16; + plane_state->src_rect.x = state->src_x >> 16; + plane_state->src_rect.y = state->src_y >> 16; /*we ignore for now mantissa and do not to deal with floating pixels :(*/ - surface->src_rect.width = state->src_w >> 16; + plane_state->src_rect.width = state->src_w >> 16; - if (surface->src_rect.width == 0) + if (plane_state->src_rect.width == 0) return false; - surface->src_rect.height = state->src_h >> 16; - if (surface->src_rect.height == 0) + plane_state->src_rect.height = state->src_h >> 16; + if (plane_state->src_rect.height == 0) return false; - surface->dst_rect.x = state->crtc_x; - surface->dst_rect.y = state->crtc_y; + plane_state->dst_rect.x = state->crtc_x; + plane_state->dst_rect.y = state->crtc_y; if (state->crtc_w == 0) return false; - surface->dst_rect.width = state->crtc_w; + plane_state->dst_rect.width = state->crtc_w; if (state->crtc_h == 0) return false; - surface->dst_rect.height = state->crtc_h; + plane_state->dst_rect.height = state->crtc_h; - surface->clip_rect = surface->dst_rect; + plane_state->clip_rect = plane_state->dst_rect; switch (state->rotation & DRM_MODE_ROTATE_MASK) { case DRM_MODE_ROTATE_0: - surface->rotation = ROTATION_ANGLE_0; + plane_state->rotation = ROTATION_ANGLE_0; break; case DRM_MODE_ROTATE_90: - surface->rotation = ROTATION_ANGLE_90; + plane_state->rotation = ROTATION_ANGLE_90; break; case DRM_MODE_ROTATE_180: - surface->rotation = ROTATION_ANGLE_180; + plane_state->rotation = ROTATION_ANGLE_180; break; case DRM_MODE_ROTATE_270: - surface->rotation = ROTATION_ANGLE_270; + plane_state->rotation = ROTATION_ANGLE_270; break; default: - surface->rotation = ROTATION_ANGLE_0; + plane_state->rotation = ROTATION_ANGLE_0; break; } @@ -1896,7 +1896,7 @@ static int get_fb_info( static int fill_plane_attributes_from_fb( struct amdgpu_device *adev, - struct dc_plane_state *surface, + struct dc_plane_state *plane_state, const struct amdgpu_framebuffer *amdgpu_fb, bool addReq) { uint64_t tiling_flags; @@ -1916,28 +1916,28 @@ static int fill_plane_attributes_from_fb( switch (fb->format->format) { case DRM_FORMAT_C8: - surface->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; + plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; break; case DRM_FORMAT_RGB565: - surface->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; + plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; break; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: - surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; + plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; break; case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_ARGB2101010: - surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; + plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; break; case DRM_FORMAT_XBGR2101010: case DRM_FORMAT_ABGR2101010: - surface->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; + plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; break; case DRM_FORMAT_NV21: - surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; + plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; break; case DRM_FORMAT_NV12: - surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; + plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; break; default: DRM_ERROR("Unsupported screen format %s\n", @@ -1945,45 +1945,45 @@ static int fill_plane_attributes_from_fb( return -EINVAL; } - if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { - surface->address.type = PLN_ADDR_TYPE_GRAPHICS; - surface->address.grph.addr.low_part = lower_32_bits(fb_location); - surface->address.grph.addr.high_part = upper_32_bits(fb_location); - surface->plane_size.grph.surface_size.x = 0; - surface->plane_size.grph.surface_size.y = 0; - surface->plane_size.grph.surface_size.width = fb->width; - surface->plane_size.grph.surface_size.height = fb->height; - surface->plane_size.grph.surface_pitch = + if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { + plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS; + plane_state->address.grph.addr.low_part = lower_32_bits(fb_location); + plane_state->address.grph.addr.high_part = upper_32_bits(fb_location); + plane_state->plane_size.grph.surface_size.x = 0; + plane_state->plane_size.grph.surface_size.y = 0; + plane_state->plane_size.grph.surface_size.width = fb->width; + plane_state->plane_size.grph.surface_size.height = fb->height; + plane_state->plane_size.grph.surface_pitch = fb->pitches[0] / fb->format->cpp[0]; /* TODO: unhardcode */ - surface->color_space = COLOR_SPACE_SRGB; + plane_state->color_space = COLOR_SPACE_SRGB; } else { awidth = ALIGN(fb->width, 64); - surface->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; - surface->address.video_progressive.luma_addr.low_part + plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; + plane_state->address.video_progressive.luma_addr.low_part = lower_32_bits(fb_location); - surface->address.video_progressive.chroma_addr.low_part + plane_state->address.video_progressive.chroma_addr.low_part = lower_32_bits(fb_location) + (awidth * fb->height); - surface->plane_size.video.luma_size.x = 0; - surface->plane_size.video.luma_size.y = 0; - surface->plane_size.video.luma_size.width = awidth; - surface->plane_size.video.luma_size.height = fb->height; + plane_state->plane_size.video.luma_size.x = 0; + plane_state->plane_size.video.luma_size.y = 0; + plane_state->plane_size.video.luma_size.width = awidth; + plane_state->plane_size.video.luma_size.height = fb->height; /* TODO: unhardcode */ - surface->plane_size.video.luma_pitch = awidth; + plane_state->plane_size.video.luma_pitch = awidth; - surface->plane_size.video.chroma_size.x = 0; - surface->plane_size.video.chroma_size.y = 0; - surface->plane_size.video.chroma_size.width = awidth; - surface->plane_size.video.chroma_size.height = fb->height; - surface->plane_size.video.chroma_pitch = awidth / 2; + plane_state->plane_size.video.chroma_size.x = 0; + plane_state->plane_size.video.chroma_size.y = 0; + plane_state->plane_size.video.chroma_size.width = awidth; + plane_state->plane_size.video.chroma_size.height = fb->height; + plane_state->plane_size.video.chroma_pitch = awidth / 2; /* TODO: unhardcode */ - surface->color_space = COLOR_SPACE_YCBCR709; + plane_state->color_space = COLOR_SPACE_YCBCR709; } - memset(&surface->tiling_info, 0, sizeof(surface->tiling_info)); + memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info)); /* Fill GFX8 params */ if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { @@ -1996,51 +1996,51 @@ static int fill_plane_attributes_from_fb( num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); /* XXX fix me for VI */ - surface->tiling_info.gfx8.num_banks = num_banks; - surface->tiling_info.gfx8.array_mode = + plane_state->tiling_info.gfx8.num_banks = num_banks; + plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_2D_TILED_THIN1; - surface->tiling_info.gfx8.tile_split = tile_split; - surface->tiling_info.gfx8.bank_width = bankw; - surface->tiling_info.gfx8.bank_height = bankh; - surface->tiling_info.gfx8.tile_aspect = mtaspect; - surface->tiling_info.gfx8.tile_mode = + plane_state->tiling_info.gfx8.tile_split = tile_split; + plane_state->tiling_info.gfx8.bank_width = bankw; + plane_state->tiling_info.gfx8.bank_height = bankh; + plane_state->tiling_info.gfx8.tile_aspect = mtaspect; + plane_state->tiling_info.gfx8.tile_mode = DC_ADDR_SURF_MICRO_TILING_DISPLAY; } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_1D_TILED_THIN1) { - surface->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; + plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; } - surface->tiling_info.gfx8.pipe_config = + plane_state->tiling_info.gfx8.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); if (adev->asic_type == CHIP_VEGA10 || adev->asic_type == CHIP_RAVEN) { /* Fill GFX9 params */ - surface->tiling_info.gfx9.num_pipes = + plane_state->tiling_info.gfx9.num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes; - surface->tiling_info.gfx9.num_banks = + plane_state->tiling_info.gfx9.num_banks = adev->gfx.config.gb_addr_config_fields.num_banks; - surface->tiling_info.gfx9.pipe_interleave = + plane_state->tiling_info.gfx9.pipe_interleave = adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; - surface->tiling_info.gfx9.num_shader_engines = + plane_state->tiling_info.gfx9.num_shader_engines = adev->gfx.config.gb_addr_config_fields.num_se; - surface->tiling_info.gfx9.max_compressed_frags = + plane_state->tiling_info.gfx9.max_compressed_frags = adev->gfx.config.gb_addr_config_fields.max_compress_frags; - surface->tiling_info.gfx9.num_rb_per_se = + plane_state->tiling_info.gfx9.num_rb_per_se = adev->gfx.config.gb_addr_config_fields.num_rb_per_se; - surface->tiling_info.gfx9.swizzle = + plane_state->tiling_info.gfx9.swizzle = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); - surface->tiling_info.gfx9.shaderEnable = 1; + plane_state->tiling_info.gfx9.shaderEnable = 1; } - surface->visible = true; - surface->scaling_quality.h_taps_c = 0; - surface->scaling_quality.v_taps_c = 0; + plane_state->visible = true; + plane_state->scaling_quality.h_taps_c = 0; + plane_state->scaling_quality.v_taps_c = 0; - /* is this needed? is surface zeroed at allocation? */ - surface->scaling_quality.h_taps = 0; - surface->scaling_quality.v_taps = 0; - surface->stereo_format = PLANE_STEREO_FORMAT_NONE; + /* is this needed? is plane_state zeroed at allocation? */ + plane_state->scaling_quality.h_taps = 0; + plane_state->scaling_quality.v_taps = 0; + plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE; return ret; @@ -2050,7 +2050,7 @@ static int fill_plane_attributes_from_fb( static void fill_gamma_from_crtc_state( const struct drm_crtc_state *crtc_state, - struct dc_plane_state *dc_surface) + struct dc_plane_state *plane_state) { int i; struct dc_gamma *gamma; @@ -2069,12 +2069,12 @@ static void fill_gamma_from_crtc_state( gamma->blue[i] = lut[i].blue; } - dc_surface->gamma_correction = gamma; + plane_state->gamma_correction = gamma; } static int fill_plane_attributes( struct amdgpu_device *adev, - struct dc_plane_state *surface, + struct dc_plane_state *dc_plane_state, struct drm_plane_state *plane_state, struct drm_crtc_state *crtc_state, bool addrReq) @@ -2085,12 +2085,12 @@ static int fill_plane_attributes( struct dc_transfer_func *input_tf; int ret = 0; - if (!fill_rects_from_plane_state(plane_state, surface)) + if (!fill_rects_from_plane_state(plane_state, dc_plane_state)) return -EINVAL; ret = fill_plane_attributes_from_fb( crtc->dev->dev_private, - surface, + dc_plane_state, amdgpu_fb, addrReq); @@ -2105,11 +2105,11 @@ static int fill_plane_attributes( input_tf->type = TF_TYPE_PREDEFINED; input_tf->tf = TRANSFER_FUNCTION_SRGB; - surface->in_transfer_func = input_tf; + dc_plane_state->in_transfer_func = input_tf; /* In case of gamma set, update gamma value */ if (crtc_state->gamma_lut) - fill_gamma_from_crtc_state(crtc_state, surface); + fill_gamma_from_crtc_state(crtc_state, dc_plane_state); return ret; } @@ -2991,9 +2991,9 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane) __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); - if (old_dm_plane_state->surface) { - dm_plane_state->surface = old_dm_plane_state->surface; - dc_surface_retain(dm_plane_state->surface); + if (old_dm_plane_state->dc_state) { + dm_plane_state->dc_state = old_dm_plane_state->dc_state; + dc_plane_state_retain(dm_plane_state->dc_state); } return &dm_plane_state->base; @@ -3004,8 +3004,8 @@ void dm_drm_plane_destroy_state(struct drm_plane *plane, { struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); - if (dm_plane_state->surface) - dc_surface_release(dm_plane_state->surface); + if (dm_plane_state->dc_state) + dc_plane_state_release(dm_plane_state->dc_state); __drm_atomic_helper_plane_destroy_state(state); kfree(dm_plane_state); @@ -3059,18 +3059,18 @@ static int dm_plane_helper_prepare_fb( amdgpu_bo_ref(rbo); - if (dm_plane_state_new->surface && - dm_plane_state_old->surface != dm_plane_state_new->surface) { - struct dc_plane_state *surface = dm_plane_state_new->surface; + if (dm_plane_state_new->dc_state && + dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { + struct dc_plane_state *plane_state = dm_plane_state_new->dc_state; - if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { - surface->address.grph.addr.low_part = lower_32_bits(afb->address); - surface->address.grph.addr.high_part = upper_32_bits(afb->address); + if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { + plane_state->address.grph.addr.low_part = lower_32_bits(afb->address); + plane_state->address.grph.addr.high_part = upper_32_bits(afb->address); } else { awidth = ALIGN(new_state->fb->width, 64); - surface->address.video_progressive.luma_addr.low_part + plane_state->address.video_progressive.luma_addr.low_part = lower_32_bits(afb->address); - surface->address.video_progressive.chroma_addr.low_part + plane_state->address.video_progressive.chroma_addr.low_part = lower_32_bits(afb->address) + (awidth * new_state->fb->height); } @@ -3159,10 +3159,10 @@ int dm_plane_atomic_check(struct drm_plane *plane, struct dc *dc = adev->dm.dc; struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); - if (!dm_plane_state->surface) + if (!dm_plane_state->dc_state) return true; - if (dc_validate_plane(dc, dm_plane_state->surface)) + if (dc_validate_plane(dc, dm_plane_state->dc_state)) return 0; return -EINVAL; @@ -3848,6 +3848,7 @@ static void amdgpu_dm_do_flip( struct amdgpu_device *adev = crtc->dev->dev_private; bool async_flip = (acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; struct dc_flip_addrs addr = { {0} }; + /* TODO eliminate or rename surface_update */ struct dc_surface_update surface_updates[1] = { {0} }; struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); @@ -3903,11 +3904,11 @@ static void amdgpu_dm_do_flip( if (acrtc->base.state->event) prepare_flip_isr(acrtc); - surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->surfaces[0]; + surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0]; surface_updates->flip_addr = &addr; - dc_update_surfaces_and_stream(adev->dm.dc, surface_updates, 1, acrtc_state->stream, NULL); + dc_update_planes_and_stream(adev->dm.dc, surface_updates, 1, acrtc_state->stream, NULL); DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n", __func__, @@ -3918,7 +3919,7 @@ static void amdgpu_dm_do_flip( spin_unlock_irqrestore(&crtc->dev->event_lock, flags); } -static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, +static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, struct drm_device *dev, struct amdgpu_display_manager *dm, struct drm_crtc *pcrtc, @@ -3928,7 +3929,7 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, struct drm_plane *plane; struct drm_plane_state *old_plane_state; struct dc_stream_state *dc_stream_attach; - struct dc_plane_state *dc_surfaces_constructed[MAX_SURFACES]; + struct dc_plane_state *plane_states_constructed[MAX_SURFACES]; struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state); int planes_count = 0; @@ -3956,8 +3957,9 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, spin_lock_irqsave(&crtc->dev->event_lock, flags); if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) { - DRM_ERROR("add_surface: acrtc %d, already busy\n", - acrtc_attach->crtc_id); + DRM_ERROR("%s: acrtc %d, already busy\n", + __func__, + acrtc_attach->crtc_id); spin_unlock_irqrestore(&crtc->dev->event_lock, flags); /* In commit tail framework this cannot happen */ WARN_ON(1); @@ -3965,9 +3967,9 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, spin_unlock_irqrestore(&crtc->dev->event_lock, flags); if (!pflip_needed) { - WARN_ON(!dm_plane_state->surface); + WARN_ON(!dm_plane_state->dc_state); - dc_surfaces_constructed[planes_count] = dm_plane_state->surface; + plane_states_constructed[planes_count] = dm_plane_state->dc_state; dc_stream_attach = acrtc_state->stream; planes_count++; @@ -4010,11 +4012,11 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); } - if (false == dc_commit_surfaces_to_stream(dm->dc, - dc_surfaces_constructed, - planes_count, - dc_stream_attach)) - dm_error("%s: Failed to attach surface!\n", __func__); + if (false == dc_commit_planes_to_stream(dm->dc, + plane_states_constructed, + planes_count, + dc_stream_attach)) + dm_error("%s: Failed to attach plane!\n", __func__); } else { /*TODO BUG Here should go disable planes on CRTC. */ } @@ -4226,16 +4228,16 @@ void amdgpu_dm_atomic_commit_tail( status = dc_stream_get_status(new_acrtc_state->stream); WARN_ON(!status); - WARN_ON(!status->surface_count); + WARN_ON(!status->plane_count); if (!new_acrtc_state->stream) continue; /*TODO How it works with MPO ?*/ - if (!dc_commit_surfaces_to_stream( + if (!dc_commit_planes_to_stream( dm->dc, - status->surfaces, - status->surface_count, + status->plane_states, + status->plane_count, new_acrtc_state->stream)) dm_error("%s: Failed to update stream scaling!\n", __func__); } @@ -4260,7 +4262,7 @@ void amdgpu_dm_atomic_commit_tail( new_acrtc_state = to_dm_crtc_state(pcrtc->state); if (new_acrtc_state->stream) - amdgpu_dm_commit_surfaces(state, dev, dm, pcrtc, &wait_for_vblank); + amdgpu_dm_commit_planes(state, dev, dm, pcrtc, &wait_for_vblank); } @@ -4375,27 +4377,27 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector dm_force_atomic_commit(&aconnector->base); } -static uint32_t add_val_sets_surface( +static uint32_t add_val_sets_plane( struct dc_validation_set *val_sets, uint32_t set_count, const struct dc_stream_state *stream, - struct dc_plane_state *surface) + struct dc_plane_state *plane_state) { uint32_t i = 0, j = 0; while (i < set_count) { if (val_sets[i].stream == stream) { - while (val_sets[i].surfaces[j]) + while (val_sets[i].plane_states[j]) j++; break; } ++i; } - val_sets[i].surfaces[j] = surface; - val_sets[i].surface_count++; + val_sets[i].plane_states[j] = plane_state; + val_sets[i].plane_count++; - return val_sets[i].surface_count; + return val_sets[i].plane_count; } static uint32_t update_in_val_sets_stream( @@ -4516,7 +4518,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, /* * This bool will be set for true for any modeset/reset - * or surface update which implies non fast surface update. + * or plane update which implies non fast surface update. */ bool lock_and_validation_needed = false; @@ -4701,13 +4703,13 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, pflip_needed = !state->allow_modeset; if (!pflip_needed) { - struct dc_plane_state *surface; + struct dc_plane_state *dc_plane_state; - surface = dc_create_surface(dc); + dc_plane_state = dc_create_plane_state(dc); ret = fill_plane_attributes( plane_crtc->dev->dev_private, - surface, + dc_plane_state, plane_state, crtc_state, false); @@ -4715,15 +4717,15 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, goto fail; - if (dm_plane_state->surface) - dc_surface_release(dm_plane_state->surface); + if (dm_plane_state->dc_state) + dc_plane_state_release(dm_plane_state->dc_state); - dm_plane_state->surface = surface; + dm_plane_state->dc_state = dc_plane_state; - add_val_sets_surface(set, + add_val_sets_plane(set, set_count, new_acrtc_state->stream, - surface); + dc_plane_state); lock_and_validation_needed = true; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index cca65a37b213..e0a5632f00a3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -196,7 +196,7 @@ struct dc_stream; struct dm_plane_state { struct drm_plane_state base; - struct dc_plane_state *surface; + struct dc_plane_state *dc_state; }; struct dm_crtc_state { diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c index 9a850227eeeb..28dbd18b2d86 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c @@ -2594,15 +2594,15 @@ static void populate_initial_data( if (!pipe[i].stream || !pipe[i].bottom_pipe) continue; - ASSERT(pipe[i].surface); + ASSERT(pipe[i].plane_state); if (num_displays == 0) { - if (!pipe[i].surface->visible) + if (!pipe[i].plane_state->visible) data->d0_underlay_mode = bw_def_underlay_only; else data->d0_underlay_mode = bw_def_blend; } else { - if (!pipe[i].surface->visible) + if (!pipe[i].plane_state->visible) data->d1_underlay_mode = bw_def_underlay_only; else data->d1_underlay_mode = bw_def_blend; @@ -2620,7 +2620,7 @@ static void populate_initial_data( data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.taps.v_taps); data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.horz.value); data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.vert.value); - switch (pipe[i].surface->rotation) { + switch (pipe[i].plane_state->rotation) { case ROTATION_ANGLE_0: data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0); break; @@ -2636,7 +2636,7 @@ static void populate_initial_data( default: break; } - switch (pipe[i].surface->format) { + switch (pipe[i].plane_state->format) { case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: case SURFACE_PIXEL_FORMAT_GRPH_RGB565: @@ -2670,14 +2670,14 @@ static void populate_initial_data( data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.viewport.height); data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.viewport.width); data->pitch_in_pixels[num_displays * 2 + j] = bw_int_to_fixed( - pipe[i].bottom_pipe->surface->plane_size.grph.surface_pitch); + pipe[i].bottom_pipe->plane_state->plane_size.grph.surface_pitch); data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.taps.h_taps); data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.taps.v_taps); data->h_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed( pipe[i].bottom_pipe->scl_data.ratios.horz.value); data->v_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed( pipe[i].bottom_pipe->scl_data.ratios.vert.value); - switch (pipe[i].bottom_pipe->surface->rotation) { + switch (pipe[i].bottom_pipe->plane_state->rotation) { case ROTATION_ANGLE_0: data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(0); break; @@ -2710,7 +2710,7 @@ static void populate_initial_data( data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total); data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total); data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_khz, 1000); - if (pipe[i].surface) { + if (pipe[i].plane_state) { data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.width); data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4]; data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.height); @@ -2718,7 +2718,7 @@ static void populate_initial_data( data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.taps.v_taps); data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.horz.value); data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.vert.value); - switch (pipe[i].surface->rotation) { + switch (pipe[i].plane_state->rotation) { case ROTATION_ANGLE_0: data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0); break; @@ -2734,7 +2734,7 @@ static void populate_initial_data( default: break; } - switch (pipe[i].surface->format) { + switch (pipe[i].plane_state->format) { case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 7f7cb8ff124d..404b39e7b44b 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -233,16 +233,16 @@ static void pipe_ctx_to_e2e_pipe_params ( struct _vcs_dpi_display_pipe_params_st *input) { input->src.is_hsplit = false; - if (pipe->top_pipe != NULL && pipe->top_pipe->surface == pipe->surface) + if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state) input->src.is_hsplit = true; - else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->surface == pipe->surface) + else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state) input->src.is_hsplit = true; - input->src.dcc = pipe->surface->dcc.enable; + input->src.dcc = pipe->plane_state->dcc.enable; input->src.dcc_rate = 1; - input->src.meta_pitch = pipe->surface->dcc.grph.meta_pitch; + input->src.meta_pitch = pipe->plane_state->dcc.grph.meta_pitch; input->src.source_scan = dm_horz; - input->src.sw_mode = pipe->surface->tiling_info.gfx9.swizzle; + input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle; input->src.viewport_width = pipe->scl_data.viewport.width; input->src.viewport_height = pipe->scl_data.viewport.height; @@ -251,7 +251,7 @@ static void pipe_ctx_to_e2e_pipe_params ( input->src.cur0_src_width = 128; /* TODO: Cursor calcs, not curently stored */ input->src.cur0_bpp = 32; - switch (pipe->surface->tiling_info.gfx9.swizzle) { + switch (pipe->plane_state->tiling_info.gfx9.swizzle) { /* for 4/8/16 high tiles */ case DC_SW_LINEAR: input->src.is_display_sw = 1; @@ -299,7 +299,7 @@ static void pipe_ctx_to_e2e_pipe_params ( break; } - switch (pipe->surface->rotation) { + switch (pipe->plane_state->rotation) { case ROTATION_ANGLE_0: case ROTATION_ANGLE_180: input->src.source_scan = dm_horz; @@ -314,7 +314,7 @@ static void pipe_ctx_to_e2e_pipe_params ( } /* TODO: Fix pixel format mappings */ - switch (pipe->surface->format) { + switch (pipe->plane_state->format) { case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: input->src.source_format = dm_420_8; @@ -455,7 +455,7 @@ static void dcn_bw_calc_rq_dlg_ttu( true, true, v->pte_enable == dcn_bw_yes, - pipe->surface->flip_immediate); + pipe->plane_state->flip_immediate); } static void dcn_dml_wm_override( @@ -478,7 +478,7 @@ static void dcn_dml_wm_override( for (i = 0, in_idx = 0; i < pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; - if (!pipe->stream || !pipe->surface) + if (!pipe->stream || !pipe->plane_state) continue; input[in_idx].clks_cfg.dcfclk_mhz = v->dcfclk; @@ -516,7 +516,7 @@ static void dcn_dml_wm_override( for (i = 0, in_idx = 0; i < pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; - if (!pipe->stream || !pipe->surface) + if (!pipe->stream || !pipe->plane_state) continue; dml_rq_dlg_get_dlg_reg(dml, @@ -527,7 +527,7 @@ static void dcn_dml_wm_override( true, true, v->pte_enable == dcn_bw_yes, - pipe->surface->flip_immediate); + pipe->plane_state->flip_immediate); in_idx++; } dm_free(input); @@ -541,7 +541,7 @@ static void split_stream_across_pipes( { int pipe_idx = secondary_pipe->pipe_idx; - if (!primary_pipe->surface) + if (!primary_pipe->plane_state) return; *secondary_pipe = *primary_pipe; @@ -843,7 +843,7 @@ bool dcn_validate_bandwidth( if (!pipe->stream) continue; /* skip all but first of split pipes */ - if (pipe->top_pipe && pipe->top_pipe->surface == pipe->surface) + if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) continue; v->underscan_output[input_idx] = false; /* taken care of in recout already*/ @@ -869,7 +869,7 @@ bool dcn_validate_bandwidth( } } - if (!pipe->surface){ + if (!pipe->plane_state) { v->dcc_enable[input_idx] = dcn_bw_yes; v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32; v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s; @@ -889,8 +889,8 @@ bool dcn_validate_bandwidth( v->viewport_width[input_idx] = pipe->scl_data.viewport.width; v->scaler_rec_out_width[input_idx] = pipe->scl_data.recout.width; v->scaler_recout_height[input_idx] = pipe->scl_data.recout.height; - if (pipe->bottom_pipe && pipe->bottom_pipe->surface == pipe->surface) { - if (pipe->surface->rotation % 2 == 0) { + if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) { + if (pipe->plane_state->rotation % 2 == 0) { int viewport_end = pipe->scl_data.viewport.width + pipe->scl_data.viewport.x; int viewport_b_end = pipe->bottom_pipe->scl_data.viewport.width @@ -919,17 +919,17 @@ bool dcn_validate_bandwidth( + pipe->bottom_pipe->scl_data.recout.width; } - v->dcc_enable[input_idx] = pipe->surface->dcc.enable ? dcn_bw_yes : dcn_bw_no; + v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no; v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs( - pipe->surface->format); + pipe->plane_state->format); v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs( - pipe->surface->tiling_info.gfx9.swizzle); + pipe->plane_state->tiling_info.gfx9.swizzle); v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->scl_data.lb_params.depth); v->override_hta_ps[input_idx] = pipe->scl_data.taps.h_taps; v->override_vta_ps[input_idx] = pipe->scl_data.taps.v_taps; v->override_hta_pschroma[input_idx] = pipe->scl_data.taps.h_taps_c; v->override_vta_pschroma[input_idx] = pipe->scl_data.taps.v_taps_c; - v->source_scan[input_idx] = (pipe->surface->rotation % 2) ? dcn_bw_vert : dcn_bw_hor; + v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor; } if (v->is_line_buffer_bpp_fixed == dcn_bw_yes) v->lb_bit_per_pixel[input_idx] = v->line_buffer_fixed_bpp; @@ -996,7 +996,7 @@ bool dcn_validate_bandwidth( if (!pipe->stream) continue; /* skip all but first of split pipes */ - if (pipe->top_pipe && pipe->top_pipe->surface == pipe->surface) + if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) continue; pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx]; @@ -1024,7 +1024,7 @@ bool dcn_validate_bandwidth( pipe->pipe_dlg_param.vblank_start = asic_blank_start; pipe->pipe_dlg_param.vblank_end = asic_blank_end; - if (pipe->surface) { + if (pipe->plane_state) { struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; if (v->dpp_per_plane[input_idx] == 2 || @@ -1036,7 +1036,7 @@ bool dcn_validate_bandwidth( TIMING_3D_FORMAT_TOP_AND_BOTTOM || pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE))) { - if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) { + if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { /* update previously split pipe */ hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx]; hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx]; @@ -1057,12 +1057,12 @@ bool dcn_validate_bandwidth( } dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe); - } else if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) { + } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { /* merge previously split pipe */ pipe->bottom_pipe = hsplit_pipe->bottom_pipe; if (hsplit_pipe->bottom_pipe) hsplit_pipe->bottom_pipe->top_pipe = pipe; - hsplit_pipe->surface = NULL; + hsplit_pipe->plane_state = NULL; hsplit_pipe->stream = NULL; hsplit_pipe->top_pipe = NULL; hsplit_pipe->bottom_pipe = NULL; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 8b6b7631d776..ffc9c05e2fb5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -639,21 +639,21 @@ static bool is_validation_required( for (i = 0; i < set_count; i++) { - if (set[i].surface_count != context->stream_status[i].surface_count) + if (set[i].plane_count != context->stream_status[i].plane_count) return true; if (!dc_is_stream_unchanged(set[i].stream, context->streams[i])) return true; - for (j = 0; j < set[i].surface_count; j++) { - struct dc_plane_state temp_surf; - memset(&temp_surf, 0, sizeof(temp_surf)); + for (j = 0; j < set[i].plane_count; j++) { + struct dc_plane_state temp_plane; + memset(&temp_plane, 0, sizeof(temp_plane)); - temp_surf = *context->stream_status[i].surfaces[j]; - temp_surf.clip_rect = set[i].surfaces[j]->clip_rect; - temp_surf.dst_rect.x = set[i].surfaces[j]->dst_rect.x; - temp_surf.dst_rect.y = set[i].surfaces[j]->dst_rect.y; + temp_plane = *context->stream_status[i].plane_states[j]; + temp_plane.clip_rect = set[i].plane_states[j]->clip_rect; + temp_plane.dst_rect.x = set[i].plane_states[j]->dst_rect.x; + temp_plane.dst_rect.y = set[i].plane_states[j]->dst_rect.y; - if (memcmp(&temp_surf, set[i].surfaces[j], sizeof(temp_surf)) != 0) + if (memcmp(&temp_plane, set[i].plane_states[j], sizeof(temp_plane)) != 0) return true; } } @@ -683,8 +683,8 @@ static bool validate_surfaces( int i, j; for (i = 0; i < set_count; i++) - for (j = 0; j < set[i].surface_count; j++) - if (!dc_validate_plane(dc, set[i].surfaces[j])) + for (j = 0; j < set[i].plane_count; j++) + if (!dc_validate_plane(dc, set[i].plane_states[j])) return false; return true; @@ -977,11 +977,11 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c for (i = 0; i < context->stream_count; i++) { const struct dc_sink *sink = context->streams[i]->sink; - for (j = 0; j < context->stream_status[i].surface_count; j++) { - const struct dc_plane_state *surface = - context->stream_status[i].surfaces[j]; + for (j = 0; j < context->stream_status[i].plane_count; j++) { + const struct dc_plane_state *plane_state = + context->stream_status[i].plane_states[j]; - core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context); + core_dc->hwss.apply_ctx_for_surface(core_dc, plane_state, context); /* * enable stereo @@ -1073,9 +1073,9 @@ bool dc_commit_streams( set[i].stream = stream; if (status) { - set[i].surface_count = status->surface_count; - for (j = 0; j < status->surface_count; j++) - set[i].surfaces[j] = status->surfaces[j]; + set[i].plane_count = status->plane_count; + for (j = 0; j < status->plane_count; j++) + set[i].plane_states[j] = status->plane_states[j]; } } @@ -1122,7 +1122,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) for (i = 0; i < core_dc->res_pool->pipe_count; i++) if (context->res_ctx.pipe_ctx[i].stream == NULL - || context->res_ctx.pipe_ctx[i].surface == NULL) + || context->res_ctx.pipe_ctx[i].plane_state == NULL) core_dc->hwss.power_down_front_end(core_dc, i); /* 3rd param should be true, temp w/a for RV*/ @@ -1134,10 +1134,10 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) return true; } -bool dc_commit_surfaces_to_stream( +bool dc_commit_planes_to_stream( struct dc *dc, - struct dc_plane_state **new_surfaces, - uint8_t new_surface_count, + struct dc_plane_state **plane_states, + uint8_t new_plane_count, struct dc_stream_state *dc_stream) { struct dc_surface_update updates[MAX_SURFACES]; @@ -1162,37 +1162,37 @@ bool dc_commit_surfaces_to_stream( stream_update->dst = dc_stream->dst; stream_update->out_transfer_func = dc_stream->out_transfer_func; - for (i = 0; i < new_surface_count; i++) { - updates[i].surface = new_surfaces[i]; + for (i = 0; i < new_plane_count; i++) { + updates[i].surface = plane_states[i]; updates[i].gamma = - (struct dc_gamma *)new_surfaces[i]->gamma_correction; - updates[i].in_transfer_func = new_surfaces[i]->in_transfer_func; - flip_addr[i].address = new_surfaces[i]->address; - flip_addr[i].flip_immediate = new_surfaces[i]->flip_immediate; - plane_info[i].color_space = new_surfaces[i]->color_space; - plane_info[i].format = new_surfaces[i]->format; - plane_info[i].plane_size = new_surfaces[i]->plane_size; - plane_info[i].rotation = new_surfaces[i]->rotation; - plane_info[i].horizontal_mirror = new_surfaces[i]->horizontal_mirror; - plane_info[i].stereo_format = new_surfaces[i]->stereo_format; - plane_info[i].tiling_info = new_surfaces[i]->tiling_info; - plane_info[i].visible = new_surfaces[i]->visible; - plane_info[i].per_pixel_alpha = new_surfaces[i]->per_pixel_alpha; - plane_info[i].dcc = new_surfaces[i]->dcc; - scaling_info[i].scaling_quality = new_surfaces[i]->scaling_quality; - scaling_info[i].src_rect = new_surfaces[i]->src_rect; - scaling_info[i].dst_rect = new_surfaces[i]->dst_rect; - scaling_info[i].clip_rect = new_surfaces[i]->clip_rect; + (struct dc_gamma *)plane_states[i]->gamma_correction; + updates[i].in_transfer_func = plane_states[i]->in_transfer_func; + flip_addr[i].address = plane_states[i]->address; + flip_addr[i].flip_immediate = plane_states[i]->flip_immediate; + plane_info[i].color_space = plane_states[i]->color_space; + plane_info[i].format = plane_states[i]->format; + plane_info[i].plane_size = plane_states[i]->plane_size; + plane_info[i].rotation = plane_states[i]->rotation; + plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror; + plane_info[i].stereo_format = plane_states[i]->stereo_format; + plane_info[i].tiling_info = plane_states[i]->tiling_info; + plane_info[i].visible = plane_states[i]->visible; + plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha; + plane_info[i].dcc = plane_states[i]->dcc; + scaling_info[i].scaling_quality = plane_states[i]->scaling_quality; + scaling_info[i].src_rect = plane_states[i]->src_rect; + scaling_info[i].dst_rect = plane_states[i]->dst_rect; + scaling_info[i].clip_rect = plane_states[i]->clip_rect; updates[i].flip_addr = &flip_addr[i]; updates[i].plane_info = &plane_info[i]; updates[i].scaling_info = &scaling_info[i]; } - dc_update_surfaces_and_stream( + dc_update_planes_and_stream( dc, updates, - new_surface_count, + new_plane_count, dc_stream, stream_update); dc_post_update_surfaces_to_stream(dc); @@ -1220,14 +1220,14 @@ void dc_release_validate_context(struct validate_context *context) static bool is_surface_in_context( const struct validate_context *context, - const struct dc_plane_state *surface) + const struct dc_plane_state *plane_state) { int j; for (j = 0; j < MAX_PIPES; j++) { const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - if (surface == pipe_ctx->surface) { + if (plane_state == pipe_ctx->plane_state) { return true; } } @@ -1371,7 +1371,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream( int i; enum surface_update_type overall_type = UPDATE_TYPE_FAST; - if (stream_status == NULL || stream_status->surface_count != surface_count) + if (stream_status == NULL || stream_status->plane_count != surface_count) return UPDATE_TYPE_FULL; if (stream_update) @@ -1393,7 +1393,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream( enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL; -void dc_update_surfaces_and_stream(struct dc *dc, +void dc_update_planes_and_stream(struct dc *dc, struct dc_surface_update *srf_updates, int surface_count, struct dc_stream_state *stream, struct dc_stream_update *stream_update) @@ -1470,10 +1470,10 @@ void dc_update_surfaces_and_stream(struct dc *dc, update_surface_trace(dc, srf_updates, surface_count); if (update_type >= UPDATE_TYPE_FULL) { - struct dc_plane_state *new_surfaces[MAX_SURFACES] = {0}; + struct dc_plane_state *new_planes[MAX_SURFACES] = {0}; for (i = 0; i < surface_count; i++) - new_surfaces[i] = srf_updates[i].surface; + new_planes[i] = srf_updates[i].surface; /* initialize scratch memory for building context */ context = dm_alloc(sizeof(*context)); @@ -1487,7 +1487,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* add surface to context */ if (!resource_attach_surfaces_to_context( - new_surfaces, surface_count, stream, + new_planes, surface_count, stream, context, core_dc->res_pool)) { BREAK_TO_DEBUGGER(); goto fail; @@ -1542,7 +1542,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, for (j = 0; j < core_dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - if (pipe_ctx->surface != surface) + if (pipe_ctx->plane_state != surface) continue; resource_build_scaling_params(pipe_ctx); @@ -1599,14 +1599,14 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* Lock pipes for provided surfaces, or all active if full update*/ for (i = 0; i < surface_count; i++) { - struct dc_plane_state *surface = srf_updates[i].surface; + struct dc_plane_state *plane_state = srf_updates[i].surface; for (j = 0; j < core_dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - if (update_type != UPDATE_TYPE_FULL && pipe_ctx->surface != surface) + if (update_type != UPDATE_TYPE_FULL && pipe_ctx->plane_state != plane_state) continue; - if (!pipe_ctx->surface || pipe_ctx->top_pipe) + if (!pipe_ctx->plane_state || pipe_ctx->top_pipe) continue; core_dc->hwss.pipe_control_lock( @@ -1622,15 +1622,15 @@ void dc_update_surfaces_and_stream(struct dc *dc, for (j = 0; j < core_dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; struct pipe_ctx *cur_pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[j]; - bool is_new_pipe_surface = cur_pipe_ctx->surface != pipe_ctx->surface; + bool is_new_pipe_surface = cur_pipe_ctx->plane_state != pipe_ctx->plane_state; struct dc_cursor_position position = { 0 }; - if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->surface) + if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->plane_state) continue; if (!pipe_ctx->top_pipe) core_dc->hwss.apply_ctx_for_surface( - core_dc, pipe_ctx->surface, context); + core_dc, pipe_ctx->plane_state, context); /* TODO: this is a hack w/a for switching from mpo to pipe split */ dc_stream_set_cursor_position(pipe_ctx->stream, &position); @@ -1638,7 +1638,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, if (is_new_pipe_surface) { core_dc->hwss.update_plane_addr(core_dc, pipe_ctx); core_dc->hwss.set_input_transfer_func( - pipe_ctx, pipe_ctx->surface); + pipe_ctx, pipe_ctx->plane_state); core_dc->hwss.set_output_transfer_func( pipe_ctx, pipe_ctx->stream); } @@ -1649,16 +1649,16 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* Perform requested Updates */ for (i = 0; i < surface_count; i++) { - struct dc_plane_state *surface = srf_updates[i].surface; + struct dc_plane_state *plane_state = srf_updates[i].surface; if (update_type == UPDATE_TYPE_MED) core_dc->hwss.apply_ctx_for_surface( - core_dc, surface, context); + core_dc, plane_state, context); for (j = 0; j < core_dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - if (pipe_ctx->surface != surface) + if (pipe_ctx->plane_state != plane_state) continue; if (srf_updates[i].flip_addr) @@ -1669,7 +1669,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, if (srf_updates[i].in_transfer_func) core_dc->hwss.set_input_transfer_func( - pipe_ctx, pipe_ctx->surface); + pipe_ctx, pipe_ctx->plane_state); if (stream_update != NULL && stream_update->out_transfer_func != NULL) { @@ -1690,9 +1690,9 @@ void dc_update_surfaces_and_stream(struct dc *dc, for (j = 0; j < surface_count; j++) { if (update_type != UPDATE_TYPE_FULL && - srf_updates[j].surface != pipe_ctx->surface) + srf_updates[j].surface != pipe_ctx->plane_state) continue; - if (!pipe_ctx->surface || pipe_ctx->top_pipe) + if (!pipe_ctx->plane_state || pipe_ctx->top_pipe) continue; core_dc->hwss.pipe_control_lock( diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index e8d4b8c3ac2b..ca4f1db4a58a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -38,7 +38,7 @@ void pre_surface_trace( const struct dc *dc, - const struct dc_plane_state *const *surfaces, + const struct dc_plane_state *const *plane_states, int surface_count) { int i; @@ -46,111 +46,111 @@ void pre_surface_trace( struct dal_logger *logger = core_dc->ctx->logger; for (i = 0; i < surface_count; i++) { - const struct dc_plane_state *surface = surfaces[i]; + const struct dc_plane_state *plane_state = plane_states[i]; - SURFACE_TRACE("Surface %d:\n", i); + SURFACE_TRACE("Planes %d:\n", i); SURFACE_TRACE( - "surface->visible = %d;\n" - "surface->flip_immediate = %d;\n" - "surface->address.type = %d;\n" - "surface->address.grph.addr.quad_part = 0x%X;\n" - "surface->address.grph.meta_addr.quad_part = 0x%X;\n" - "surface->scaling_quality.h_taps = %d;\n" - "surface->scaling_quality.v_taps = %d;\n" - "surface->scaling_quality.h_taps_c = %d;\n" - "surface->scaling_quality.v_taps_c = %d;\n", - surface->visible, - surface->flip_immediate, - surface->address.type, - surface->address.grph.addr.quad_part, - surface->address.grph.meta_addr.quad_part, - surface->scaling_quality.h_taps, - surface->scaling_quality.v_taps, - surface->scaling_quality.h_taps_c, - surface->scaling_quality.v_taps_c); + "plane_state->visible = %d;\n" + "plane_state->flip_immediate = %d;\n" + "plane_state->address.type = %d;\n" + "plane_state->address.grph.addr.quad_part = 0x%X;\n" + "plane_state->address.grph.meta_addr.quad_part = 0x%X;\n" + "plane_state->scaling_quality.h_taps = %d;\n" + "plane_state->scaling_quality.v_taps = %d;\n" + "plane_state->scaling_quality.h_taps_c = %d;\n" + "plane_state->scaling_quality.v_taps_c = %d;\n", + plane_state->visible, + plane_state->flip_immediate, + plane_state->address.type, + plane_state->address.grph.addr.quad_part, + plane_state->address.grph.meta_addr.quad_part, + plane_state->scaling_quality.h_taps, + plane_state->scaling_quality.v_taps, + plane_state->scaling_quality.h_taps_c, + plane_state->scaling_quality.v_taps_c); SURFACE_TRACE( - "surface->src_rect.x = %d;\n" - "surface->src_rect.y = %d;\n" - "surface->src_rect.width = %d;\n" - "surface->src_rect.height = %d;\n" - "surface->dst_rect.x = %d;\n" - "surface->dst_rect.y = %d;\n" - "surface->dst_rect.width = %d;\n" - "surface->dst_rect.height = %d;\n" - "surface->clip_rect.x = %d;\n" - "surface->clip_rect.y = %d;\n" - "surface->clip_rect.width = %d;\n" - "surface->clip_rect.height = %d;\n", - surface->src_rect.x, - surface->src_rect.y, - surface->src_rect.width, - surface->src_rect.height, - surface->dst_rect.x, - surface->dst_rect.y, - surface->dst_rect.width, - surface->dst_rect.height, - surface->clip_rect.x, - surface->clip_rect.y, - surface->clip_rect.width, - surface->clip_rect.height); + "plane_state->src_rect.x = %d;\n" + "plane_state->src_rect.y = %d;\n" + "plane_state->src_rect.width = %d;\n" + "plane_state->src_rect.height = %d;\n" + "plane_state->dst_rect.x = %d;\n" + "plane_state->dst_rect.y = %d;\n" + "plane_state->dst_rect.width = %d;\n" + "plane_state->dst_rect.height = %d;\n" + "plane_state->clip_rect.x = %d;\n" + "plane_state->clip_rect.y = %d;\n" + "plane_state->clip_rect.width = %d;\n" + "plane_state->clip_rect.height = %d;\n", + plane_state->src_rect.x, + plane_state->src_rect.y, + plane_state->src_rect.width, + plane_state->src_rect.height, + plane_state->dst_rect.x, + plane_state->dst_rect.y, + plane_state->dst_rect.width, + plane_state->dst_rect.height, + plane_state->clip_rect.x, + plane_state->clip_rect.y, + plane_state->clip_rect.width, + plane_state->clip_rect.height); SURFACE_TRACE( - "surface->plane_size.grph.surface_size.x = %d;\n" - "surface->plane_size.grph.surface_size.y = %d;\n" - "surface->plane_size.grph.surface_size.width = %d;\n" - "surface->plane_size.grph.surface_size.height = %d;\n" - "surface->plane_size.grph.surface_pitch = %d;\n", - surface->plane_size.grph.surface_size.x, - surface->plane_size.grph.surface_size.y, - surface->plane_size.grph.surface_size.width, - surface->plane_size.grph.surface_size.height, - surface->plane_size.grph.surface_pitch); + "plane_state->plane_size.grph.surface_size.x = %d;\n" + "plane_state->plane_size.grph.surface_size.y = %d;\n" + "plane_state->plane_size.grph.surface_size.width = %d;\n" + "plane_state->plane_size.grph.surface_size.height = %d;\n" + "plane_state->plane_size.grph.surface_pitch = %d;\n", + plane_state->plane_size.grph.surface_size.x, + plane_state->plane_size.grph.surface_size.y, + plane_state->plane_size.grph.surface_size.width, + plane_state->plane_size.grph.surface_size.height, + plane_state->plane_size.grph.surface_pitch); SURFACE_TRACE( - "surface->tiling_info.gfx8.num_banks = %d;\n" - "surface->tiling_info.gfx8.bank_width = %d;\n" - "surface->tiling_info.gfx8.bank_width_c = %d;\n" - "surface->tiling_info.gfx8.bank_height = %d;\n" - "surface->tiling_info.gfx8.bank_height_c = %d;\n" - "surface->tiling_info.gfx8.tile_aspect = %d;\n" - "surface->tiling_info.gfx8.tile_aspect_c = %d;\n" - "surface->tiling_info.gfx8.tile_split = %d;\n" - "surface->tiling_info.gfx8.tile_split_c = %d;\n" - "surface->tiling_info.gfx8.tile_mode = %d;\n" - "surface->tiling_info.gfx8.tile_mode_c = %d;\n", - surface->tiling_info.gfx8.num_banks, - surface->tiling_info.gfx8.bank_width, - surface->tiling_info.gfx8.bank_width_c, - surface->tiling_info.gfx8.bank_height, - surface->tiling_info.gfx8.bank_height_c, - surface->tiling_info.gfx8.tile_aspect, - surface->tiling_info.gfx8.tile_aspect_c, - surface->tiling_info.gfx8.tile_split, - surface->tiling_info.gfx8.tile_split_c, - surface->tiling_info.gfx8.tile_mode, - surface->tiling_info.gfx8.tile_mode_c); + "plane_state->tiling_info.gfx8.num_banks = %d;\n" + "plane_state->tiling_info.gfx8.bank_width = %d;\n" + "plane_state->tiling_info.gfx8.bank_width_c = %d;\n" + "plane_state->tiling_info.gfx8.bank_height = %d;\n" + "plane_state->tiling_info.gfx8.bank_height_c = %d;\n" + "plane_state->tiling_info.gfx8.tile_aspect = %d;\n" + "plane_state->tiling_info.gfx8.tile_aspect_c = %d;\n" + "plane_state->tiling_info.gfx8.tile_split = %d;\n" + "plane_state->tiling_info.gfx8.tile_split_c = %d;\n" + "plane_state->tiling_info.gfx8.tile_mode = %d;\n" + "plane_state->tiling_info.gfx8.tile_mode_c = %d;\n", + plane_state->tiling_info.gfx8.num_banks, + plane_state->tiling_info.gfx8.bank_width, + plane_state->tiling_info.gfx8.bank_width_c, + plane_state->tiling_info.gfx8.bank_height, + plane_state->tiling_info.gfx8.bank_height_c, + plane_state->tiling_info.gfx8.tile_aspect, + plane_state->tiling_info.gfx8.tile_aspect_c, + plane_state->tiling_info.gfx8.tile_split, + plane_state->tiling_info.gfx8.tile_split_c, + plane_state->tiling_info.gfx8.tile_mode, + plane_state->tiling_info.gfx8.tile_mode_c); SURFACE_TRACE( - "surface->tiling_info.gfx8.pipe_config = %d;\n" - "surface->tiling_info.gfx8.array_mode = %d;\n" - "surface->color_space = %d;\n" - "surface->dcc.enable = %d;\n" - "surface->format = %d;\n" - "surface->rotation = %d;\n" - "surface->stereo_format = %d;\n", - surface->tiling_info.gfx8.pipe_config, - surface->tiling_info.gfx8.array_mode, - surface->color_space, - surface->dcc.enable, - surface->format, - surface->rotation, - surface->stereo_format); - - SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n", - surface->tiling_info.gfx9.swizzle); + "plane_state->tiling_info.gfx8.pipe_config = %d;\n" + "plane_state->tiling_info.gfx8.array_mode = %d;\n" + "plane_state->color_space = %d;\n" + "plane_state->dcc.enable = %d;\n" + "plane_state->format = %d;\n" + "plane_state->rotation = %d;\n" + "plane_state->stereo_format = %d;\n", + plane_state->tiling_info.gfx8.pipe_config, + plane_state->tiling_info.gfx8.array_mode, + plane_state->color_space, + plane_state->dcc.enable, + plane_state->format, + plane_state->rotation, + plane_state->stereo_format); + + SURFACE_TRACE("plane_state->tiling_info.gfx9.swizzle = %d;\n", + plane_state->tiling_info.gfx9.swizzle); SURFACE_TRACE("\n"); } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index ce0415f26600..4eef400cb551 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -430,17 +430,17 @@ static void rect_swap_helper(struct rect *rect) static void calculate_viewport(struct pipe_ctx *pipe_ctx) { - const struct dc_plane_state *surface = pipe_ctx->surface; + const struct dc_plane_state *plane_state = pipe_ctx->plane_state; const struct dc_stream_state *stream = pipe_ctx->stream; struct scaler_data *data = &pipe_ctx->scl_data; - struct rect surf_src = surface->src_rect; + struct rect surf_src = plane_state->src_rect; struct rect clip = { 0 }; int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; bool pri_split = pipe_ctx->bottom_pipe && - pipe_ctx->bottom_pipe->surface == pipe_ctx->surface; + pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state; bool sec_split = pipe_ctx->top_pipe && - pipe_ctx->top_pipe->surface == pipe_ctx->surface; + pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE || stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { @@ -448,41 +448,41 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) sec_split = false; } - if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 || - pipe_ctx->surface->rotation == ROTATION_ANGLE_270) + if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || + pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) rect_swap_helper(&surf_src); /* The actual clip is an intersection between stream * source and surface clip */ - clip.x = stream->src.x > surface->clip_rect.x ? - stream->src.x : surface->clip_rect.x; + clip.x = stream->src.x > plane_state->clip_rect.x ? + stream->src.x : plane_state->clip_rect.x; clip.width = stream->src.x + stream->src.width < - surface->clip_rect.x + surface->clip_rect.width ? + plane_state->clip_rect.x + plane_state->clip_rect.width ? stream->src.x + stream->src.width - clip.x : - surface->clip_rect.x + surface->clip_rect.width - clip.x ; + plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ; - clip.y = stream->src.y > surface->clip_rect.y ? - stream->src.y : surface->clip_rect.y; + clip.y = stream->src.y > plane_state->clip_rect.y ? + stream->src.y : plane_state->clip_rect.y; clip.height = stream->src.y + stream->src.height < - surface->clip_rect.y + surface->clip_rect.height ? + plane_state->clip_rect.y + plane_state->clip_rect.height ? stream->src.y + stream->src.height - clip.y : - surface->clip_rect.y + surface->clip_rect.height - clip.y ; + plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ; /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio * num_pixels = clip.num_pix * scl_ratio */ - data->viewport.x = surf_src.x + (clip.x - surface->dst_rect.x) * - surf_src.width / surface->dst_rect.width; + data->viewport.x = surf_src.x + (clip.x - plane_state->dst_rect.x) * + surf_src.width / plane_state->dst_rect.width; data->viewport.width = clip.width * - surf_src.width / surface->dst_rect.width; + surf_src.width / plane_state->dst_rect.width; - data->viewport.y = surf_src.y + (clip.y - surface->dst_rect.y) * - surf_src.height / surface->dst_rect.height; + data->viewport.y = surf_src.y + (clip.y - plane_state->dst_rect.y) * + surf_src.height / plane_state->dst_rect.height; data->viewport.height = clip.height * - surf_src.height / surface->dst_rect.height; + surf_src.height / plane_state->dst_rect.height; /* Round down, compensate in init */ data->viewport_c.x = data->viewport.x / vpc_div; @@ -498,13 +498,13 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) /* Handle hsplit */ if (pri_split || sec_split) { /* HMirror XOR Secondary_pipe XOR Rotation_180 */ - bool right_view = (sec_split != surface->horizontal_mirror) != - (surface->rotation == ROTATION_ANGLE_180); + bool right_view = (sec_split != plane_state->horizontal_mirror) != + (plane_state->rotation == ROTATION_ANGLE_180); - if (surface->rotation == ROTATION_ANGLE_90 - || surface->rotation == ROTATION_ANGLE_270) + if (plane_state->rotation == ROTATION_ANGLE_90 + || plane_state->rotation == ROTATION_ANGLE_270) /* Secondary_pipe XOR Rotation_270 */ - right_view = (surface->rotation == ROTATION_ANGLE_270) != sec_split; + right_view = (plane_state->rotation == ROTATION_ANGLE_270) != sec_split; if (right_view) { data->viewport.width /= 2; @@ -520,8 +520,8 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) } } - if (surface->rotation == ROTATION_ANGLE_90 || - surface->rotation == ROTATION_ANGLE_270) { + if (plane_state->rotation == ROTATION_ANGLE_90 || + plane_state->rotation == ROTATION_ANGLE_270) { rect_swap_helper(&data->viewport_c); rect_swap_helper(&data->viewport); } @@ -529,14 +529,14 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip) { - const struct dc_plane_state *surface = pipe_ctx->surface; + const struct dc_plane_state *plane_state = pipe_ctx->plane_state; const struct dc_stream_state *stream = pipe_ctx->stream; - struct rect surf_src = surface->src_rect; - struct rect surf_clip = surface->clip_rect; + struct rect surf_src = plane_state->src_rect; + struct rect surf_clip = plane_state->clip_rect; int recout_full_x, recout_full_y; - if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 || - pipe_ctx->surface->rotation == ROTATION_ANGLE_270) + if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || + pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) rect_swap_helper(&surf_src); pipe_ctx->scl_data.recout.x = stream->dst.x; @@ -568,8 +568,8 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip - pipe_ctx->scl_data.recout.y; /* Handle h & vsplit */ - if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == - pipe_ctx->surface) { + if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == + pipe_ctx->plane_state) { if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { pipe_ctx->scl_data.recout.height /= 2; pipe_ctx->scl_data.recout.y += pipe_ctx->scl_data.recout.height; @@ -581,7 +581,7 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip pipe_ctx->scl_data.recout.width += pipe_ctx->scl_data.recout.width % 2; } } else if (pipe_ctx->bottom_pipe && - pipe_ctx->bottom_pipe->surface == pipe_ctx->surface) { + pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state) { if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) pipe_ctx->scl_data.recout.height /= 2; else @@ -592,13 +592,13 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip * * 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl * ratio) */ - recout_full_x = stream->dst.x + (surface->dst_rect.x - stream->src.x) + recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x) * stream->dst.width / stream->src.width - - surf_src.x * surface->dst_rect.width / surf_src.width + surf_src.x * plane_state->dst_rect.width / surf_src.width * stream->dst.width / stream->src.width; - recout_full_y = stream->dst.y + (surface->dst_rect.y - stream->src.y) + recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y) * stream->dst.height / stream->src.height - - surf_src.y * surface->dst_rect.height / surf_src.height + surf_src.y * plane_state->dst_rect.height / surf_src.height * stream->dst.height / stream->src.height; recout_skip->width = pipe_ctx->scl_data.recout.x - recout_full_x; @@ -607,24 +607,24 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) { - const struct dc_plane_state *surface = pipe_ctx->surface; + const struct dc_plane_state *plane_state = pipe_ctx->plane_state; const struct dc_stream_state *stream = pipe_ctx->stream; - struct rect surf_src = surface->src_rect; + struct rect surf_src = plane_state->src_rect; const int in_w = stream->src.width; const int in_h = stream->src.height; const int out_w = stream->dst.width; const int out_h = stream->dst.height; - if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 || - pipe_ctx->surface->rotation == ROTATION_ANGLE_270) + if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || + pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) rect_swap_helper(&surf_src); pipe_ctx->scl_data.ratios.horz = dal_fixed31_32_from_fraction( surf_src.width, - surface->dst_rect.width); + plane_state->dst_rect.width); pipe_ctx->scl_data.ratios.vert = dal_fixed31_32_from_fraction( surf_src.height, - surface->dst_rect.height); + plane_state->dst_rect.height); if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) pipe_ctx->scl_data.ratios.horz.value *= 2; @@ -649,13 +649,13 @@ static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip) { struct scaler_data *data = &pipe_ctx->scl_data; - struct rect src = pipe_ctx->surface->src_rect; + struct rect src = pipe_ctx->plane_state->src_rect; int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; - if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 || - pipe_ctx->surface->rotation == ROTATION_ANGLE_270) { + if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || + pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) { rect_swap_helper(&src); rect_swap_helper(&data->viewport_c); rect_swap_helper(&data->viewport); @@ -805,8 +805,8 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r data->inits.v_bot = dal_fixed31_32_add(data->inits.v, data->ratios.vert); data->inits.v_c_bot = dal_fixed31_32_add(data->inits.v_c, data->ratios.vert_c); - if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 || - pipe_ctx->surface->rotation == ROTATION_ANGLE_270) { + if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || + pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) { rect_swap_helper(&data->viewport_c); rect_swap_helper(&data->viewport); } @@ -814,7 +814,7 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) { - const struct dc_plane_state *surface = pipe_ctx->surface; + const struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; struct view recout_skip = { 0 }; bool res = false; @@ -824,7 +824,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) * Inits require viewport, taps, ratios and recout of split pipe */ pipe_ctx->scl_data.format = convert_pixel_format_to_dalsurface( - pipe_ctx->surface->format); + pipe_ctx->plane_state->format); calculate_scaling_ratios(pipe_ctx); @@ -846,14 +846,14 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) /* Taps calculations */ res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps( - pipe_ctx->xfm, &pipe_ctx->scl_data, &surface->scaling_quality); + pipe_ctx->xfm, &pipe_ctx->scl_data, &plane_state->scaling_quality); if (!res) { /* Try 24 bpp linebuffer */ pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP; res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps( - pipe_ctx->xfm, &pipe_ctx->scl_data, &surface->scaling_quality); + pipe_ctx->xfm, &pipe_ctx->scl_data, &plane_state->scaling_quality); } if (res) @@ -869,10 +869,10 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) pipe_ctx->scl_data.viewport.width, pipe_ctx->scl_data.viewport.x, pipe_ctx->scl_data.viewport.y, - surface->dst_rect.height, - surface->dst_rect.width, - surface->dst_rect.x, - surface->dst_rect.y); + plane_state->dst_rect.height, + plane_state->dst_rect.width, + plane_state->dst_rect.x, + plane_state->dst_rect.y); return res; } @@ -885,7 +885,7 @@ enum dc_status resource_build_scaling_params_for_context( int i; for (i = 0; i < MAX_PIPES; i++) { - if (context->res_ctx.pipe_ctx[i].surface != NULL && + if (context->res_ctx.pipe_ctx[i].plane_state != NULL && context->res_ctx.pipe_ctx[i].stream != NULL) if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i])) return DC_FAIL_SCALING; @@ -954,13 +954,13 @@ static struct pipe_ctx *acquire_free_pipe_for_stream( if (!head_pipe) ASSERT(0); - if (!head_pipe->surface) + if (!head_pipe->plane_state) return head_pipe; /* Re-use pipe already acquired for this stream if available*/ for (i = pool->pipe_count - 1; i >= 0; i--) { if (res_ctx->pipe_ctx[i].stream == stream && - !res_ctx->pipe_ctx[i].surface) { + !res_ctx->pipe_ctx[i].plane_state) { return &res_ctx->pipe_ctx[i]; } } @@ -987,7 +987,7 @@ static void release_free_pipes_for_stream( /* never release the topmost pipe*/ if (res_ctx->pipe_ctx[i].stream == stream && res_ctx->pipe_ctx[i].top_pipe && - !res_ctx->pipe_ctx[i].surface) { + !res_ctx->pipe_ctx[i].plane_state) { memset(&res_ctx->pipe_ctx[i], 0, sizeof(struct pipe_ctx)); } } @@ -1005,7 +1005,7 @@ static int acquire_first_split_pipe( struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; if (pipe_ctx->top_pipe && - pipe_ctx->top_pipe->surface == pipe_ctx->surface) { + pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state) { pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe; if (pipe_ctx->bottom_pipe) pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe; @@ -1028,7 +1028,7 @@ static int acquire_first_split_pipe( #endif bool resource_attach_surfaces_to_context( - struct dc_plane_state * const *surfaces, + struct dc_plane_state * const *plane_states, int surface_count, struct dc_stream_state *stream, struct validate_context *context, @@ -1057,25 +1057,25 @@ bool resource_attach_surfaces_to_context( /* retain new surfaces */ for (i = 0; i < surface_count; i++) - dc_surface_retain(surfaces[i]); + dc_plane_state_retain(plane_states[i]); /* detach surfaces from pipes */ for (i = 0; i < pool->pipe_count; i++) if (context->res_ctx.pipe_ctx[i].stream == stream) { - context->res_ctx.pipe_ctx[i].surface = NULL; + context->res_ctx.pipe_ctx[i].plane_state = NULL; context->res_ctx.pipe_ctx[i].bottom_pipe = NULL; } /* release existing surfaces*/ - for (i = 0; i < stream_status->surface_count; i++) - dc_surface_release(stream_status->surfaces[i]); + for (i = 0; i < stream_status->plane_count; i++) + dc_plane_state_release(stream_status->plane_states[i]); - for (i = surface_count; i < stream_status->surface_count; i++) - stream_status->surfaces[i] = NULL; + for (i = surface_count; i < stream_status->plane_count; i++) + stream_status->plane_states[i] = NULL; tail_pipe = NULL; for (i = 0; i < surface_count; i++) { - struct dc_plane_state *surface = surfaces[i]; + struct dc_plane_state *plane_state = plane_states[i]; struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream( context, pool, stream); @@ -1087,11 +1087,11 @@ bool resource_attach_surfaces_to_context( } #endif if (!free_pipe) { - stream_status->surfaces[i] = NULL; + stream_status->plane_states[i] = NULL; return false; } - free_pipe->surface = surface; + free_pipe->plane_state = plane_state; if (tail_pipe) { free_pipe->tg = tail_pipe->tg; @@ -1110,9 +1110,9 @@ bool resource_attach_surfaces_to_context( /* assign new surfaces*/ for (i = 0; i < surface_count; i++) - stream_status->surfaces[i] = surfaces[i]; + stream_status->plane_states[i] = plane_states[i]; - stream_status->surface_count = surface_count; + stream_status->plane_count = surface_count; return true; } @@ -1180,17 +1180,17 @@ bool resource_validate_attach_surfaces( old_context->streams[j], context->streams[i])) { if (!resource_attach_surfaces_to_context( - old_context->stream_status[j].surfaces, - old_context->stream_status[j].surface_count, + old_context->stream_status[j].plane_states, + old_context->stream_status[j].plane_count, context->streams[i], context, pool)) return false; context->stream_status[i] = old_context->stream_status[j]; } - if (set[i].surface_count != 0) + if (set[i].plane_count != 0) if (!resource_attach_surfaces_to_context( - set[i].surfaces, - set[i].surface_count, + set[i].plane_states, + set[i].plane_count, context->streams[i], context, pool)) return false; @@ -1351,13 +1351,13 @@ bool resource_is_stream_unchanged( static void copy_pipe_ctx( const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx) { - struct dc_plane_state *surface = to_pipe_ctx->surface; + struct dc_plane_state *plane_state = to_pipe_ctx->plane_state; struct dc_stream_state *stream = to_pipe_ctx->stream; *to_pipe_ctx = *from_pipe_ctx; to_pipe_ctx->stream = stream; - if (surface != NULL) - to_pipe_ctx->surface = surface; + if (plane_state != NULL) + to_pipe_ctx->plane_state = plane_state; } static struct dc_stream_state *find_pll_sharable_stream( @@ -2055,7 +2055,7 @@ static void set_spd_info_packet( static void set_hdr_static_info_packet( struct encoder_info_packet *info_packet, - struct dc_plane_state *surface, + struct dc_plane_state *plane_state, struct dc_stream_state *stream) { uint16_t i = 0; @@ -2063,10 +2063,10 @@ static void set_hdr_static_info_packet( struct dc_hdr_static_metadata hdr_metadata; uint32_t data; - if (!surface) + if (!plane_state) return; - hdr_metadata = surface->hdr_static_ctx; + hdr_metadata = plane_state->hdr_static_ctx; if (!hdr_metadata.hdr_supported) return; @@ -2204,11 +2204,11 @@ void dc_resource_validate_ctx_destruct(struct validate_context *context) int i, j; for (i = 0; i < context->stream_count; i++) { - for (j = 0; j < context->stream_status[i].surface_count; j++) - dc_surface_release( - context->stream_status[i].surfaces[j]); + for (j = 0; j < context->stream_status[i].plane_count; j++) + dc_plane_state_release( + context->stream_status[i].plane_states[j]); - context->stream_status[i].surface_count = 0; + context->stream_status[i].plane_count = 0; dc_stream_release(context->streams[i]); context->streams[i] = NULL; } @@ -2240,9 +2240,9 @@ void dc_resource_validate_ctx_copy_construct( for (i = 0; i < dst_ctx->stream_count; i++) { dc_stream_retain(dst_ctx->streams[i]); - for (j = 0; j < dst_ctx->stream_status[i].surface_count; j++) - dc_surface_retain( - dst_ctx->stream_status[i].surfaces[j]); + for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++) + dc_plane_state_retain( + dst_ctx->stream_status[i].plane_states[j]); } /* context refcount should not be overridden */ @@ -2288,7 +2288,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) set_spd_info_packet(&info->spd, pipe_ctx->stream); set_hdr_static_info_packet(&info->hdrsmd, - pipe_ctx->surface, pipe_ctx->stream); + pipe_ctx->plane_state, pipe_ctx->stream); } else if (dc_is_dp_signal(signal)) { set_vsc_info_packet(&info->vsc, pipe_ctx->stream); @@ -2296,7 +2296,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) set_spd_info_packet(&info->spd, pipe_ctx->stream); set_hdr_static_info_packet(&info->hdrsmd, - pipe_ctx->surface, pipe_ctx->stream); + pipe_ctx->plane_state, pipe_ctx->stream); } patch_gamut_packet_checksum(&info->gamut); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 7a87f38f2324..2b6506822cca 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -185,7 +185,7 @@ bool dc_stream_set_cursor_attributes( if (pipe_ctx->stream != stream || !pipe_ctx->ipp) continue; - if (pipe_ctx->top_pipe && pipe_ctx->surface != pipe_ctx->top_pipe->surface) + if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) continue; pipe_ctx->ipp->funcs->ipp_cursor_set_attributes( @@ -229,14 +229,14 @@ bool dc_stream_set_cursor_position( }; if (pipe_ctx->stream != stream || - !pipe_ctx->ipp || !pipe_ctx->surface) + !pipe_ctx->ipp || !pipe_ctx->plane_state) continue; - if (pipe_ctx->surface->address.type + if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) pos_cpy.enable = false; - if (pipe_ctx->top_pipe && pipe_ctx->surface != pipe_ctx->top_pipe->surface) + if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) pos_cpy.enable = false; ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index 941b3671375d..3bcca2d1872b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -34,75 +34,75 @@ /******************************************************************************* * Private functions ******************************************************************************/ -static bool construct(struct dc_context *ctx, struct dc_plane_state *surface) +static bool construct(struct dc_context *ctx, struct dc_plane_state *plane_state) { - surface->ctx = ctx; - memset(&surface->hdr_static_ctx, + plane_state->ctx = ctx; + memset(&plane_state->hdr_static_ctx, 0, sizeof(struct dc_hdr_static_metadata)); return true; } -static void destruct(struct dc_plane_state *surface) +static void destruct(struct dc_plane_state *plane_state) { - if (surface->gamma_correction != NULL) { - dc_gamma_release(&surface->gamma_correction); + if (plane_state->gamma_correction != NULL) { + dc_gamma_release(&plane_state->gamma_correction); } - if (surface->in_transfer_func != NULL) { + if (plane_state->in_transfer_func != NULL) { dc_transfer_func_release( - surface->in_transfer_func); - surface->in_transfer_func = NULL; + plane_state->in_transfer_func); + plane_state->in_transfer_func = NULL; } } /******************************************************************************* * Public functions ******************************************************************************/ -void enable_surface_flip_reporting(struct dc_plane_state *surface, +void enable_surface_flip_reporting(struct dc_plane_state *plane_state, uint32_t controller_id) { - surface->irq_source = controller_id + DC_IRQ_SOURCE_PFLIP1 - 1; + plane_state->irq_source = controller_id + DC_IRQ_SOURCE_PFLIP1 - 1; /*register_flip_interrupt(surface);*/ } -struct dc_plane_state *dc_create_surface(const struct dc *dc) +struct dc_plane_state *dc_create_plane_state(const struct dc *dc) { struct core_dc *core_dc = DC_TO_CORE(dc); - struct dc_plane_state *surface = dm_alloc(sizeof(*surface)); + struct dc_plane_state *plane_state = dm_alloc(sizeof(*plane_state)); - if (NULL == surface) + if (NULL == plane_state) goto alloc_fail; - if (false == construct(core_dc->ctx, surface)) + if (false == construct(core_dc->ctx, plane_state)) goto construct_fail; - ++surface->ref_count; + ++plane_state->ref_count; - return surface; + return plane_state; construct_fail: - dm_free(surface); + dm_free(plane_state); alloc_fail: return NULL; } -const struct dc_surface_status *dc_surface_get_status( - const struct dc_plane_state *dc_surface) +const struct dc_plane_status *dc_plane_get_status( + const struct dc_plane_state *plane_state) { - const struct dc_surface_status *surface_status; + const struct dc_plane_status *plane_status; struct core_dc *core_dc; int i; - if (!dc_surface || - !dc_surface->ctx || - !dc_surface->ctx->dc) { + if (!plane_state || + !plane_state->ctx || + !plane_state->ctx->dc) { ASSERT(0); return NULL; /* remove this if above assert never hit */ } - surface_status = &dc_surface->status; - core_dc = DC_TO_CORE(dc_surface->ctx->dc); + plane_status = &plane_state->status; + core_dc = DC_TO_CORE(plane_state->ctx->dc); if (core_dc->current_context == NULL) return NULL; @@ -111,29 +111,29 @@ const struct dc_surface_status *dc_surface_get_status( struct pipe_ctx *pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[i]; - if (pipe_ctx->surface != dc_surface) + if (pipe_ctx->plane_state != plane_state) continue; core_dc->hwss.update_pending_status(pipe_ctx); } - return surface_status; + return plane_status; } -void dc_surface_retain(struct dc_plane_state *surface) +void dc_plane_state_retain(struct dc_plane_state *plane_state) { - ASSERT(surface->ref_count > 0); - ++surface->ref_count; + ASSERT(plane_state->ref_count > 0); + ++plane_state->ref_count; } -void dc_surface_release(struct dc_plane_state *surface) +void dc_plane_state_release(struct dc_plane_state *plane_state) { - ASSERT(surface->ref_count > 0); - --surface->ref_count; + ASSERT(plane_state->ref_count > 0); + --plane_state->ref_count; - if (surface->ref_count == 0) { - destruct(surface); - dm_free(surface); + if (plane_state->ref_count == 0) { + destruct(plane_state); + dm_free(plane_state); } } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index ab805965e321..d1a6398043a3 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -47,7 +47,7 @@ struct dc_caps { uint32_t max_links; uint32_t max_audios; uint32_t max_slave_planes; - uint32_t max_surfaces; + uint32_t max_planes; uint32_t max_downscale_ratio; uint32_t i2c_speed_in_khz; @@ -303,7 +303,7 @@ struct dc_transfer_func { * the last requested address and the currently active address so the called * can determine if there are any outstanding flips */ -struct dc_surface_status { +struct dc_plane_status { struct dc_plane_address requested_address; struct dc_plane_address current_address; bool is_flip_pending; @@ -338,7 +338,7 @@ struct dc_plane_state { bool horizontal_mirror; /* private to DC core */ - struct dc_surface_status status; + struct dc_plane_status status; struct dc_context *ctx; /* private to dc_surface.c */ @@ -385,12 +385,12 @@ struct dc_surface_update { /* * Create a new surface with default parameters; */ -struct dc_plane_state *dc_create_surface(const struct dc *dc); -const struct dc_surface_status *dc_surface_get_status( - const struct dc_plane_state *dc_surface); +struct dc_plane_state *dc_create_plane_state(const struct dc *dc); +const struct dc_plane_status *dc_plane_get_status( + const struct dc_plane_state *plane_state); -void dc_surface_retain(struct dc_plane_state *dc_surface); -void dc_surface_release(struct dc_plane_state *dc_surface); +void dc_plane_state_retain(struct dc_plane_state *plane_state); +void dc_plane_state_release(struct dc_plane_state *plane_state); void dc_gamma_retain(struct dc_gamma *dc_gamma); void dc_gamma_release(struct dc_gamma **dc_gamma); @@ -422,10 +422,10 @@ struct dc_flip_addrs { * This does not trigger a flip. No surface address is programmed. */ -bool dc_commit_surfaces_to_stream( +bool dc_commit_planes_to_stream( struct dc *dc, - struct dc_plane_state **dc_surfaces, - uint8_t surface_count, + struct dc_plane_state **plane_states, + uint8_t new_plane_count, struct dc_stream_state *stream); bool dc_post_update_surfaces_to_stream( @@ -469,8 +469,8 @@ enum surface_update_type { struct dc_stream_status { int primary_otg_inst; - int surface_count; - struct dc_plane_state *surfaces[MAX_SURFACE_NUM]; + int plane_count; + struct dc_plane_state *plane_states[MAX_SURFACE_NUM]; /* * link this stream passes through @@ -546,7 +546,7 @@ bool dc_is_stream_unchanged( * */ -void dc_update_surfaces_and_stream(struct dc *dc, +void dc_update_planes_and_stream(struct dc *dc, struct dc_surface_update *surface_updates, int surface_count, struct dc_stream_state *dc_stream, struct dc_stream_update *stream_update); @@ -582,8 +582,8 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, */ struct dc_validation_set { struct dc_stream_state *stream; - struct dc_plane_state *surfaces[MAX_SURFACES]; - uint8_t surface_count; + struct dc_plane_state *plane_states[MAX_SURFACES]; + uint8_t plane_count; }; bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c index af59ab93796a..8140ff31c3bd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c @@ -197,9 +197,9 @@ void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, } /* Only use LUT for 8 bit formats */ -bool dce_use_lut(const struct dc_plane_state *surface) +bool dce_use_lut(const struct dc_plane_state *plane_state) { - switch (surface->format) { + switch (plane_state->format) { case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: return true; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index d5cb98a92c53..a0531b3aa6a1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -552,5 +552,5 @@ void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, struct clock_source *clk_src, unsigned int tg_inst); -bool dce_use_lut(const struct dc_plane_state *surface); +bool dce_use_lut(const struct dc_plane_state *plane_state); #endif /*__DCE_HWSEQ_H__*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 98fb7f02a6fe..46f0c71fbac4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -705,13 +705,13 @@ static bool dce100_validate_surface_sets( int i; for (i = 0; i < set_count; i++) { - if (set[i].surface_count == 0) + if (set[i].plane_count == 0) continue; - if (set[i].surface_count > 1) + if (set[i].plane_count > 1) return false; - if (set[i].surfaces[0]->format + if (set[i].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; } @@ -958,7 +958,7 @@ static bool construct( } } - dc->public.caps.max_surfaces = pool->base.pipe_count; + dc->public.caps.max_planes = pool->base.pipe_count; if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index e4310a376116..ea9ce87d348a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -215,11 +215,11 @@ static bool dce110_enable_display_power_gating( } static void build_prescale_params(struct ipp_prescale_params *prescale_params, - const struct dc_plane_state *surface) + const struct dc_plane_state *plane_state) { prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; - switch (surface->format) { + switch (plane_state->format) { case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: prescale_params->scale = 0x2020; @@ -240,7 +240,7 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params, static bool dce110_set_input_transfer_func( struct pipe_ctx *pipe_ctx, - const struct dc_plane_state *surface) + const struct dc_plane_state *plane_state) { struct input_pixel_processor *ipp = pipe_ctx->ipp; const struct dc_transfer_func *tf = NULL; @@ -250,14 +250,14 @@ static bool dce110_set_input_transfer_func( if (ipp == NULL) return false; - if (surface->in_transfer_func) - tf = surface->in_transfer_func; + if (plane_state->in_transfer_func) + tf = plane_state->in_transfer_func; - build_prescale_params(&prescale_params, surface); + build_prescale_params(&prescale_params, plane_state); ipp->funcs->ipp_program_prescale(ipp, &prescale_params); - if (surface->gamma_correction && dce_use_lut(surface)) - ipp->funcs->ipp_program_input_lut(ipp, surface->gamma_correction); + if (plane_state->gamma_correction && dce_use_lut(plane_state)) + ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction); if (tf == NULL) { /* Default case if no input transfer function specified */ @@ -1119,7 +1119,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( if ((!pipe_ctx_old || memcmp(&pipe_ctx_old->scl_data, &pipe_ctx->scl_data, sizeof(struct scaler_data)) != 0) && - pipe_ctx->surface) { + pipe_ctx->plane_state) { program_scaler(dc, pipe_ctx); } @@ -1916,11 +1916,11 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx) struct default_adjustment default_adjust = { 0 }; default_adjust.force_hw_default = false; - if (pipe_ctx->surface == NULL) + if (pipe_ctx->plane_state == NULL) default_adjust.in_color_space = COLOR_SPACE_SRGB; else default_adjust.in_color_space = - pipe_ctx->surface->color_space; + pipe_ctx->plane_state->color_space; if (pipe_ctx->stream == NULL) default_adjust.out_color_space = COLOR_SPACE_SRGB; else @@ -1971,16 +1971,16 @@ static void program_surface_visibility(const struct core_dc *dc, /* For now we are supporting only two pipes */ ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); - if (pipe_ctx->bottom_pipe->surface->visible) { - if (pipe_ctx->surface->visible) + if (pipe_ctx->bottom_pipe->plane_state->visible) { + if (pipe_ctx->plane_state->visible) blender_mode = BLND_MODE_BLENDING; else blender_mode = BLND_MODE_OTHER_PIPE; - } else if (!pipe_ctx->surface->visible) + } else if (!pipe_ctx->plane_state->visible) blank_target = true; - } else if (!pipe_ctx->surface->visible) + } else if (!pipe_ctx->plane_state->visible) blank_target = true; dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode); @@ -2038,7 +2038,7 @@ static void set_plane_config( struct resource_context *res_ctx) { struct mem_input *mi = pipe_ctx->mi; - struct dc_plane_state *surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct xfm_grph_csc_adjustment adjust; struct out_csc_color_matrix tbl_entry; unsigned int i; @@ -2103,57 +2103,57 @@ static void set_plane_config( mi->funcs->mem_input_program_surface_config( mi, - surface->format, - &surface->tiling_info, - &surface->plane_size, - surface->rotation, + plane_state->format, + &plane_state->tiling_info, + &plane_state->plane_size, + plane_state->rotation, NULL, false); if (mi->funcs->set_blank) - mi->funcs->set_blank(mi, pipe_ctx->surface->visible); + mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); if (dc->public.config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( pipe_ctx->mi, - surface->format, - &surface->tiling_info, - surface->rotation); + plane_state->format, + &plane_state->tiling_info, + plane_state->rotation); } static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ctx) { - struct dc_plane_state *surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; - if (surface == NULL) + if (plane_state == NULL) return; pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr( pipe_ctx->mi, - &surface->address, - surface->flip_immediate); + &plane_state->address, + plane_state->flip_immediate); - surface->status.requested_address = surface->address; + plane_state->status.requested_address = plane_state->address; } void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) { - struct dc_plane_state *surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; - if (surface == NULL) + if (plane_state == NULL) return; - surface->status.is_flip_pending = + plane_state->status.is_flip_pending = pipe_ctx->mi->funcs->mem_input_is_flip_pending( pipe_ctx->mi); - if (surface->status.is_flip_pending && !surface->visible) + if (plane_state->status.is_flip_pending && !plane_state->visible) pipe_ctx->mi->current_address = pipe_ctx->mi->request_address; - surface->status.current_address = pipe_ctx->mi->current_address; + plane_state->status.current_address = pipe_ctx->mi->current_address; if (pipe_ctx->mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && pipe_ctx->tg->funcs->is_stereo_left_eye) { - surface->status.is_right_eye =\ + plane_state->status.is_right_eye =\ !pipe_ctx->tg->funcs->is_stereo_left_eye(pipe_ctx->tg); } } @@ -2490,7 +2490,7 @@ static void dce110_program_front_end_for_pipe( { struct mem_input *mi = pipe_ctx->mi; struct pipe_ctx *old_pipe = NULL; - struct dc_plane_state *surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct xfm_grph_csc_adjustment adjust; struct out_csc_color_matrix tbl_entry; unsigned int i; @@ -2558,21 +2558,21 @@ static void dce110_program_front_end_for_pipe( mi->funcs->mem_input_program_surface_config( mi, - surface->format, - &surface->tiling_info, - &surface->plane_size, - surface->rotation, + plane_state->format, + &plane_state->tiling_info, + &plane_state->plane_size, + plane_state->rotation, NULL, false); if (mi->funcs->set_blank) - mi->funcs->set_blank(mi, pipe_ctx->surface->visible); + mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); if (dc->public.config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( pipe_ctx->mi, - surface->format, - &surface->tiling_info, - surface->rotation); + plane_state->format, + &plane_state->tiling_info, + plane_state->rotation); dm_logger_write(dc->ctx->logger, LOG_SURFACE, "Pipe:%d 0x%x: addr hi:0x%x, " @@ -2581,21 +2581,21 @@ static void dce110_program_front_end_for_pipe( " %d; dst: %d, %d, %d, %d;" "clip: %d, %d, %d, %d\n", pipe_ctx->pipe_idx, - pipe_ctx->surface, - pipe_ctx->surface->address.grph.addr.high_part, - pipe_ctx->surface->address.grph.addr.low_part, - pipe_ctx->surface->src_rect.x, - pipe_ctx->surface->src_rect.y, - pipe_ctx->surface->src_rect.width, - pipe_ctx->surface->src_rect.height, - pipe_ctx->surface->dst_rect.x, - pipe_ctx->surface->dst_rect.y, - pipe_ctx->surface->dst_rect.width, - pipe_ctx->surface->dst_rect.height, - pipe_ctx->surface->clip_rect.x, - pipe_ctx->surface->clip_rect.y, - pipe_ctx->surface->clip_rect.width, - pipe_ctx->surface->clip_rect.height); + pipe_ctx->plane_state, + pipe_ctx->plane_state->address.grph.addr.high_part, + pipe_ctx->plane_state->address.grph.addr.low_part, + pipe_ctx->plane_state->src_rect.x, + pipe_ctx->plane_state->src_rect.y, + pipe_ctx->plane_state->src_rect.width, + pipe_ctx->plane_state->src_rect.height, + pipe_ctx->plane_state->dst_rect.x, + pipe_ctx->plane_state->dst_rect.y, + pipe_ctx->plane_state->dst_rect.width, + pipe_ctx->plane_state->dst_rect.height, + pipe_ctx->plane_state->clip_rect.x, + pipe_ctx->plane_state->clip_rect.y, + pipe_ctx->plane_state->clip_rect.width, + pipe_ctx->plane_state->clip_rect.height); dm_logger_write(dc->ctx->logger, LOG_SURFACE, "Pipe %d: width, height, x, y\n" @@ -2614,19 +2614,18 @@ static void dce110_program_front_end_for_pipe( static void dce110_apply_ctx_for_surface( struct core_dc *dc, - const struct dc_plane_state *surface, + const struct dc_plane_state *plane_state, struct validate_context *context) { int i; - /* TODO remove when removing the surface reset workaroud*/ - if (!surface) + if (!plane_state) return; for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - if (pipe_ctx->surface != surface) + if (pipe_ctx->plane_state != plane_state) continue; dce110_program_front_end_for_pipe(dc, pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 89b21bd57a35..f580da1b3249 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -764,9 +764,9 @@ static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigne { if (pipe_ctx->pipe_idx != underlay_idx) return true; - if (!pipe_ctx->surface) + if (!pipe_ctx->plane_state) return false; - if (pipe_ctx->surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) + if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; return true; } @@ -901,22 +901,22 @@ static bool dce110_validate_surface_sets( int i; for (i = 0; i < set_count; i++) { - if (set[i].surface_count == 0) + if (set[i].plane_count == 0) continue; - if (set[i].surface_count > 2) + if (set[i].plane_count > 2) return false; - if (set[i].surfaces[0]->format + if (set[i].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; - if (set[i].surface_count == 2) { - if (set[i].surfaces[1]->format + if (set[i].plane_count == 2) { + if (set[i].plane_states[1]->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; - if (set[i].surfaces[1]->src_rect.width > 1920 - || set[i].surfaces[1]->src_rect.height > 1080) + if (set[i].plane_states[1]->src_rect.width > 1920 + || set[i].plane_states[1]->src_rect.height > 1080) return false; if (set[i].stream->timing.pixel_encoding != PIXEL_ENCODING_RGB) @@ -1351,7 +1351,7 @@ static bool construct( if (!dce110_hw_sequencer_construct(dc)) goto res_create_fail; - dc->public.caps.max_surfaces = pool->base.pipe_count; + dc->public.caps.max_planes = pool->base.pipe_count; bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id); diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 68554d6edd94..420434d7283e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -889,13 +889,13 @@ static bool dce112_validate_surface_sets( int i; for (i = 0; i < set_count; i++) { - if (set[i].surface_count == 0) + if (set[i].plane_count == 0) continue; - if (set[i].surface_count > 1) + if (set[i].plane_count > 1) return false; - if (set[i].surfaces[0]->format + if (set[i].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; } @@ -1319,7 +1319,7 @@ static bool construct( &res_create_funcs)) goto res_create_fail; - dc->public.caps.max_surfaces = pool->base.pipe_count; + dc->public.caps.max_planes = pool->base.pipe_count; /* Create hardware sequencer */ if (!dce112_hw_sequencer_construct(dc)) diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index 45f5fd63ce14..6448d15c02f5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -982,7 +982,7 @@ static bool construct( if (!dce120_hw_sequencer_create(dc)) goto controller_create_fail; - dc->public.caps.max_surfaces = pool->base.pipe_count; + dc->public.caps.max_planes = pool->base.pipe_count; bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id); diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 734b35eddeed..7473f58584c3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -722,13 +722,13 @@ static bool dce80_validate_surface_sets( int i; for (i = 0; i < set_count; i++) { - if (set[i].surface_count == 0) + if (set[i].plane_count == 0) continue; - if (set[i].surface_count > 1) + if (set[i].plane_count > 1) return false; - if (set[i].surfaces[0]->format + if (set[i].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; } @@ -959,7 +959,7 @@ static bool construct( } } - dc->public.caps.max_surfaces = pool->base.pipe_count; + dc->public.caps.max_planes = pool->base.pipe_count; if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 866f63d1259d..5922cf8272f5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -986,7 +986,7 @@ static void reset_hw_ctx_wrap( struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; if (!pipe_ctx->stream || - !pipe_ctx->surface || + !pipe_ctx->plane_state || pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { plane_atomic_disconnect(dc, i); @@ -1010,13 +1010,13 @@ static void reset_hw_ctx_wrap( /*if (!pipe_ctx_old->stream) continue;*/ - if (pipe_ctx->stream && pipe_ctx->surface + if (pipe_ctx->stream && pipe_ctx->plane_state && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) continue; plane_atomic_disable(dc, i); - if (!pipe_ctx->stream || !pipe_ctx->surface) + if (!pipe_ctx->stream || !pipe_ctx->plane_state) plane_atomic_power_down(dc, i); } @@ -1038,24 +1038,24 @@ static void reset_hw_ctx_wrap( static bool patch_address_for_sbs_tb_stereo( struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) { - struct dc_plane_state *surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; bool sec_split = pipe_ctx->top_pipe && - pipe_ctx->top_pipe->surface == pipe_ctx->surface; - if (sec_split && surface->address.type == PLN_ADDR_TYPE_GRPH_STEREO && + pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; + if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && (pipe_ctx->stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE || pipe_ctx->stream->timing.timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { - *addr = surface->address.grph_stereo.left_addr; - surface->address.grph_stereo.left_addr = - surface->address.grph_stereo.right_addr; + *addr = plane_state->address.grph_stereo.left_addr; + plane_state->address.grph_stereo.left_addr = + plane_state->address.grph_stereo.right_addr; return true; } else { if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && - surface->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { - surface->address.type = PLN_ADDR_TYPE_GRPH_STEREO; - surface->address.grph_stereo.right_addr = - surface->address.grph_stereo.left_addr; + plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { + plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO; + plane_state->address.grph_stereo.right_addr = + plane_state->address.grph_stereo.left_addr; } } return false; @@ -1065,22 +1065,22 @@ static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ct { bool addr_patched = false; PHYSICAL_ADDRESS_LOC addr; - struct dc_plane_state *surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; - if (surface == NULL) + if (plane_state == NULL) return; addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr( pipe_ctx->mi, - &surface->address, - surface->flip_immediate); - surface->status.requested_address = surface->address; + &plane_state->address, + plane_state->flip_immediate); + plane_state->status.requested_address = plane_state->address; if (addr_patched) - pipe_ctx->surface->address.grph_stereo.left_addr = addr; + pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; } static bool dcn10_set_input_transfer_func( - struct pipe_ctx *pipe_ctx, const struct dc_plane_state *surface) + struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) { struct input_pixel_processor *ipp = pipe_ctx->ipp; const struct dc_transfer_func *tf = NULL; @@ -1089,12 +1089,12 @@ static bool dcn10_set_input_transfer_func( if (ipp == NULL) return false; - if (surface->in_transfer_func) - tf = surface->in_transfer_func; + if (plane_state->in_transfer_func) + tf = plane_state->in_transfer_func; - if (surface->gamma_correction && dce_use_lut(surface)) + if (plane_state->gamma_correction && dce_use_lut(plane_state)) ipp->funcs->ipp_program_input_lut(ipp, - surface->gamma_correction); + plane_state->gamma_correction); if (tf == NULL) ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); @@ -1689,7 +1689,7 @@ static void dcn10_power_on_fe( struct pipe_ctx *pipe_ctx, struct validate_context *context) { - struct dc_plane_state *dc_surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct dce_hwseq *hws = dc->hwseq; power_on_plane(dc->hwseq, @@ -1704,24 +1704,24 @@ static void dcn10_power_on_fe( OPP_PIPE_CLOCK_EN, 1); /*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 0x1f);*/ - if (dc_surface) { + if (plane_state) { dm_logger_write(dc->ctx->logger, LOG_DC, "Pipe:%d 0x%x: addr hi:0x%x, " "addr low:0x%x, " "src: %d, %d, %d," " %d; dst: %d, %d, %d, %d;\n", pipe_ctx->pipe_idx, - dc_surface, - dc_surface->address.grph.addr.high_part, - dc_surface->address.grph.addr.low_part, - dc_surface->src_rect.x, - dc_surface->src_rect.y, - dc_surface->src_rect.width, - dc_surface->src_rect.height, - dc_surface->dst_rect.x, - dc_surface->dst_rect.y, - dc_surface->dst_rect.width, - dc_surface->dst_rect.height); + plane_state, + plane_state->address.grph.addr.high_part, + plane_state->address.grph.addr.low_part, + plane_state->src_rect.x, + plane_state->src_rect.y, + plane_state->src_rect.width, + plane_state->src_rect.height, + plane_state->dst_rect.x, + plane_state->dst_rect.y, + plane_state->dst_rect.width, + plane_state->dst_rect.height); dm_logger_write(dc->ctx->logger, LOG_HW_SET_MODE, "Pipe %d: width, height, x, y\n" @@ -1805,7 +1805,7 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, } static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx) { - if (pipe_ctx->surface->visible) + if (pipe_ctx->plane_state->visible) return true; if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe)) return true; @@ -1814,7 +1814,7 @@ static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx) static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx) { - if (pipe_ctx->surface->visible) + if (pipe_ctx->plane_state->visible) return true; if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) return true; @@ -1823,7 +1823,7 @@ static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx) static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx) { - if (pipe_ctx->surface->visible) + if (pipe_ctx->plane_state->visible) return true; if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) return true; @@ -1898,12 +1898,12 @@ static void update_dchubp_dpp( struct dce_hwseq *hws = dc->hwseq; struct mem_input *mi = pipe_ctx->mi; struct input_pixel_processor *ipp = pipe_ctx->ipp; - struct dc_plane_state *surface = pipe_ctx->surface; - union plane_size size = surface->plane_size; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; + union plane_size size = plane_state->plane_size; struct default_adjustment ocsc = {0}; struct mpcc_cfg mpcc_cfg = {0}; struct pipe_ctx *top_pipe; - bool per_pixel_alpha = surface->per_pixel_alpha && pipe_ctx->bottom_pipe; + bool per_pixel_alpha = plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; /* TODO: proper fix once fpga works */ /* depends on DML calculation, DPP clock value may change dynamically */ @@ -1936,12 +1936,12 @@ static void update_dchubp_dpp( if (dc->public.config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( pipe_ctx->mi, - surface->format, - &surface->tiling_info, - surface->rotation); + plane_state->format, + &plane_state->tiling_info, + plane_state->rotation); ipp->funcs->ipp_setup(ipp, - surface->format, + plane_state->format, 1, IPP_OUTPUT_FORMAT_12_BIT_FIX); @@ -1982,12 +1982,12 @@ static void update_dchubp_dpp( mi->funcs->mem_input_program_surface_config( mi, - surface->format, - &surface->tiling_info, + plane_state->format, + &plane_state->tiling_info, &size, - surface->rotation, - &surface->dcc, - surface->horizontal_mirror); + plane_state->rotation, + &plane_state->dcc, + plane_state->horizontal_mirror); mi->funcs->set_blank(mi, !is_pipe_tree_visible(pipe_ctx)); } @@ -2025,7 +2025,7 @@ static void program_all_pipe_in_tree( pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, !is_pipe_tree_visible(pipe_ctx)); } - if (pipe_ctx->surface != NULL) { + if (pipe_ctx->plane_state != NULL) { dcn10_power_on_fe(dc, pipe_ctx, context); update_dchubp_dpp(dc, pipe_ctx, context); } @@ -2068,7 +2068,7 @@ static void dcn10_pplib_apply_display_requirements( static void dcn10_apply_ctx_for_surface( struct core_dc *dc, - const struct dc_plane_state *surface, + const struct dc_plane_state *plane_state, struct validate_context *context) { int i, be_idx; @@ -2076,11 +2076,11 @@ static void dcn10_apply_ctx_for_surface( if (dc->public.debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); - if (!surface) + if (!plane_state) return; for (be_idx = 0; be_idx < dc->res_pool->pipe_count; be_idx++) - if (surface == context->res_ctx.pipe_ctx[be_idx].surface) + if (plane_state == context->res_ctx.pipe_ctx[be_idx].plane_state) break; /* reset unused mpcc */ @@ -2089,7 +2089,7 @@ static void dcn10_apply_ctx_for_surface( struct pipe_ctx *old_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i]; - if (!pipe_ctx->surface && !old_pipe_ctx->surface) + if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) continue; /* @@ -2097,7 +2097,7 @@ static void dcn10_apply_ctx_for_surface( * fairly hacky right now, using opp_id as indicator */ - if (pipe_ctx->surface && !old_pipe_ctx->surface) { + if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) { if (pipe_ctx->mi->opp_id != 0xf && pipe_ctx->tg->inst == be_idx) { dcn10_power_down_fe(dc, pipe_ctx->pipe_idx); /* @@ -2109,7 +2109,7 @@ static void dcn10_apply_ctx_for_surface( } - if ((!pipe_ctx->surface && old_pipe_ctx->surface) + if ((!pipe_ctx->plane_state && old_pipe_ctx->plane_state) || (!pipe_ctx->stream && old_pipe_ctx->stream)) { if (old_pipe_ctx->tg->inst != be_idx) continue; @@ -2135,7 +2135,7 @@ static void dcn10_apply_ctx_for_surface( old_pipe_ctx->top_pipe = NULL; old_pipe_ctx->bottom_pipe = NULL; - old_pipe_ctx->surface = NULL; + old_pipe_ctx->plane_state = NULL; dm_logger_write(dc->ctx->logger, LOG_DC, "Reset mpcc for pipe %d\n", @@ -2146,7 +2146,7 @@ static void dcn10_apply_ctx_for_surface( for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - if (pipe_ctx->surface != surface) + if (pipe_ctx->plane_state != plane_state) continue; /* looking for top pipe to program */ @@ -2468,34 +2468,34 @@ static bool dcn10_dummy_display_power_gating( void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) { - struct dc_plane_state *surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct timing_generator *tg = pipe_ctx->tg; - if (surface->ctx->dc->debug.sanity_checks) { - struct core_dc *dc = DC_TO_CORE(surface->ctx->dc); + if (plane_state->ctx->dc->debug.sanity_checks) { + struct core_dc *dc = DC_TO_CORE(plane_state->ctx->dc); verify_allow_pstate_change_high(dc->hwseq); } - if (surface == NULL) + if (plane_state == NULL) return; - surface->status.is_flip_pending = + plane_state->status.is_flip_pending = pipe_ctx->mi->funcs->mem_input_is_flip_pending( pipe_ctx->mi); /* DCN we read INUSE address in MI, do we still need this wa? */ - if (surface->status.is_flip_pending && - !surface->visible) { + if (plane_state->status.is_flip_pending && + !plane_state->visible) { pipe_ctx->mi->current_address = pipe_ctx->mi->request_address; BREAK_TO_DEBUGGER(); } - surface->status.current_address = pipe_ctx->mi->current_address; + plane_state->status.current_address = pipe_ctx->mi->current_address; if (pipe_ctx->mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && tg->funcs->is_stereo_left_eye) { - surface->status.is_right_eye = + plane_state->status.is_right_eye = !tg->funcs->is_stereo_left_eye(pipe_ctx->tg); } } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 5a9fcbc22d04..3fe6df92f91f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -1406,7 +1406,7 @@ static bool construct( goto res_create_fail; dcn10_hw_sequencer_construct(dc); - dc->public.caps.max_surfaces = pool->base.pipe_count; + dc->public.caps.max_planes = pool->base.pipe_count; dc->public.cap_funcs = cap_funcs; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index d5c0f9e34ce9..3b3330c563e0 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -36,7 +36,7 @@ #define MAX_CLOCK_SOURCES 7 -void enable_surface_flip_reporting(struct dc_plane_state *dc_surface, +void enable_surface_flip_reporting(struct dc_plane_state *plane_state, uint32_t controller_id); #include "grph_object_id.h" @@ -153,7 +153,7 @@ struct resource_pool { }; struct pipe_ctx { - struct dc_plane_state *surface; + struct dc_plane_state *plane_state; struct dc_stream_state *stream; struct mem_input *mi; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 7e03f8d45b2b..5d075f93b4b9 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -59,7 +59,7 @@ struct hw_sequencer_funcs { void (*apply_ctx_for_surface)( struct core_dc *dc, - const struct dc_plane_state *surface, + const struct dc_plane_state *plane_state, struct validate_context *context); void (*set_plane_config)( @@ -88,7 +88,7 @@ struct hw_sequencer_funcs { bool (*set_input_transfer_func)( struct pipe_ctx *pipe_ctx, - const struct dc_plane_state *surface); + const struct dc_plane_state *plane_state); bool (*set_output_transfer_func)( struct pipe_ctx *pipe_ctx, diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index aef1197cf749..7f30d9937d10 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -119,7 +119,7 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( struct dc_stream_state *stream); bool resource_attach_surfaces_to_context( - struct dc_plane_state *const *surfaces, + struct dc_plane_state *const *plane_state, int surface_count, struct dc_stream_state *dc_stream, struct validate_context *context, diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index 0e978d921fdf..beb790937769 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -77,7 +77,7 @@ void logger_write(struct dal_logger *logger, void pre_surface_trace( const struct dc *dc, - const struct dc_plane_state *const *surfaces, + const struct dc_plane_state *const *plane_states, int surface_count); void update_surface_trace( -- cgit v1.2.3 From fb3466a450cc4684654367ae2f47fc3fc7846574 Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Tue, 1 Aug 2017 15:00:25 -0400 Subject: drm/amd/display: Flattening core_dc to dc -Flattening core_dc to dc Signed-off-by: Bhawanpreet Lakha Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 73 +++++----- drivers/gpu/drm/amd/display/dc/core/dc.c | 162 ++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 20 +-- .../gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 3 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 19 ++- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 1 - drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 22 +-- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 14 +- drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 10 +- drivers/gpu/drm/amd/display/dc/dc.h | 71 +++++++-- .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 5 +- drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 10 +- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 4 +- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 2 +- .../amd/display/dc/dce100/dce100_hw_sequencer.c | 9 +- .../amd/display/dc/dce100/dce100_hw_sequencer.h | 6 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 22 +-- .../drm/amd/display/dc/dce100/dce100_resource.h | 4 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 72 ++++----- .../amd/display/dc/dce110/dce110_hw_sequencer.h | 12 +- .../drm/amd/display/dc/dce110/dce110_resource.c | 26 ++-- .../drm/amd/display/dc/dce110/dce110_resource.h | 4 +- .../amd/display/dc/dce112/dce112_hw_sequencer.c | 5 +- .../amd/display/dc/dce112/dce112_hw_sequencer.h | 4 +- .../drm/amd/display/dc/dce112/dce112_resource.c | 26 ++-- .../drm/amd/display/dc/dce112/dce112_resource.h | 10 +- .../amd/display/dc/dce120/dce120_hw_sequencer.c | 5 +- .../amd/display/dc/dce120/dce120_hw_sequencer.h | 4 +- .../drm/amd/display/dc/dce120/dce120_resource.c | 18 +-- .../drm/amd/display/dc/dce120/dce120_resource.h | 4 +- .../drm/amd/display/dc/dce80/dce80_hw_sequencer.c | 5 +- .../drm/amd/display/dc/dce80/dce80_hw_sequencer.h | 4 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 46 +++--- .../gpu/drm/amd/display/dc/dce80/dce80_resource.h | 8 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c | 1 - .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 108 +++++++------- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 4 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 34 ++--- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.h | 4 +- drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 55 ------- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 8 +- drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 12 +- drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 1 + drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 50 ++++--- drivers/gpu/drm/amd/display/dc/inc/resource.h | 15 +- .../amd/display/dc/irq/dce110/irq_service_dce110.c | 6 +- .../amd/display/dc/irq/dce80/irq_service_dce80.c | 1 - .../gpu/drm/amd/display/include/logger_interface.h | 10 +- .../drm/amd/display/modules/freesync/freesync.c | 11 +- 51 files changed, 507 insertions(+), 527 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/dc/inc/core_dc.h (limited to 'drivers/gpu/drm/amd/display/include/logger_interface.h') diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 6fb1b9a91993..f0dfd3c3c12c 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -27,7 +27,6 @@ #include "dcn_calcs.h" #include "dcn_calc_auto.h" #include "dc.h" -#include "core_dc.h" #include "dal_asic_id.h" #include "resource.h" @@ -399,7 +398,7 @@ static void pipe_ctx_to_e2e_pipe_params ( } static void dcn_bw_calc_rq_dlg_ttu( - const struct core_dc *dc, + const struct dc *dc, const struct dcn_bw_internal_vars *v, struct pipe_ctx *pipe, int in_idx) @@ -674,45 +673,45 @@ static void calc_wm_sets_and_perf_params( context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a; } -static bool dcn_bw_apply_registry_override(struct core_dc *dc) +static bool dcn_bw_apply_registry_override(struct dc *dc) { bool updated = false; kernel_fpu_begin(); - if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->public.debug.sr_exit_time_ns - && dc->public.debug.sr_exit_time_ns) { + if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns + && dc->debug.sr_exit_time_ns) { updated = true; - dc->dcn_soc->sr_exit_time = dc->public.debug.sr_exit_time_ns / 1000.0; + dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0; } if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000) - != dc->public.debug.sr_enter_plus_exit_time_ns - && dc->public.debug.sr_enter_plus_exit_time_ns) { + != dc->debug.sr_enter_plus_exit_time_ns + && dc->debug.sr_enter_plus_exit_time_ns) { updated = true; dc->dcn_soc->sr_enter_plus_exit_time = - dc->public.debug.sr_enter_plus_exit_time_ns / 1000.0; + dc->debug.sr_enter_plus_exit_time_ns / 1000.0; } - if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->public.debug.urgent_latency_ns - && dc->public.debug.urgent_latency_ns) { + if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->debug.urgent_latency_ns + && dc->debug.urgent_latency_ns) { updated = true; - dc->dcn_soc->urgent_latency = dc->public.debug.urgent_latency_ns / 1000.0; + dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0; } if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000) - != dc->public.debug.percent_of_ideal_drambw - && dc->public.debug.percent_of_ideal_drambw) { + != dc->debug.percent_of_ideal_drambw + && dc->debug.percent_of_ideal_drambw) { updated = true; dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency = - dc->public.debug.percent_of_ideal_drambw; + dc->debug.percent_of_ideal_drambw; } if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000) - != dc->public.debug.dram_clock_change_latency_ns - && dc->public.debug.dram_clock_change_latency_ns) { + != dc->debug.dram_clock_change_latency_ns + && dc->debug.dram_clock_change_latency_ns) { updated = true; dc->dcn_soc->dram_clock_change_latency = - dc->public.debug.dram_clock_change_latency_ns / 1000.0; + dc->debug.dram_clock_change_latency_ns / 1000.0; } kernel_fpu_end(); @@ -720,7 +719,7 @@ static bool dcn_bw_apply_registry_override(struct core_dc *dc) } bool dcn_validate_bandwidth( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context) { const struct resource_pool *pool = dc->res_pool; @@ -730,8 +729,8 @@ bool dcn_validate_bandwidth( bool bw_limit_pass; float bw_limit; - if (dcn_bw_apply_registry_override(DC_TO_CORE(&dc->public))) - dcn_bw_sync_calcs_and_dml(DC_TO_CORE(&dc->public)); + if (dcn_bw_apply_registry_override(dc)) + dcn_bw_sync_calcs_and_dml(dc); memset(v, 0, sizeof(*v)); kernel_fpu_begin(); @@ -850,7 +849,7 @@ bool dcn_validate_bandwidth( v->phyclk_per_state[1] = v->phyclkv_mid0p72; v->phyclk_per_state[0] = v->phyclkv_min0p65; - if (dc->public.debug.disable_pipe_split) { + if (dc->debug.disable_pipe_split) { v->max_dispclk[0] = v->max_dppclk_vmin0p65; } @@ -982,15 +981,15 @@ bool dcn_validate_bandwidth( mode_support_and_system_configuration(v); if (v->voltage_level == 0 && - (dc->public.debug.sr_exit_time_dpm0_ns - || dc->public.debug.sr_enter_plus_exit_time_dpm0_ns)) { - struct core_dc *dc_core = DC_TO_CORE(&dc->public); + (dc->debug.sr_exit_time_dpm0_ns + || dc->debug.sr_enter_plus_exit_time_dpm0_ns)) { + struct dc *dc_core = dc; - if (dc->public.debug.sr_enter_plus_exit_time_dpm0_ns) + if (dc->debug.sr_enter_plus_exit_time_dpm0_ns) v->sr_enter_plus_exit_time = - dc->public.debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f; - if (dc->public.debug.sr_exit_time_dpm0_ns) - v->sr_exit_time = dc->public.debug.sr_exit_time_dpm0_ns / 1000.0f; + dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f; + if (dc->debug.sr_exit_time_dpm0_ns) + v->sr_exit_time = dc->debug.sr_exit_time_dpm0_ns / 1000.0f; dc_core->dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time; dc_core->dml.soc.sr_exit_time_us = v->sr_exit_time; mode_support_and_system_configuration(v); @@ -1020,7 +1019,7 @@ bool dcn_validate_bandwidth( context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000); context->bw.dcn.calc_clk.dcfclk_khz = (int)(v->dcfclk * 1000); context->bw.dcn.calc_clk.dispclk_khz = (int)(v->dispclk * 1000); - if (dc->public.debug.max_disp_clk == true) + if (dc->debug.max_disp_clk == true) context->bw.dcn.calc_clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000); context->bw.dcn.calc_clk.dppclk_div = (int)(v->dispclk_dppclk_ratio) == 2; @@ -1109,13 +1108,13 @@ bool dcn_validate_bandwidth( input_idx++; } - if (dc->public.debug.use_dml_wm) + if (dc->debug.use_dml_wm) dcn_dml_wm_override(v, (struct display_mode_lib *) &dc->dml, context, pool); } if (v->voltage_level == 0) { - struct core_dc *dc_core = DC_TO_CORE(&dc->public); + struct dc *dc_core = dc; dc_core->dml.soc.sr_enter_plus_exit_time_us = dc_core->dcn_soc->sr_enter_plus_exit_time; @@ -1138,7 +1137,7 @@ bool dcn_validate_bandwidth( } unsigned int dcn_find_normalized_clock_vdd_Level( - const struct core_dc *dc, + const struct dc *dc, enum dm_pp_clock_type clocks_type, int clocks_in_khz) { @@ -1228,7 +1227,7 @@ unsigned int dcn_find_normalized_clock_vdd_Level( } unsigned int dcn_find_dcfclk_suits_all( - const struct core_dc *dc, + const struct dc *dc, struct clocks_value *clocks) { unsigned vdd_level, vdd_level_temp; @@ -1270,7 +1269,7 @@ unsigned int dcn_find_dcfclk_suits_all( return dcf_clk; } -void dcn_bw_update_from_pplib(struct core_dc *dc) +void dcn_bw_update_from_pplib(struct dc *dc) { struct dc_context *ctx = dc->ctx; struct dm_pp_clock_levels_with_voltage clks = {0}; @@ -1310,7 +1309,7 @@ void dcn_bw_update_from_pplib(struct core_dc *dc) kernel_fpu_end(); } -void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc) +void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc) { struct dm_pp_wm_sets_with_clock_ranges_soc15 clk_ranges = {0}; int max_fclk_khz, nom_fclk_khz, min_fclk_khz, max_dcfclk_khz, @@ -1388,7 +1387,7 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc) dm_pp_notify_wm_clock_changes_soc15(dc->ctx, &clk_ranges); } -void dcn_bw_sync_calcs_and_dml(struct core_dc *dc) +void dcn_bw_sync_calcs_and_dml(struct dc *dc) { kernel_fpu_begin(); dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 40d65b758994..44c7b52e4a00 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -35,7 +35,6 @@ #include "clock_source.h" #include "dc_bios_types.h" -#include "dce_calcs.h" #include "bios_parser_interface.h" #include "include/irq_service_interface.h" #include "transform.h" @@ -52,7 +51,7 @@ /******************************************************************************* * Private functions ******************************************************************************/ -static void destroy_links(struct core_dc *dc) +static void destroy_links(struct dc *dc) { uint32_t i; @@ -63,7 +62,7 @@ static void destroy_links(struct core_dc *dc) } static bool create_links( - struct core_dc *dc, + struct dc *dc, uint32_t num_virtual_links) { int i; @@ -153,7 +152,7 @@ static bool stream_adjust_vmin_vmax(struct dc *dc, int vmin, int vmax) { /* TODO: Support multiple streams */ - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_stream_state *stream = streams[0]; int i = 0; bool ret = false; @@ -179,7 +178,7 @@ static bool stream_get_crtc_position(struct dc *dc, unsigned int *v_pos, unsigned int *nom_v_pos) { /* TODO: Support multiple streams */ - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_stream_state *stream = streams[0]; int i = 0; bool ret = false; @@ -202,7 +201,7 @@ static bool stream_get_crtc_position(struct dc *dc, static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; int i = 0; bool ret = false; struct pipe_ctx *pipes; @@ -220,7 +219,7 @@ static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) static bool program_csc_matrix(struct dc *dc, struct dc_stream_state *stream) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; int i = 0; bool ret = false; struct pipe_ctx *pipes; @@ -245,7 +244,7 @@ static void set_static_screen_events(struct dc *dc, int num_streams, const struct dc_static_screen_events *events) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; int i = 0; int j = 0; struct pipe_ctx *pipes_affected[MAX_PIPES]; @@ -270,7 +269,7 @@ static void set_drive_settings(struct dc *dc, struct link_training_settings *lt_settings, const struct dc_link *link) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; int i; for (i = 0; i < core_dc->link_count; i++) { @@ -288,7 +287,7 @@ static void perform_link_training(struct dc *dc, struct dc_link_settings *link_setting, bool skip_video_pattern) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; int i; for (i = 0; i < core_dc->link_count; i++) @@ -369,48 +368,48 @@ void set_dither_option(struct dc_stream_state *stream, opp_program_bit_depth_reduction(pipes->stream_res.opp, ¶ms); } -static void allocate_dc_stream_funcs(struct core_dc *core_dc) +static void allocate_dc_stream_funcs(struct dc *core_dc) { if (core_dc->hwss.set_drr != NULL) { - core_dc->public.stream_funcs.adjust_vmin_vmax = + core_dc->stream_funcs.adjust_vmin_vmax = stream_adjust_vmin_vmax; } - core_dc->public.stream_funcs.set_static_screen_events = + core_dc->stream_funcs.set_static_screen_events = set_static_screen_events; - core_dc->public.stream_funcs.get_crtc_position = + core_dc->stream_funcs.get_crtc_position = stream_get_crtc_position; - core_dc->public.stream_funcs.set_gamut_remap = + core_dc->stream_funcs.set_gamut_remap = set_gamut_remap; - core_dc->public.stream_funcs.program_csc_matrix = + core_dc->stream_funcs.program_csc_matrix = program_csc_matrix; - core_dc->public.stream_funcs.set_dither_option = + core_dc->stream_funcs.set_dither_option = set_dither_option; - core_dc->public.link_funcs.set_drive_settings = + core_dc->link_funcs.set_drive_settings = set_drive_settings; - core_dc->public.link_funcs.perform_link_training = + core_dc->link_funcs.perform_link_training = perform_link_training; - core_dc->public.link_funcs.set_preferred_link_settings = + core_dc->link_funcs.set_preferred_link_settings = set_preferred_link_settings; - core_dc->public.link_funcs.enable_hpd = + core_dc->link_funcs.enable_hpd = enable_hpd; - core_dc->public.link_funcs.disable_hpd = + core_dc->link_funcs.disable_hpd = disable_hpd; - core_dc->public.link_funcs.set_test_pattern = + core_dc->link_funcs.set_test_pattern = set_test_pattern; } -static void destruct(struct core_dc *dc) +static void destruct(struct dc *dc) { dc_release_validate_context(dc->current_context); dc->current_context = NULL; @@ -446,10 +445,11 @@ static void destruct(struct core_dc *dc) dm_free(dc->dcn_ip); dc->dcn_ip = NULL; + #endif } -static bool construct(struct core_dc *dc, +static bool construct(struct dc *dc, const struct dc_init_data *init_params) { struct dal_logger *logger; @@ -508,7 +508,7 @@ static bool construct(struct core_dc *dc, dc_ctx->cgs_device = init_params->cgs_device; dc_ctx->driver_context = init_params->driver; - dc_ctx->dc = &dc->public; + dc_ctx->dc = dc; dc_ctx->asic_id = init_params->asic_id; /* Create logger */ @@ -621,7 +621,7 @@ void ProgramPixelDurationV(unsigned int pixelClockInKHz ) struct dc *dc_create(const struct dc_init_data *init_params) { - struct core_dc *core_dc = dm_alloc(sizeof(*core_dc)); + struct dc *core_dc = dm_alloc(sizeof(*core_dc)); unsigned int full_pipe_count; if (NULL == core_dc) @@ -636,23 +636,23 @@ struct dc *dc_create(const struct dc_init_data *init_params) full_pipe_count = core_dc->res_pool->pipe_count; if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE) full_pipe_count--; - core_dc->public.caps.max_streams = min( + core_dc->caps.max_streams = min( full_pipe_count, core_dc->res_pool->stream_enc_count); - core_dc->public.caps.max_links = core_dc->link_count; - core_dc->public.caps.max_audios = core_dc->res_pool->audio_count; + core_dc->caps.max_links = core_dc->link_count; + core_dc->caps.max_audios = core_dc->res_pool->audio_count; - core_dc->public.config = init_params->flags; + core_dc->config = init_params->flags; dm_logger_write(core_dc->ctx->logger, LOG_DC, "Display Core initialized\n"); /* TODO: missing feature to be enabled */ - core_dc->public.debug.disable_dfs_bypass = true; + core_dc->debug.disable_dfs_bypass = true; - return &core_dc->public; + return core_dc; construct_fail: dm_free(core_dc); @@ -663,14 +663,14 @@ alloc_fail: void dc_destroy(struct dc **dc) { - struct core_dc *core_dc = DC_TO_CORE(*dc); + struct dc *core_dc = *dc; destruct(core_dc); dm_free(core_dc); *dc = NULL; } static bool is_validation_required( - const struct core_dc *dc, + const struct dc *dc, const struct dc_validation_set set[], int set_count) { @@ -705,7 +705,7 @@ static bool is_validation_required( } static bool validate_streams ( - const struct dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count) { @@ -719,7 +719,7 @@ static bool validate_streams ( } static bool validate_surfaces( - const struct dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count) { @@ -734,11 +734,11 @@ static bool validate_surfaces( } struct validate_context *dc_get_validate_context( - const struct dc *dc, + struct dc *dc, const struct dc_validation_set set[], uint8_t set_count) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; enum dc_status result = DC_ERROR_UNEXPECTED; struct validate_context *context; @@ -773,11 +773,11 @@ context_alloc_fail: } bool dc_validate_resources( - const struct dc *dc, + struct dc *dc, const struct dc_validation_set set[], uint8_t set_count) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; enum dc_status result = DC_ERROR_UNEXPECTED; struct validate_context *context; @@ -811,10 +811,10 @@ context_alloc_fail: } bool dc_validate_guaranteed( - const struct dc *dc, + struct dc *dc, struct dc_stream_state *stream) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; enum dc_status result = DC_ERROR_UNEXPECTED; struct validate_context *context; @@ -844,7 +844,7 @@ context_alloc_fail: } static void program_timing_sync( - struct core_dc *core_dc, + struct dc *core_dc, struct validate_context *ctx) { int i, j; @@ -918,7 +918,7 @@ static void program_timing_sync( } static bool context_changed( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { uint8_t i; @@ -935,7 +935,7 @@ static bool context_changed( } static bool streams_changed( - struct core_dc *dc, + struct dc *dc, struct dc_stream_state *streams[], uint8_t stream_count) { @@ -961,7 +961,7 @@ bool dc_enable_stereo( bool ret = true; int i, j; struct pipe_ctx *pipe; - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; #ifdef ENABLE_FBC struct compressor *fbc_compressor = core_dc->fbc_compressor; @@ -996,7 +996,7 @@ bool dc_enable_stereo( */ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *context) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_bios *dcb = core_dc->ctx->dc_bios; enum dc_status result = DC_ERROR_UNEXPECTED; struct pipe_ctx *pipe; @@ -1064,7 +1064,7 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c bool dc_commit_context(struct dc *dc, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; int i; if (false == context_changed(core_dc, context)) @@ -1092,7 +1092,7 @@ bool dc_commit_streams( struct dc_stream_state *streams[], uint8_t stream_count) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; enum dc_status result = DC_ERROR_UNEXPECTED; struct validate_context *context; struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } }; @@ -1158,7 +1158,7 @@ context_alloc_fail: bool dc_post_update_surfaces_to_stream(struct dc *dc) { int i; - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct validate_context *context = core_dc->current_context; post_surface_trace(dc); @@ -1375,7 +1375,7 @@ static enum surface_update_type get_scaling_info_update_type( } static enum surface_update_type det_surface_update( - const struct core_dc *dc, + const struct dc *dc, const struct dc_surface_update *u, int surface_index) { @@ -1410,7 +1410,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream( struct dc_stream_update *stream_update, const struct dc_stream_status *stream_status) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; int i; enum surface_update_type overall_type = UPDATE_TYPE_FAST; @@ -1456,7 +1456,7 @@ void dc_update_planes_and_stream(struct dc *dc, struct dc_stream_state *stream, struct dc_stream_update *stream_update) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct validate_context *context; int i, j; enum surface_update_type update_type; @@ -1781,29 +1781,29 @@ context_alloc_fail: DC_ERROR("Failed to allocate new validate context!\n"); } -uint8_t dc_get_current_stream_count(const struct dc *dc) +uint8_t dc_get_current_stream_count(struct dc *dc) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; return core_dc->current_context->stream_count; } -struct dc_stream_state *dc_get_stream_at_index(const struct dc *dc, uint8_t i) +struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; if (i < core_dc->current_context->stream_count) return core_dc->current_context->streams[i]; return NULL; } -struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index) +struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; return core_dc->links[link_index]; } -struct dwbc *dc_get_dwb_at_pipe(const struct dc *dc, uint32_t pipe) +struct dwbc *dc_get_dwb_at_pipe(struct dc *dc, uint32_t pipe) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; if ((pipe >= dwb_pipe0) && (pipe < dwb_pipe_max_num)) { return core_dc->res_pool->dwbc[(int)pipe]; } else { @@ -1814,20 +1814,20 @@ struct dwbc *dc_get_dwb_at_pipe(const struct dc *dc, uint32_t pipe) const struct graphics_object_id dc_get_link_id_at_index( struct dc *dc, uint32_t link_index) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; return core_dc->links[link_index]->link_id; } enum dc_irq_source dc_get_hpd_irq_source_at_index( struct dc *dc, uint32_t link_index) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; return core_dc->links[link_index]->irq_source_hpd; } const struct audio **dc_get_audios(struct dc *dc) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; return (const struct audio **)core_dc->res_pool->audios; } @@ -1836,24 +1836,24 @@ enum dc_irq_source dc_interrupt_to_irq_source( uint32_t src_id, uint32_t ext_id) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; return dal_irq_service_to_irq_source(core_dc->res_pool->irqs, src_id, ext_id); } -void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable) +void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable) { - struct core_dc *core_dc; + struct dc *core_dc; if (dc == NULL) return; - core_dc = DC_TO_CORE(dc); + core_dc = dc; dal_irq_service_set(core_dc->res_pool->irqs, src, enable); } void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; dal_irq_service_ack(core_dc->res_pool->irqs, src); } @@ -1861,7 +1861,7 @@ void dc_set_power_state( struct dc *dc, enum dc_acpi_cm_power_state power_state) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; atomic_t ref_count; switch (power_state) { @@ -1889,9 +1889,9 @@ void dc_set_power_state( } -void dc_resume(const struct dc *dc) +void dc_resume(struct dc *dc) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; uint32_t i; @@ -1906,7 +1906,7 @@ bool dc_read_aux_dpcd( uint8_t *data, uint32_t size) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_link *link = core_dc->links[link_index]; enum ddc_result r = dal_ddc_service_read_dpcd_data( @@ -1926,7 +1926,7 @@ bool dc_write_aux_dpcd( const uint8_t *data, uint32_t size) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_link *link = core_dc->links[link_index]; enum ddc_result r = dal_ddc_service_write_dpcd_data( @@ -1947,7 +1947,7 @@ bool dc_read_aux_i2c( uint8_t *data, uint32_t size) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_link *link = core_dc->links[link_index]; enum ddc_result r = dal_ddc_service_read_dpcd_data( @@ -1968,7 +1968,7 @@ bool dc_write_aux_i2c( const uint8_t *data, uint32_t size) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_link *link = core_dc->links[link_index]; enum ddc_result r = dal_ddc_service_write_dpcd_data( @@ -1990,7 +1990,7 @@ bool dc_query_ddc_data( uint8_t *read_buf, uint32_t read_size) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_link *link = core_dc->links[link_index]; @@ -2010,7 +2010,7 @@ bool dc_submit_i2c( uint32_t link_index, struct i2c_command *cmd) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_link *link = core_dc->links[link_index]; struct ddc_service *ddc = link->ddc; @@ -2129,7 +2129,7 @@ void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) { int i; - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct mem_input *mi = NULL; for (i = 0; i < core_dc->res_pool->pipe_count; i++) { @@ -2155,7 +2155,7 @@ bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) void dc_log_hw_state(struct dc *dc) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; if (core_dc->hwss.log_hw_state) core_dc->hwss.log_hw_state(core_dc); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index 21af3bc057c7..d74eed8f9b96 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -37,12 +37,12 @@ } while (0) void pre_surface_trace( - const struct dc *dc, + struct dc *dc, const struct dc_plane_state *const *plane_states, int surface_count) { int i; - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dal_logger *logger = core_dc->ctx->logger; for (i = 0; i < surface_count; i++) { @@ -158,12 +158,12 @@ void pre_surface_trace( } void update_surface_trace( - const struct dc *dc, + struct dc *dc, const struct dc_surface_update *updates, int surface_count) { int i; - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dal_logger *logger = core_dc->ctx->logger; for (i = 0; i < surface_count; i++) { @@ -279,9 +279,9 @@ void update_surface_trace( SURFACE_TRACE("\n"); } -void post_surface_trace(const struct dc *dc) +void post_surface_trace(struct dc *dc) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dal_logger *logger = core_dc->ctx->logger; SURFACE_TRACE("post surface process.\n"); @@ -289,11 +289,11 @@ void post_surface_trace(const struct dc *dc) } void context_timing_trace( - const struct dc *dc, + struct dc *dc, struct resource_context *res_ctx) { int i; - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dal_logger *logger = core_dc->ctx->logger; int h_pos[MAX_PIPES], v_pos[MAX_PIPES]; struct crtc_position position; @@ -328,11 +328,11 @@ void context_timing_trace( } void context_clock_trace( - const struct dc *dc, + struct dc *dc, struct validate_context *context) { #if defined(CONFIG_DRM_AMD_DC_DCN1_0) - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dal_logger *logger = core_dc->ctx->logger; CLOCK_TRACE("Current: dispclk_khz:%d dppclk_div:%d dcfclk_khz:%d\n" diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index 7b1f2493cbc9..71993d5983bf 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -25,7 +25,6 @@ #include "dm_services.h" #include "core_types.h" -#include "core_dc.h" #include "timing_generator.h" #include "hw_sequencer.h" @@ -55,7 +54,7 @@ static const struct tg_color black_color_format[] = { }; void color_space_to_black_color( - const struct core_dc *dc, + const struct dc *dc, enum dc_color_space colorspace, struct tg_color *black_color) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index b858fec72bd7..1888bf4d2c3f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -26,14 +26,13 @@ #include "dm_services.h" #include "dm_helpers.h" #include "dc.h" -#include "core_dc.h" #include "grph_object_id.h" #include "gpio_service_interface.h" #include "core_status.h" #include "dc_link_dp.h" #include "dc_link_ddc.h" #include "link_hwss.h" -#include "stream_encoder.h" + #include "link_encoder.h" #include "hw_sequencer.h" #include "resource.h" @@ -1392,7 +1391,7 @@ enum dc_status dc_link_validate_mode_timing( bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, uint32_t frame_ramp, const struct dc_stream_state *stream) { - struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); + struct dc *core_dc = link->ctx->dc; struct abm *abm = core_dc->res_pool->abm; unsigned int controller_id = 0; int i; @@ -1431,7 +1430,7 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, bool dc_link_set_abm_disable(const struct dc_link *link) { - struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); + struct dc *core_dc = link->ctx->dc; struct abm *abm = core_dc->res_pool->abm; if ((abm == NULL) || (abm->funcs->set_backlight_level == NULL)) @@ -1445,7 +1444,7 @@ bool dc_link_set_abm_disable(const struct dc_link *link) bool dc_link_set_psr_enable(const struct dc_link *link, bool enable) { - struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); + struct dc *core_dc = link->ctx->dc; struct dmcu *dmcu = core_dc->res_pool->dmcu; if (dmcu != NULL && link->psr_enabled) @@ -1456,7 +1455,7 @@ bool dc_link_set_psr_enable(const struct dc_link *link, bool enable) bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state) { - struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); + struct dc *core_dc = link->ctx->dc; struct dmcu *dmcu = core_dc->res_pool->dmcu; if (dmcu != NULL && link->psr_enabled) @@ -1469,7 +1468,7 @@ bool dc_link_setup_psr(struct dc_link *link, const struct dc_stream_state *stream, struct psr_config *psr_config, struct psr_context *psr_context) { - struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); + struct dc *core_dc = link->ctx->dc; struct dmcu *dmcu = core_dc->res_pool->dmcu; int i; @@ -1874,7 +1873,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) void core_link_enable_stream(struct pipe_ctx *pipe_ctx) { - struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc); + struct dc *core_dc = pipe_ctx->stream->ctx->dc; enum dc_status status = enable_link(pipe_ctx); @@ -1907,7 +1906,7 @@ void core_link_enable_stream(struct pipe_ctx *pipe_ctx) void core_link_disable_stream(struct pipe_ctx *pipe_ctx) { - struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc); + struct dc *core_dc = pipe_ctx->stream->ctx->dc; if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) deallocate_mst_payload(pipe_ctx); @@ -1919,7 +1918,7 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx) void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) { - struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc); + struct dc *core_dc = pipe_ctx->stream->ctx->dc; if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) return; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 9d5fe658d14c..0144c98fd0d5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -10,7 +10,6 @@ #include "core_status.h" #include "dpcd_defs.h" -#include "core_dc.h" #include "resource.h" /* maximum pre emphasis level allowed for each voltage swing level*/ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index d19c663c257f..da880bd02ad7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -3,7 +3,7 @@ #include "dm_services.h" #include "dc.h" -#include "inc/core_dc.h" +#include "inc/core_types.h" #include "include/ddc_service_types.h" #include "include/i2caux_interface.h" #include "link_hwss.h" diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index d2b8f27416d6..2b357318f945 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -92,7 +92,7 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) } struct resource_pool *dc_create_resource_pool( - struct core_dc *dc, + struct dc *dc, int num_virtual_links, enum dce_version dc_version, struct hw_asic_id asic_id) @@ -153,7 +153,7 @@ struct resource_pool *dc_create_resource_pool( return res_pool; } -void dc_destroy_resource_pool(struct core_dc *dc) +void dc_destroy_resource_pool(struct dc *dc) { if (dc) { if (dc->res_pool) @@ -193,7 +193,7 @@ static void update_num_audio( bool resource_construct( unsigned int num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct resource_pool *pool, const struct resource_create_funcs *create_funcs) { @@ -892,7 +892,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) enum dc_status resource_build_scaling_params_for_context( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context) { int i; @@ -1438,7 +1438,7 @@ static void calculate_phy_pix_clks(struct dc_stream_state *stream) } enum dc_status resource_map_pool_resources( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -2316,7 +2316,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) } enum dc_status resource_map_clock_resources( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -2343,7 +2343,7 @@ enum dc_status resource_map_clock_resources( else { pipe_ctx->clock_source = NULL; - if (!dc->public.config.disable_disp_pll_sharing) + if (!dc->config.disable_disp_pll_sharing) resource_find_used_clk_src_for_sharing( &context->res_ctx, pipe_ctx); @@ -2515,9 +2515,9 @@ void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, fmt_bit_depth->pixel_encoding = pixel_encoding; } -bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream) +bool dc_validate_stream(struct dc *dc, struct dc_stream_state *stream) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_context *dc_ctx = core_dc->ctx; struct dc_link *link = stream->sink->link; struct timing_generator *tg = core_dc->res_pool->timing_generators[0]; @@ -2547,9 +2547,9 @@ bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream) return res == DC_OK; } -bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_state) +bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; /* TODO For now validates pixel format only */ if (core_dc->res_pool->funcs->validate_plane) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 47e407dab4a3..5e4f7f08e3db 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -144,7 +144,7 @@ struct dc_stream_status *dc_stream_get_status( struct dc_stream_state *stream) { uint8_t i; - struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); + struct dc *dc = stream->ctx->dc; for (i = 0; i < dc->current_context->stream_count; i++) { if (stream == dc->current_context->streams[i]) { @@ -163,7 +163,7 @@ bool dc_stream_set_cursor_attributes( const struct dc_cursor_attributes *attributes) { int i; - struct core_dc *core_dc; + struct dc *core_dc; struct resource_context *res_ctx; if (NULL == stream) { @@ -175,7 +175,7 @@ bool dc_stream_set_cursor_attributes( return false; } - core_dc = DC_TO_CORE(stream->ctx->dc); + core_dc = stream->ctx->dc; res_ctx = &core_dc->current_context->res_ctx; for (i = 0; i < MAX_PIPES; i++) { @@ -198,7 +198,7 @@ bool dc_stream_set_cursor_position( const struct dc_cursor_position *position) { int i; - struct core_dc *core_dc; + struct dc *core_dc; struct resource_context *res_ctx; if (NULL == stream) { @@ -211,7 +211,7 @@ bool dc_stream_set_cursor_position( return false; } - core_dc = DC_TO_CORE(stream->ctx->dc); + core_dc = stream->ctx->dc; res_ctx = &core_dc->current_context->res_ctx; for (i = 0; i < MAX_PIPES; i++) { @@ -246,7 +246,7 @@ bool dc_stream_set_cursor_position( uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) { uint8_t i; - struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); + struct dc *core_dc = stream->ctx->dc; struct resource_context *res_ctx = &core_dc->current_context->res_ctx; @@ -270,7 +270,7 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, { uint8_t i; bool ret = false; - struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); + struct dc *core_dc = stream->ctx->dc; struct resource_context *res_ctx = &core_dc->current_context->res_ctx; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index da19c7fa5151..0b6410fb2f3e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -28,7 +28,7 @@ #include "dc.h" /* DC core (private) */ -#include "core_dc.h" +#include "core_types.h" #include "transform.h" /******************************************************************************* @@ -64,9 +64,9 @@ void enable_surface_flip_reporting(struct dc_plane_state *plane_state, /*register_flip_interrupt(surface);*/ } -struct dc_plane_state *dc_create_plane_state(const struct dc *dc) +struct dc_plane_state *dc_create_plane_state(struct dc *dc) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_plane_state *plane_state = dm_alloc(sizeof(*plane_state)); @@ -91,7 +91,7 @@ const struct dc_plane_status *dc_plane_get_status( const struct dc_plane_state *plane_state) { const struct dc_plane_status *plane_status; - struct core_dc *core_dc; + struct dc *core_dc; int i; if (!plane_state || @@ -102,7 +102,7 @@ const struct dc_plane_status *dc_plane_get_status( } plane_status = &plane_state->status; - core_dc = DC_TO_CORE(plane_state->ctx->dc); + core_dc = plane_state->ctx->dc; if (core_dc->current_context == NULL) return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e62d15d90fdb..68056d888def 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -34,14 +34,19 @@ #include "grph_object_ctrl_defs.h" #include +#include "inc/hw_sequencer.h" +#include "dml/display_mode_lib.h" + + + #define MAX_SURFACES 3 #define MAX_STREAMS 6 #define MAX_SINKS_PER_LINK 4 + /******************************************************************************* * Display Core Interfaces ******************************************************************************/ - struct dc_caps { uint32_t max_streams; uint32_t max_links; @@ -186,7 +191,9 @@ struct dc_debug { bool disable_psr; bool force_abm_enable; }; - +struct validate_context; +struct resource_pool; +struct dce_hwseq; struct dc { struct dc_caps caps; struct dc_cap_funcs cap_funcs; @@ -194,6 +201,40 @@ struct dc { struct dc_link_funcs link_funcs; struct dc_config config; struct dc_debug debug; + + struct dc_context *ctx; + + uint8_t link_count; + struct dc_link *links[MAX_PIPES * 2]; + + struct validate_context *current_context; + struct resource_pool *res_pool; + + /* Display Engine Clock levels */ + struct dm_pp_clock_levels sclk_lvls; + + /* Inputs into BW and WM calculations. */ + struct bw_calcs_dceip *bw_dceip; + struct bw_calcs_vbios *bw_vbios; +#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + struct dcn_soc_bounding_box *dcn_soc; + struct dcn_ip_params *dcn_ip; + struct display_mode_lib dml; +#endif + + /* HW functions */ + struct hw_sequencer_funcs hwss; + struct dce_hwseq *hwseq; + + /* temp store of dm_pp_display_configuration + * to compare to see if display config changed + */ + struct dm_pp_display_configuration prev_display_config; + + /* FBC compressor */ +#ifdef ENABLE_FBC + struct compressor *fbc_compressor; +#endif }; enum frame_buffer_mode { @@ -384,7 +425,7 @@ struct dc_surface_update { /* * Create a new surface with default parameters; */ -struct dc_plane_state *dc_create_plane_state(const struct dc *dc); +struct dc_plane_state *dc_create_plane_state(struct dc *dc); const struct dc_plane_status *dc_plane_get_status( const struct dc_plane_state *plane_state); @@ -558,8 +599,8 @@ void dc_stream_log( struct dal_logger *dc_logger, enum dc_log_type log_type); -uint8_t dc_get_current_stream_count(const struct dc *dc); -struct dc_stream_state *dc_get_stream_at_index(const struct dc *dc, uint8_t i); +uint8_t dc_get_current_stream_count(struct dc *dc); +struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i); /* * Return the current frame counter. @@ -585,9 +626,9 @@ struct dc_validation_set { uint8_t plane_count; }; -bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream); +bool dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); -bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_state); +bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); /* * This function takes a set of resources and checks that they are cofunctional. * @@ -595,12 +636,12 @@ bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_s * No hardware is programmed for call. Only validation is done. */ struct validate_context *dc_get_validate_context( - const struct dc *dc, + struct dc *dc, const struct dc_validation_set set[], uint8_t set_count); bool dc_validate_resources( - const struct dc *dc, + struct dc *dc, const struct dc_validation_set set[], uint8_t set_count); @@ -613,7 +654,7 @@ bool dc_validate_resources( */ bool dc_validate_guaranteed( - const struct dc *dc, + struct dc *dc, struct dc_stream_state *stream); void dc_resource_validate_ctx_copy_construct( @@ -764,7 +805,7 @@ struct dc_link { /* Private to DC core */ - const struct core_dc *dc; + const struct dc *dc; struct dc_context *ctx; @@ -795,9 +836,9 @@ const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link); * boot time. They cannot be created or destroyed. * Use dc_get_caps() to get number of links. */ -struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index); +struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); -struct dwbc *dc_get_dwb_at_pipe(const struct dc *dc, uint32_t pipe); +struct dwbc *dc_get_dwb_at_pipe(struct dc *dc, uint32_t pipe); /* Return id of physical connector represented by a dc_link at link_index.*/ const struct graphics_object_id dc_get_link_id_at_index( @@ -948,7 +989,7 @@ enum dc_irq_source dc_interrupt_to_irq_source( struct dc *dc, uint32_t src_id, uint32_t ext_id); -void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable); +void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); enum dc_irq_source dc_get_hpd_irq_source_at_index( struct dc *dc, uint32_t link_index); @@ -960,7 +1001,7 @@ enum dc_irq_source dc_get_hpd_irq_source_at_index( void dc_set_power_state( struct dc *dc, enum dc_acpi_cm_power_state power_state); -void dc_resume(const struct dc *dc); +void dc_resume(struct dc *dc); /* * DPCD access interfaces diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 922af2d1b91a..0654fe34627c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -34,7 +34,6 @@ #include "dce_clock_source.h" -#include "core_dc.h" #include "reg_helper.h" #define REG(reg)\ @@ -609,7 +608,7 @@ static uint32_t dce110_get_pll_pixel_rate_in_hz( struct pll_settings *pll_settings) { uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; - struct core_dc *dc_core = DC_TO_CORE(cs->ctx->dc); + struct dc *dc_core = cs->ctx->dc; struct validate_context *context = dc_core->current_context; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst]; @@ -624,7 +623,7 @@ static uint32_t dce110_get_dp_pixel_rate_from_combo_phy_pll( struct pll_settings *pll_settings) { uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; - struct core_dc *dc_core = DC_TO_CORE(cs->ctx->dc); + struct dc *dc_core = cs->ctx->dc; struct validate_context *context = dc_core->current_context; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst]; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c index 7bb2eaf07da5..9d67340a6b8b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c @@ -29,14 +29,12 @@ #include "fixed32_32.h" #include "bios_parser_interface.h" #include "dc.h" -#include "core_dc.h" #include "dce_abm.h" #include "dmcu.h" #if defined(CONFIG_DRM_AMD_DC_DCN1_0) #include "dcn_calcs.h" -#include "core_dc.h" #endif - +#include "core_types.h" #define TO_DCE_CLOCKS(clocks)\ @@ -368,7 +366,7 @@ static int dce_psr_set_clock( { struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk); struct dc_context *ctx = clk_dce->base.ctx; - struct core_dc *core_dc = DC_TO_CORE(ctx->dc); + struct dc *core_dc = ctx->dc; struct dmcu *dmcu = core_dc->res_pool->dmcu; int actual_clk_khz = requested_clk_khz; @@ -385,7 +383,7 @@ static int dce112_set_clock( struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk); struct bp_set_dce_clock_parameters dce_clk_params; struct dc_bios *bp = clk->ctx->dc_bios; - struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc); + struct dc *core_dc = clk->ctx->dc; struct abm *abm = core_dc->res_pool->abm; struct dmcu *dmcu = core_dc->res_pool->dmcu; int actual_clock = requested_clk_khz; @@ -621,7 +619,7 @@ static bool dce_apply_clock_voltage_request( if (send_request) { #if defined(CONFIG_DRM_AMD_DC_DCN1_0) if (clk->ctx->dce_version >= DCN_VERSION_1_0) { - struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc); + struct dc *core_dc = clk->ctx->dc; /*use dcfclk request voltage*/ clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; clock_voltage_req.clocks_in_khz = diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c index 4894e1755d84..d2e66b1bc0ef 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c @@ -26,7 +26,7 @@ #include "dce_hwseq.h" #include "reg_helper.h" #include "hw_sequencer.h" -#include "core_dc.h" +#include "core_types.h" #define CTX \ hws->ctx @@ -44,7 +44,7 @@ void dce_enable_fe_clock(struct dce_hwseq *hws, DCFE_CLOCK_ENABLE, enable); } -void dce_pipe_control_lock(struct core_dc *dc, +void dce_pipe_control_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock) { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index 9a97d8ee7971..3a1eb6a79d66 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -528,7 +528,7 @@ enum blnd_mode { void dce_enable_fe_clock(struct dce_hwseq *hwss, unsigned int inst, bool enable); -void dce_pipe_control_lock(struct core_dc *dc, +void dce_pipe_control_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock); diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c index c638f47acefc..b7e51c5ed1b1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c @@ -24,7 +24,6 @@ */ #include "dm_services.h" #include "dc.h" -#include "core_dc.h" #include "core_types.h" #include "hw_sequencer.h" #include "dce100_hw_sequencer.h" @@ -71,7 +70,7 @@ static const struct dce100_hw_seq_reg_offsets reg_offsets[] = { /***************************PIPE_CONTROL***********************************/ static bool dce100_enable_display_power_gating( - struct core_dc *dc, + struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating) @@ -107,7 +106,7 @@ static bool dce100_enable_display_power_gating( } static void dce100_pplib_apply_display_requirements( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; @@ -127,7 +126,7 @@ static void dce100_pplib_apply_display_requirements( } void dce100_set_bandwidth( - struct core_dc *dc, + struct dc *dc, struct validate_context *context, bool decrease_allowed) { @@ -143,7 +142,7 @@ void dce100_set_bandwidth( /**************************************************************************/ -bool dce100_hw_sequencer_construct(struct core_dc *dc) +bool dce100_hw_sequencer_construct(struct dc *dc) { dce110_hw_sequencer_construct(dc); diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h index 24433f0e770b..c04aa15cd656 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h @@ -28,13 +28,13 @@ #include "core_types.h" -struct core_dc; +struct dc; struct validate_context; -bool dce100_hw_sequencer_construct(struct core_dc *dc); +bool dce100_hw_sequencer_construct(struct dc *dc); void dce100_set_bandwidth( - struct core_dc *dc, + struct dc *dc, struct validate_context *context, bool decrease_allowed); diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 46f0c71fbac4..b2b03633eb4f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -652,7 +652,7 @@ static void destruct(struct dce110_resource_pool *pool) } static enum dc_status build_mapped_resource( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -688,7 +688,7 @@ static enum dc_status build_mapped_resource( } bool dce100_validate_bandwidth( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context) { /* TODO implement when needed but for now hardcode max value*/ @@ -720,7 +720,7 @@ static bool dce100_validate_surface_sets( } enum dc_status dce100_validate_with_context( - const struct core_dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count, struct validate_context *context, @@ -764,7 +764,7 @@ enum dc_status dce100_validate_with_context( } enum dc_status dce100_validate_guaranteed( - const struct core_dc *dc, + struct dc *dc, struct dc_stream_state *dc_stream, struct validate_context *context) { @@ -784,7 +784,7 @@ enum dc_status dce100_validate_guaranteed( if (result == DC_OK) { validate_guaranteed_copy_streams( - context, dc->public.caps.max_streams); + context, dc->caps.max_streams); result = resource_build_scaling_params_for_context(dc, context); } @@ -824,7 +824,7 @@ static const struct resource_funcs dce100_res_pool_funcs = { static bool construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dce110_resource_pool *pool) { unsigned int i; @@ -909,9 +909,9 @@ static bool construct( *************************************************/ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = res_cap.num_timing_generator; - dc->public.caps.max_downscale_ratio = 200; - dc->public.caps.i2c_speed_in_khz = 40; - dc->public.caps.max_cursor_size = 128; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 40; + dc->caps.max_cursor_size = 128; for (i = 0; i < pool->base.pipe_count; i++) { pool->base.timing_generators[i] = @@ -958,7 +958,7 @@ static bool construct( } } - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) @@ -978,7 +978,7 @@ res_create_fail: struct resource_pool *dce100_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc) + struct dc *dc) { struct dce110_resource_pool *pool = dm_alloc(sizeof(struct dce110_resource_pool)); diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h index edc50caf04d1..ca7b2b7c1a48 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h @@ -8,13 +8,13 @@ #ifndef DCE100_RESOURCE_H_ #define DCE100_RESOURCE_H_ -struct core_dc; +struct dc; struct resource_pool; struct dc_validation_set; struct resource_pool *dce100_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc); + struct dc *dc); enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index ccde7c80d658..e6c6f1108078 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -164,7 +164,7 @@ static void enable_display_pipe_clock_gating( } static bool dce110_enable_display_power_gating( - struct core_dc *dc, + struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating) @@ -944,7 +944,7 @@ static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, } } -static void program_scaler(const struct core_dc *dc, +static void program_scaler(const struct dc *dc, const struct pipe_ctx *pipe_ctx) { struct tg_color color = {0}; @@ -955,7 +955,7 @@ static void program_scaler(const struct core_dc *dc, return; #endif - if (dc->public.debug.surface_visual_confirm) + if (dc->debug.surface_visual_confirm) get_surface_visual_confirm_color(pipe_ctx, &color); else color_space_to_black_color(dc, @@ -979,7 +979,7 @@ static void program_scaler(const struct core_dc *dc, static enum dc_status dce110_prog_pixclk_crtc_otg( struct pipe_ctx *pipe_ctx, struct validate_context *context, - struct core_dc *dc) + struct dc *dc) { struct dc_stream_state *stream = pipe_ctx->stream; struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. @@ -1035,7 +1035,7 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( static enum dc_status apply_single_controller_ctx_to_hw( struct pipe_ctx *pipe_ctx, struct validate_context *context, - struct core_dc *dc) + struct dc *dc) { struct dc_stream_state *stream = pipe_ctx->stream; struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. @@ -1146,7 +1146,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( /******************************************************************************/ -static void power_down_encoders(struct core_dc *dc) +static void power_down_encoders(struct dc *dc) { int i; @@ -1156,7 +1156,7 @@ static void power_down_encoders(struct core_dc *dc) } } -static void power_down_controllers(struct core_dc *dc) +static void power_down_controllers(struct dc *dc) { int i; @@ -1166,7 +1166,7 @@ static void power_down_controllers(struct core_dc *dc) } } -static void power_down_clock_sources(struct core_dc *dc) +static void power_down_clock_sources(struct dc *dc) { int i; @@ -1181,7 +1181,7 @@ static void power_down_clock_sources(struct core_dc *dc) } } -static void power_down_all_hw_blocks(struct core_dc *dc) +static void power_down_all_hw_blocks(struct dc *dc) { power_down_encoders(dc); @@ -1196,7 +1196,7 @@ static void power_down_all_hw_blocks(struct core_dc *dc) } static void disable_vga_and_power_gate_all_controllers( - struct core_dc *dc) + struct dc *dc) { int i; struct timing_generator *tg; @@ -1224,7 +1224,7 @@ static void disable_vga_and_power_gate_all_controllers( * 3. Enable power gating for controller * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) */ -void dce110_enable_accelerated_mode(struct core_dc *dc) +void dce110_enable_accelerated_mode(struct dc *dc) { power_down_all_hw_blocks(dc); @@ -1250,7 +1250,7 @@ static uint32_t compute_pstate_blackout_duration( } void dce110_set_displaymarks( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context) { uint8_t i, num_pipes; @@ -1316,7 +1316,7 @@ static void set_safe_displaymarks( } static void switch_dp_clock_sources( - const struct core_dc *dc, + const struct dc *dc, struct resource_context *res_ctx) { uint8_t i; @@ -1408,7 +1408,7 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx, * may read PLL register to get pixel clock */ static uint32_t get_max_pixel_clock_for_all_paths( - struct core_dc *dc, + struct dc *dc, struct validate_context *context, bool pre_mode_set) { @@ -1449,7 +1449,7 @@ static uint32_t get_max_pixel_clock_for_all_paths( * etc support for dcn1.0 */ static void apply_min_clocks( - struct core_dc *dc, + struct dc *dc, struct validate_context *context, enum dm_pp_clocks_state *clocks_state, bool pre_mode_set) @@ -1538,7 +1538,7 @@ static void apply_min_clocks( /* * Check if FBC can be enabled */ -static enum dc_status validate_fbc(struct core_dc *dc, +static enum dc_status validate_fbc(struct dc *dc, struct validate_context *context) { struct pipe_ctx *pipe_ctx = @@ -1568,7 +1568,7 @@ static enum dc_status validate_fbc(struct core_dc *dc, /* * Enable FBC */ -static enum dc_status enable_fbc(struct core_dc *dc, +static enum dc_status enable_fbc(struct dc *dc, struct validate_context *context) { enum dc_status status = validate_fbc(dc, context); @@ -1597,7 +1597,7 @@ static enum dc_status enable_fbc(struct core_dc *dc, #endif static enum dc_status apply_ctx_to_hw_fpga( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { enum dc_status status = DC_ERROR_UNEXPECTED; @@ -1627,7 +1627,7 @@ static enum dc_status apply_ctx_to_hw_fpga( } static void dce110_reset_hw_ctx_wrap( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { int i; @@ -1672,7 +1672,7 @@ static void dce110_reset_hw_ctx_wrap( enum dc_status dce110_apply_ctx_to_hw( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { struct dc_bios *dcb = dc->ctx->dc_bios; @@ -1965,7 +1965,7 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx) * -------------------------------------------------| * ******************************************************************************/ -static void program_surface_visibility(const struct core_dc *dc, +static void program_surface_visibility(const struct dc *dc, struct pipe_ctx *pipe_ctx) { enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; @@ -2038,7 +2038,7 @@ static void program_gamut_remap(struct pipe_ctx *pipe_ctx) * TODO REMOVE, USE UPDATE INSTEAD */ static void set_plane_config( - const struct core_dc *dc, + const struct dc *dc, struct pipe_ctx *pipe_ctx, struct resource_context *res_ctx) { @@ -2117,7 +2117,7 @@ static void set_plane_config( if (mi->funcs->set_blank) mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); - if (dc->public.config.gpu_vm_support) + if (dc->config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( pipe_ctx->plane_res.mi, plane_state->format, @@ -2125,7 +2125,7 @@ static void set_plane_config( plane_state->rotation); } -static void update_plane_addr(const struct core_dc *dc, +static void update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) { struct dc_plane_state *plane_state = pipe_ctx->plane_state; @@ -2163,7 +2163,7 @@ void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) } } -void dce110_power_down(struct core_dc *dc) +void dce110_power_down(struct dc *dc) { power_down_all_hw_blocks(dc); disable_vga_and_power_gate_all_controllers(dc); @@ -2208,7 +2208,7 @@ static bool wait_for_reset_trigger_to_occur( /* Enable timing synchronization for a group of Timing Generators. */ static void dce110_enable_timing_synchronization( - struct core_dc *dc, + struct dc *dc, int group_index, int group_size, struct pipe_ctx *grouped_pipes[]) @@ -2257,7 +2257,7 @@ static void dce110_enable_timing_synchronization( DC_SYNC_INFO("GSL: Set-up complete.\n"); } -static void init_hw(struct core_dc *dc) +static void init_hw(struct dc *dc) { int i; struct dc_bios *bp; @@ -2394,7 +2394,7 @@ uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context) } static int determine_sclk_from_bounding_box( - const struct core_dc *dc, + const struct dc *dc, int required_sclk) { int i; @@ -2420,7 +2420,7 @@ static int determine_sclk_from_bounding_box( } static void pplib_apply_display_requirements( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; @@ -2474,7 +2474,7 @@ static void pplib_apply_display_requirements( } static void dce110_set_bandwidth( - struct core_dc *dc, + struct dc *dc, struct validate_context *context, bool decrease_allowed) { @@ -2491,7 +2491,7 @@ static void dce110_set_bandwidth( } static void dce110_program_front_end_for_pipe( - struct core_dc *dc, struct pipe_ctx *pipe_ctx) + struct dc *dc, struct pipe_ctx *pipe_ctx) { struct mem_input *mi = pipe_ctx->plane_res.mi; struct pipe_ctx *old_pipe = NULL; @@ -2572,7 +2572,7 @@ static void dce110_program_front_end_for_pipe( if (mi->funcs->set_blank) mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); - if (dc->public.config.gpu_vm_support) + if (dc->config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( pipe_ctx->plane_res.mi, plane_state->format, @@ -2618,7 +2618,7 @@ static void dce110_program_front_end_for_pipe( } static void dce110_apply_ctx_for_surface( - struct core_dc *dc, + struct dc *dc, const struct dc_stream_state *stream, int num_planes, struct validate_context *context) @@ -2648,7 +2648,7 @@ static void dce110_apply_ctx_for_surface( } } -static void dce110_power_down_fe(struct core_dc *dc, int fe_idx) +static void dce110_power_down_fe(struct dc *dc, int fe_idx) { /* Do not power down fe when stream is active on dce*/ if (dc->current_context->res_ctx.pipe_ctx[fe_idx].stream) @@ -2662,7 +2662,7 @@ static void dce110_power_down_fe(struct core_dc *dc, int fe_idx) } static void dce110_wait_for_mpcc_disconnect( - struct core_dc *dc, + struct dc *dc, struct resource_pool *res_pool, struct pipe_ctx *pipe_ctx) { @@ -2724,7 +2724,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect }; -bool dce110_hw_sequencer_construct(struct core_dc *dc) +bool dce110_hw_sequencer_construct(struct dc *dc) { dc->hwss = dce110_funcs; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h index 89782ca1917f..d710f6e6dc07 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h @@ -29,20 +29,20 @@ #include "core_types.h" #define GAMMA_HW_POINTS_NUM 256 -struct core_dc; +struct dc; struct validate_context; struct dm_pp_display_configuration; -bool dce110_hw_sequencer_construct(struct core_dc *dc); +bool dce110_hw_sequencer_construct(struct dc *dc); enum dc_status dce110_apply_ctx_to_hw( - struct core_dc *dc, + struct dc *dc, struct validate_context *context); void dce110_set_display_clock(struct validate_context *context); void dce110_set_displaymarks( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context); void dce110_enable_stream(struct pipe_ctx *pipe_ctx); @@ -55,9 +55,9 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, void dce110_update_info_frame(struct pipe_ctx *pipe_ctx); void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); -void dce110_enable_accelerated_mode(struct core_dc *dc); +void dce110_enable_accelerated_mode(struct dc *dc); -void dce110_power_down(struct core_dc *dc); +void dce110_power_down(struct dc *dc); void dce110_update_pending_status(struct pipe_ctx *pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 56be84ce5a0d..2154c2e567f2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -772,7 +772,7 @@ static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigne } static enum dc_status build_mapped_resource( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -814,7 +814,7 @@ static enum dc_status build_mapped_resource( } static bool dce110_validate_bandwidth( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context) { bool result = false; @@ -928,7 +928,7 @@ static bool dce110_validate_surface_sets( } static enum dc_status dce110_validate_with_context( - const struct core_dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count, struct validate_context *context, @@ -972,7 +972,7 @@ static enum dc_status dce110_validate_with_context( } static enum dc_status dce110_validate_guaranteed( - const struct core_dc *dc, + struct dc *dc, struct dc_stream_state *dc_stream, struct validate_context *context) { @@ -992,7 +992,7 @@ static enum dc_status dce110_validate_guaranteed( if (result == DC_OK) { validate_guaranteed_copy_streams( - context, dc->public.caps.max_streams); + context, dc->caps.max_streams); result = resource_build_scaling_params_for_context(dc, context); } @@ -1008,7 +1008,7 @@ static struct pipe_ctx *dce110_acquire_underlay( const struct resource_pool *pool, struct dc_stream_state *stream) { - struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); + struct dc *dc = stream->ctx->dc; struct resource_context *res_ctx = &context->res_ctx; unsigned int underlay_idx = pool->underlay_pipe_index; struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; @@ -1117,7 +1117,7 @@ static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) return true; } -static void bw_calcs_data_update_from_pplib(struct core_dc *dc) +static void bw_calcs_data_update_from_pplib(struct dc *dc) { struct dm_pp_clock_levels clks = {0}; @@ -1184,7 +1184,7 @@ const struct resource_caps *dce110_resource_cap( static bool construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dce110_resource_pool *pool, struct hw_asic_id asic_id) { @@ -1206,9 +1206,9 @@ static bool construct( pool->base.pipe_count = pool->base.res_cap->num_timing_generator; pool->base.underlay_pipe_index = pool->base.pipe_count; - dc->public.caps.max_downscale_ratio = 150; - dc->public.caps.i2c_speed_in_khz = 100; - dc->public.caps.max_cursor_size = 128; + dc->caps.max_downscale_ratio = 150; + dc->caps.i2c_speed_in_khz = 100; + dc->caps.max_cursor_size = 128; /************************************************* * Create resources * @@ -1351,7 +1351,7 @@ static bool construct( if (!dce110_hw_sequencer_construct(dc)) goto res_create_fail; - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); @@ -1366,7 +1366,7 @@ res_create_fail: struct resource_pool *dce110_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct hw_asic_id asic_id) { struct dce110_resource_pool *pool = diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h index 8e2e85dd30b9..5bb692d037d9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h @@ -28,7 +28,7 @@ #include "core_types.h" -struct core_dc; +struct dc; struct resource_pool; #define TO_DCE110_RES_POOL(pool)\ @@ -42,7 +42,7 @@ enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx); struct resource_pool *dce110_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct hw_asic_id asic_id); #endif /* __DC_RESOURCE_DCE110_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c index 204f613467b7..8816e09110e1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c @@ -25,7 +25,6 @@ #include "dm_services.h" #include "dc.h" -#include "core_dc.h" #include "core_types.h" #include "dce112_hw_sequencer.h" @@ -112,7 +111,7 @@ static void dce112_init_pte(struct dc_context *ctx) } static bool dce112_enable_display_power_gating( - struct core_dc *dc, + struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating) @@ -153,7 +152,7 @@ static bool dce112_enable_display_power_gating( return false; } -bool dce112_hw_sequencer_construct(struct core_dc *dc) +bool dce112_hw_sequencer_construct(struct dc *dc) { /* All registers used by dce11.2 match those in dce11 in offset and * structure diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h index d96c582da45c..37bd60cc93f9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h @@ -28,9 +28,9 @@ #include "core_types.h" -struct core_dc; +struct dc; -bool dce112_hw_sequencer_construct(struct core_dc *dc); +bool dce112_hw_sequencer_construct(struct dc *dc); #endif /* __DC_HWSS_DCE112_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index d6e58a25f3d0..89a8dfa68c01 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -723,7 +723,7 @@ static struct clock_source *find_matching_pll( } static enum dc_status build_mapped_resource( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -759,7 +759,7 @@ static enum dc_status build_mapped_resource( } bool dce112_validate_bandwidth( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context) { bool result = false; @@ -837,7 +837,7 @@ bool dce112_validate_bandwidth( } enum dc_status resource_map_phy_clock_resources( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -904,7 +904,7 @@ static bool dce112_validate_surface_sets( } enum dc_status dce112_validate_with_context( - const struct core_dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count, struct validate_context *context, @@ -948,7 +948,7 @@ enum dc_status dce112_validate_with_context( } enum dc_status dce112_validate_guaranteed( - const struct core_dc *dc, + struct dc *dc, struct dc_stream_state *stream, struct validate_context *context) { @@ -968,7 +968,7 @@ enum dc_status dce112_validate_guaranteed( if (result == DC_OK) { validate_guaranteed_copy_streams( - context, dc->public.caps.max_streams); + context, dc->caps.max_streams); result = resource_build_scaling_params_for_context(dc, context); } @@ -997,7 +997,7 @@ static const struct resource_funcs dce112_res_pool_funcs = { .validate_plane = dce100_validate_plane }; -static void bw_calcs_data_update_from_pplib(struct core_dc *dc) +static void bw_calcs_data_update_from_pplib(struct dc *dc) { struct dm_pp_clock_levels_with_latency eng_clks = {0}; struct dm_pp_clock_levels_with_latency mem_clks = {0}; @@ -1153,7 +1153,7 @@ const struct resource_caps *dce112_resource_cap( static bool construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dce110_resource_pool *pool) { unsigned int i; @@ -1170,9 +1170,9 @@ static bool construct( *************************************************/ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = pool->base.res_cap->num_timing_generator; - dc->public.caps.max_downscale_ratio = 200; - dc->public.caps.i2c_speed_in_khz = 100; - dc->public.caps.max_cursor_size = 128; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 100; + dc->caps.max_cursor_size = 128; /************************************************* * Create resources * @@ -1319,7 +1319,7 @@ static bool construct( &res_create_funcs)) goto res_create_fail; - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; /* Create hardware sequencer */ if (!dce112_hw_sequencer_construct(dc)) @@ -1338,7 +1338,7 @@ res_create_fail: struct resource_pool *dce112_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc) + struct dc *dc) { struct dce110_resource_pool *pool = dm_alloc(sizeof(struct dce110_resource_pool)); diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h index feef559f1ecd..69f8f689196d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h @@ -28,27 +28,27 @@ #include "core_types.h" -struct core_dc; +struct dc; struct resource_pool; struct resource_pool *dce112_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc); + struct dc *dc); enum dc_status dce112_validate_with_context( - const struct core_dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count, struct validate_context *context, struct validate_context *old_context); enum dc_status dce112_validate_guaranteed( - const struct core_dc *dc, + struct dc *dc, struct dc_stream_state *dc_stream, struct validate_context *context); bool dce112_validate_bandwidth( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context); diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c index 91301b412aa0..d6225f332431 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c @@ -25,7 +25,6 @@ #include "dm_services.h" #include "dc.h" -#include "core_dc.h" #include "core_types.h" #include "dce120_hw_sequencer.h" #include "dce/dce_hwseq.h" @@ -149,7 +148,7 @@ static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id) #endif static bool dce120_enable_display_power_gating( - struct core_dc *dc, + struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating) @@ -247,7 +246,7 @@ static void dce120_update_dchub( -bool dce120_hw_sequencer_construct(struct core_dc *dc) +bool dce120_hw_sequencer_construct(struct dc *dc) { /* All registers used by dce11.2 match those in dce11 in offset and * structure diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h index 3402413c7156..6448a17c2fde 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h @@ -28,9 +28,9 @@ #include "core_types.h" -struct core_dc; +struct dc; -bool dce120_hw_sequencer_construct(struct core_dc *dc); +bool dce120_hw_sequencer_construct(struct dc *dc); #endif /* __DC_HWSS_DCE112_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index 562ae2205a90..b8fcdff40db3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -410,7 +410,7 @@ void dce120_clock_source_destroy(struct clock_source **clk_src) } -bool dce120_hw_sequencer_create(struct core_dc *dc) +bool dce120_hw_sequencer_create(struct dc *dc) { /* All registers used by dce11.2 match those in dce11 in offset and * structure @@ -704,7 +704,7 @@ static const struct resource_funcs dce120_res_pool_funcs = { .validate_plane = dce100_validate_plane }; -static void bw_calcs_data_update_from_pplib(struct core_dc *dc) +static void bw_calcs_data_update_from_pplib(struct dc *dc) { struct dm_pp_clock_levels_with_latency eng_clks = {0}; struct dm_pp_clock_levels_with_latency mem_clks = {0}; @@ -831,7 +831,7 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) static bool construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dce110_resource_pool *pool) { unsigned int i; @@ -847,10 +847,10 @@ static bool construct( pool->base.pipe_count = res_cap.num_timing_generator; pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; - dc->public.caps.max_downscale_ratio = 200; - dc->public.caps.i2c_speed_in_khz = 100; - dc->public.caps.max_cursor_size = 128; - dc->public.debug = debug_defaults; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 100; + dc->caps.max_cursor_size = 128; + dc->debug = debug_defaults; /************************************************* * Create resources * @@ -982,7 +982,7 @@ static bool construct( if (!dce120_hw_sequencer_create(dc)) goto controller_create_fail; - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); @@ -1003,7 +1003,7 @@ res_create_fail: struct resource_pool *dce120_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc) + struct dc *dc) { struct dce110_resource_pool *pool = dm_alloc(sizeof(struct dce110_resource_pool)); diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h index 038c78dcc247..3d1f3cf012f4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h @@ -28,12 +28,12 @@ #include "core_types.h" -struct core_dc; +struct dc; struct resource_pool; struct resource_pool *dce120_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc); + struct dc *dc); #endif /* __DC_RESOURCE_DCE120_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c index 4cba80ff6ca4..28fe3824441f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c @@ -25,7 +25,6 @@ #include "dm_services.h" #include "dc.h" -#include "core_dc.h" #include "core_types.h" #include "dce80_hw_sequencer.h" @@ -72,7 +71,7 @@ static const struct dce80_hw_seq_reg_offsets reg_offsets[] = { /***************************PIPE_CONTROL***********************************/ static bool dce80_enable_display_power_gating( - struct core_dc *dc, + struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating) @@ -107,7 +106,7 @@ static bool dce80_enable_display_power_gating( return false; } -bool dce80_hw_sequencer_construct(struct core_dc *dc) +bool dce80_hw_sequencer_construct(struct dc *dc) { dce110_hw_sequencer_construct(dc); diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h index 7cc203f433d3..9d6dd05bd596 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h @@ -28,9 +28,9 @@ #include "core_types.h" -struct core_dc; +struct dc; -bool dce80_hw_sequencer_construct(struct core_dc *dc); +bool dce80_hw_sequencer_construct(struct dc *dc); #endif /* __DC_HWSS_DCE80_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 132117e8bb77..838bfdaee009 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -684,7 +684,7 @@ static void destruct(struct dce110_resource_pool *pool) } static enum dc_status build_mapped_resource( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -720,7 +720,7 @@ static enum dc_status build_mapped_resource( } bool dce80_validate_bandwidth( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context) { /* TODO implement when needed but for now hardcode max value*/ @@ -752,7 +752,7 @@ static bool dce80_validate_surface_sets( } enum dc_status dce80_validate_with_context( - const struct core_dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count, struct validate_context *context, @@ -795,7 +795,7 @@ enum dc_status dce80_validate_with_context( } enum dc_status dce80_validate_guaranteed( - const struct core_dc *dc, + struct dc *dc, struct dc_stream_state *dc_stream, struct validate_context *context) { @@ -815,7 +815,7 @@ enum dc_status dce80_validate_guaranteed( if (result == DC_OK) { validate_guaranteed_copy_streams( - context, dc->public.caps.max_streams); + context, dc->caps.max_streams); result = resource_build_scaling_params_for_context(dc, context); } @@ -845,7 +845,7 @@ static const struct resource_funcs dce80_res_pool_funcs = { static bool dce80_construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dce110_resource_pool *pool) { unsigned int i; @@ -865,9 +865,9 @@ static bool dce80_construct( *************************************************/ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = res_cap.num_timing_generator; - dc->public.caps.max_downscale_ratio = 200; - dc->public.caps.i2c_speed_in_khz = 40; - dc->public.caps.max_cursor_size = 128; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 40; + dc->caps.max_cursor_size = 128; /************************************************* * Create resources * @@ -974,7 +974,7 @@ static bool dce80_construct( } } - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) @@ -993,7 +993,7 @@ res_create_fail: struct resource_pool *dce80_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc) + struct dc *dc) { struct dce110_resource_pool *pool = dm_alloc(sizeof(struct dce110_resource_pool)); @@ -1010,7 +1010,7 @@ struct resource_pool *dce80_create_resource_pool( static bool dce81_construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dce110_resource_pool *pool) { unsigned int i; @@ -1030,9 +1030,9 @@ static bool dce81_construct( *************************************************/ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = res_cap_81.num_timing_generator; - dc->public.caps.max_downscale_ratio = 200; - dc->public.caps.i2c_speed_in_khz = 40; - dc->public.caps.max_cursor_size = 128; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 40; + dc->caps.max_cursor_size = 128; /************************************************* * Create resources * @@ -1139,7 +1139,7 @@ static bool dce81_construct( } } - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) @@ -1158,7 +1158,7 @@ res_create_fail: struct resource_pool *dce81_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc) + struct dc *dc) { struct dce110_resource_pool *pool = dm_alloc(sizeof(struct dce110_resource_pool)); @@ -1175,7 +1175,7 @@ struct resource_pool *dce81_create_resource_pool( static bool dce83_construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dce110_resource_pool *pool) { unsigned int i; @@ -1195,9 +1195,9 @@ static bool dce83_construct( *************************************************/ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = res_cap_83.num_timing_generator; - dc->public.caps.max_downscale_ratio = 200; - dc->public.caps.i2c_speed_in_khz = 40; - dc->public.caps.max_cursor_size = 128; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 40; + dc->caps.max_cursor_size = 128; /************************************************* * Create resources * @@ -1300,7 +1300,7 @@ static bool dce83_construct( } } - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) @@ -1319,7 +1319,7 @@ res_create_fail: struct resource_pool *dce83_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc) + struct dc *dc) { struct dce110_resource_pool *pool = dm_alloc(sizeof(struct dce110_resource_pool)); diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h index 04f0cfe24ef2..eff31ab83a39 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h @@ -28,20 +28,20 @@ #include "core_types.h" -struct core_dc; +struct dc; struct resource_pool; struct resource_pool *dce80_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc); + struct dc *dc); struct resource_pool *dce81_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc); + struct dc *dc); struct resource_pool *dce83_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc); + struct dc *dc); #endif /* __DC_RESOURCE_DCE80_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c index 11386121f8ed..684241cb40d7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c @@ -26,7 +26,6 @@ #if defined(CONFIG_DRM_AMD_DC_DCN1_0) #include "reg_helper.h" -#include "core_dc.h" #include "resource.h" #include "dwb.h" #include "dcn10_dwb.h" diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 184627c8685e..d5d2398d92b8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -52,7 +52,7 @@ #define FN(reg_name, field_name) \ hws->shifts->field_name, hws->masks->field_name -static void log_mpc_crc(struct core_dc *dc) +static void log_mpc_crc(struct dc *dc) { struct dc_context *dc_ctx = dc->ctx; struct dce_hwseq *hws = dc->hwseq; @@ -130,7 +130,7 @@ static void dcn10_hubbub_wm_read_state(struct dce_hwseq *hws, s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); } -static void dcn10_log_hubbub_state(struct core_dc *dc) +static void dcn10_log_hubbub_state(struct dc *dc) { struct dc_context *dc_ctx = dc->ctx; struct dcn_hubbub_wm wm; @@ -157,7 +157,7 @@ static void dcn10_log_hubbub_state(struct core_dc *dc) DTN_INFO("\n"); } -static void dcn10_log_hw_state(struct core_dc *dc) +static void dcn10_log_hw_state(struct dc *dc) { struct dc_context *dc_ctx = dc->ctx; struct resource_pool *pool = dc->res_pool; @@ -273,7 +273,7 @@ static void verify_allow_pstate_change_high( forced_pstate_allow = true; if (should_log_hw_state) { - dcn10_log_hw_state(DC_TO_CORE(hws->ctx->dc)); + dcn10_log_hw_state(hws->ctx->dc); } BREAK_TO_DEBUGGER(); @@ -746,7 +746,7 @@ static void power_on_plane( "Un-gated front end for pipe %d\n", plane_id); } -static void bios_golden_init(struct core_dc *dc) +static void bios_golden_init(struct dc *dc) { struct dc_bios *bp = dc->ctx->dc_bios; int i; @@ -762,7 +762,7 @@ static void bios_golden_init(struct core_dc *dc) } } -static void dcn10_init_hw(struct core_dc *dc) +static void dcn10_init_hw(struct dc *dc) { int i; struct abm *abm = dc->res_pool->abm; @@ -773,7 +773,7 @@ static void dcn10_init_hw(struct core_dc *dc) REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); REG_WRITE(DIO_MEM_PWR_CTRL, 0); - if (!dc->public.debug.disable_clock_gate) { + if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); @@ -830,7 +830,7 @@ static void dcn10_init_hw(struct core_dc *dc) /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ REG_WRITE(DIO_MEM_PWR_CTRL, 0); - if (!dc->public.debug.disable_clock_gate) { + if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); @@ -845,7 +845,7 @@ static void dcn10_init_hw(struct core_dc *dc) static enum dc_status dcn10_prog_pixclk_crtc_otg( struct pipe_ctx *pipe_ctx, struct validate_context *context, - struct core_dc *dc) + struct dc *dc) { struct dc_stream_state *stream = pipe_ctx->stream; enum dc_color_space color_space; @@ -932,7 +932,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( } static void reset_back_end_for_pipe( - struct core_dc *dc, + struct dc *dc, struct pipe_ctx *pipe_ctx, struct validate_context *context) { @@ -979,7 +979,7 @@ static void reset_back_end_for_pipe( } /* trigger HW to start disconnect plane from stream on the next vsync */ -static void plane_atomic_disconnect(struct core_dc *dc, +static void plane_atomic_disconnect(struct dc *dc, int fe_idx) { struct mem_input *mi = dc->res_pool->mis[fe_idx]; @@ -1004,10 +1004,10 @@ static void plane_atomic_disconnect(struct core_dc *dc, if (opp_id == dc->res_pool->pipe_count) return; - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); mi->funcs->dcc_control(mi, false, false); - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); mpc->funcs->remove(mpc, dc->res_pool->opps[opp_id], fe_idx); @@ -1015,7 +1015,7 @@ static void plane_atomic_disconnect(struct core_dc *dc, /* disable HW used by plane. * note: cannot disable until disconnect is complete */ -static void plane_atomic_disable(struct core_dc *dc, +static void plane_atomic_disable(struct dc *dc, int fe_idx) { struct dce_hwseq *hws = dc->hwseq; @@ -1037,7 +1037,7 @@ static void plane_atomic_disable(struct core_dc *dc, mi->opp_id = 0xf; mi->mpcc_id = 0xf; - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); REG_UPDATE(HUBP_CLK_CNTL[fe_idx], @@ -1049,7 +1049,7 @@ static void plane_atomic_disable(struct core_dc *dc, REG_UPDATE(OPP_PIPE_CONTROL[opp_id], OPP_PIPE_CLOCK_EN, 0); - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); } @@ -1057,7 +1057,7 @@ static void plane_atomic_disable(struct core_dc *dc, * kill power to plane hw * note: cannot power down until plane is disable */ -static void plane_atomic_power_down(struct core_dc *dc, int fe_idx) +static void plane_atomic_power_down(struct dc *dc, int fe_idx) { struct dce_hwseq *hws = dc->hwseq; struct transform *xfm = dc->res_pool->transforms[fe_idx]; @@ -1072,13 +1072,13 @@ static void plane_atomic_power_down(struct core_dc *dc, int fe_idx) dm_logger_write(dc->ctx->logger, LOG_DC, "Power gated front end %d\n", fe_idx); - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); } static void reset_front_end( - struct core_dc *dc, + struct dc *dc, int fe_idx) { struct dce_hwseq *hws = dc->hwseq; @@ -1097,7 +1097,7 @@ static void reset_front_end( REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst], VUPDATE_NO_LOCK_EVENT_CLEAR, 1); tg->funcs->unlock(tg); - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(hws); if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) @@ -1112,7 +1112,7 @@ static void reset_front_end( fe_idx); } -static void dcn10_power_down_fe(struct core_dc *dc, int fe_idx) +static void dcn10_power_down_fe(struct dc *dc, int fe_idx) { struct dce_hwseq *hws = dc->hwseq; struct transform *xfm = dc->res_pool->transforms[fe_idx]; @@ -1129,12 +1129,12 @@ static void dcn10_power_down_fe(struct core_dc *dc, int fe_idx) dm_logger_write(dc->ctx->logger, LOG_DC, "Power gated front end %d\n", fe_idx); - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); } static void reset_hw_ctx_wrap( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { int i; @@ -1246,7 +1246,7 @@ static void toggle_watermark_change_req(struct dce_hwseq *hws) DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req); } -static void dcn10_update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ctx) +static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) { bool addr_patched = false; PHYSICAL_ADDRESS_LOC addr; @@ -1657,7 +1657,7 @@ static bool dcn10_set_output_transfer_func( } static void dcn10_pipe_control_lock( - struct core_dc *dc, + struct dc *dc, struct pipe_ctx *pipe, bool lock) { @@ -1669,7 +1669,7 @@ static void dcn10_pipe_control_lock( if (pipe->top_pipe) return; - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); if (lock) @@ -1677,7 +1677,7 @@ static void dcn10_pipe_control_lock( else pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); } @@ -1719,7 +1719,7 @@ static bool wait_for_reset_trigger_to_occur( } static void dcn10_enable_timing_synchronization( - struct core_dc *dc, + struct dc *dc, int group_index, int group_size, struct pipe_ctx *grouped_pipes[]) @@ -1748,7 +1748,7 @@ static void dcn10_enable_timing_synchronization( } static void print_rq_dlg_ttu( - struct core_dc *core_dc, + struct dc *core_dc, struct pipe_ctx *pipe_ctx) { dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS, @@ -1870,14 +1870,14 @@ static void print_rq_dlg_ttu( } static void dcn10_power_on_fe( - struct core_dc *dc, + struct dc *dc, struct pipe_ctx *pipe_ctx, struct validate_context *context) { struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct dce_hwseq *hws = dc->hwseq; - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { verify_allow_pstate_change_high(dc->hwseq); } @@ -1928,7 +1928,7 @@ static void dcn10_power_on_fe( print_rq_dlg_ttu(dc, pipe_ctx); } - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { verify_allow_pstate_change_high(dc->hwseq); } } @@ -2084,7 +2084,7 @@ static void dcn10_get_surface_visual_confirm_color( } static void update_dchubp_dpp( - struct core_dc *dc, + struct dc *dc, struct pipe_ctx *pipe_ctx, struct validate_context *context) { @@ -2126,7 +2126,7 @@ static void update_dchubp_dpp( size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport; - if (dc->public.config.gpu_vm_support) + if (dc->config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( pipe_ctx->plane_res.mi, plane_state->format, @@ -2142,7 +2142,7 @@ static void update_dchubp_dpp( mpcc_cfg.opp = pipe_ctx->stream_res.opp; for (top_pipe = pipe_ctx->top_pipe; top_pipe; top_pipe = top_pipe->top_pipe) mpcc_cfg.z_index++; - if (dc->public.debug.surface_visual_confirm) + if (dc->debug.surface_visual_confirm) dcn10_get_surface_visual_confirm_color( pipe_ctx, &mpcc_cfg.black_color); else @@ -2187,7 +2187,7 @@ static void update_dchubp_dpp( static void program_all_pipe_in_tree( - struct core_dc *dc, + struct dc *dc, struct pipe_ctx *pipe_ctx, struct validate_context *context) { @@ -2201,7 +2201,7 @@ static void program_all_pipe_in_tree( /* watermark is for all pipes */ program_watermarks(dc->hwseq, &context->bw.dcn.watermarks, ref_clk_mhz); - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { /* pstate stuck check after watermark update */ verify_allow_pstate_change_high(dc->hwseq); } @@ -2236,7 +2236,7 @@ static void program_all_pipe_in_tree( update_dchubp_dpp(dc, pipe_ctx, context); } - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { /* pstate stuck check after each pipe is programmed */ verify_allow_pstate_change_high(dc->hwseq); } @@ -2246,7 +2246,7 @@ static void program_all_pipe_in_tree( } static void dcn10_pplib_apply_display_requirements( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; @@ -2273,14 +2273,14 @@ static void dcn10_pplib_apply_display_requirements( } static void dcn10_apply_ctx_for_surface( - struct core_dc *dc, + struct dc *dc, const struct dc_stream_state *stream, int num_planes, struct validate_context *context) { int i, be_idx; - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); be_idx = -1; @@ -2351,7 +2351,7 @@ static void dcn10_apply_ctx_for_surface( "[debug_mpo: apply_ctx disconnect pending on mpcc %d]\n", old_pipe_ctx->mpcc->inst);*/ - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); old_pipe_ctx->top_pipe = NULL; @@ -2422,18 +2422,18 @@ static void dcn10_apply_ctx_for_surface( context->bw.dcn.watermarks.d.pte_meta_urgent_ns ); - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); } static void dcn10_set_bandwidth( - struct core_dc *dc, + struct dc *dc, struct validate_context *context, bool decrease_allowed) { struct dm_pp_clock_for_voltage_req clock; - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { verify_allow_pstate_change_high(dc->hwseq); } @@ -2488,7 +2488,7 @@ static void dcn10_set_bandwidth( } dcn10_pplib_apply_display_requirements(dc, context); - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { verify_allow_pstate_change_high(dc->hwseq); } @@ -2541,7 +2541,7 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx, } static void set_plane_config( - const struct core_dc *dc, + const struct dc *dc, struct pipe_ctx *pipe_ctx, struct resource_context *res_ctx) { @@ -2586,7 +2586,7 @@ static void dcn10_config_stereo_parameters( return; } -static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc) +static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc) { struct crtc_stereo_flags flags = { 0 }; struct dc_stream_state *stream = pipe_ctx->stream; @@ -2607,13 +2607,13 @@ static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc) } static void dcn10_wait_for_mpcc_disconnect( - struct core_dc *dc, + struct dc *dc, struct resource_pool *res_pool, struct pipe_ctx *pipe_ctx) { int i; - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { verify_allow_pstate_change_high(dc->hwseq); } @@ -2631,14 +2631,14 @@ static void dcn10_wait_for_mpcc_disconnect( } } - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { verify_allow_pstate_change_high(dc->hwseq); } } static bool dcn10_dummy_display_power_gating( - struct core_dc *dc, + struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating) @@ -2652,7 +2652,7 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) struct timing_generator *tg = pipe_ctx->stream_res.tg; if (plane_state->ctx->dc->debug.sanity_checks) { - struct core_dc *dc = DC_TO_CORE(plane_state->ctx->dc); + struct dc *dc = plane_state->ctx->dc; verify_allow_pstate_change_high(dc->hwseq); } @@ -2716,7 +2716,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { }; -void dcn10_hw_sequencer_construct(struct core_dc *dc) +void dcn10_hw_sequencer_construct(struct dc *dc) { dc->hwss = dcn10_funcs; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h index 28218dc43522..8bb09de8dcd7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h @@ -28,9 +28,9 @@ #include "core_types.h" -struct core_dc; +struct dc; -void dcn10_hw_sequencer_construct(struct core_dc *dc); +void dcn10_hw_sequencer_construct(struct dc *dc); extern void fill_display_configs( const struct validate_context *context, struct dm_pp_display_configuration *pp_display_cfg); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index c36843d497ac..2d9e88f08abb 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -825,7 +825,7 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) } static enum dc_status build_mapped_resource( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -872,7 +872,7 @@ static enum dc_status build_mapped_resource( } enum dc_status dcn10_validate_with_context( - const struct core_dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count, struct validate_context *context, @@ -917,7 +917,7 @@ enum dc_status dcn10_validate_with_context( } enum dc_status dcn10_validate_guaranteed( - const struct core_dc *dc, + struct dc *dc, struct dc_stream_state *dc_stream, struct validate_context *context) { @@ -937,7 +937,7 @@ enum dc_status dcn10_validate_guaranteed( if (result == DC_OK) { validate_guaranteed_copy_streams( - context, dc->public.caps.max_streams); + context, dc->caps.max_streams); result = resource_build_scaling_params_for_context(dc, context); } if (result == DC_OK && !dcn_validate_bandwidth(dc, context)) @@ -1221,7 +1221,7 @@ static struct resource_funcs dcn10_res_pool_funcs = { static bool construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dcn10_resource_pool *pool) { int i; @@ -1244,16 +1244,16 @@ static bool construct( /* TODO: Hardcode to correct number of functional controllers */ pool->base.pipe_count = 4; - dc->public.caps.max_downscale_ratio = 200; - dc->public.caps.i2c_speed_in_khz = 100; - dc->public.caps.max_cursor_size = 256; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 100; + dc->caps.max_cursor_size = 256; - dc->public.caps.max_slave_planes = 1; + dc->caps.max_slave_planes = 1; if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) - dc->public.debug = debug_defaults_drv; + dc->debug = debug_defaults_drv; else - dc->public.debug = debug_defaults_diags; + dc->debug = debug_defaults_diags; /************************************************* * Create resources * @@ -1327,7 +1327,7 @@ static bool construct( if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { dc->dcn_soc->urgent_latency = 3; - dc->public.debug.disable_dmcu = true; + dc->debug.disable_dmcu = true; dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; } @@ -1347,10 +1347,10 @@ static bool construct( } } - if (!dc->public.debug.disable_pplib_clock_request) + if (!dc->debug.disable_pplib_clock_request) dcn_bw_update_from_pplib(dc); dcn_bw_sync_calcs_and_dml(dc); - if (!dc->public.debug.disable_pplib_wm_range) + if (!dc->debug.disable_pplib_wm_range) dcn_bw_notify_pplib_of_wm_ranges(dc); { @@ -1424,9 +1424,9 @@ static bool construct( goto res_create_fail; dcn10_hw_sequencer_construct(dc); - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; - dc->public.cap_funcs = cap_funcs; + dc->cap_funcs = cap_funcs; return true; @@ -1449,7 +1449,7 @@ dwbc_create_fail: struct resource_pool *dcn10_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc) + struct dc *dc) { struct dcn10_resource_pool *pool = dm_alloc(sizeof(struct dcn10_resource_pool)); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h index 5f84dbd0bdea..8f71225bc61b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h @@ -31,7 +31,7 @@ #define TO_DCN10_RES_POOL(pool)\ container_of(pool, struct dcn10_resource_pool, base) -struct core_dc; +struct dc; struct resource_pool; struct _vcs_dpi_display_pipe_params_st; @@ -40,7 +40,7 @@ struct dcn10_resource_pool { }; struct resource_pool *dcn10_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc); + struct dc *dc); #endif /* __DC_RESOURCE_DCN10_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h deleted file mode 100644 index ebe1fd78a92a..000000000000 --- a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * core_dc.h - * - * Created on: Nov 13, 2015 - * Author: yonsun - */ - -#ifndef __CORE_DC_H__ -#define __CORE_DC_H__ - -#include "core_types.h" -#include "hw_sequencer.h" -#include "compressor.h" - -#define DC_TO_CORE(dc)\ - container_of(dc, struct core_dc, public) - -struct core_dc { - struct dc public; - struct dc_context *ctx; - - uint8_t link_count; - struct dc_link *links[MAX_PIPES * 2]; - - struct validate_context *current_context; - struct resource_pool *res_pool; - - /* Display Engine Clock levels */ - struct dm_pp_clock_levels sclk_lvls; - - /* Inputs into BW and WM calculations. */ - struct bw_calcs_dceip *bw_dceip; - struct bw_calcs_vbios *bw_vbios; -#ifdef CONFIG_DRM_AMD_DC_DCN1_0 - struct dcn_soc_bounding_box *dcn_soc; - struct dcn_ip_params *dcn_ip; - struct display_mode_lib dml; -#endif - - /* HW functions */ - struct hw_sequencer_funcs hwss; - struct dce_hwseq *hwseq; - - /* temp store of dm_pp_display_configuration - * to compare to see if display config changed - */ - struct dm_pp_display_configuration prev_display_config; - - /* FBC compressor */ -#ifdef ENABLE_FBC - struct compressor *fbc_compressor; -#endif -}; - -#endif /* __CORE_DC_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 28454028434c..f8ade552c595 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -52,7 +52,7 @@ void enable_surface_flip_reporting(struct dc_plane_state *plane_state, /************ link *****************/ struct link_init_data { - const struct core_dc *dc; + const struct dc *dc; struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ uint32_t connector_index; /* this will be mapped to the HPD pins */ uint32_t link_index; /* this is mapped to DAL display_index @@ -87,19 +87,19 @@ struct resource_funcs { struct link_encoder *(*link_enc_create)( const struct encoder_init_data *init); enum dc_status (*validate_with_context)( - const struct core_dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count, struct validate_context *context, struct validate_context *old_context); enum dc_status (*validate_guaranteed)( - const struct core_dc *dc, + struct dc *dc, struct dc_stream_state *stream, struct validate_context *context); bool (*validate_bandwidth)( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context); struct pipe_ctx *(*acquire_idle_pipe_for_layer)( diff --git a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h index 36c48f7d3f56..6a205b010084 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h @@ -33,7 +33,7 @@ #include "bw_fixed.h" struct pipe_ctx; -struct core_dc; +struct dc; struct validate_context; struct dce_bw_output; diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h index 7e8abcd60d12..58744fe87ed8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h @@ -34,7 +34,7 @@ #include "display_clock.h" #include "../dml/display_mode_lib.h" -struct core_dc; +struct dc; struct validate_context; /******************************************************************************* @@ -620,16 +620,16 @@ struct dcn_ip_params { extern const struct dcn_ip_params dcn10_ip_defaults; bool dcn_validate_bandwidth( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context); unsigned int dcn_find_dcfclk_suits_all( - const struct core_dc *dc, + const struct dc *dc, struct clocks_value *clocks); -void dcn_bw_update_from_pplib(struct core_dc *dc); -void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc); -void dcn_bw_sync_calcs_and_dml(struct core_dc *dc); +void dcn_bw_update_from_pplib(struct dc *dc); +void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc); +void dcn_bw_sync_calcs_and_dml(struct dc *dc); #endif /* __DCN_CALCS_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index a02f18ae527d..f876a11c903f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -30,6 +30,7 @@ #include "dml/display_mode_structs.h" +struct dchub_init_data; struct cstate_pstate_watermarks_st { uint32_t cstate_exit_ns; uint32_t cstate_enter_plus_exit_ns; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 7689e372b9da..c73dca9f6d46 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -25,8 +25,10 @@ #ifndef __DC_HW_SEQUENCER_H__ #define __DC_HW_SEQUENCER_H__ -#include "core_types.h" -#include "timing_generator.h" +#include "dc_types.h" +#include "clock_source.h" +#include "inc/hw/timing_generator.h" +#include "core_status.h" enum pipe_gating_control { PIPE_GATING_CONTROL_DISABLE = 0, @@ -46,25 +48,31 @@ struct dce_hwseq { struct dce_hwseq_wa wa; }; +struct pipe_ctx; +struct validate_context; +struct dchub_init_data; +struct dc_static_screen_events; +struct resource_pool; +struct resource_context; struct hw_sequencer_funcs { - void (*init_hw)(struct core_dc *dc); + void (*init_hw)(struct dc *dc); enum dc_status (*apply_ctx_to_hw)( - struct core_dc *dc, struct validate_context *context); + struct dc *dc, struct validate_context *context); void (*reset_hw_ctx_wrap)( - struct core_dc *dc, struct validate_context *context); + struct dc *dc, struct validate_context *context); void (*apply_ctx_for_surface)( - struct core_dc *dc, + struct dc *dc, const struct dc_stream_state *stream, int num_planes, struct validate_context *context); void (*set_plane_config)( - const struct core_dc *dc, + const struct dc *dc, struct pipe_ctx *pipe_ctx, struct resource_context *res_ctx); @@ -77,7 +85,7 @@ struct hw_sequencer_funcs { uint16_t *matrix); void (*update_plane_addr)( - const struct core_dc *dc, + const struct dc *dc, struct pipe_ctx *pipe_ctx); void (*update_dchub)( @@ -95,12 +103,12 @@ struct hw_sequencer_funcs { struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream); - void (*power_down)(struct core_dc *dc); + void (*power_down)(struct dc *dc); - void (*enable_accelerated_mode)(struct core_dc *dc); + void (*enable_accelerated_mode)(struct dc *dc); void (*enable_timing_synchronization)( - struct core_dc *dc, + struct dc *dc, int group_index, int group_size, struct pipe_ctx *grouped_pipes[]); @@ -110,14 +118,14 @@ struct hw_sequencer_funcs { bool clock_gating); bool (*enable_display_power_gating)( - struct core_dc *dc, + struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating); - void (*power_down_front_end)(struct core_dc *dc, int fe_idx); + void (*power_down_front_end)(struct dc *dc, int fe_idx); - void (*power_on_front_end)(struct core_dc *dc, + void (*power_on_front_end)(struct dc *dc, struct pipe_ctx *pipe, struct validate_context *context); @@ -131,12 +139,12 @@ struct hw_sequencer_funcs { struct dc_link_settings *link_settings); void (*pipe_control_lock)( - struct core_dc *dc, + struct dc *dc, struct pipe_ctx *pipe, bool lock); void (*set_bandwidth)( - struct core_dc *dc, + struct dc *dc, struct validate_context *context, bool decrease_allowed); @@ -152,23 +160,23 @@ struct hw_sequencer_funcs { enum dc_status (*prog_pixclk_crtc_otg)( struct pipe_ctx *pipe_ctx, struct validate_context *context, - struct core_dc *dc); + struct dc *dc); void (*setup_stereo)( struct pipe_ctx *pipe_ctx, - struct core_dc *dc); + struct dc *dc); void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); - void (*log_hw_state)(struct core_dc *dc); + void (*log_hw_state)(struct dc *dc); - void (*wait_for_mpcc_disconnect)(struct core_dc *dc, + void (*wait_for_mpcc_disconnect)(struct dc *dc, struct resource_pool *res_pool, struct pipe_ctx *pipe_ctx); }; void color_space_to_black_color( - const struct core_dc *dc, + const struct dc *dc, enum dc_color_space colorspace, struct tg_color *black_color); diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index 7f30d9937d10..13218a52e2fa 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -27,7 +27,6 @@ #include "core_types.h" #include "core_status.h" -#include "core_dc.h" #include "dal_asic_id.h" /* TODO unhardcode, 4 for CZ*/ @@ -67,27 +66,27 @@ struct resource_create_funcs { bool resource_construct( unsigned int num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct resource_pool *pool, const struct resource_create_funcs *create_funcs); struct resource_pool *dc_create_resource_pool( - struct core_dc *dc, + struct dc *dc, int num_virtual_links, enum dce_version dc_version, struct hw_asic_id asic_id); -void dc_destroy_resource_pool(struct core_dc *dc); +void dc_destroy_resource_pool(struct dc *dc); enum dc_status resource_map_pool_resources( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context); bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx); enum dc_status resource_build_scaling_params_for_context( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context); void resource_build_info_frame(struct pipe_ctx *pipe_ctx); @@ -148,12 +147,12 @@ void resource_validate_ctx_update_pointer_after_copy( struct validate_context *dst_ctx); enum dc_status resource_map_clock_resources( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context); enum dc_status resource_map_phy_clock_resources( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context); diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c index 24e47eb8cf3f..e3a12f3e0642 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c @@ -34,8 +34,8 @@ #include "ivsrcid/ivsrcid_vislands30.h" -#include "core_dc.h" - +#include "dc.h" +#include "core_types.h" static bool hpd_ack( struct irq_service *irq_service, const struct irq_source_info *info) @@ -206,7 +206,7 @@ bool dce110_vblank_set( bool enable) { struct dc_context *dc_ctx = irq_service->ctx; - struct core_dc *core_dc = DC_TO_CORE(irq_service->ctx->dc); + struct dc *core_dc = irq_service->ctx->dc; enum dc_irq_source dal_irq_src = dc_interrupt_to_irq_source( irq_service->ctx->dc, info->src_id, diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c index 7e8cb22f280f..f458ef8e4c57 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c @@ -36,7 +36,6 @@ #include "ivsrcid/ivsrcid_vislands30.h" #include "dc_types.h" -#include "inc/core_dc.h" static bool hpd_ack( struct irq_service *irq_service, diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index beb790937769..93c8556358f0 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -76,23 +76,23 @@ void logger_write(struct dal_logger *logger, void *paralist); void pre_surface_trace( - const struct dc *dc, + struct dc *dc, const struct dc_plane_state *const *plane_states, int surface_count); void update_surface_trace( - const struct dc *dc, + struct dc *dc, const struct dc_surface_update *updates, int surface_count); -void post_surface_trace(const struct dc *dc); +void post_surface_trace(struct dc *dc); void context_timing_trace( - const struct dc *dc, + struct dc *dc, struct resource_context *res_ctx); void context_clock_trace( - const struct dc *dc, + struct dc *dc, struct validate_context *context); /* Any function which is empty or have incomplete implementation should be diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index f0a3e4332a09..f49203b3eb94 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -27,7 +27,6 @@ #include "dc.h" #include "mod_freesync.h" #include "core_types.h" -#include "core_dc.h" #define MOD_FREESYNC_MAX_CONCURRENT_STREAMS 32 @@ -146,7 +145,7 @@ struct mod_freesync *mod_freesync_create(struct dc *dc) struct core_freesync *core_freesync = dm_alloc(sizeof(struct core_freesync)); - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct persistent_data_flag flag; @@ -246,7 +245,7 @@ static unsigned int map_index_from_stream(struct core_freesync *core_freesync, bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, struct dc_stream_state *stream, struct mod_freesync_caps *caps) { - struct core_dc *core_dc = NULL; + struct dc *core_dc = NULL; struct core_freesync *core_freesync = NULL; int persistent_freesync_enable = 0; struct persistent_data_flag flag; @@ -257,7 +256,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, return false; core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); - core_dc = DC_TO_CORE(core_freesync->dc); + core_dc = core_freesync->dc; flag.save_per_edid = true; flag.save_per_link = false; @@ -971,14 +970,14 @@ bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, unsigned int stream_index, map_index; int persistent_data = 0; struct persistent_data_flag flag; - struct core_dc *core_dc = NULL; + struct dc *core_dc = NULL; struct core_freesync *core_freesync = NULL; if (mod_freesync == NULL) return false; core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); - core_dc = DC_TO_CORE(core_freesync->dc); + core_dc = core_freesync->dc; flag.save_per_edid = true; flag.save_per_link = false; -- cgit v1.2.3 From 608ac7bb3924178d7bfa8b88d79d3d9d72b8f485 Mon Sep 17 00:00:00 2001 From: Jerry Zuo Date: Fri, 25 Aug 2017 16:16:10 -0400 Subject: drm/amd/display: Rename dc validate_context and current_context MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename all the dc validate_context to dc_state and dc current_context to current_state. Signed-off-by: Jerry Zuo Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 6 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 108 ++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 +- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 40 ++++---- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 15 ++- drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 4 +- drivers/gpu/drm/amd/display/dc/dc.h | 38 ++++---- .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 4 +- .../amd/display/dc/dce100/dce100_hw_sequencer.c | 8 +- .../amd/display/dc/dce100/dce100_hw_sequencer.h | 4 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 10 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 70 ++++++------- .../amd/display/dc/dce110/dce110_hw_sequencer.h | 12 +-- .../drm/amd/display/dc/dce110/dce110_resource.c | 16 +-- .../drm/amd/display/dc/dce112/dce112_resource.c | 16 +-- .../drm/amd/display/dc/dce112/dce112_resource.h | 10 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 10 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 62 ++++++------ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 2 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 8 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 14 +-- drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 4 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 14 +-- drivers/gpu/drm/amd/display/dc/inc/resource.h | 22 ++--- .../amd/display/dc/irq/dce110/irq_service_dce110.c | 2 +- .../gpu/drm/amd/display/include/logger_interface.h | 4 +- 32 files changed, 263 insertions(+), 264 deletions(-) (limited to 'drivers/gpu/drm/amd/display/include/logger_interface.h') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9c44b82036fa..9b018115d97e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -711,7 +711,7 @@ dm_atomic_state_clear(struct drm_atomic_state *state) struct dm_atomic_state *dm_state = to_dm_atomic_state(state); if (dm_state->context) { - dc_release_validate_context(dm_state->context); + dc_release_state(dm_state->context); dm_state->context = NULL; } @@ -4098,7 +4098,7 @@ void amdgpu_dm_atomic_commit_tail( } if (dm_state->context) - WARN_ON(!dc_commit_context(dm->dc, dm_state->context)); + WARN_ON(!dc_commit_state(dm->dc, dm_state->context)); list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index e0a5632f00a3..71cbee199016 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -209,7 +209,7 @@ struct dm_crtc_state { struct dm_atomic_state { struct drm_atomic_state base; - struct validate_context *context; + struct dc_state *context; }; #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 6c85a54e47d6..ee1b76c074e6 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -476,7 +476,7 @@ static void dcn_bw_calc_rq_dlg_ttu( static void dcn_dml_wm_override( const struct dcn_bw_internal_vars *v, struct display_mode_lib *dml, - struct validate_context *context, + struct dc_state *context, const struct resource_pool *pool) { int i, in_idx, active_count; @@ -593,7 +593,7 @@ static void split_stream_across_pipes( } static void calc_wm_sets_and_perf_params( - struct validate_context *context, + struct dc_state *context, struct dcn_bw_internal_vars *v) { /* Calculate set A last to keep internal var state consistent for required config */ @@ -721,7 +721,7 @@ static bool dcn_bw_apply_registry_override(struct dc *dc) bool dcn_validate_bandwidth( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { const struct resource_pool *pool = dc->res_pool; struct dcn_bw_internal_vars *v = &context->dcn_bw_vars; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index a20dc24db0d5..53f814dcc24d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -160,7 +160,7 @@ static bool stream_adjust_vmin_vmax(struct dc *dc, bool ret = false; for (i = 0; i < MAX_PIPES; i++) { - struct pipe_ctx *pipe = &dc->current_context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; if (pipe->stream == stream && pipe->stream_res.stream_enc) { dc->hwss.set_drr(&pipe, 1, vmin, vmax); @@ -187,7 +187,7 @@ static bool stream_get_crtc_position(struct dc *dc, for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; if (pipe->stream == stream && pipe->stream_res.stream_enc) { dc->hwss.get_position(&pipe, 1, &position); @@ -207,8 +207,8 @@ static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) struct pipe_ctx *pipes; for (i = 0; i < MAX_PIPES; i++) { - if (dc->current_context->res_ctx.pipe_ctx[i].stream == stream) { - pipes = &dc->current_context->res_ctx.pipe_ctx[i]; + if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) { + pipes = &dc->current_state->res_ctx.pipe_ctx[i]; dc->hwss.program_gamut_remap(pipes); ret = true; } @@ -224,10 +224,10 @@ static bool program_csc_matrix(struct dc *dc, struct dc_stream_state *stream) struct pipe_ctx *pipes; for (i = 0; i < MAX_PIPES; i++) { - if (dc->current_context->res_ctx.pipe_ctx[i].stream + if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) { - pipes = &dc->current_context->res_ctx.pipe_ctx[i]; + pipes = &dc->current_state->res_ctx.pipe_ctx[i]; dc->hwss.program_csc_matrix(pipes, stream->output_color_space, stream->csc_color_matrix.matrix); @@ -252,10 +252,10 @@ static void set_static_screen_events(struct dc *dc, struct dc_stream_state *stream = streams[i]; for (j = 0; j < MAX_PIPES; j++) { - if (dc->current_context->res_ctx.pipe_ctx[j].stream + if (dc->current_state->res_ctx.pipe_ctx[j].stream == stream) { pipes_affected[num_pipes_affected++] = - &dc->current_context->res_ctx.pipe_ctx[j]; + &dc->current_state->res_ctx.pipe_ctx[j]; } } } @@ -334,7 +334,7 @@ void set_dither_option(struct dc_stream_state *stream, { struct bit_depth_reduction_params params; struct dc_link *link = stream->status.link; - struct pipe_ctx *pipes = link->dc->current_context->res_ctx.pipe_ctx; + struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; memset(¶ms, 0, sizeof(params)); if (!stream) @@ -408,8 +408,8 @@ static void allocate_dc_stream_funcs(struct dc *dc) static void destruct(struct dc *dc) { - dc_release_validate_context(dc->current_context); - dc->current_context = NULL; + dc_release_state(dc->current_state); + dc->current_state = NULL; destroy_links(dc); @@ -494,9 +494,9 @@ static bool construct(struct dc *dc, goto fail; } - dc->current_context = dc_create_state(); + dc->current_state = dc_create_state(); - if (!dc->current_context) { + if (!dc->current_state) { dm_error("%s: failed to create validate ctx\n", __func__); goto fail; } @@ -668,12 +668,12 @@ bool dc_validate_guaranteed( struct dc_stream_state *stream) { enum dc_status result = DC_ERROR_UNEXPECTED; - struct validate_context *context; + struct dc_state *context; if (!dc_validate_stream(dc, stream)) return false; - context = dm_alloc(sizeof(struct validate_context)); + context = dm_alloc(sizeof(struct dc_state)); if (context == NULL) goto context_alloc_fail; @@ -682,7 +682,7 @@ bool dc_validate_guaranteed( result = dc->res_pool->funcs->validate_guaranteed( dc, stream, context); - dc_release_validate_context(context); + dc_release_state(context); context_alloc_fail: if (result != DC_OK) { @@ -697,7 +697,7 @@ context_alloc_fail: static void program_timing_sync( struct dc *dc, - struct validate_context *ctx) + struct dc_state *ctx) { int i, j; int group_index = 0; @@ -771,15 +771,15 @@ static void program_timing_sync( static bool context_changed( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { uint8_t i; - if (context->stream_count != dc->current_context->stream_count) + if (context->stream_count != dc->current_state->stream_count) return true; - for (i = 0; i < dc->current_context->stream_count; i++) { - if (dc->current_context->streams[i] != context->streams[i]) + for (i = 0; i < dc->current_state->stream_count; i++) { + if (dc->current_state->streams[i] != context->streams[i]) return true; } @@ -788,7 +788,7 @@ static bool context_changed( bool dc_enable_stereo( struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *streams[], uint8_t stream_count) { @@ -800,7 +800,7 @@ bool dc_enable_stereo( if (context != NULL) pipe = &context->res_ctx.pipe_ctx[i]; else - pipe = &dc->current_context->res_ctx.pipe_ctx[i]; + pipe = &dc->current_state->res_ctx.pipe_ctx[i]; for (j = 0 ; pipe && j < stream_count; j++) { if (streams[j] && streams[j] == pipe->stream && dc->hwss.setup_stereo) @@ -816,7 +816,7 @@ bool dc_enable_stereo( * Applies given context to HW and copy it into current context. * It's up to the user to release the src context afterwards. */ -static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *context) +static bool dc_commit_state_no_check(struct dc *dc, struct dc_state *context) { struct dc_bios *dcb = dc->ctx->dc_bios; enum dc_status result = DC_ERROR_UNEXPECTED; @@ -875,18 +875,18 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c dc_enable_stereo(dc, context, dc_streams, context->stream_count); - dc_release_validate_context(dc->current_context); + dc_release_state(dc->current_state); - dc->current_context = context; + dc->current_state = context; - dc_retain_validate_context(dc->current_context); + dc_retain_state(dc->current_state); dc->hwss.optimize_shared_resources(dc); return (result == DC_OK); } -bool dc_commit_context(struct dc *dc, struct validate_context *context) +bool dc_commit_state(struct dc *dc, struct dc_state *context) { enum dc_status result = DC_ERROR_UNEXPECTED; int i; @@ -905,7 +905,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context) LOG_DC); } - result = dc_commit_context_no_check(dc, context); + result = dc_commit_state_no_check(dc, context); return (result == DC_OK); } @@ -914,7 +914,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context) bool dc_post_update_surfaces_to_stream(struct dc *dc) { int i; - struct validate_context *context = dc->current_context; + struct dc_state *context = dc->current_state; post_surface_trace(dc); @@ -999,9 +999,9 @@ bool dc_commit_planes_to_stream( return true; } -struct validate_context *dc_create_state(void) +struct dc_state *dc_create_state(void) { - struct validate_context *context = dm_alloc(sizeof(struct validate_context)); + struct dc_state *context = dm_alloc(sizeof(struct dc_state)); if (!context) return NULL; @@ -1010,13 +1010,13 @@ struct validate_context *dc_create_state(void) return context; } -void dc_retain_validate_context(struct validate_context *context) +void dc_retain_state(struct dc_state *context) { ASSERT(atomic_read(&context->ref_count) > 0); atomic_inc(&context->ref_count); } -void dc_release_validate_context(struct validate_context *context) +void dc_release_state(struct dc_state *context) { ASSERT(atomic_read(&context->ref_count) > 0); atomic_dec(&context->ref_count); @@ -1028,7 +1028,7 @@ void dc_release_validate_context(struct validate_context *context) } static bool is_surface_in_context( - const struct validate_context *context, + const struct dc_state *context, const struct dc_plane_state *plane_state) { int j; @@ -1145,7 +1145,7 @@ static enum surface_update_type det_surface_update( const struct dc_surface_update *u, int surface_index) { - const struct validate_context *context = dc->current_context; + const struct dc_state *context = dc->current_state; enum surface_update_type type = UPDATE_TYPE_FAST; enum surface_update_type overall_type = UPDATE_TYPE_FAST; @@ -1200,7 +1200,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream( } static struct dc_stream_status *stream_get_status( - struct validate_context *ctx, + struct dc_state *ctx, struct dc_stream_state *stream) { uint8_t i; @@ -1221,7 +1221,7 @@ void dc_update_planes_and_stream(struct dc *dc, struct dc_stream_state *stream, struct dc_stream_update *stream_update) { - struct validate_context *context; + struct dc_state *context; int i, j; enum surface_update_type update_type; const struct dc_stream_status *stream_status; @@ -1239,7 +1239,7 @@ void dc_update_planes_and_stream(struct dc *dc, ASSERT(0); } #endif - context = dc->current_context; + context = dc->current_state; /* update current stream with the new updates */ if (stream_update) { @@ -1293,7 +1293,7 @@ void dc_update_planes_and_stream(struct dc *dc, goto context_alloc_fail; dc_resource_validate_ctx_copy_construct( - dc->current_context, context); + dc->current_state, context); /*remove old surfaces from context */ if (!dc_rem_all_planes_for_stream(dc, stream, context)) { @@ -1437,7 +1437,7 @@ void dc_update_planes_and_stream(struct dc *dc, /* Full fe update*/ for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[j]; + struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[j]; bool is_new_pipe_surface = cur_pipe_ctx->plane_state != pipe_ctx->plane_state; struct dc_cursor_position position = { 0 }; @@ -1524,7 +1524,7 @@ void dc_update_planes_and_stream(struct dc *dc, } } - if (dc->current_context != context) { + if (dc->current_state != context) { /* Since memory free requires elevated IRQL, an interrupt * request is generated by mem free. If this happens @@ -1534,16 +1534,16 @@ void dc_update_planes_and_stream(struct dc *dc, * then free the old context. */ - struct validate_context *old = dc->current_context; + struct dc_state *old = dc->current_state; - dc->current_context = context; - dc_release_validate_context(old); + dc->current_state = context; + dc_release_state(old); } return; fail: - dc_release_validate_context(context); + dc_release_state(context); context_alloc_fail: DC_ERROR("Failed to allocate new validate context!\n"); @@ -1551,13 +1551,13 @@ context_alloc_fail: uint8_t dc_get_current_stream_count(struct dc *dc) { - return dc->current_context->stream_count; + return dc->current_state->stream_count; } struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i) { - if (i < dc->current_context->stream_count) - return dc->current_context->streams[i]; + if (i < dc->current_state->stream_count) + return dc->current_state->streams[i]; return NULL; } @@ -1634,11 +1634,11 @@ void dc_set_power_state( */ /* Preserve refcount */ - ref_count = dc->current_context->ref_count; - dc_resource_validate_ctx_destruct(dc->current_context); - memset(dc->current_context, 0, - sizeof(*dc->current_context)); - dc->current_context->ref_count = ref_count; + ref_count = dc->current_state->ref_count; + dc_resource_validate_ctx_destruct(dc->current_state); + memset(dc->current_state, 0, + sizeof(*dc->current_state)); + dc->current_state->ref_count = ref_count; break; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index d74eed8f9b96..6acee5426e4b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -329,7 +329,7 @@ void context_timing_trace( void context_clock_trace( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { #if defined(CONFIG_DRM_AMD_DC_DCN1_0) struct dc *core_dc = dc; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 0bdd41ca8799..65e12614d96c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1819,14 +1819,14 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, if (dc_is_embedded_signal(link->connector_signal)) { if (stream != NULL) { for (i = 0; i < MAX_PIPES; i++) { - if (core_dc->current_context->res_ctx. + if (core_dc->current_state->res_ctx. pipe_ctx[i].stream == stream) /* DMCU -1 for all controller id values, * therefore +1 here */ controller_id = - core_dc->current_context-> + core_dc->current_state-> res_ctx.pipe_ctx[i].stream_res.tg->inst + 1; } @@ -1926,13 +1926,13 @@ bool dc_link_setup_psr(struct dc_link *link, psr_context->engineId = link->link_enc->preferred_engine; for (i = 0; i < MAX_PIPES; i++) { - if (core_dc->current_context->res_ctx.pipe_ctx[i].stream + if (core_dc->current_state->res_ctx.pipe_ctx[i].stream == stream) { /* dmcu -1 for all controller id values, * therefore +1 here */ psr_context->controllerId = - core_dc->current_context->res_ctx. + core_dc->current_state->res_ctx. pipe_ctx[i].stream_res.tg->inst + 1; break; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 446e2933474c..5f2b52e41427 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -2406,7 +2406,7 @@ bool dc_link_dp_set_test_pattern( const unsigned char *p_custom_pattern, unsigned int cust_pattern_size) { - struct pipe_ctx *pipes = link->dc->current_context->res_ctx.pipe_ctx; + struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; struct pipe_ctx *pipe_ctx = &pipes[0]; unsigned int lane; unsigned int i; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index 23d8b614e0fd..3427fb5b7e30 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -62,7 +62,7 @@ void dp_enable_link_phy( struct link_encoder *link_enc = link->link_enc; struct pipe_ctx *pipes = - link->dc->current_context->res_ctx.pipe_ctx; + link->dc->current_state->res_ctx.pipe_ctx; struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source; unsigned int i; @@ -262,7 +262,7 @@ void dp_retrain_link_dp_test(struct dc_link *link, bool skip_video_pattern) { struct pipe_ctx *pipes = - &link->dc->current_context->res_ctx.pipe_ctx[0]; + &link->dc->current_state->res_ctx.pipe_ctx[0]; unsigned int i; for (i = 0; i < MAX_PIPES; i++) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 9eb8d48bc889..727afeaa3830 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -893,7 +893,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) enum dc_status resource_build_scaling_params_for_context( const struct dc *dc, - struct validate_context *context) + struct dc_state *context) { int i; @@ -971,7 +971,7 @@ static struct pipe_ctx *resource_get_tail_pipe_for_stream( * that has no surface attached yet */ static struct pipe_ctx *acquire_free_pipe_for_stream( - struct validate_context *context, + struct dc_state *context, const struct resource_pool *pool, struct dc_stream_state *stream) { @@ -1048,7 +1048,7 @@ bool dc_add_plane_to_context( const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, - struct validate_context *context) + struct dc_state *context) { int i; struct resource_pool *pool = dc->res_pool; @@ -1124,7 +1124,7 @@ bool dc_remove_plane_from_context( const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, - struct validate_context *context) + struct dc_state *context) { int i; struct dc_stream_status *stream_status = NULL; @@ -1199,7 +1199,7 @@ bool dc_remove_plane_from_context( bool dc_rem_all_planes_for_stream( const struct dc *dc, struct dc_stream_state *stream, - struct validate_context *context) + struct dc_state *context) { int i, old_plane_count; struct dc_stream_status *stream_status = NULL; @@ -1233,7 +1233,7 @@ static bool add_all_planes_for_stream( struct dc_stream_state *stream, const struct dc_validation_set set[], int set_count, - struct validate_context *context) + struct dc_state *context) { int i, j; @@ -1258,7 +1258,7 @@ bool dc_add_all_planes_for_stream( struct dc_stream_state *stream, struct dc_plane_state * const *plane_states, int plane_count, - struct validate_context *context) + struct dc_state *context) { struct dc_validation_set set; int i; @@ -1434,7 +1434,7 @@ static struct audio *find_first_free_audio( } bool resource_is_stream_unchanged( - struct validate_context *old_context, struct dc_stream_state *stream) + struct dc_state *old_context, struct dc_stream_state *stream) { int i; @@ -1450,7 +1450,7 @@ bool resource_is_stream_unchanged( bool dc_add_stream_to_ctx( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *stream) { struct dc_context *dc_ctx = dc->ctx; @@ -1474,7 +1474,7 @@ bool dc_add_stream_to_ctx( bool dc_remove_stream_from_ctx( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *stream) { int i; @@ -1553,7 +1553,7 @@ static void copy_pipe_ctx( static struct dc_stream_state *find_pll_sharable_stream( struct dc_stream_state *stream_needs_pll, - struct validate_context *context) + struct dc_state *context) { int i; @@ -1615,7 +1615,7 @@ static void calculate_phy_pix_clks(struct dc_stream_state *stream) enum dc_status resource_map_pool_resources( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { const struct resource_pool *pool = dc->res_pool; @@ -1689,7 +1689,7 @@ enum dc_status resource_map_pool_resources( /* first stream in the context is used to populate the rest */ void validate_guaranteed_copy_streams( - struct validate_context *context, + struct dc_state *context, int max_streams) { int i; @@ -1709,14 +1709,14 @@ void validate_guaranteed_copy_streams( void dc_resource_validate_ctx_copy_construct_current( const struct dc *dc, - struct validate_context *dst_ctx) + struct dc_state *dst_ctx) { - dc_resource_validate_ctx_copy_construct(dc->current_context, dst_ctx); + dc_resource_validate_ctx_copy_construct(dc->current_state, dst_ctx); } bool dc_validate_global_state( struct dc *dc, - struct validate_context *new_ctx) + struct dc_state *new_ctx) { enum dc_status result = DC_ERROR_UNEXPECTED; int i, j; @@ -2413,7 +2413,7 @@ static void set_vsc_info_packet( /*TODO: stereo 3D support and extend pixel encoding colorimetry*/ } -void dc_resource_validate_ctx_destruct(struct validate_context *context) +void dc_resource_validate_ctx_destruct(struct dc_state *context) { int i, j; @@ -2433,8 +2433,8 @@ void dc_resource_validate_ctx_destruct(struct validate_context *context) * by the src_ctx */ void dc_resource_validate_ctx_copy_construct( - const struct validate_context *src_ctx, - struct validate_context *dst_ctx) + const struct dc_state *src_ctx, + struct dc_state *dst_ctx) { int i, j; atomic_t ref_count = dst_ctx->ref_count; @@ -2518,7 +2518,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) enum dc_status resource_map_clock_resources( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { /* acquire new resources */ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 0e7cc293184e..a421779093d9 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -169,10 +169,9 @@ struct dc_stream_status *dc_stream_get_status( uint8_t i; struct dc *dc = stream->ctx->dc; - for (i = 0; i < dc->current_context->stream_count; i++) { - if (stream == dc->current_context->streams[i]) { - return &dc->current_context->stream_status[i]; - } + for (i = 0; i < dc->current_state->stream_count; i++) { + if (stream == dc->current_state->streams[i]) + return &dc->current_state->stream_status[i]; } return NULL; @@ -199,7 +198,7 @@ bool dc_stream_set_cursor_attributes( } core_dc = stream->ctx->dc; - res_ctx = &core_dc->current_context->res_ctx; + res_ctx = &core_dc->current_state->res_ctx; for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; @@ -235,7 +234,7 @@ bool dc_stream_set_cursor_position( } core_dc = stream->ctx->dc; - res_ctx = &core_dc->current_context->res_ctx; + res_ctx = &core_dc->current_state->res_ctx; for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; @@ -271,7 +270,7 @@ uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) uint8_t i; struct dc *core_dc = stream->ctx->dc; struct resource_context *res_ctx = - &core_dc->current_context->res_ctx; + &core_dc->current_state->res_ctx; for (i = 0; i < MAX_PIPES; i++) { struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; @@ -295,7 +294,7 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, bool ret = false; struct dc *core_dc = stream->ctx->dc; struct resource_context *res_ctx = - &core_dc->current_context->res_ctx; + &core_dc->current_state->res_ctx; for (i = 0; i < MAX_PIPES; i++) { struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index 0b6410fb2f3e..e96f63eed070 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -104,12 +104,12 @@ const struct dc_plane_status *dc_plane_get_status( plane_status = &plane_state->status; core_dc = plane_state->ctx->dc; - if (core_dc->current_context == NULL) + if (core_dc->current_state == NULL) return NULL; for (i = 0; i < core_dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = - &core_dc->current_context->res_ctx.pipe_ctx[i]; + &core_dc->current_state->res_ctx.pipe_ctx[i]; if (pipe_ctx->plane_state != plane_state) continue; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 55fc58102515..d1d5737398df 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -99,7 +99,7 @@ struct dc_static_screen_events { /* Forward declaration*/ struct dc; struct dc_plane_state; -struct validate_context; +struct dc_state; struct dc_cap_funcs { bool (*get_dcc_compression_cap)(const struct dc *dc, @@ -192,7 +192,7 @@ struct dc_debug { bool disable_psr; bool force_abm_enable; }; -struct validate_context; +struct dc_state; struct resource_pool; struct dce_hwseq; struct dc { @@ -208,7 +208,7 @@ struct dc { uint8_t link_count; struct dc_link *links[MAX_PIPES * 2]; - struct validate_context *current_context; + struct dc_state *current_state; struct resource_pool *res_pool; /* Display Engine Clock levels */ @@ -621,12 +621,12 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, bool dc_add_stream_to_ctx( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *stream); bool dc_remove_stream_from_ctx( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *stream); @@ -634,25 +634,25 @@ bool dc_add_plane_to_context( const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, - struct validate_context *context); + struct dc_state *context); bool dc_remove_plane_from_context( const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, - struct validate_context *context); + struct dc_state *context); bool dc_rem_all_planes_for_stream( const struct dc *dc, struct dc_stream_state *stream, - struct validate_context *context); + struct dc_state *context); bool dc_add_all_planes_for_stream( const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state * const *plane_states, int plane_count, - struct validate_context *context); + struct dc_state *context); /* * Structure to store surface/stream associations for validation @@ -669,7 +669,7 @@ bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); bool dc_validate_global_state( struct dc *dc, - struct validate_context *new_ctx); + struct dc_state *new_ctx); /* * This function takes a stream and checks if it is guaranteed to be supported. @@ -680,14 +680,14 @@ bool dc_validate_global_state( */ void dc_resource_validate_ctx_copy_construct( - const struct validate_context *src_ctx, - struct validate_context *dst_ctx); + const struct dc_state *src_ctx, + struct dc_state *dst_ctx); void dc_resource_validate_ctx_copy_construct_current( const struct dc *dc, - struct validate_context *dst_ctx); + struct dc_state *dst_ctx); -void dc_resource_validate_ctx_destruct(struct validate_context *context); +void dc_resource_validate_ctx_destruct(struct dc_state *context); /* * TODO update to make it about validation sets @@ -698,7 +698,7 @@ void dc_resource_validate_ctx_destruct(struct validate_context *context); * Phy, Encoder, Timing Generator are programmed and enabled. * New streams are enabled with blank stream; no memory read. */ -bool dc_commit_context(struct dc *dc, struct validate_context *context); +bool dc_commit_state(struct dc *dc, struct dc_state *context); /* * Set up streams and links associated to drive sinks @@ -714,7 +714,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context); */ bool dc_enable_stereo( struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *streams[], uint8_t stream_count); @@ -737,9 +737,9 @@ enum surface_update_type dc_check_update_surfaces_for_stream( const struct dc_stream_status *stream_status); -struct validate_context *dc_create_state(void); -void dc_retain_validate_context(struct validate_context *context); -void dc_release_validate_context(struct validate_context *context); +struct dc_state *dc_create_state(void); +void dc_retain_state(struct dc_state *context); +void dc_release_state(struct dc_state *context); /******************************************************************************* * Link Interfaces diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 0654fe34627c..d3b61b92ebec 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -609,7 +609,7 @@ static uint32_t dce110_get_pll_pixel_rate_in_hz( { uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; struct dc *dc_core = cs->ctx->dc; - struct validate_context *context = dc_core->current_context; + struct dc_state *context = dc_core->current_state; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst]; /* This function need separate to different DCE version, before separate, just use pixel clock */ @@ -624,7 +624,7 @@ static uint32_t dce110_get_dp_pixel_rate_from_combo_phy_pll( { uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; struct dc *dc_core = cs->ctx->dc; - struct validate_context *context = dc_core->current_context; + struct dc_state *context = dc_core->current_state; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst]; /* This function need separate to different DCE version, before separate, just use pixel clock */ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c index b7e51c5ed1b1..492ea6069eb4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c @@ -107,7 +107,7 @@ static bool dce100_enable_display_power_gating( static void dce100_pplib_apply_display_requirements( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; @@ -127,14 +127,14 @@ static void dce100_pplib_apply_display_requirements( void dce100_set_bandwidth( struct dc *dc, - struct validate_context *context, + struct dc_state *context, bool decrease_allowed) { - if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_context->bw.dce.dispclk_khz) { + if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_state->bw.dce.dispclk_khz) { dc->res_pool->display_clock->funcs->set_clock( dc->res_pool->display_clock, context->bw.dce.dispclk_khz * 115 / 100); - dc->current_context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz; + dc->current_state->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz; } dce100_pplib_apply_display_requirements(dc, context); } diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h index c04aa15cd656..770b5bb1ff40 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h @@ -29,13 +29,13 @@ #include "core_types.h" struct dc; -struct validate_context; +struct dc_state; bool dce100_hw_sequencer_construct(struct dc *dc); void dce100_set_bandwidth( struct dc *dc, - struct validate_context *context, + struct dc_state *context, bool decrease_allowed); #endif /* __DC_HWSS_DCE100_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index c991610315b2..36d79175354c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -653,7 +653,7 @@ static void destruct(struct dce110_resource_pool *pool) static enum dc_status build_mapped_resource( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { enum dc_status status = DC_OK; @@ -674,7 +674,7 @@ static enum dc_status build_mapped_resource( bool dce100_validate_bandwidth( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { /* TODO implement when needed but for now hardcode max value*/ context->bw.dce.dispclk_khz = 681000; @@ -684,7 +684,7 @@ bool dce100_validate_bandwidth( } static bool dce100_validate_surface_sets( - struct validate_context *context) + struct dc_state *context) { int i; @@ -705,7 +705,7 @@ static bool dce100_validate_surface_sets( enum dc_status dce100_validate_global( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { if (!dce100_validate_surface_sets(context)) return DC_FAIL_SURFACE_VALIDATE; @@ -716,7 +716,7 @@ enum dc_status dce100_validate_global( enum dc_status dce100_validate_guaranteed( struct dc *dc, struct dc_stream_state *dc_stream, - struct validate_context *context) + struct dc_state *context) { enum dc_status result = DC_ERROR_UNEXPECTED; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 3502faa1458f..1c6e2006f2a1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -976,11 +976,11 @@ static void program_scaler(const struct dc *dc, static enum dc_status dce110_prog_pixclk_crtc_otg( struct pipe_ctx *pipe_ctx, - struct validate_context *context, + struct dc_state *context, struct dc *dc) { struct dc_stream_state *stream = pipe_ctx->stream; - struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. + struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. pipe_ctx[pipe_ctx->pipe_idx]; struct tg_color black_color = {0}; @@ -1032,11 +1032,11 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( static enum dc_status apply_single_controller_ctx_to_hw( struct pipe_ctx *pipe_ctx, - struct validate_context *context, + struct dc_state *context, struct dc *dc) { struct dc_stream_state *stream = pipe_ctx->stream; - struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. + struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. pipe_ctx[pipe_ctx->pipe_idx]; /* */ @@ -1257,7 +1257,7 @@ static uint32_t compute_pstate_blackout_duration( void dce110_set_displaymarks( const struct dc *dc, - struct validate_context *context) + struct dc_state *context) { uint8_t i, num_pipes; unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; @@ -1415,7 +1415,7 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx, */ static uint32_t get_max_pixel_clock_for_all_paths( struct dc *dc, - struct validate_context *context, + struct dc_state *context, bool pre_mode_set) { uint32_t max_pix_clk = 0; @@ -1456,7 +1456,7 @@ static uint32_t get_max_pixel_clock_for_all_paths( */ static void apply_min_clocks( struct dc *dc, - struct validate_context *context, + struct dc_state *context, enum dm_pp_clocks_state *clocks_state, bool pre_mode_set) { @@ -1545,7 +1545,7 @@ static void apply_min_clocks( * Check if FBC can be enabled */ static enum dc_status validate_fbc(struct dc *dc, - struct validate_context *context) + struct dc_state *context) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[0]; @@ -1575,7 +1575,7 @@ static enum dc_status validate_fbc(struct dc *dc, * Enable FBC */ static enum dc_status enable_fbc(struct dc *dc, - struct validate_context *context) + struct dc_state *context) { enum dc_status status = validate_fbc(dc, context); @@ -1604,14 +1604,14 @@ static enum dc_status enable_fbc(struct dc *dc, static enum dc_status apply_ctx_to_hw_fpga( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { enum dc_status status = DC_ERROR_UNEXPECTED; int i; for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx_old = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; if (pipe_ctx->stream == NULL) @@ -1634,7 +1634,7 @@ static enum dc_status apply_ctx_to_hw_fpga( static void dce110_reset_hw_ctx_wrap( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { int i; @@ -1642,7 +1642,7 @@ static void dce110_reset_hw_ctx_wrap( /* look up the targets that have been removed since last commit */ for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx_old = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; /* Note: We need to disable output if clock sources change, @@ -1664,9 +1664,9 @@ static void dce110_reset_hw_ctx_wrap( } pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); pipe_ctx_old->plane_res.mi->funcs->free_mem_input( - pipe_ctx_old->plane_res.mi, dc->current_context->stream_count); + pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); resource_unreference_clock_source( - &dc->current_context->res_ctx, dc->res_pool, + &dc->current_state->res_ctx, dc->res_pool, &pipe_ctx_old->clock_source); dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx); @@ -1679,7 +1679,7 @@ static void dce110_reset_hw_ctx_wrap( enum dc_status dce110_apply_ctx_to_hw( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { struct dc_bios *dcb = dc->ctx->dc_bios; enum dc_status status; @@ -1705,7 +1705,7 @@ enum dc_status dce110_apply_ctx_to_hw( /* below is for real asic only */ for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx_old = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) @@ -1735,31 +1735,31 @@ enum dc_status dce110_apply_ctx_to_hw( #if defined(CONFIG_DRM_AMD_DC_DCN1_0) if (dc->ctx->dce_version >= DCN_VERSION_1_0) { if (context->bw.dcn.calc_clk.fclk_khz - > dc->current_context->bw.dcn.cur_clk.fclk_khz) { + > dc->current_state->bw.dcn.cur_clk.fclk_khz) { struct dm_pp_clock_for_voltage_req clock; clock.clk_type = DM_PP_CLOCK_TYPE_FCLK; clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz; dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); - dc->current_context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; + dc->current_state->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; } if (context->bw.dcn.calc_clk.dcfclk_khz - > dc->current_context->bw.dcn.cur_clk.dcfclk_khz) { + > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) { struct dm_pp_clock_for_voltage_req clock; clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz; dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); - dc->current_context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; + dc->current_state->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; } if (context->bw.dcn.calc_clk.dispclk_khz - > dc->current_context->bw.dcn.cur_clk.dispclk_khz) { + > dc->current_state->bw.dcn.cur_clk.dispclk_khz) { dc->res_pool->display_clock->funcs->set_clock( dc->res_pool->display_clock, context->bw.dcn.calc_clk.dispclk_khz); - dc->current_context->bw.dcn.cur_clk.dispclk_khz = + dc->current_state->bw.dcn.cur_clk.dispclk_khz = context->bw.dcn.calc_clk.dispclk_khz; context->bw.dcn.cur_clk.dispclk_khz = context->bw.dcn.calc_clk.dispclk_khz; @@ -1767,7 +1767,7 @@ enum dc_status dce110_apply_ctx_to_hw( } else #endif if (context->bw.dce.dispclk_khz - > dc->current_context->bw.dce.dispclk_khz) { + > dc->current_state->bw.dce.dispclk_khz) { dc->res_pool->display_clock->funcs->set_clock( dc->res_pool->display_clock, context->bw.dce.dispclk_khz * 115 / 100); @@ -1848,7 +1848,7 @@ enum dc_status dce110_apply_ctx_to_hw( for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx_old = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; if (pipe_ctx->stream == NULL) @@ -2327,7 +2327,7 @@ static void init_hw(struct dc *dc) } void dce110_fill_display_configs( - const struct validate_context *context, + const struct dc_state *context, struct dm_pp_display_configuration *pp_display_cfg) { int j; @@ -2375,7 +2375,7 @@ void dce110_fill_display_configs( pp_display_cfg->display_count = num_cfgs; } -uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context) +uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context) { uint8_t j; uint32_t min_vertical_blank_time = -1; @@ -2427,7 +2427,7 @@ static int determine_sclk_from_bounding_box( static void pplib_apply_display_requirements( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; @@ -2481,16 +2481,16 @@ static void pplib_apply_display_requirements( static void dce110_set_bandwidth( struct dc *dc, - struct validate_context *context, + struct dc_state *context, bool decrease_allowed) { dce110_set_displaymarks(dc, context); - if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_context->bw.dce.dispclk_khz) { + if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_state->bw.dce.dispclk_khz) { dc->res_pool->display_clock->funcs->set_clock( dc->res_pool->display_clock, context->bw.dce.dispclk_khz * 115 / 100); - dc->current_context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz; + dc->current_state->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz; } pplib_apply_display_requirements(dc, context); @@ -2508,8 +2508,8 @@ static void dce110_program_front_end_for_pipe( memset(&tbl_entry, 0, sizeof(tbl_entry)); - if (dc->current_context) - old_pipe = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; + if (dc->current_state) + old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; memset(&adjust, 0, sizeof(adjust)); adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; @@ -2627,7 +2627,7 @@ static void dce110_apply_ctx_for_surface( struct dc *dc, const struct dc_stream_state *stream, int num_planes, - struct validate_context *context) + struct dc_state *context) { int i, be_idx; @@ -2657,7 +2657,7 @@ static void dce110_apply_ctx_for_surface( static void dce110_power_down_fe(struct dc *dc, int fe_idx) { /* Do not power down fe when stream is active on dce*/ - if (dc->current_context->res_ctx.pipe_ctx[fe_idx].stream) + if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) return; dc->hwss.enable_display_power_gating( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h index ac418fd83894..baa20c1f17ad 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h @@ -30,20 +30,20 @@ #define GAMMA_HW_POINTS_NUM 256 struct dc; -struct validate_context; +struct dc_state; struct dm_pp_display_configuration; bool dce110_hw_sequencer_construct(struct dc *dc); enum dc_status dce110_apply_ctx_to_hw( struct dc *dc, - struct validate_context *context); + struct dc_state *context); -void dce110_set_display_clock(struct validate_context *context); +void dce110_set_display_clock(struct dc_state *context); void dce110_set_displaymarks( const struct dc *dc, - struct validate_context *context); + struct dc_state *context); void dce110_enable_stream(struct pipe_ctx *pipe_ctx); @@ -62,10 +62,10 @@ void dce110_power_down(struct dc *dc); void dce110_update_pending_status(struct pipe_ctx *pipe_ctx); void dce110_fill_display_configs( - const struct validate_context *context, + const struct dc_state *context, struct dm_pp_display_configuration *pp_display_cfg); -uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context); +uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context); void dp_receiver_power_ctrl(struct dc_link *link, bool on); #endif /* __DC_HWSS_DCE110_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 18c67f89e9b5..94b6eb83e01e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -773,7 +773,7 @@ static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigne static enum dc_status build_mapped_resource( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { enum dc_status status = DC_OK; @@ -800,7 +800,7 @@ static enum dc_status build_mapped_resource( static bool dce110_validate_bandwidth( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { bool result = false; @@ -826,7 +826,7 @@ static bool dce110_validate_bandwidth( context->streams[0]->timing.v_addressable, context->streams[0]->timing.pix_clk_khz); - if (memcmp(&dc->current_context->bw.dce, + if (memcmp(&dc->current_state->bw.dce, &context->bw.dce, sizeof(context->bw.dce))) { struct log_entry log_entry; dm_logger_open( @@ -880,7 +880,7 @@ static bool dce110_validate_bandwidth( } static bool dce110_validate_surface_sets( - struct validate_context *context) + struct dc_state *context) { int i; @@ -913,7 +913,7 @@ static bool dce110_validate_surface_sets( enum dc_status dce110_validate_global( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { if (!dce110_validate_surface_sets(context)) return DC_FAIL_SURFACE_VALIDATE; @@ -924,7 +924,7 @@ enum dc_status dce110_validate_global( static enum dc_status dce110_validate_guaranteed( struct dc *dc, struct dc_stream_state *dc_stream, - struct validate_context *context) + struct dc_state *context) { enum dc_status result = DC_ERROR_UNEXPECTED; @@ -954,7 +954,7 @@ static enum dc_status dce110_validate_guaranteed( } static struct pipe_ctx *dce110_acquire_underlay( - struct validate_context *context, + struct dc_state *context, const struct resource_pool *pool, struct dc_stream_state *stream) { @@ -976,7 +976,7 @@ static struct pipe_ctx *dce110_acquire_underlay( pipe_ctx->stream = stream; - if (!dc->current_context->res_ctx.pipe_ctx[underlay_idx].stream) { + if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { struct tg_color black_color = {0}; struct dc_bios *dcb = dc->ctx->dc_bios; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index d5a8ee69171d..de6f71d8a89b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -724,7 +724,7 @@ static struct clock_source *find_matching_pll( static enum dc_status build_mapped_resource( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { enum dc_status status = DC_OK; @@ -745,7 +745,7 @@ static enum dc_status build_mapped_resource( bool dce112_validate_bandwidth( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { bool result = false; @@ -768,7 +768,7 @@ bool dce112_validate_bandwidth( "%s: Bandwidth validation failed!", __func__); - if (memcmp(&dc->current_context->bw.dce, + if (memcmp(&dc->current_state->bw.dce, &context->bw.dce, sizeof(context->bw.dce))) { struct log_entry log_entry; dm_logger_open( @@ -823,7 +823,7 @@ bool dce112_validate_bandwidth( enum dc_status resource_map_phy_clock_resources( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { @@ -855,7 +855,7 @@ enum dc_status resource_map_phy_clock_resources( } static bool dce112_validate_surface_sets( - struct validate_context *context) + struct dc_state *context) { int i; @@ -876,7 +876,7 @@ static bool dce112_validate_surface_sets( enum dc_status dce112_add_stream_to_ctx( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *dc_stream) { enum dc_status result = DC_ERROR_UNEXPECTED; @@ -896,7 +896,7 @@ enum dc_status dce112_add_stream_to_ctx( enum dc_status dce112_validate_guaranteed( struct dc *dc, struct dc_stream_state *stream, - struct validate_context *context) + struct dc_state *context) { enum dc_status result = DC_ERROR_UNEXPECTED; @@ -927,7 +927,7 @@ enum dc_status dce112_validate_guaranteed( enum dc_status dce112_validate_global( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { if (!dce112_validate_surface_sets(context)) return DC_FAIL_SURFACE_VALIDATE; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h index f1834bfe3d1e..d5c19d34eb0a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h @@ -39,21 +39,21 @@ enum dc_status dce112_validate_with_context( struct dc *dc, const struct dc_validation_set set[], int set_count, - struct validate_context *context, - struct validate_context *old_context); + struct dc_state *context, + struct dc_state *old_context); enum dc_status dce112_validate_guaranteed( struct dc *dc, struct dc_stream_state *dc_stream, - struct validate_context *context); + struct dc_state *context); bool dce112_validate_bandwidth( struct dc *dc, - struct validate_context *context); + struct dc_state *context); enum dc_status dce112_add_stream_to_ctx( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *dc_stream); diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 945ff7ee6cd9..316080767a21 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -685,7 +685,7 @@ static void destruct(struct dce110_resource_pool *pool) static enum dc_status build_mapped_resource( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { enum dc_status status = DC_OK; @@ -706,7 +706,7 @@ static enum dc_status build_mapped_resource( bool dce80_validate_bandwidth( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { /* TODO implement when needed but for now hardcode max value*/ context->bw.dce.dispclk_khz = 681000; @@ -716,7 +716,7 @@ bool dce80_validate_bandwidth( } static bool dce80_validate_surface_sets( - struct validate_context *context) + struct dc_state *context) { int i; @@ -737,7 +737,7 @@ static bool dce80_validate_surface_sets( enum dc_status dce80_validate_global( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { if (!dce80_validate_surface_sets(context)) return DC_FAIL_SURFACE_VALIDATE; @@ -748,7 +748,7 @@ enum dc_status dce80_validate_global( enum dc_status dce80_validate_guaranteed( struct dc *dc, struct dc_stream_state *dc_stream, - struct validate_context *context) + struct dc_state *context) { enum dc_status result = DC_ERROR_UNEXPECTED; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 9c54cae28997..71ff1cedbdf4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -793,7 +793,7 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc) static void ready_shared_resources(struct dc *dc) { - if (dc->current_context->stream_count == 0 && + if (dc->current_state->stream_count == 0 && !dc->debug.disable_stutter) undo_DEGVIDCN10_253_wa(dc); } @@ -815,7 +815,7 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc) static void optimize_shared_resources(struct dc *dc) { - if (dc->current_context->stream_count == 0 && + if (dc->current_state->stream_count == 0 && !dc->debug.disable_stutter) apply_DEGVIDCN10_253_wa(dc); } @@ -918,7 +918,7 @@ static void dcn10_init_hw(struct dc *dc) static enum dc_status dcn10_prog_pixclk_crtc_otg( struct pipe_ctx *pipe_ctx, - struct validate_context *context, + struct dc_state *context, struct dc *dc) { struct dc_stream_state *stream = pipe_ctx->stream; @@ -1008,7 +1008,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( static void reset_back_end_for_pipe( struct dc *dc, struct pipe_ctx *pipe_ctx, - struct validate_context *context) + struct dc_state *context) { int i; @@ -1040,7 +1040,7 @@ static void reset_back_end_for_pipe( &pipe_ctx->clock_source); for (i = 0; i < dc->res_pool->pipe_count; i++) - if (&dc->current_context->res_ctx.pipe_ctx[i] == pipe_ctx) + if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) break; if (i == dc->res_pool->pipe_count) @@ -1206,14 +1206,14 @@ static void dcn10_power_down_fe(struct dc *dc, int fe_idx) static void reset_hw_ctx_wrap( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { int i; /* Reset Front End*/ /* Lock*/ for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; struct timing_generator *tg = cur_pipe_ctx->stream_res.tg; if (cur_pipe_ctx->stream) @@ -1222,7 +1222,7 @@ static void reset_hw_ctx_wrap( /* Disconnect*/ for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { struct pipe_ctx *pipe_ctx_old = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; if (!pipe_ctx->stream || @@ -1234,7 +1234,7 @@ static void reset_hw_ctx_wrap( } /* Unlock*/ for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { - struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; struct timing_generator *tg = cur_pipe_ctx->stream_res.tg; if (cur_pipe_ctx->stream) @@ -1244,7 +1244,7 @@ static void reset_hw_ctx_wrap( /* Disable and Powerdown*/ for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { struct pipe_ctx *pipe_ctx_old = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; /*if (!pipe_ctx_old->stream) @@ -1263,7 +1263,7 @@ static void reset_hw_ctx_wrap( /* Reset Back End*/ for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { struct pipe_ctx *pipe_ctx_old = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; if (!pipe_ctx_old->stream) @@ -1271,7 +1271,7 @@ static void reset_hw_ctx_wrap( if (!pipe_ctx->stream || pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) - reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_context); + reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); } } @@ -1943,7 +1943,7 @@ static void print_rq_dlg_ttu( static void dcn10_power_on_fe( struct dc *dc, struct pipe_ctx *pipe_ctx, - struct validate_context *context) + struct dc_state *context) { struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct dce_hwseq *hws = dc->hwseq; @@ -2244,7 +2244,7 @@ static void dcn10_program_pte_vm(struct mem_input *mem_input, static void update_dchubp_dpp( struct dc *dc, struct pipe_ctx *pipe_ctx, - struct validate_context *context) + struct dc_state *context) { struct dce_hwseq *hws = dc->hwseq; struct mem_input *mi = pipe_ctx->plane_res.mi; @@ -2263,7 +2263,7 @@ static void update_dchubp_dpp( pipe_ctx->pipe_idx, pipe_ctx->stream_res.pix_clk_params.requested_pix_clk, context->bw.dcn.calc_clk.dppclk_div); - dc->current_context->bw.dcn.cur_clk.dppclk_div = + dc->current_state->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div; context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div; @@ -2350,7 +2350,7 @@ static void update_dchubp_dpp( static void program_all_pipe_in_tree( struct dc *dc, struct pipe_ctx *pipe_ctx, - struct validate_context *context) + struct dc_state *context) { unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000; @@ -2408,7 +2408,7 @@ static void program_all_pipe_in_tree( static void dcn10_pplib_apply_display_requirements( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; @@ -2437,7 +2437,7 @@ static void dcn10_apply_ctx_for_surface( struct dc *dc, const struct dc_stream_state *stream, int num_planes, - struct validate_context *context) + struct dc_state *context) { int i, be_idx; @@ -2457,7 +2457,7 @@ static void dcn10_apply_ctx_for_surface( if (num_planes == 0) { for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { struct pipe_ctx *old_pipe_ctx = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; if (old_pipe_ctx->stream_res.tg && old_pipe_ctx->stream_res.tg->inst == be_idx) { old_pipe_ctx->stream_res.tg->funcs->set_blank(old_pipe_ctx->stream_res.tg, true); @@ -2471,7 +2471,7 @@ static void dcn10_apply_ctx_for_surface( for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; struct pipe_ctx *old_pipe_ctx = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) continue; @@ -2591,7 +2591,7 @@ static void dcn10_apply_ctx_for_surface( static void dcn10_set_bandwidth( struct dc *dc, - struct validate_context *context, + struct dc_state *context, bool decrease_allowed) { struct pp_smu_display_requirement_rv *smu_req_cur = @@ -2607,25 +2607,25 @@ static void dcn10_set_bandwidth( return; if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz - > dc->current_context->bw.dcn.cur_clk.dispclk_khz) { + > dc->current_state->bw.dcn.cur_clk.dispclk_khz) { dc->res_pool->display_clock->funcs->set_clock( dc->res_pool->display_clock, context->bw.dcn.calc_clk.dispclk_khz); - dc->current_context->bw.dcn.cur_clk.dispclk_khz = + dc->current_state->bw.dcn.cur_clk.dispclk_khz = context->bw.dcn.calc_clk.dispclk_khz; } if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz - > dc->current_context->bw.dcn.cur_clk.dcfclk_khz) { + > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) { smu_req.hard_min_dcefclk_khz = context->bw.dcn.calc_clk.dcfclk_khz; } if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz - > dc->current_context->bw.dcn.cur_clk.fclk_khz) { + > dc->current_state->bw.dcn.cur_clk.fclk_khz) { smu_req.hard_min_fclk_khz = context->bw.dcn.calc_clk.fclk_khz; } if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz - > dc->current_context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) { - dc->current_context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = + > dc->current_state->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) { + dc->current_state->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz; context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz = context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz; @@ -2640,15 +2640,15 @@ static void dcn10_set_bandwidth( /* Decrease in freq is increase in period so opposite comparison for dram_ccm */ if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us - < dc->current_context->bw.dcn.cur_clk.dram_ccm_us) { - dc->current_context->bw.dcn.calc_clk.dram_ccm_us = + < dc->current_state->bw.dcn.cur_clk.dram_ccm_us) { + dc->current_state->bw.dcn.calc_clk.dram_ccm_us = context->bw.dcn.calc_clk.dram_ccm_us; context->bw.dcn.cur_clk.dram_ccm_us = context->bw.dcn.calc_clk.dram_ccm_us; } if (decrease_allowed || context->bw.dcn.calc_clk.min_active_dram_ccm_us - < dc->current_context->bw.dcn.cur_clk.min_active_dram_ccm_us) { - dc->current_context->bw.dcn.calc_clk.min_active_dram_ccm_us = + < dc->current_state->bw.dcn.cur_clk.min_active_dram_ccm_us) { + dc->current_state->bw.dcn.calc_clk.min_active_dram_ccm_us = context->bw.dcn.calc_clk.min_active_dram_ccm_us; context->bw.dcn.cur_clk.min_active_dram_ccm_us = context->bw.dcn.calc_clk.min_active_dram_ccm_us; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h index 8bb09de8dcd7..ca53dc1cc19b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h @@ -32,7 +32,7 @@ struct dc; void dcn10_hw_sequencer_construct(struct dc *dc); extern void fill_display_configs( - const struct validate_context *context, + const struct dc_state *context, struct dm_pp_display_configuration *pp_display_cfg); #endif /* __DC_HWSS_DCN10_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index d09ed13fb8ea..fff86ad0c411 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -850,7 +850,7 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) static enum dc_status build_mapped_resource( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { enum dc_status status = DC_OK; @@ -887,7 +887,7 @@ static enum dc_status build_mapped_resource( enum dc_status dcn10_add_stream_to_ctx( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *dc_stream) { enum dc_status result = DC_ERROR_UNEXPECTED; @@ -907,7 +907,7 @@ enum dc_status dcn10_add_stream_to_ctx( enum dc_status dcn10_validate_guaranteed( struct dc *dc, struct dc_stream_state *dc_stream, - struct validate_context *context) + struct dc_state *context) { enum dc_status result = DC_ERROR_UNEXPECTED; @@ -935,7 +935,7 @@ enum dc_status dcn10_validate_guaranteed( } static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( - struct validate_context *context, + struct dc_state *context, const struct resource_pool *pool, struct dc_stream_state *stream) { diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index bd1a6367872f..71eb9859faf2 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -80,7 +80,7 @@ void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); #include "transform.h" struct resource_pool; -struct validate_context; +struct dc_state; struct resource_context; struct resource_funcs { @@ -91,18 +91,18 @@ struct resource_funcs { enum dc_status (*validate_guaranteed)( struct dc *dc, struct dc_stream_state *stream, - struct validate_context *context); + struct dc_state *context); bool (*validate_bandwidth)( struct dc *dc, - struct validate_context *context); + struct dc_state *context); enum dc_status (*validate_global)( struct dc *dc, - struct validate_context *context); + struct dc_state *context); struct pipe_ctx *(*acquire_idle_pipe_for_layer)( - struct validate_context *context, + struct dc_state *context, const struct resource_pool *pool, struct dc_stream_state *stream); @@ -110,7 +110,7 @@ struct resource_funcs { enum dc_status (*add_stream_to_ctx)( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *dc_stream); }; @@ -252,7 +252,7 @@ union bw_context { struct dce_bw_output dce; }; -struct validate_context { +struct dc_state { struct dc_stream_state *streams[MAX_PIPES]; struct dc_stream_status stream_status[MAX_PIPES]; uint8_t stream_count; diff --git a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h index 6a205b010084..ae2399f16d1c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h @@ -34,7 +34,7 @@ struct pipe_ctx; struct dc; -struct validate_context; +struct dc_state; struct dce_bw_output; enum bw_calcs_version { diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h index 58744fe87ed8..1e231f6de732 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h @@ -35,7 +35,7 @@ #include "../dml/display_mode_lib.h" struct dc; -struct validate_context; +struct dc_state; /******************************************************************************* * DCN data structures. @@ -621,7 +621,7 @@ extern const struct dcn_ip_params dcn10_ip_defaults; bool dcn_validate_bandwidth( struct dc *dc, - struct validate_context *context); + struct dc_state *context); unsigned int dcn_find_dcfclk_suits_all( const struct dc *dc, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 01e426194163..aae7629b1c08 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -49,7 +49,7 @@ struct dce_hwseq { }; struct pipe_ctx; -struct validate_context; +struct dc_state; struct dchub_init_data; struct dc_static_screen_events; struct resource_pool; @@ -60,16 +60,16 @@ struct hw_sequencer_funcs { void (*init_hw)(struct dc *dc); enum dc_status (*apply_ctx_to_hw)( - struct dc *dc, struct validate_context *context); + struct dc *dc, struct dc_state *context); void (*reset_hw_ctx_wrap)( - struct dc *dc, struct validate_context *context); + struct dc *dc, struct dc_state *context); void (*apply_ctx_for_surface)( struct dc *dc, const struct dc_stream_state *stream, int num_planes, - struct validate_context *context); + struct dc_state *context); void (*set_plane_config)( const struct dc *dc, @@ -127,7 +127,7 @@ struct hw_sequencer_funcs { void (*power_on_front_end)(struct dc *dc, struct pipe_ctx *pipe, - struct validate_context *context); + struct dc_state *context); void (*update_info_frame)(struct pipe_ctx *pipe_ctx); @@ -145,7 +145,7 @@ struct hw_sequencer_funcs { void (*set_bandwidth)( struct dc *dc, - struct validate_context *context, + struct dc_state *context, bool decrease_allowed); void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, @@ -159,7 +159,7 @@ struct hw_sequencer_funcs { enum dc_status (*prog_pixclk_crtc_otg)( struct pipe_ctx *pipe_ctx, - struct validate_context *context, + struct dc_state *context, struct dc *dc); void (*setup_stereo)( diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index ebc0f5b02365..41437da5fb9b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -81,14 +81,14 @@ void dc_destroy_resource_pool(struct dc *dc); enum dc_status resource_map_pool_resources( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream); bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx); enum dc_status resource_build_scaling_params_for_context( const struct dc *dc, - struct validate_context *context); + struct dc_state *context); void resource_build_info_frame(struct pipe_ctx *pipe_ctx); @@ -122,7 +122,7 @@ bool resource_attach_surfaces_to_context( struct dc_plane_state *const *plane_state, int surface_count, struct dc_stream_state *dc_stream, - struct validate_context *context, + struct dc_state *context, const struct resource_pool *pool); struct pipe_ctx *find_idle_secondary_pipe( @@ -130,31 +130,31 @@ struct pipe_ctx *find_idle_secondary_pipe( const struct resource_pool *pool); bool resource_is_stream_unchanged( - struct validate_context *old_context, struct dc_stream_state *stream); + struct dc_state *old_context, struct dc_stream_state *stream); bool resource_validate_attach_surfaces( const struct dc_validation_set set[], int set_count, - const struct validate_context *old_context, - struct validate_context *context, + const struct dc_state *old_context, + struct dc_state *context, const struct resource_pool *pool); void validate_guaranteed_copy_streams( - struct validate_context *context, + struct dc_state *context, int max_streams); void resource_validate_ctx_update_pointer_after_copy( - const struct validate_context *src_ctx, - struct validate_context *dst_ctx); + const struct dc_state *src_ctx, + struct dc_state *dst_ctx); enum dc_status resource_map_clock_resources( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream); enum dc_status resource_map_phy_clock_resources( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream); bool pipe_need_reprogram( diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c index e3a12f3e0642..7cce28489dba 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c @@ -214,7 +214,7 @@ bool dce110_vblank_set( uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK; struct timing_generator *tg = - core_dc->current_context->res_ctx.pipe_ctx[pipe_offset].stream_res.tg; + core_dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg; if (enable) { if (!tg->funcs->arm_vert_intr(tg, 2)) { diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index 93c8556358f0..6641e8001e97 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -32,7 +32,7 @@ struct dc_context; struct dc_link; struct dc_surface_update; struct resource_context; -struct validate_context; +struct dc_state; /* * @@ -93,7 +93,7 @@ void context_timing_trace( void context_clock_trace( struct dc *dc, - struct validate_context *context); + struct dc_state *context); /* Any function which is empty or have incomplete implementation should be * marked by this macro. -- cgit v1.2.3 From 01a526f3dee9abe1e2db9e37e4ceb4149f8ae77b Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 12 Sep 2017 19:33:40 -0400 Subject: drm/amd/display: Pass log_mask from DM Linux and Windows often desire different log levels. Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ drivers/gpu/drm/amd/display/dc/basics/logger.c | 41 +++------------------- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- drivers/gpu/drm/amd/display/dc/dc.h | 1 + .../gpu/drm/amd/display/include/logger_interface.h | 2 +- drivers/gpu/drm/amd/display/include/logger_types.h | 32 +++++++++++++++++ 6 files changed, 42 insertions(+), 38 deletions(-) (limited to 'drivers/gpu/drm/amd/display/include/logger_interface.h') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index bb4f415746d5..5f4e7dc92797 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -374,6 +374,8 @@ int amdgpu_dm_init(struct amdgpu_device *adev) init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; + init_data.log_mask = DC_DEFAULT_LOG_MASK; + #ifdef ENABLE_FBC if (adev->family == FAMILY_CZ) amdgpu_dm_initialize_fbc(adev); diff --git a/drivers/gpu/drm/amd/display/dc/basics/logger.c b/drivers/gpu/drm/amd/display/dc/basics/logger.c index 0b17374b1535..5895dd3903a3 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/logger.c +++ b/drivers/gpu/drm/amd/display/dc/basics/logger.c @@ -64,40 +64,9 @@ static const struct dc_log_type_info log_type_info_tbl[] = { }; -#define DC_DEFAULT_LOG_MASK ((1 << LOG_ERROR) | \ - (1 << LOG_WARNING) | \ - (1 << LOG_EVENT_MODE_SET) | \ - (1 << LOG_EVENT_DETECTION) | \ - (1 << LOG_EVENT_LINK_TRAINING) | \ - (1 << LOG_EVENT_LINK_LOSS) | \ - (1 << LOG_EVENT_UNDERFLOW) | \ - (1 << LOG_RESOURCE) | \ - (1 << LOG_FEATURE_OVERRIDE) | \ - (1 << LOG_DETECTION_EDID_PARSER) | \ - (1 << LOG_DC) | \ - (1 << LOG_HW_HOTPLUG) | \ - (1 << LOG_HW_SET_MODE) | \ - (1 << LOG_HW_RESUME_S3) | \ - (1 << LOG_HW_HPD_IRQ) | \ - (1 << LOG_SYNC) | \ - (1 << LOG_BANDWIDTH_VALIDATION) | \ - (1 << LOG_MST) | \ - (1 << LOG_DETECTION_DP_CAPS) | \ - (1 << LOG_BACKLIGHT)) | \ - (1 << LOG_I2C_AUX) | \ - (1 << LOG_IF_TRACE) | \ - (1 << LOG_DTN) /* | \ - (1 << LOG_DEBUG) | \ - (1 << LOG_BIOS) | \ - (1 << LOG_SURFACE) | \ - (1 << LOG_SCALER) | \ - (1 << LOG_DML) | \ - (1 << LOG_HW_LINK_TRAINING) | \ - (1 << LOG_HW_AUDIO)| \ - (1 << LOG_BANDWIDTH_CALCS)*/ - /* ----------- Object init and destruction ----------- */ -static bool construct(struct dc_context *ctx, struct dal_logger *logger) +static bool construct(struct dc_context *ctx, struct dal_logger *logger, + uint32_t log_mask) { /* malloc buffer and init offsets */ logger->log_buffer_size = DAL_LOGGER_BUFFER_MAX_SIZE; @@ -120,7 +89,7 @@ static bool construct(struct dc_context *ctx, struct dal_logger *logger) logger->ctx = ctx; - logger->mask = DC_DEFAULT_LOG_MASK; + logger->mask = log_mask; return true; } @@ -133,14 +102,14 @@ static void destruct(struct dal_logger *logger) } } -struct dal_logger *dal_logger_create(struct dc_context *ctx) +struct dal_logger *dal_logger_create(struct dc_context *ctx, uint32_t log_mask) { /* malloc struct */ struct dal_logger *logger = dm_alloc(sizeof(struct dal_logger)); if (!logger) return NULL; - if (!construct(ctx, logger)) { + if (!construct(ctx, logger, log_mask)) { dm_free(logger); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 5579d2167a9a..75a5fa2296d7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -493,7 +493,7 @@ static bool construct(struct dc *dc, dc_ctx->asic_id = init_params->asic_id; /* Create logger */ - logger = dal_logger_create(dc_ctx); + logger = dal_logger_create(dc_ctx, init_params->log_mask); if (!logger) { /* can *not* call logger. call base driver 'print error' */ diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 1f0521ff4614..9c0e00050753 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -267,6 +267,7 @@ struct dc_init_data { enum dce_environment dce_environment; struct dc_config flags; + uint32_t log_mask; #ifdef ENABLE_FBC uint64_t fbc_gpu_addr; #endif diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index 6641e8001e97..5aaf2dacfe38 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -40,7 +40,7 @@ struct dc_state; * */ -struct dal_logger *dal_logger_create(struct dc_context *ctx); +struct dal_logger *dal_logger_create(struct dc_context *ctx, uint32_t log_mask); uint32_t dal_logger_destroy(struct dal_logger **logger); diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h b/drivers/gpu/drm/amd/display/include/logger_types.h index 42ffb93e3172..044805ccac25 100644 --- a/drivers/gpu/drm/amd/display/include/logger_types.h +++ b/drivers/gpu/drm/amd/display/include/logger_types.h @@ -70,6 +70,38 @@ enum dc_log_type { LOG_SECTION_TOTAL_COUNT }; +#define DC_DEFAULT_LOG_MASK ((1 << LOG_ERROR) | \ + (1 << LOG_WARNING) | \ + (1 << LOG_EVENT_MODE_SET) | \ + (1 << LOG_EVENT_DETECTION) | \ + (1 << LOG_EVENT_LINK_TRAINING) | \ + (1 << LOG_EVENT_LINK_LOSS) | \ + (1 << LOG_EVENT_UNDERFLOW) | \ + (1 << LOG_RESOURCE) | \ + (1 << LOG_FEATURE_OVERRIDE) | \ + (1 << LOG_DETECTION_EDID_PARSER) | \ + (1 << LOG_DC) | \ + (1 << LOG_HW_HOTPLUG) | \ + (1 << LOG_HW_SET_MODE) | \ + (1 << LOG_HW_RESUME_S3) | \ + (1 << LOG_HW_HPD_IRQ) | \ + (1 << LOG_SYNC) | \ + (1 << LOG_BANDWIDTH_VALIDATION) | \ + (1 << LOG_MST) | \ + (1 << LOG_DETECTION_DP_CAPS) | \ + (1 << LOG_BACKLIGHT)) | \ + (1 << LOG_I2C_AUX) | \ + (1 << LOG_IF_TRACE) | \ + (1 << LOG_DTN) /* | \ + (1 << LOG_DEBUG) | \ + (1 << LOG_BIOS) | \ + (1 << LOG_SURFACE) | \ + (1 << LOG_SCALER) | \ + (1 << LOG_DML) | \ + (1 << LOG_HW_LINK_TRAINING) | \ + (1 << LOG_HW_AUDIO)| \ + (1 << LOG_BANDWIDTH_CALCS)*/ + union logger_flags { struct { uint32_t ENABLE_CONSOLE:1; /* Print to console */ -- cgit v1.2.3 From 215a6f05bcc18ffcd953a8527639ea1f571f4d81 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Fri, 6 Oct 2017 15:40:07 -0400 Subject: drm/amd/display: add performance trace macro to dc Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 6 ++ drivers/gpu/drm/amd/display/dc/basics/logger.c | 78 ++++++---------------- drivers/gpu/drm/amd/display/dc/basics/logger.h | 37 ---------- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 5 +- drivers/gpu/drm/amd/display/dc/dc.h | 1 + .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 5 -- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 40 +++++------ .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1 + drivers/gpu/drm/amd/display/dc/dm_services.h | 2 + .../gpu/drm/amd/display/include/logger_interface.h | 28 ++++++++ drivers/gpu/drm/amd/display/include/logger_types.h | 36 +++++++++- 11 files changed, 118 insertions(+), 121 deletions(-) (limited to 'drivers/gpu/drm/amd/display/include/logger_interface.h') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c index 26bf9918fcb7..5df8fd5b537c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c @@ -35,6 +35,12 @@ #include "amdgpu_dm_irq.h" #include "amdgpu_pm.h" +unsigned long long dm_get_timestamp(struct dc_context *ctx) +{ + /* TODO: return actual timestamp */ + return 0; +} + bool dm_write_persistent_data(struct dc_context *ctx, const struct dc_sink *sink, const char *module_name, diff --git a/drivers/gpu/drm/amd/display/dc/basics/logger.c b/drivers/gpu/drm/amd/display/dc/basics/logger.c index afb6d2d80e0c..e04e8ecd4874 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/logger.c +++ b/drivers/gpu/drm/amd/display/dc/basics/logger.c @@ -80,8 +80,6 @@ static bool construct(struct dc_context *ctx, struct dal_logger *logger, logger->buffer_read_offset = 0; logger->buffer_write_offset = 0; - logger->write_wrap_count = 0; - logger->read_wrap_count = 0; logger->open_count = 0; logger->flags.bits.ENABLE_CONSOLE = 1; @@ -162,23 +160,24 @@ static void log_to_debug_console(struct log_entry *entry) } /* Print everything unread existing in log_buffer to debug console*/ -static void flush_to_debug_console(struct dal_logger *logger) +void dm_logger_flush_buffer(struct dal_logger *logger, bool should_warn) { - int i = logger->buffer_read_offset; - char *string_start = &logger->log_buffer[i]; + char *string_start = &logger->log_buffer[logger->buffer_read_offset]; - dm_output_to_console( - "---------------- FLUSHING LOG BUFFER ----------------\n"); - while (i < logger->buffer_write_offset) { + if (should_warn) + dm_output_to_console( + "---------------- FLUSHING LOG BUFFER ----------------\n"); + while (logger->buffer_read_offset < logger->buffer_write_offset) { - if (logger->log_buffer[i] == '\0') { + if (logger->log_buffer[logger->buffer_read_offset] == '\0') { dm_output_to_console("%s", string_start); - string_start = (char *)logger->log_buffer + i + 1; + string_start = logger->log_buffer + logger->buffer_read_offset + 1; } - i++; + logger->buffer_read_offset++; } - dm_output_to_console( - "-------------- END FLUSHING LOG BUFFER --------------\n\n"); + if (should_warn) + dm_output_to_console( + "-------------- END FLUSHING LOG BUFFER --------------\n\n"); } static void log_to_internal_buffer(struct log_entry *entry) @@ -195,35 +194,17 @@ static void log_to_internal_buffer(struct log_entry *entry) if (size > 0 && size < logger->log_buffer_size) { - int total_free_space = 0; - int space_before_wrap = 0; - - if (logger->buffer_write_offset > logger->buffer_read_offset) { - total_free_space = logger->log_buffer_size - - logger->buffer_write_offset + - logger->buffer_read_offset; - space_before_wrap = logger->log_buffer_size - - logger->buffer_write_offset; - } else if (logger->buffer_write_offset < - logger->buffer_read_offset) { - total_free_space = logger->log_buffer_size - - logger->buffer_read_offset + - logger->buffer_write_offset; - space_before_wrap = total_free_space; - } else if (logger->write_wrap_count != - logger->read_wrap_count) { - /* Buffer is completely full already */ - total_free_space = 0; - space_before_wrap = 0; - } else { + int buffer_space = logger->log_buffer_size - + logger->buffer_write_offset; + + if (logger->buffer_write_offset == logger->buffer_read_offset) { /* Buffer is empty, start writing at beginning */ - total_free_space = logger->log_buffer_size; - space_before_wrap = logger->log_buffer_size; + buffer_space = logger->log_buffer_size; logger->buffer_write_offset = 0; logger->buffer_read_offset = 0; } - if (space_before_wrap > size) { + if (buffer_space > size) { /* No wrap around, copy 'size' bytes * from 'entry->buf' to 'log_buffer' */ @@ -232,28 +213,12 @@ static void log_to_internal_buffer(struct log_entry *entry) entry->buf, size); logger->buffer_write_offset += size; - } else if (total_free_space > size) { - /* We have enough room without flushing, - * but need to wrap around */ - - int space_after_wrap = total_free_space - - space_before_wrap; - - memmove(logger->log_buffer + - logger->buffer_write_offset, - entry->buf, space_before_wrap); - memmove(logger->log_buffer, entry->buf + - space_before_wrap, space_after_wrap); - - logger->buffer_write_offset = space_after_wrap; - logger->write_wrap_count++; - } else { /* Not enough room remaining, we should flush * existing logs */ /* Flush existing unread logs to console */ - flush_to_debug_console(logger); + dm_logger_flush_buffer(logger, true); /* Start writing to beginning of buffer */ memmove(logger->log_buffer, entry->buf, size); @@ -325,9 +290,10 @@ void dm_logger_write( log_heading(&entry); size = dm_log_to_buffer( - buffer, LOG_MAX_LINE_SIZE, msg, args); + buffer, LOG_MAX_LINE_SIZE - 1, msg, args); - entry.buf_offset += size; + buffer[entry.buf_offset + size] = '\0'; + entry.buf_offset += size + 1; /* --Flush log_entry buffer-- */ /* print to kernel console */ diff --git a/drivers/gpu/drm/amd/display/dc/basics/logger.h b/drivers/gpu/drm/amd/display/dc/basics/logger.h index 2f7a5df4c811..09722f0f8aa3 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/logger.h +++ b/drivers/gpu/drm/amd/display/dc/basics/logger.h @@ -26,42 +26,5 @@ #ifndef __DAL_LOGGER_H__ #define __DAL_LOGGER_H__ -/* Structure for keeping track of offsets, buffer, etc */ - -#define DAL_LOGGER_BUFFER_MAX_SIZE 2048 - -/*Connectivity log needs to output EDID, which needs at lease 256x3 bytes, - * change log line size to 896 to meet the request. - */ -#define LOG_MAX_LINE_SIZE 896 - -#include "include/logger_types.h" - -struct dal_logger { - - /* How far into the circular buffer has been read by dsat - * Read offset should never cross write offset. Write \0's to - * read data just to be sure? - */ - uint32_t buffer_read_offset; - - /* How far into the circular buffer we have written - * Write offset should never cross read offset - */ - uint32_t buffer_write_offset; - - uint32_t write_wrap_count; - uint32_t read_wrap_count; - - uint32_t open_count; - - char *log_buffer; /* Pointer to malloc'ed buffer */ - uint32_t log_buffer_size; /* Size of circular buffer */ - - uint32_t mask; /*array of masks for major elements*/ - - union logger_flags flags; - struct dc_context *ctx; -}; #endif /* __DAL_LOGGER_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index cf0c1459f546..e1515230c661 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -682,6 +682,7 @@ bool dcn_validate_bandwidth( bool bw_limit_pass; float bw_limit; + PERFORMANCE_TRACE_START(); if (dcn_bw_apply_registry_override(dc)) dcn_bw_sync_calcs_and_dml(dc); @@ -1089,6 +1090,8 @@ bool dcn_validate_bandwidth( kernel_fpu_end(); + PERFORMANCE_TRACE_END(); + if (bw_limit_pass && v->voltage_level != 5) return true; else @@ -1223,7 +1226,7 @@ unsigned int dcn_find_dcfclk_suits_all( else dcf_clk = dc->dcn_soc->dcfclkv_min0p65*1000; - dm_logger_write(dc->ctx->logger, LOG_HW_MARKS, + dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, "\tdcf_clk for voltage = %d\n", dcf_clk); return dcf_clk; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index c7b31adc736e..ace17d13683a 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -224,6 +224,7 @@ struct dc_debug { bool disable_dpp_pg; bool disable_stereo_support; bool vsr_support; + bool performance_trace; }; struct dc_state; struct resource_pool; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index 0cf0fff74d44..fe88852b4774 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -757,11 +757,6 @@ void dce110_link_encoder_construct( enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; } - dm_logger_write(init_data->ctx->logger, LOG_I2C_AUX, - "Using channel: %s [%d]\n", - DECODE_CHANNEL_ID(init_data->channel), - init_data->channel); - /* Override features with DCE-specific values */ if (BP_RESULT_OK == bp_funcs->get_encoder_cap_info( enc110->base.ctx->dc_bios, enc110->base.id, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index b69884549fc5..6e2cec643f31 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -468,7 +468,7 @@ static void program_watermarks( refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, "URGENCY_WATERMARK_A calculated =%d\n" "HW register value = 0x%x\n", watermarks->a.urgent_ns, prog_wm_value); @@ -476,7 +476,7 @@ static void program_watermarks( prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, "PTE_META_URGENCY_WATERMARK_A calculated =%d\n" "HW register value = 0x%x\n", watermarks->a.pte_meta_urgent_ns, prog_wm_value); @@ -487,7 +487,7 @@ static void program_watermarks( refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, "SR_ENTER_EXIT_WATERMARK_A calculated =%d\n" "HW register value = 0x%x\n", watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); @@ -497,7 +497,7 @@ static void program_watermarks( watermarks->a.cstate_pstate.cstate_exit_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, "SR_EXIT_WATERMARK_A calculated =%d\n" "HW register value = 0x%x\n", watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value); @@ -507,7 +507,7 @@ static void program_watermarks( watermarks->a.cstate_pstate.pstate_change_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, "DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n" "HW register value = 0x%x\n\n", watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value); @@ -517,7 +517,7 @@ static void program_watermarks( prog_wm_value = convert_and_clamp( watermarks->b.urgent_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, "URGENCY_WATERMARK_B calculated =%d\n" "HW register value = 0x%x\n", watermarks->b.urgent_ns, prog_wm_value); @@ -527,7 +527,7 @@ static void program_watermarks( watermarks->b.pte_meta_urgent_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, "PTE_META_URGENCY_WATERMARK_B calculated =%d\n" "HW register value = 0x%x\n", watermarks->b.pte_meta_urgent_ns, prog_wm_value); @@ -537,7 +537,7 @@ static void program_watermarks( watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, "SR_ENTER_WATERMARK_B calculated =%d\n" "HW register value = 0x%x\n", watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); @@ -547,7 +547,7 @@ static void program_watermarks( watermarks->b.cstate_pstate.cstate_exit_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, "SR_EXIT_WATERMARK_B calculated =%d\n" "HW register value = 0x%x\n", watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value); @@ -556,7 +556,7 @@ static void program_watermarks( watermarks->b.cstate_pstate.pstate_change_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, "DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n\n" "HW register value = 0x%x\n", watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value); @@ -565,7 +565,7 @@ static void program_watermarks( prog_wm_value = convert_and_clamp( watermarks->c.urgent_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, "URGENCY_WATERMARK_C calculated =%d\n" "HW register value = 0x%x\n", watermarks->c.urgent_ns, prog_wm_value); @@ -575,7 +575,7 @@ static void program_watermarks( watermarks->c.pte_meta_urgent_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, "PTE_META_URGENCY_WATERMARK_C calculated =%d\n" "HW register value = 0x%x\n", watermarks->c.pte_meta_urgent_ns, prog_wm_value); @@ -585,7 +585,7 @@ static void program_watermarks( watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, "SR_ENTER_WATERMARK_C calculated =%d\n" "HW register value = 0x%x\n", watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); @@ -595,7 +595,7 @@ static void program_watermarks( watermarks->c.cstate_pstate.cstate_exit_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, "SR_EXIT_WATERMARK_C calculated =%d\n" "HW register value = 0x%x\n", watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value); @@ -605,7 +605,7 @@ static void program_watermarks( watermarks->c.cstate_pstate.pstate_change_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, "DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n\n" "HW register value = 0x%x\n", watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value); @@ -614,7 +614,7 @@ static void program_watermarks( prog_wm_value = convert_and_clamp( watermarks->d.urgent_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, "URGENCY_WATERMARK_D calculated =%d\n" "HW register value = 0x%x\n", watermarks->d.urgent_ns, prog_wm_value); @@ -623,7 +623,7 @@ static void program_watermarks( watermarks->d.pte_meta_urgent_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, "PTE_META_URGENCY_WATERMARK_D calculated =%d\n" "HW register value = 0x%x\n", watermarks->d.pte_meta_urgent_ns, prog_wm_value); @@ -633,7 +633,7 @@ static void program_watermarks( watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, "SR_ENTER_WATERMARK_D calculated =%d\n" "HW register value = 0x%x\n", watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); @@ -643,7 +643,7 @@ static void program_watermarks( watermarks->d.cstate_pstate.cstate_exit_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, "SR_EXIT_WATERMARK_D calculated =%d\n" "HW register value = 0x%x\n", watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value); @@ -653,7 +653,7 @@ static void program_watermarks( watermarks->d.cstate_pstate.pstate_change_ns, refclk_mhz, 0x1fffff); REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_HW_MARKS, + dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, "DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n" "HW register value = 0x%x\n\n", watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 4dbaf9a2f275..d47ff7e6a525 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -434,6 +434,7 @@ static const struct dc_debug debug_defaults_drv = { .voltage_align_fclk = true, .disable_stereo_support = true, .vsr_support = true, + .performance_trace = false, }; static const struct dc_debug debug_defaults_diags = { diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index a11991c382de..d6b3b832986b 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -418,6 +418,8 @@ bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id); #define dm_log_to_buffer(buffer, size, fmt, args)\ vsnprintf(buffer, size, fmt, args) +unsigned long long dm_get_timestamp(struct dc_context *ctx); + /* * Debug and verification hooks */ diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index 5aaf2dacfe38..8e1fe70097be 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -44,6 +44,8 @@ struct dal_logger *dal_logger_create(struct dc_context *ctx, uint32_t log_mask); uint32_t dal_logger_destroy(struct dal_logger **logger); +void dm_logger_flush_buffer(struct dal_logger *logger, bool should_warn); + void dm_logger_write( struct dal_logger *logger, enum dc_log_type log_type, @@ -157,4 +159,30 @@ void context_clock_trace( #define DTN_INFO_END() \ dm_dtn_log_end(dc_ctx) +#define PERFORMANCE_TRACE_START() \ + unsigned long long perf_trc_start_stmp = dm_get_timestamp(dc->ctx); \ + unsigned long long perf_trc_start_log_msk = dc->ctx->logger->mask; \ + unsigned int perf_trc_start_log_flags = dc->ctx->logger->flags.value; \ + if (dc->debug.performance_trace) {\ + dm_logger_flush_buffer(dc->ctx->logger, false);\ + dc->ctx->logger->mask = 1<ctx->logger->flags.bits.ENABLE_CONSOLE = 0;\ + dc->ctx->logger->flags.bits.ENABLE_BUFFER = 1;\ + } + +#define PERFORMANCE_TRACE_END() do {\ + unsigned long long perf_trc_end_stmp = dm_get_timestamp(dc->ctx);\ + if (dc->debug.performance_trace) {\ + dm_logger_write(dc->ctx->logger, \ + LOG_PERF_TRACE, \ + "%s duration: %d ticks\n", __func__,\ + perf_trc_end_stmp - perf_trc_start_stmp); \ + if (perf_trc_start_log_msk != 1<ctx->logger->mask = perf_trc_start_log_msk;\ + dc->ctx->logger->flags.value = perf_trc_start_log_flags;\ + dm_logger_flush_buffer(dc->ctx->logger, false);\ + } \ + } \ +} while (0) + #endif /* __DAL_LOGGER_INTERFACE_H__ */ diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h b/drivers/gpu/drm/amd/display/include/logger_types.h index 1f22e84cedb9..e2ff8cd423d6 100644 --- a/drivers/gpu/drm/amd/display/include/logger_types.h +++ b/drivers/gpu/drm/amd/display/include/logger_types.h @@ -64,8 +64,7 @@ enum dc_log_type { LOG_EVENT_LINK_LOSS, LOG_EVENT_UNDERFLOW, LOG_IF_TRACE, - LOG_HW_MARKS, - LOG_PPLIB, + LOG_PERF_TRACE, LOG_SECTION_TOTAL_COUNT }; @@ -131,4 +130,37 @@ struct dc_log_type_info { char name[MAX_NAME_LEN]; }; +/* Structure for keeping track of offsets, buffer, etc */ + +#define DAL_LOGGER_BUFFER_MAX_SIZE 2048 + +/*Connectivity log needs to output EDID, which needs at lease 256x3 bytes, + * change log line size to 896 to meet the request. + */ +#define LOG_MAX_LINE_SIZE 896 + +struct dal_logger { + + /* How far into the circular buffer has been read by dsat + * Read offset should never cross write offset. Write \0's to + * read data just to be sure? + */ + uint32_t buffer_read_offset; + + /* How far into the circular buffer we have written + * Write offset should never cross read offset + */ + uint32_t buffer_write_offset; + + uint32_t open_count; + + char *log_buffer; /* Pointer to malloc'ed buffer */ + uint32_t log_buffer_size; /* Size of circular buffer */ + + uint32_t mask; /*array of masks for major elements*/ + + union logger_flags flags; + struct dc_context *ctx; +}; + #endif /* __DAL_LOGGER_TYPES_H__ */ -- cgit v1.2.3