From 4562236b3bc0a28aeb6ee93b2d8a849a4c4e1c7c Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 12 Sep 2017 15:58:20 -0400 Subject: drm/amd/dc: Add dc display driver (v2) Supported DCE versions: 8.0, 10.0, 11.0, 11.2 v2: rebase against 4.11 Signed-off-by: Harry Wentland Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- .../drm/amd/display/modules/freesync/freesync.c | 1158 ++++++++++++++++++++ 1 file changed, 1158 insertions(+) create mode 100644 drivers/gpu/drm/amd/display/modules/freesync/freesync.c (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c new file mode 100644 index 000000000000..eb912baa0169 --- /dev/null +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -0,0 +1,1158 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" +#include "dc.h" +#include "mod_freesync.h" +#include "core_types.h" +#include "core_dc.h" + +#define MOD_FREESYNC_MAX_CONCURRENT_STREAMS 32 + +/* Refresh rate ramp at a fixed rate of 65 Hz/second */ +#define STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME ((1000 / 60) * 65) +/* Number of elements in the render times cache array */ +#define RENDER_TIMES_MAX_COUNT 20 +/* Threshold to exit BTR (to avoid frequent enter-exits at the lower limit) */ +#define BTR_EXIT_MARGIN 2000 + +#define FREESYNC_REGISTRY_NAME "freesync_v1" + +struct gradual_static_ramp { + bool ramp_is_active; + bool ramp_direction_is_up; + unsigned int ramp_current_frame_duration_in_ns; +}; + +struct time_cache { + /* video (48Hz feature) related */ + unsigned int update_duration_in_ns; + + /* BTR/fixed refresh related */ + unsigned int prev_time_stamp_in_us; + + unsigned int min_render_time_in_us; + unsigned int max_render_time_in_us; + + unsigned int render_times_index; + unsigned int render_times[RENDER_TIMES_MAX_COUNT]; +}; + +struct below_the_range { + bool btr_active; + bool program_btr; + + unsigned int mid_point_in_us; + + unsigned int inserted_frame_duration_in_us; + unsigned int frames_to_insert; + unsigned int frame_counter; +}; + +struct fixed_refresh { + bool fixed_refresh_active; + bool program_fixed_refresh; +}; + +struct freesync_state { + bool fullscreen; + bool static_screen; + bool video; + + unsigned int nominal_refresh_rate_in_micro_hz; + bool windowed_fullscreen; + + struct time_cache time; + + struct gradual_static_ramp static_ramp; + struct below_the_range btr; + struct fixed_refresh fixed_refresh; +}; + +struct freesync_entity { + const struct dc_stream *stream; + struct mod_freesync_caps *caps; + struct freesync_state state; + struct mod_freesync_user_enable user_enable; +}; + +struct core_freesync { + struct mod_freesync public; + struct dc *dc; + struct freesync_entity *map; + int num_entities; +}; + +#define MOD_FREESYNC_TO_CORE(mod_freesync)\ + container_of(mod_freesync, struct core_freesync, public) + +static bool check_dc_support(const struct dc *dc) +{ + if (dc->stream_funcs.adjust_vmin_vmax == NULL) + return false; + + return true; +} + +struct mod_freesync *mod_freesync_create(struct dc *dc) +{ + struct core_freesync *core_freesync = + dm_alloc(sizeof(struct core_freesync)); + + struct core_dc *core_dc = DC_TO_CORE(dc); + + struct persistent_data_flag flag; + + int i = 0; + + if (core_freesync == NULL) + goto fail_alloc_context; + + core_freesync->map = dm_alloc(sizeof(struct freesync_entity) * + MOD_FREESYNC_MAX_CONCURRENT_STREAMS); + + if (core_freesync->map == NULL) + goto fail_alloc_map; + + for (i = 0; i < MOD_FREESYNC_MAX_CONCURRENT_STREAMS; i++) + core_freesync->map[i].stream = NULL; + + core_freesync->num_entities = 0; + + if (dc == NULL) + goto fail_construct; + + core_freesync->dc = dc; + + if (!check_dc_support(dc)) + goto fail_construct; + + /* Create initial module folder in registry for freesync enable data */ + flag.save_per_edid = true; + flag.save_per_link = false; + dm_write_persistent_data(core_dc->ctx, NULL, FREESYNC_REGISTRY_NAME, NULL, NULL, + 0, &flag); + + return &core_freesync->public; + +fail_construct: + dm_free(core_freesync->map); + +fail_alloc_map: + dm_free(core_freesync); + +fail_alloc_context: + return NULL; +} + +void mod_freesync_destroy(struct mod_freesync *mod_freesync) +{ + if (mod_freesync != NULL) { + int i; + struct core_freesync *core_freesync = + MOD_FREESYNC_TO_CORE(mod_freesync); + + for (i = 0; i < core_freesync->num_entities; i++) + if (core_freesync->map[i].stream) + dc_stream_release(core_freesync->map[i].stream); + + dm_free(core_freesync->map); + + dm_free(core_freesync); + } +} + +/* Given a specific dc_stream* this function finds its equivalent + * on the core_freesync->map and returns the corresponding index + */ +static unsigned int map_index_from_stream(struct core_freesync *core_freesync, + const struct dc_stream *stream) +{ + unsigned int index = 0; + + for (index = 0; index < core_freesync->num_entities; index++) { + if (core_freesync->map[index].stream == stream) { + return index; + } + } + /* Could not find stream requested */ + ASSERT(false); + return index; +} + +bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, + const struct dc_stream *stream, struct mod_freesync_caps *caps) +{ + struct core_freesync *core_freesync = + MOD_FREESYNC_TO_CORE(mod_freesync); + struct core_stream *core_stream = + DC_STREAM_TO_CORE(stream); + struct core_dc *core_dc = DC_TO_CORE(core_freesync->dc); + + int persistent_freesync_enable = 0; + struct persistent_data_flag flag; + + flag.save_per_edid = true; + flag.save_per_link = false; + + if (core_freesync->num_entities < MOD_FREESYNC_MAX_CONCURRENT_STREAMS) { + + dc_stream_retain(stream); + + core_freesync->map[core_freesync->num_entities].stream = stream; + core_freesync->map[core_freesync->num_entities].caps = caps; + + core_freesync->map[core_freesync->num_entities].state. + fullscreen = false; + core_freesync->map[core_freesync->num_entities].state. + static_screen = false; + core_freesync->map[core_freesync->num_entities].state. + video = false; + core_freesync->map[core_freesync->num_entities].state.time. + update_duration_in_ns = 0; + core_freesync->map[core_freesync->num_entities].state. + static_ramp.ramp_is_active = false; + + /* get persistent data from registry */ + if (dm_read_persistent_data(core_dc->ctx, stream->sink, + FREESYNC_REGISTRY_NAME, + "userenable", &persistent_freesync_enable, + sizeof(int), &flag)) { + core_freesync->map[core_freesync->num_entities].user_enable. + enable_for_gaming = + (persistent_freesync_enable & 1) ? true : false; + core_freesync->map[core_freesync->num_entities].user_enable. + enable_for_static = + (persistent_freesync_enable & 2) ? true : false; + core_freesync->map[core_freesync->num_entities].user_enable. + enable_for_video = + (persistent_freesync_enable & 4) ? true : false; + } else { + core_freesync->map[core_freesync->num_entities].user_enable. + enable_for_gaming = false; + core_freesync->map[core_freesync->num_entities].user_enable. + enable_for_static = false; + core_freesync->map[core_freesync->num_entities].user_enable. + enable_for_video = false; + } + + if (caps->supported) + core_stream->public.ignore_msa_timing_param = 1; + + core_freesync->num_entities++; + return true; + } + return false; +} + +bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync, + const struct dc_stream *stream) +{ + struct core_freesync *core_freesync = + MOD_FREESYNC_TO_CORE(mod_freesync); + + int i = 0; + unsigned int index = map_index_from_stream(core_freesync, stream); + dc_stream_release(core_freesync->map[index].stream); + core_freesync->map[index].stream = NULL; + /* To remove this entity, shift everything after down */ + for (i = index; i < core_freesync->num_entities - 1; i++) + core_freesync->map[i] = core_freesync->map[i + 1]; + core_freesync->num_entities--; + return true; +} + +static void update_stream_freesync_context(struct core_freesync *core_freesync, + const struct dc_stream *stream) +{ + unsigned int index; + struct freesync_context *ctx; + struct core_stream *core_stream; + + core_stream = DC_STREAM_TO_CORE(stream); + ctx = &core_stream->public.freesync_ctx; + + index = map_index_from_stream(core_freesync, stream); + + ctx->supported = core_freesync->map[index].caps->supported; + ctx->enabled = (core_freesync->map[index].user_enable.enable_for_gaming || + core_freesync->map[index].user_enable.enable_for_video || + core_freesync->map[index].user_enable.enable_for_static); + ctx->active = (core_freesync->map[index].state.fullscreen || + core_freesync->map[index].state.video || + core_freesync->map[index].state.static_ramp.ramp_is_active); + ctx->min_refresh_in_micro_hz = + core_freesync->map[index].caps->min_refresh_in_micro_hz; + ctx->nominal_refresh_in_micro_hz = core_freesync-> + map[index].state.nominal_refresh_rate_in_micro_hz; + +} + +static void update_stream(struct core_freesync *core_freesync, + const struct dc_stream *stream) +{ + struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); + + unsigned int index = map_index_from_stream(core_freesync, stream); + if (core_freesync->map[index].caps->supported) { + core_stream->public.ignore_msa_timing_param = 1; + update_stream_freesync_context(core_freesync, stream); + } +} + +static void calc_vmin_vmax(struct core_freesync *core_freesync, + const struct dc_stream *stream, int *vmin, int *vmax) +{ + unsigned int min_frame_duration_in_ns = 0, max_frame_duration_in_ns = 0; + unsigned int index = map_index_from_stream(core_freesync, stream); + + min_frame_duration_in_ns = ((unsigned int) (div64_u64( + (1000000000ULL * 1000000), + core_freesync->map[index].state. + nominal_refresh_rate_in_micro_hz))); + max_frame_duration_in_ns = ((unsigned int) (div64_u64( + (1000000000ULL * 1000000), + core_freesync->map[index].caps->min_refresh_in_micro_hz))); + + *vmax = div64_u64(div64_u64(((unsigned long long)( + max_frame_duration_in_ns) * stream->timing.pix_clk_khz), + stream->timing.h_total), 1000000); + *vmin = div64_u64(div64_u64(((unsigned long long)( + min_frame_duration_in_ns) * stream->timing.pix_clk_khz), + stream->timing.h_total), 1000000); +} + +static void calc_v_total_from_duration(const struct dc_stream *stream, + unsigned int duration_in_ns, int *v_total_nominal) +{ + *v_total_nominal = div64_u64(div64_u64(((unsigned long long)( + duration_in_ns) * stream->timing.pix_clk_khz), + stream->timing.h_total), 1000000); +} + +static void calc_v_total_for_static_ramp(struct core_freesync *core_freesync, + const struct dc_stream *stream, + unsigned int index, int *v_total) +{ + unsigned int frame_duration = 0; + + struct gradual_static_ramp *static_ramp_variables = + &core_freesync->map[index].state.static_ramp; + + /* Calc ratio between new and current frame duration with 3 digit */ + unsigned int frame_duration_ratio = div64_u64(1000000, + (1000 + div64_u64(((unsigned long long)( + STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME) * + static_ramp_variables->ramp_current_frame_duration_in_ns), + 1000000000))); + + /* Calculate delta between new and current frame duration in ns */ + unsigned int frame_duration_delta = div64_u64(((unsigned long long)( + static_ramp_variables->ramp_current_frame_duration_in_ns) * + (1000 - frame_duration_ratio)), 1000); + + /* Adjust frame duration delta based on ratio between current and + * standard frame duration (frame duration at 60 Hz refresh rate). + */ + unsigned int ramp_rate_interpolated = div64_u64(((unsigned long long)( + frame_duration_delta) * static_ramp_variables-> + ramp_current_frame_duration_in_ns), 16666666); + + /* Going to a higher refresh rate (lower frame duration) */ + if (static_ramp_variables->ramp_direction_is_up) { + /* reduce frame duration */ + static_ramp_variables->ramp_current_frame_duration_in_ns -= + ramp_rate_interpolated; + + /* min frame duration */ + frame_duration = ((unsigned int) (div64_u64( + (1000000000ULL * 1000000), + core_freesync->map[index].state. + nominal_refresh_rate_in_micro_hz))); + + /* adjust for frame duration below min */ + if (static_ramp_variables->ramp_current_frame_duration_in_ns <= + frame_duration) { + + static_ramp_variables->ramp_is_active = false; + static_ramp_variables-> + ramp_current_frame_duration_in_ns = + frame_duration; + } + /* Going to a lower refresh rate (larger frame duration) */ + } else { + /* increase frame duration */ + static_ramp_variables->ramp_current_frame_duration_in_ns += + ramp_rate_interpolated; + + /* max frame duration */ + frame_duration = ((unsigned int) (div64_u64( + (1000000000ULL * 1000000), + core_freesync->map[index].caps->min_refresh_in_micro_hz))); + + /* adjust for frame duration above max */ + if (static_ramp_variables->ramp_current_frame_duration_in_ns >= + frame_duration) { + + static_ramp_variables->ramp_is_active = false; + static_ramp_variables-> + ramp_current_frame_duration_in_ns = + frame_duration; + } + } + + calc_v_total_from_duration(stream, static_ramp_variables-> + ramp_current_frame_duration_in_ns, v_total); +} + +static void reset_freesync_state_variables(struct freesync_state* state) +{ + state->static_ramp.ramp_is_active = false; + if (state->nominal_refresh_rate_in_micro_hz) + state->static_ramp.ramp_current_frame_duration_in_ns = + ((unsigned int) (div64_u64( + (1000000000ULL * 1000000), + state->nominal_refresh_rate_in_micro_hz))); + + state->btr.btr_active = false; + state->btr.frame_counter = 0; + state->btr.frames_to_insert = 0; + state->btr.inserted_frame_duration_in_us = 0; + state->btr.program_btr = false; + + state->fixed_refresh.fixed_refresh_active = false; + state->fixed_refresh.program_fixed_refresh = false; +} +/* + * Sets freesync mode on a stream depending on current freesync state. + */ +static bool set_freesync_on_streams(struct core_freesync *core_freesync, + const struct dc_stream **streams, int num_streams) +{ + int v_total_nominal = 0, v_total_min = 0, v_total_max = 0; + unsigned int stream_idx, map_index = 0; + struct freesync_state *state; + + if (num_streams == 0 || streams == NULL || num_streams > 1) + return false; + + for (stream_idx = 0; stream_idx < num_streams; stream_idx++) { + + map_index = map_index_from_stream(core_freesync, + streams[stream_idx]); + + state = &core_freesync->map[map_index].state; + + if (core_freesync->map[map_index].caps->supported) { + + /* Fullscreen has the topmost priority. If the + * fullscreen bit is set, we are in a fullscreen + * application where it should not matter if it is + * static screen. We should not check the static_screen + * or video bit. + * + * Special cases of fullscreen include btr and fixed + * refresh. We program btr on every flip and involves + * programming full range right before the last inserted frame. + * However, we do not want to program the full freesync range + * when fixed refresh is active, because we only program + * that logic once and this will override it. + */ + if (core_freesync->map[map_index].user_enable. + enable_for_gaming == true && + state->fullscreen == true && + state->fixed_refresh.fixed_refresh_active == false) { + /* Enable freesync */ + + calc_vmin_vmax(core_freesync, + streams[stream_idx], + &v_total_min, &v_total_max); + + /* Update the freesync context for the stream */ + update_stream_freesync_context(core_freesync, + streams[stream_idx]); + + core_freesync->dc->stream_funcs. + adjust_vmin_vmax(core_freesync->dc, streams, + num_streams, v_total_min, + v_total_max); + + return true; + + } else if (core_freesync->map[map_index].user_enable. + enable_for_video && state->video == true) { + /* Enable 48Hz feature */ + + calc_v_total_from_duration(streams[stream_idx], + state->time.update_duration_in_ns, + &v_total_nominal); + + /* Program only if v_total_nominal is in range*/ + if (v_total_nominal >= + streams[stream_idx]->timing.v_total) { + + /* Update the freesync context for + * the stream + */ + update_stream_freesync_context( + core_freesync, + streams[stream_idx]); + + core_freesync->dc->stream_funcs. + adjust_vmin_vmax( + core_freesync->dc, streams, + num_streams, v_total_nominal, + v_total_nominal); + } + return true; + + } else { + /* Disable freesync */ + v_total_nominal = streams[stream_idx]-> + timing.v_total; + + /* Update the freesync context for + * the stream + */ + update_stream_freesync_context( + core_freesync, + streams[stream_idx]); + + core_freesync->dc->stream_funcs. + adjust_vmin_vmax( + core_freesync->dc, streams, + num_streams, v_total_nominal, + v_total_nominal); + + /* Reset the cached variables */ + reset_freesync_state_variables(state); + + return true; + } + } else { + /* Disable freesync */ + v_total_nominal = streams[stream_idx]-> + timing.v_total; + /* + * we have to reset drr always even sink does + * not support freesync because a former stream has + * be programmed + */ + core_freesync->dc->stream_funcs. + adjust_vmin_vmax( + core_freesync->dc, streams, + num_streams, v_total_nominal, + v_total_nominal); + /* Reset the cached variables */ + reset_freesync_state_variables(state); + } + + } + + return false; +} + +static void set_static_ramp_variables(struct core_freesync *core_freesync, + unsigned int index, bool enable_static_screen) +{ + unsigned int frame_duration = 0; + + struct gradual_static_ramp *static_ramp_variables = + &core_freesync->map[index].state.static_ramp; + + /* If ramp is not active, set initial frame duration depending on + * whether we are enabling/disabling static screen mode. If the ramp is + * already active, ramp should continue in the opposite direction + * starting with the current frame duration + */ + if (!static_ramp_variables->ramp_is_active) { + + static_ramp_variables->ramp_is_active = true; + + if (enable_static_screen == true) { + /* Going to lower refresh rate, so start from max + * refresh rate (min frame duration) + */ + frame_duration = ((unsigned int) (div64_u64( + (1000000000ULL * 1000000), + core_freesync->map[index].state. + nominal_refresh_rate_in_micro_hz))); + } else { + /* Going to higher refresh rate, so start from min + * refresh rate (max frame duration) + */ + frame_duration = ((unsigned int) (div64_u64( + (1000000000ULL * 1000000), + core_freesync->map[index].caps->min_refresh_in_micro_hz))); + } + + static_ramp_variables-> + ramp_current_frame_duration_in_ns = frame_duration; + } + + /* If we are ENABLING static screen, refresh rate should go DOWN. + * If we are DISABLING static screen, refresh rate should go UP. + */ + static_ramp_variables->ramp_direction_is_up = !enable_static_screen; +} + +void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, + const struct dc_stream **streams, int num_streams) +{ + struct core_freesync *core_freesync = + MOD_FREESYNC_TO_CORE(mod_freesync); + + unsigned int index, v_total = 0; + struct freesync_state *state; + + if (core_freesync->num_entities == 0) + return; + + index = map_index_from_stream(core_freesync, + streams[0]); + + if (core_freesync->map[index].caps->supported == false) + return; + + state = &core_freesync->map[index].state; + + /* Below the Range Logic */ + + /* Only execute if in fullscreen mode */ + if (state->fullscreen == true && + core_freesync->map[index].user_enable.enable_for_gaming) { + + if (state->btr.btr_active) + if (state->btr.frame_counter > 0) + + state->btr.frame_counter--; + + if (state->btr.frame_counter == 1) { + + /* Restore FreeSync */ + set_freesync_on_streams(core_freesync, streams, + num_streams); + } + } + + /* If in fullscreen freesync mode or in video, do not program + * static screen ramp values + */ + if (state->fullscreen == true || state->video == true) { + + state->static_ramp.ramp_is_active = false; + + return; + } + + /* Gradual Static Screen Ramping Logic */ + + /* Execute if ramp is active and user enabled freesync static screen*/ + if (state->static_ramp.ramp_is_active && + core_freesync->map[index].user_enable.enable_for_static) { + + calc_v_total_for_static_ramp(core_freesync, streams[0], + index, &v_total); + + /* Update the freesync context for the stream */ + update_stream_freesync_context(core_freesync, streams[0]); + + /* Program static screen ramp values */ + core_freesync->dc->stream_funcs.adjust_vmin_vmax( + core_freesync->dc, streams, + num_streams, v_total, + v_total); + } +} + +void mod_freesync_update_state(struct mod_freesync *mod_freesync, + const struct dc_stream **streams, int num_streams, + struct mod_freesync_params *freesync_params) +{ + struct core_freesync *core_freesync = + MOD_FREESYNC_TO_CORE(mod_freesync); + bool freesync_program_required = false; + unsigned int stream_index; + struct freesync_state *state; + + if (core_freesync->num_entities == 0) + return; + + for(stream_index = 0; stream_index < num_streams; stream_index++) { + + unsigned int map_index = map_index_from_stream(core_freesync, + streams[stream_index]); + + state = &core_freesync->map[map_index].state; + + switch (freesync_params->state){ + case FREESYNC_STATE_FULLSCREEN: + state->fullscreen = freesync_params->enable; + freesync_program_required = true; + state->windowed_fullscreen = + freesync_params->windowed_fullscreen; + break; + case FREESYNC_STATE_STATIC_SCREEN: + /* Static screen ramp is only enabled for embedded + * panels. Also change core variables only if there + * is a change. + */ + if (dc_is_embedded_signal( + streams[stream_index]->sink->sink_signal) && + state->static_screen != + freesync_params->enable) { + + /* Change the state flag */ + state->static_screen = freesync_params->enable; + + /* Change static screen ramp variables */ + set_static_ramp_variables(core_freesync, + map_index, + freesync_params->enable); + } + /* We program the ramp starting next VUpdate */ + break; + case FREESYNC_STATE_VIDEO: + /* Change core variables only if there is a change*/ + if(freesync_params->update_duration_in_ns != + state->time.update_duration_in_ns) { + + state->video = freesync_params->enable; + state->time.update_duration_in_ns = + freesync_params->update_duration_in_ns; + + freesync_program_required = true; + } + break; + } + } + + if (freesync_program_required) + /* Program freesync according to current state*/ + set_freesync_on_streams(core_freesync, streams, num_streams); +} + + +bool mod_freesync_get_state(struct mod_freesync *mod_freesync, + const struct dc_stream *stream, + struct mod_freesync_params *freesync_params) +{ + struct core_freesync *core_freesync = + MOD_FREESYNC_TO_CORE(mod_freesync); + + unsigned int index = map_index_from_stream(core_freesync, stream); + + if (core_freesync->map[index].state.fullscreen) { + freesync_params->state = FREESYNC_STATE_FULLSCREEN; + freesync_params->enable = true; + } else if (core_freesync->map[index].state.static_screen) { + freesync_params->state = FREESYNC_STATE_STATIC_SCREEN; + freesync_params->enable = true; + } else if (core_freesync->map[index].state.video) { + freesync_params->state = FREESYNC_STATE_VIDEO; + freesync_params->enable = true; + } else { + freesync_params->state = FREESYNC_STATE_NONE; + freesync_params->enable = false; + } + + freesync_params->update_duration_in_ns = + core_freesync->map[index].state.time.update_duration_in_ns; + + return true; +} + +bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, + const struct dc_stream **streams, int num_streams, + struct mod_freesync_user_enable *user_enable) +{ + struct core_freesync *core_freesync = + MOD_FREESYNC_TO_CORE(mod_freesync); + struct core_dc *core_dc = DC_TO_CORE(core_freesync->dc); + + unsigned int stream_index, map_index; + int persistent_data = 0; + struct persistent_data_flag flag; + + flag.save_per_edid = true; + flag.save_per_link = false; + + for(stream_index = 0; stream_index < num_streams; + stream_index++){ + + map_index = map_index_from_stream(core_freesync, + streams[stream_index]); + + core_freesync->map[map_index].user_enable = *user_enable; + + /* Write persistent data in registry*/ + if (core_freesync->map[map_index].user_enable. + enable_for_gaming) + persistent_data = persistent_data | 1; + if (core_freesync->map[map_index].user_enable. + enable_for_static) + persistent_data = persistent_data | 2; + if (core_freesync->map[map_index].user_enable. + enable_for_video) + persistent_data = persistent_data | 4; + + dm_write_persistent_data(core_dc->ctx, + streams[stream_index]->sink, + FREESYNC_REGISTRY_NAME, + "userenable", + &persistent_data, + sizeof(int), + &flag); + } + + set_freesync_on_streams(core_freesync, streams, num_streams); + + return true; +} + +bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, + const struct dc_stream *stream, + struct mod_freesync_user_enable *user_enable) +{ + struct core_freesync *core_freesync = + MOD_FREESYNC_TO_CORE(mod_freesync); + + unsigned int index = map_index_from_stream(core_freesync, stream); + + *user_enable = core_freesync->map[index].user_enable; + + return true; +} + +void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, + const struct dc_stream **streams, int num_streams) +{ + struct core_freesync *core_freesync = + MOD_FREESYNC_TO_CORE(mod_freesync); + + unsigned int stream_index, map_index; + unsigned min_frame_duration_in_ns, max_frame_duration_in_ns; + struct freesync_state *state; + + for (stream_index = 0; stream_index < num_streams; stream_index++) { + + map_index = map_index_from_stream(core_freesync, + streams[stream_index]); + + state = &core_freesync->map[map_index].state; + + if (core_freesync->map[map_index].caps->supported) { + /* Update the field rate for new timing */ + state->nominal_refresh_rate_in_micro_hz = 1000000 * + div64_u64(div64_u64((streams[stream_index]-> + timing.pix_clk_khz * 1000), + streams[stream_index]->timing.v_total), + streams[stream_index]->timing.h_total); + + /* Update the stream */ + update_stream(core_freesync, streams[stream_index]); + + /* Determine whether BTR can be supported */ + min_frame_duration_in_ns = ((unsigned int) (div64_u64( + (1000000000ULL * 1000000), + state->nominal_refresh_rate_in_micro_hz))); + + max_frame_duration_in_ns = ((unsigned int) (div64_u64( + (1000000000ULL * 1000000), + core_freesync->map[map_index].caps->min_refresh_in_micro_hz))); + + if (max_frame_duration_in_ns >= + 2 * min_frame_duration_in_ns) + core_freesync->map[map_index].caps->btr_supported = true; + else + core_freesync->map[map_index].caps->btr_supported = false; + + /* Cache the time variables */ + state->time.max_render_time_in_us = + max_frame_duration_in_ns / 1000; + state->time.min_render_time_in_us = + min_frame_duration_in_ns / 1000; + state->btr.mid_point_in_us = + (max_frame_duration_in_ns + + min_frame_duration_in_ns) / 2000; + + } + } + + /* Program freesync according to current state*/ + set_freesync_on_streams(core_freesync, streams, num_streams); +} + +/* Add the timestamps to the cache and determine whether BTR programming + * is required, depending on the times calculated + */ +static void update_timestamps(struct core_freesync *core_freesync, + const struct dc_stream *stream, unsigned int map_index, + unsigned int last_render_time_in_us) +{ + struct freesync_state *state = &core_freesync->map[map_index].state; + + state->time.render_times[state->time.render_times_index] = + last_render_time_in_us; + state->time.render_times_index++; + + if (state->time.render_times_index >= RENDER_TIMES_MAX_COUNT) + state->time.render_times_index = 0; + + if (last_render_time_in_us + BTR_EXIT_MARGIN < + state->time.max_render_time_in_us) { + + /* Exit Below the Range */ + if (state->btr.btr_active) { + + state->btr.program_btr = true; + state->btr.btr_active = false; + state->btr.frame_counter = 0; + + /* Exit Fixed Refresh mode */ + } else if (state->fixed_refresh.fixed_refresh_active) { + + state->fixed_refresh.program_fixed_refresh = true; + state->fixed_refresh.fixed_refresh_active = false; + + } + + } else if (last_render_time_in_us > state->time.max_render_time_in_us) { + + /* Enter Below the Range */ + if (!state->btr.btr_active && + core_freesync->map[map_index].caps->btr_supported) { + + state->btr.program_btr = true; + state->btr.btr_active = true; + + /* Enter Fixed Refresh mode */ + } else if (!state->fixed_refresh.fixed_refresh_active && + !core_freesync->map[map_index].caps->btr_supported) { + + state->fixed_refresh.program_fixed_refresh = true; + state->fixed_refresh.fixed_refresh_active = true; + + } + } + + /* When Below the Range is active, must react on every frame */ + if (state->btr.btr_active) + state->btr.program_btr = true; +} + +static void apply_below_the_range(struct core_freesync *core_freesync, + const struct dc_stream *stream, unsigned int map_index, + unsigned int last_render_time_in_us) +{ + unsigned int inserted_frame_duration_in_us = 0; + unsigned int mid_point_frames_ceil = 0; + unsigned int mid_point_frames_floor = 0; + unsigned int frame_time_in_us = 0; + unsigned int delta_from_mid_point_in_us_1 = 0xFFFFFFFF; + unsigned int delta_from_mid_point_in_us_2 = 0xFFFFFFFF; + unsigned int frames_to_insert = 0; + unsigned int inserted_frame_v_total = 0; + unsigned int vmin = 0, vmax = 0; + unsigned int min_frame_duration_in_ns = 0; + struct freesync_state *state = &core_freesync->map[map_index].state; + + if (!state->btr.program_btr) + return; + + state->btr.program_btr = false; + + min_frame_duration_in_ns = ((unsigned int) (div64_u64( + (1000000000ULL * 1000000), + state->nominal_refresh_rate_in_micro_hz))); + + /* Program BTR */ + + /* BTR set to "not active" so disengage */ + if (!state->btr.btr_active) + + /* Restore FreeSync */ + set_freesync_on_streams(core_freesync, &stream, 1); + + /* BTR set to "active" so engage */ + else { + + /* Calculate number of midPoint frames that could fit within + * the render time interval- take ceil of this value + */ + mid_point_frames_ceil = (last_render_time_in_us + + state->btr.mid_point_in_us- 1) / + state->btr.mid_point_in_us; + + if (mid_point_frames_ceil > 0) { + + frame_time_in_us = last_render_time_in_us / + mid_point_frames_ceil; + delta_from_mid_point_in_us_1 = (state->btr.mid_point_in_us > + frame_time_in_us) ? + (state->btr.mid_point_in_us - frame_time_in_us): + (frame_time_in_us - state->btr.mid_point_in_us); + } + + /* Calculate number of midPoint frames that could fit within + * the render time interval- take floor of this value + */ + mid_point_frames_floor = last_render_time_in_us / + state->btr.mid_point_in_us; + + if (mid_point_frames_floor > 0) { + + frame_time_in_us = last_render_time_in_us / + mid_point_frames_floor; + delta_from_mid_point_in_us_2 = (state->btr.mid_point_in_us > + frame_time_in_us) ? + (state->btr.mid_point_in_us - frame_time_in_us): + (frame_time_in_us - state->btr.mid_point_in_us); + } + + /* Choose number of frames to insert based on how close it + * can get to the mid point of the variable range. + */ + if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) + frames_to_insert = mid_point_frames_ceil; + else + frames_to_insert = mid_point_frames_floor; + + /* Either we've calculated the number of frames to insert, + * or we need to insert min duration frames + */ + if (frames_to_insert > 0) + inserted_frame_duration_in_us = last_render_time_in_us / + frames_to_insert; + + if (inserted_frame_duration_in_us < + state->time.min_render_time_in_us) + + inserted_frame_duration_in_us = + state->time.min_render_time_in_us; + + /* We need the v_total_min from capability */ + calc_vmin_vmax(core_freesync, stream, &vmin, &vmax); + + inserted_frame_v_total = vmin; + if (min_frame_duration_in_ns / 1000) + inserted_frame_v_total = inserted_frame_duration_in_us * + vmin / (min_frame_duration_in_ns / 1000); + + /* Set length of inserted frames as v_total_max*/ + vmax = inserted_frame_v_total; + + /* Program V_TOTAL */ + core_freesync->dc->stream_funcs.adjust_vmin_vmax( + core_freesync->dc, &stream, + 1, vmin, + vmax); + + /* Cache the calculated variables */ + state->btr.inserted_frame_duration_in_us = + inserted_frame_duration_in_us; + state->btr.frames_to_insert = frames_to_insert; + state->btr.frame_counter = frames_to_insert; + + } +} + +static void apply_fixed_refresh(struct core_freesync *core_freesync, + const struct dc_stream *stream, unsigned int map_index) +{ + unsigned int vmin = 0, vmax = 0; + struct freesync_state *state = &core_freesync->map[map_index].state; + + if (!state->fixed_refresh.program_fixed_refresh) + return; + + state->fixed_refresh.program_fixed_refresh = false; + + /* Program Fixed Refresh */ + + /* Fixed Refresh set to "not active" so disengage */ + if (!state->fixed_refresh.fixed_refresh_active) { + set_freesync_on_streams(core_freesync, &stream, 1); + + /* Fixed Refresh set to "active" so engage (fix to max) */ + } else { + + calc_vmin_vmax(core_freesync, stream, &vmin, &vmax); + + vmax = vmin; + + core_freesync->dc->stream_funcs.adjust_vmin_vmax( + core_freesync->dc, &stream, + 1, vmin, + vmax); + } +} + +void mod_freesync_pre_update_plane_addresses(struct mod_freesync *mod_freesync, + const struct dc_stream **streams, int num_streams, + unsigned int curr_time_stamp_in_us) +{ + unsigned int stream_index, map_index, last_render_time_in_us = 0; + struct core_freesync *core_freesync = + MOD_FREESYNC_TO_CORE(mod_freesync); + + for (stream_index = 0; stream_index < num_streams; stream_index++) { + + map_index = map_index_from_stream(core_freesync, + streams[stream_index]); + + if (core_freesync->map[map_index].caps->supported) { + + last_render_time_in_us = curr_time_stamp_in_us - + core_freesync->map[map_index].state.time. + prev_time_stamp_in_us; + + /* Add the timestamps to the cache and determine + * whether BTR program is required + */ + update_timestamps(core_freesync, streams[stream_index], + map_index, last_render_time_in_us); + + if (core_freesync->map[map_index].state.fullscreen && + core_freesync->map[map_index].user_enable. + enable_for_gaming) { + + if (core_freesync->map[map_index].caps->btr_supported) { + + apply_below_the_range(core_freesync, + streams[stream_index], map_index, + last_render_time_in_us); + } else { + apply_fixed_refresh(core_freesync, + streams[stream_index], map_index); + } + } + + core_freesync->map[map_index].state.time. + prev_time_stamp_in_us = curr_time_stamp_in_us; + } + + } +} -- cgit v1.2.3 From eaf9094475504effe1a798199a1a118299cf0f74 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 6 Dec 2016 12:01:23 -0500 Subject: drm/amd/display: Fix warning in freesync module Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index eb912baa0169..8892e8bec7c3 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -746,6 +746,9 @@ void mod_freesync_update_state(struct mod_freesync *mod_freesync, freesync_program_required = true; } break; + case FREESYNC_STATE_NONE: + /* handle here to avoid warning */ + break; } } -- cgit v1.2.3 From 4b5752c7422f36664cea2ed300b698b4755b6dc5 Mon Sep 17 00:00:00 2001 From: Andrew Wong Date: Mon, 12 Dec 2016 11:47:47 -0500 Subject: drm/amd/display: Retrieve windowed fullscreen state - Retrieve windowed fullscreen state when getting freesync params. Signed-off-by: Andrew Wong Reviewed-by: Anthony Koo Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 8892e8bec7c3..6f4d169f4e4e 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -784,6 +784,9 @@ bool mod_freesync_get_state(struct mod_freesync *mod_freesync, freesync_params->update_duration_in_ns = core_freesync->map[index].state.time.update_duration_in_ns; + freesync_params->windowed_fullscreen = + core_freesync->map[index].state.windowed_fullscreen; + return true; } -- cgit v1.2.3 From 7a1c37e00a660b380fe258fed54fd5af6735814e Mon Sep 17 00:00:00 2001 From: Anthony Koo Date: Thu, 12 Jan 2017 14:24:11 -0500 Subject: drm/amd/display: Disable Modules at Runtime Add NULL check in modules Signed-off-by: Anthony Koo Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- .../drm/amd/display/modules/freesync/freesync.c | 94 +++++++++++++++------- .../gpu/drm/amd/display/modules/inc/mod_freesync.h | 7 -- 2 files changed, 65 insertions(+), 36 deletions(-) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 6f4d169f4e4e..e0703c588e47 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -205,11 +205,16 @@ static unsigned int map_index_from_stream(struct core_freesync *core_freesync, bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, const struct dc_stream *stream, struct mod_freesync_caps *caps) { - struct core_freesync *core_freesync = - MOD_FREESYNC_TO_CORE(mod_freesync); - struct core_stream *core_stream = - DC_STREAM_TO_CORE(stream); - struct core_dc *core_dc = DC_TO_CORE(core_freesync->dc); + struct core_stream *core_stream = NULL; + struct core_dc *core_dc = NULL; + struct core_freesync *core_freesync = NULL; + + if (mod_freesync == NULL) + return false; + + core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); + core_stream = DC_STREAM_TO_CORE(stream); + core_dc = DC_TO_CORE(core_freesync->dc); int persistent_freesync_enable = 0; struct persistent_data_flag flag; @@ -270,11 +275,16 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync, const struct dc_stream *stream) { - struct core_freesync *core_freesync = - MOD_FREESYNC_TO_CORE(mod_freesync); - int i = 0; - unsigned int index = map_index_from_stream(core_freesync, stream); + struct core_freesync *core_freesync = NULL; + unsigned int index = 0; + + if (mod_freesync == NULL) + return false; + + core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); + index = map_index_from_stream(core_freesync, stream); + dc_stream_release(core_freesync->map[index].stream); core_freesync->map[index].stream = NULL; /* To remove this entity, shift everything after down */ @@ -621,11 +631,14 @@ static void set_static_ramp_variables(struct core_freesync *core_freesync, void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, const struct dc_stream **streams, int num_streams) { - struct core_freesync *core_freesync = - MOD_FREESYNC_TO_CORE(mod_freesync); - unsigned int index, v_total = 0; struct freesync_state *state; + struct core_freesync *core_freesync = NULL; + + if (mod_freesync == NULL) + return; + + core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); if (core_freesync->num_entities == 0) return; @@ -691,11 +704,15 @@ void mod_freesync_update_state(struct mod_freesync *mod_freesync, const struct dc_stream **streams, int num_streams, struct mod_freesync_params *freesync_params) { - struct core_freesync *core_freesync = - MOD_FREESYNC_TO_CORE(mod_freesync); bool freesync_program_required = false; unsigned int stream_index; struct freesync_state *state; + struct core_freesync *core_freesync = NULL; + + if (mod_freesync == NULL) + return; + + core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); if (core_freesync->num_entities == 0) return; @@ -762,10 +779,14 @@ bool mod_freesync_get_state(struct mod_freesync *mod_freesync, const struct dc_stream *stream, struct mod_freesync_params *freesync_params) { - struct core_freesync *core_freesync = - MOD_FREESYNC_TO_CORE(mod_freesync); + unsigned int index = NULL; + struct core_freesync *core_freesync = NULL; - unsigned int index = map_index_from_stream(core_freesync, stream); + if (mod_freesync == NULL) + return false; + + core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); + index = map_index_from_stream(core_freesync, stream); if (core_freesync->map[index].state.fullscreen) { freesync_params->state = FREESYNC_STATE_FULLSCREEN; @@ -794,13 +815,17 @@ bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, const struct dc_stream **streams, int num_streams, struct mod_freesync_user_enable *user_enable) { - struct core_freesync *core_freesync = - MOD_FREESYNC_TO_CORE(mod_freesync); - struct core_dc *core_dc = DC_TO_CORE(core_freesync->dc); - unsigned int stream_index, map_index; int persistent_data = 0; struct persistent_data_flag flag; + struct core_dc *core_dc = NULL; + struct core_freesync *core_freesync = NULL; + + if (mod_freesync == NULL) + return false; + + core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); + core_dc = DC_TO_CORE(core_freesync->dc); flag.save_per_edid = true; flag.save_per_link = false; @@ -842,10 +867,14 @@ bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, const struct dc_stream *stream, struct mod_freesync_user_enable *user_enable) { - struct core_freesync *core_freesync = - MOD_FREESYNC_TO_CORE(mod_freesync); + unsigned int index = 0; + struct core_freesync *core_freesync = NULL; - unsigned int index = map_index_from_stream(core_freesync, stream); + if (mod_freesync == NULL) + return false; + + core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); + index = map_index_from_stream(core_freesync, stream); *user_enable = core_freesync->map[index].user_enable; @@ -855,12 +884,15 @@ bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, const struct dc_stream **streams, int num_streams) { - struct core_freesync *core_freesync = - MOD_FREESYNC_TO_CORE(mod_freesync); - unsigned int stream_index, map_index; unsigned min_frame_duration_in_ns, max_frame_duration_in_ns; struct freesync_state *state; + struct core_freesync *core_freesync = NULL; + + if (mod_freesync == NULL) + return; + + core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); for (stream_index = 0; stream_index < num_streams; stream_index++) { @@ -1121,8 +1153,12 @@ void mod_freesync_pre_update_plane_addresses(struct mod_freesync *mod_freesync, unsigned int curr_time_stamp_in_us) { unsigned int stream_index, map_index, last_render_time_in_us = 0; - struct core_freesync *core_freesync = - MOD_FREESYNC_TO_CORE(mod_freesync); + struct core_freesync *core_freesync = NULL; + + if (mod_freesync == NULL) + return; + + core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); for (stream_index = 0; stream_index < num_streams; stream_index++) { diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h index 7abfe34dc2d9..783ff2ef3bee 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h @@ -109,13 +109,6 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync, const struct dc_stream *stream); -/* - * Build additional parameters for dc_stream when creating stream for - * sink to support freesync - */ -void mod_freesync_update_stream(struct mod_freesync *mod_freesync, - struct dc_stream *stream); - /* * Update the freesync state flags for each display and program * freesync accordingly -- cgit v1.2.3 From c7141c47d371fbe6dfbdadf92cd4abb750111a62 Mon Sep 17 00:00:00 2001 From: Anthony Koo Date: Wed, 25 Jan 2017 09:31:45 -0500 Subject: drm/amd/display: Fix compile warnings 1. Fix init of integer 2. Fix mixed declarations Signed-off-by: Anthony Koo Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index e0703c588e47..1ee732768f6e 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -208,6 +208,8 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, struct core_stream *core_stream = NULL; struct core_dc *core_dc = NULL; struct core_freesync *core_freesync = NULL; + int persistent_freesync_enable = 0; + struct persistent_data_flag flag; if (mod_freesync == NULL) return false; @@ -216,9 +218,6 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, core_stream = DC_STREAM_TO_CORE(stream); core_dc = DC_TO_CORE(core_freesync->dc); - int persistent_freesync_enable = 0; - struct persistent_data_flag flag; - flag.save_per_edid = true; flag.save_per_link = false; @@ -779,7 +778,7 @@ bool mod_freesync_get_state(struct mod_freesync *mod_freesync, const struct dc_stream *stream, struct mod_freesync_params *freesync_params) { - unsigned int index = NULL; + unsigned int index = 0; struct core_freesync *core_freesync = NULL; if (mod_freesync == NULL) -- cgit v1.2.3 From 8f16f28936afcf68b92625d331a8ca760a386139 Mon Sep 17 00:00:00 2001 From: Sylvia Tsai Date: Thu, 9 Feb 2017 16:35:39 -0500 Subject: drm/amd/display: Set ignore_msa_timing flag for freesync modes - Set ignore_msa_timing_param to 1 only for modes that can support freesync Signed-off-by: Sylvia Tsai Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 1ee732768f6e..b00b1df71f3e 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -262,7 +262,11 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, enable_for_video = false; } - if (caps->supported) + unsigned int nom_refresh_rate_micro_hz = (unsigned int) + (((unsigned long long) core_stream->public.timing.pix_clk_khz) * 1000ULL * 1000ULL * 1000ULL + / core_stream->public.timing.h_total / core_stream->public.timing.v_total); + + if (caps->supported && nom_refresh_rate_micro_hz >= caps->min_refresh_in_micro_hz && nom_refresh_rate_micro_hz <= caps->max_refresh_in_micro_hz) core_stream->public.ignore_msa_timing_param = 1; core_freesync->num_entities++; -- cgit v1.2.3 From 4a9054dda6df8e94b6a54a181277e25d189198c4 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 14 Feb 2017 14:51:06 -0500 Subject: drm/amd/display: Fix 64-bit division, yet again Also make the code somewhat more readable. Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index b00b1df71f3e..2026ef34b11b 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -210,6 +210,8 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, struct core_freesync *core_freesync = NULL; int persistent_freesync_enable = 0; struct persistent_data_flag flag; + unsigned int nom_refresh_rate_micro_hz; + unsigned long long temp; if (mod_freesync == NULL) return false; @@ -262,11 +264,16 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, enable_for_video = false; } - unsigned int nom_refresh_rate_micro_hz = (unsigned int) - (((unsigned long long) core_stream->public.timing.pix_clk_khz) * 1000ULL * 1000ULL * 1000ULL - / core_stream->public.timing.h_total / core_stream->public.timing.v_total); + temp = core_stream->public.timing.pix_clk_khz; + temp *= 1000ULL * 1000ULL * 1000ULL; + temp = div_u64(temp, core_stream->public.timing.h_total); + temp = div_u64(temp, core_stream->public.timing.v_total); - if (caps->supported && nom_refresh_rate_micro_hz >= caps->min_refresh_in_micro_hz && nom_refresh_rate_micro_hz <= caps->max_refresh_in_micro_hz) + nom_refresh_rate_micro_hz = (unsigned int) temp; + + if (caps->supported && + nom_refresh_rate_micro_hz >= caps->min_refresh_in_micro_hz && + nom_refresh_rate_micro_hz <= caps->max_refresh_in_micro_hz) core_stream->public.ignore_msa_timing_param = 1; core_freesync->num_entities++; -- cgit v1.2.3 From 3e337d15bf211ce1fe388d00a7f6a955550b3edf Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Wed, 1 Mar 2017 18:20:58 -0500 Subject: drm/amd/display: sometime VtotalMin less than VTotal (rounding issue) Signed-off-by: Charlene Liu Acked-by: Harry Wentland Reviewed-by: Jordan Lazare Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 2026ef34b11b..7a0731e2dbb0 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -905,7 +905,6 @@ void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); for (stream_index = 0; stream_index < num_streams; stream_index++) { - map_index = map_index_from_stream(core_freesync, streams[stream_index]); @@ -913,11 +912,12 @@ void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, if (core_freesync->map[map_index].caps->supported) { /* Update the field rate for new timing */ - state->nominal_refresh_rate_in_micro_hz = 1000000 * - div64_u64(div64_u64((streams[stream_index]-> - timing.pix_clk_khz * 1000), - streams[stream_index]->timing.v_total), - streams[stream_index]->timing.h_total); + unsigned long long temp; + temp = streams[stream_index]->timing.pix_clk_khz; + temp *= 1000ULL * 1000ULL * 1000ULL; + temp = div_u64(temp, streams[stream_index]->timing.h_total); + temp = div_u64(temp, streams[stream_index]->timing.v_total); + state->nominal_refresh_rate_in_micro_hz = (unsigned int) temp; /* Update the stream */ update_stream(core_freesync, streams[stream_index]); -- cgit v1.2.3 From 09e2d07f9d4d30f7d219b562d656d7c7611e2b65 Mon Sep 17 00:00:00 2001 From: Eric Cook Date: Wed, 12 Apr 2017 11:05:08 -0400 Subject: drm/amd/display: FreeSync LFC MIN/MAX update on current frame - Update BTR/LFC logic so that V_TOTAL_MIN/MAX will take affect on current frame - Add in FreeSync update to MPO code path Signed-off-by: Eric Cook Acked-by: Harry Wentland Reviewed-by: Anthony Koo Signed-off-by: Alex Deucher --- .../drm/amd/display/modules/freesync/freesync.c | 67 +++++++++++++--------- 1 file changed, 39 insertions(+), 28 deletions(-) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 7a0731e2dbb0..94566c0a0e62 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -641,7 +641,8 @@ static void set_static_ramp_variables(struct core_freesync *core_freesync, void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, const struct dc_stream **streams, int num_streams) { - unsigned int index, v_total = 0; + unsigned int index, v_total, inserted_frame_v_total = 0; + unsigned int min_frame_duration_in_ns, vmax, vmin = 0; struct freesync_state *state; struct core_freesync *core_freesync = NULL; @@ -665,19 +666,48 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, /* Only execute if in fullscreen mode */ if (state->fullscreen == true && - core_freesync->map[index].user_enable.enable_for_gaming) { + core_freesync->map[index].user_enable.enable_for_gaming && + core_freesync->map[index].caps->btr_supported && + state->btr.btr_active) { + + /* TODO: pass in flag for Pre-DCE12 ASIC + * in order for frame variable duration to take affect, + * it needs to be done one VSYNC early, which is at + * frameCounter == 1. + * For DCE12 and newer updates to V_TOTAL_MIN/MAX + * will take affect on current frame + */ + if (state->btr.frames_to_insert == state->btr.frame_counter) { + + min_frame_duration_in_ns = ((unsigned int) (div64_u64( + (1000000000ULL * 1000000), + state->nominal_refresh_rate_in_micro_hz))); + + calc_vmin_vmax(core_freesync, *streams, &vmin, &vmax); - if (state->btr.btr_active) - if (state->btr.frame_counter > 0) + inserted_frame_v_total = vmin; - state->btr.frame_counter--; + if (min_frame_duration_in_ns / 1000) + inserted_frame_v_total = + state->btr.inserted_frame_duration_in_us * + vmin / (min_frame_duration_in_ns / 1000); - if (state->btr.frame_counter == 1) { + /* Set length of inserted frames as v_total_max*/ + vmax = inserted_frame_v_total; + vmin = inserted_frame_v_total; - /* Restore FreeSync */ - set_freesync_on_streams(core_freesync, streams, - num_streams); + /* Program V_TOTAL */ + core_freesync->dc->stream_funcs.adjust_vmin_vmax( + core_freesync->dc, streams, + num_streams, vmin, vmax); } + + if (state->btr.frame_counter > 0) + state->btr.frame_counter--; + + /* Restore FreeSync */ + if (state->btr.frame_counter == 0) + set_freesync_on_streams(core_freesync, streams, num_streams); } /* If in fullscreen freesync mode or in video, do not program @@ -1022,8 +1052,6 @@ static void apply_below_the_range(struct core_freesync *core_freesync, unsigned int delta_from_mid_point_in_us_1 = 0xFFFFFFFF; unsigned int delta_from_mid_point_in_us_2 = 0xFFFFFFFF; unsigned int frames_to_insert = 0; - unsigned int inserted_frame_v_total = 0; - unsigned int vmin = 0, vmax = 0; unsigned int min_frame_duration_in_ns = 0; struct freesync_state *state = &core_freesync->map[map_index].state; @@ -1101,23 +1129,6 @@ static void apply_below_the_range(struct core_freesync *core_freesync, inserted_frame_duration_in_us = state->time.min_render_time_in_us; - /* We need the v_total_min from capability */ - calc_vmin_vmax(core_freesync, stream, &vmin, &vmax); - - inserted_frame_v_total = vmin; - if (min_frame_duration_in_ns / 1000) - inserted_frame_v_total = inserted_frame_duration_in_us * - vmin / (min_frame_duration_in_ns / 1000); - - /* Set length of inserted frames as v_total_max*/ - vmax = inserted_frame_v_total; - - /* Program V_TOTAL */ - core_freesync->dc->stream_funcs.adjust_vmin_vmax( - core_freesync->dc, &stream, - 1, vmin, - vmax); - /* Cache the calculated variables */ state->btr.inserted_frame_duration_in_us = inserted_frame_duration_in_us; -- cgit v1.2.3 From 6c626ffb1bfa2705e71376fe20bcdc6b89aace85 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Fri, 21 Apr 2017 11:00:43 -0400 Subject: drm/amd/display: Make sure v_total_min and max not less than v_total. Signed-off-by: Yongqiang Sun Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c | 4 ++-- .../gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c | 4 ++-- drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 12 ++++++++++++ 3 files changed, 16 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c index 69ae3a83d2fe..7070aaf9e433 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c @@ -393,12 +393,12 @@ void dce110_timing_generator_set_drr( params->vertical_total_min > 0) { set_reg_field_value(v_total_max, - params->vertical_total_max, + params->vertical_total_max - 1, CRTC_V_TOTAL_MAX, CRTC_V_TOTAL_MAX); set_reg_field_value(v_total_min, - params->vertical_total_min, + params->vertical_total_min - 1, CRTC_V_TOTAL_MIN, CRTC_V_TOTAL_MIN); diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c index 6e3e7b6bc58c..1318df7ed47e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c @@ -540,10 +540,10 @@ void dce120_timing_generator_set_drr( CRTC_REG_UPDATE( CRTC0_CRTC_V_TOTAL_MIN, - CRTC_V_TOTAL_MIN, params->vertical_total_min); + CRTC_V_TOTAL_MIN, params->vertical_total_min - 1); CRTC_REG_UPDATE( CRTC0_CRTC_V_TOTAL_MAX, - CRTC_V_TOTAL_MAX, params->vertical_total_max); + CRTC_V_TOTAL_MAX, params->vertical_total_max - 1); CRTC_REG_SET_N(CRTC0_CRTC_V_TOTAL_CONTROL, 6, FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL), 1, FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL), 1, diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 94566c0a0e62..5c6de723da5d 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -347,6 +347,7 @@ static void calc_vmin_vmax(struct core_freesync *core_freesync, { unsigned int min_frame_duration_in_ns = 0, max_frame_duration_in_ns = 0; unsigned int index = map_index_from_stream(core_freesync, stream); + uint32_t vtotal = stream->timing.v_total; min_frame_duration_in_ns = ((unsigned int) (div64_u64( (1000000000ULL * 1000000), @@ -362,6 +363,17 @@ static void calc_vmin_vmax(struct core_freesync *core_freesync, *vmin = div64_u64(div64_u64(((unsigned long long)( min_frame_duration_in_ns) * stream->timing.pix_clk_khz), stream->timing.h_total), 1000000); + + /* In case of 4k free sync monitor, vmin or vmax cannot be less than vtotal */ + if (*vmin < vtotal) { + ASSERT(false); + *vmin = vtotal; + } + + if (*vmax < vtotal) { + ASSERT(false); + *vmax = vtotal; + } } static void calc_v_total_from_duration(const struct dc_stream *stream, -- cgit v1.2.3 From 94267b3df7ee00f21fa0ff7d618ca7e0574db5ed Mon Sep 17 00:00:00 2001 From: Sylvia Tsai Date: Fri, 21 Apr 2017 15:29:55 -0400 Subject: drm/amd/display: PSR Refactor - Refacotr PSR to follow correct module pattern - fix eDP only working on sink index 0. Signed-off-by: Sylvia Tsai Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 74 +++++++++------------- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 22 +++---- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 53 +--------------- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dc.h | 17 +++-- drivers/gpu/drm/amd/display/dc/dc_types.h | 24 +++---- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 18 +++++- .../display/dc/dce110/dce110_timing_generator.c | 16 ----- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 1 + drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 +- .../drm/amd/display/modules/freesync/freesync.c | 14 +++- 11 files changed, 93 insertions(+), 150 deletions(-) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 1dd9c736aedc..93c936d92f5a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -199,6 +199,32 @@ static bool set_gamut_remap(struct dc *dc, return ret; } +static void set_static_screen_events(struct dc *dc, + const struct dc_stream **stream, + int num_streams, + const struct dc_static_screen_events *events) +{ + struct core_dc *core_dc = DC_TO_CORE(dc); + int i = 0; + int j = 0; + struct pipe_ctx *pipes_affected[MAX_PIPES]; + int num_pipes_affected = 0; + + for (i = 0; i < num_streams; i++) { + struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[i]); + + for (j = 0; j < MAX_PIPES; j++) { + if (core_dc->current_context->res_ctx.pipe_ctx[j].stream + == core_stream) { + pipes_affected[num_pipes_affected++] = + &core_dc->current_context->res_ctx.pipe_ctx[j]; + } + } + } + + core_dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events); +} + /* This function is not expected to fail, proper implementation of * validation will prevent this from ever being called for unsupported * configurations. @@ -240,45 +266,6 @@ static void stream_update_scaling( } } -static bool set_psr_enable(struct dc *dc, bool enable) -{ - struct core_dc *core_dc = DC_TO_CORE(dc); - int i; - - for (i = 0; i < core_dc->link_count; i++) - dc_link_set_psr_enable(&core_dc->links[i]->public, - enable); - - return true; -} - - -static bool setup_psr(struct dc *dc, const struct dc_stream *stream) -{ - struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); - struct pipe_ctx *pipes; - int i; - unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index; - - for (i = 0; i < core_dc->link_count; i++) { - if (core_stream->sink->link == core_dc->links[i]) - dc_link_setup_psr(&core_dc->links[i]->public, - stream); - } - - for (i = 0; i < MAX_PIPES; i++) { - if (core_dc->current_context->res_ctx.pipe_ctx[i].stream - == core_stream && i != underlay_idx) { - pipes = &core_dc->current_context->res_ctx.pipe_ctx[i]; - core_dc->hwss.set_static_screen_control(&pipes, 1, - 0x182); - } - } - - return true; -} - static void set_drive_settings(struct dc *dc, struct link_training_settings *lt_settings, const struct dc_link *link) @@ -359,15 +346,12 @@ static void allocate_dc_stream_funcs(struct core_dc *core_dc) stream_adjust_vmin_vmax; } + core_dc->public.stream_funcs.set_static_screen_events = + set_static_screen_events; + core_dc->public.stream_funcs.set_gamut_remap = set_gamut_remap; - core_dc->public.stream_funcs.set_psr_enable = - set_psr_enable; - - core_dc->public.stream_funcs.setup_psr = - setup_psr; - core_dc->public.link_funcs.set_drive_settings = set_drive_settings; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 426f7f8187a6..6f78403e2d64 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1430,14 +1430,14 @@ bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable) struct core_dc *core_dc = DC_TO_CORE(ctx->dc); struct dmcu *dmcu = core_dc->res_pool->dmcu; - if (dmcu != NULL && dc_link->psr_caps.psr_version > 0) + if (dmcu != NULL && link->psr_enabled) dmcu->funcs->set_psr_enable(dmcu, enable); return true; } bool dc_link_setup_psr(const struct dc_link *dc_link, - const struct dc_stream *stream) + const struct dc_stream *stream, struct psr_config *psr_config) { struct core_link *link = DC_LINK_TO_CORE(dc_link); struct dc_context *ctx = link->ctx; @@ -1449,10 +1449,8 @@ bool dc_link_setup_psr(const struct dc_link *dc_link, psr_context.controllerId = CONTROLLER_ID_UNDEFINED; - if (dc_link != NULL && - dmcu != NULL && - dc_link->psr_caps.psr_version > 0) { + dmcu != NULL) { /* updateSinkPsrDpcdConfig*/ union dpcd_psr_configuration psr_configuration; @@ -1461,10 +1459,10 @@ bool dc_link_setup_psr(const struct dc_link *dc_link, psr_configuration.bits.ENABLE = 1; psr_configuration.bits.CRC_VERIFICATION = 1; psr_configuration.bits.FRAME_CAPTURE_INDICATION = - dc_link->psr_caps.psr_frame_capture_indication_req; + psr_config->psr_frame_capture_indication_req; /* Check for PSR v2*/ - if (dc_link->psr_caps.psr_version == 0x2) { + if (psr_config->psr_version == 0x2) { /* For PSR v2 selective update. * Indicates whether sink should start capturing * immediately following active scan line, @@ -1512,14 +1510,13 @@ bool dc_link_setup_psr(const struct dc_link *dc_link, stream->timing.v_total), stream->timing.h_total); - psr_context.psrSupportedDisplayConfig = - (dc_link->psr_caps.psr_version > 0) ? true : false; + psr_context.psrSupportedDisplayConfig = true; psr_context.psrExitLinkTrainingRequired = - dc_link->psr_caps.psr_exit_link_training_required; + psr_config->psr_exit_link_training_required; psr_context.sdpTransmitLineNumDeadline = - dc_link->psr_caps.psr_sdp_transmit_line_num_deadline; + psr_config->psr_sdp_transmit_line_num_deadline; psr_context.psrFrameCaptureIndicationReq = - dc_link->psr_caps.psr_frame_capture_indication_req; + psr_config->psr_frame_capture_indication_req; psr_context.skipPsrWaitForPllLock = 0; /* only = 1 in KV */ @@ -1550,6 +1547,7 @@ bool dc_link_setup_psr(const struct dc_link *dc_link, */ psr_context.frame_delay = 0; + link->psr_enabled = true; dmcu->funcs->setup_psr(dmcu, link, &psr_context); return true; } else diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 17286465e850..f883fdb820c8 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -1478,7 +1478,7 @@ static bool handle_hpd_irq_psr_sink(const struct core_link *link) { union dpcd_psr_configuration psr_configuration; - if (link->public.psr_caps.psr_version == 0) + if (!link->psr_enabled) return false; dm_helpers_dp_read_dpcd( @@ -2060,36 +2060,6 @@ static void dp_wa_power_up_0010FA(struct core_link *link, uint8_t *dpcd_data, link->wa_flags.dp_keep_receiver_powered = false; } -static void retrieve_psr_link_cap(struct core_link *link, - enum edp_revision edp_revision) -{ - if (edp_revision >= EDP_REVISION_13) { - core_link_read_dpcd(link, - DP_PSR_SUPPORT, - (uint8_t *)(&link->public.psr_caps), - sizeof(link->public.psr_caps)); - if (link->public.psr_caps.psr_version != 0) { - unsigned char psr_capability = 0; - - core_link_read_dpcd(link, - DP_PSR_CAPS, - &psr_capability, - sizeof(psr_capability)); - /* Bit 0 determines whether fast link training is - * required on PSR exit. If set to 0, link training - * is required. If set to 1, sink must lock within - * five Idle Patterns after Main Link is turned on. - */ - link->public.psr_caps.psr_exit_link_training_required - = !(psr_capability & 0x1); - - psr_capability = (psr_capability >> 1) & 0x7; - link->public.psr_caps.psr_rfb_setup_time = - 55 * (6 - psr_capability); - } - } -} - static void retrieve_link_cap(struct core_link *link) { uint8_t dpcd_data[DP_TRAINING_AUX_RD_INTERVAL - DP_DPCD_REV + 1]; @@ -2157,38 +2127,17 @@ static void retrieve_link_cap(struct core_link *link) link->dpcd_caps.panel_mode_edp = edp_config_cap.bits.ALT_SCRAMBLER_RESET; - link->edp_revision = EDP_REVISION_11; - link->public.test_pattern_enabled = false; link->public.compliance_test_state.raw = 0; - link->public.psr_caps.psr_exit_link_training_required = false; - link->public.psr_caps.psr_frame_capture_indication_req = false; - link->public.psr_caps.psr_rfb_setup_time = 0; - link->public.psr_caps.psr_sdp_transmit_line_num_deadline = 0; - link->public.psr_caps.psr_version = 0; - /* read sink count */ core_link_read_dpcd(link, DP_SINK_COUNT, &link->dpcd_caps.sink_count.raw, sizeof(link->dpcd_caps.sink_count.raw)); - /* Display control registers starting at DPCD 700h are only valid and - * enabled if this eDP config cap bit is set. */ - if (edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE) { - /* Read the Panel's eDP revision at DPCD 700h. */ - core_link_read_dpcd(link, - DP_EDP_DPCD_REV, - (uint8_t *)(&link->edp_revision), - sizeof(link->edp_revision)); - } - /* Connectivity log: detection */ CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: "); - - /* TODO: Confirm if need retrieve_psr_link_cap */ - retrieve_psr_link_cap(link, link->edp_revision); } void detect_dp_sink_caps(struct core_link *link) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 2e12a0ba5ddf..cdb98d5f7caa 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -2015,7 +2015,7 @@ static void set_vsc_info_packet( unsigned int vscPacketRevision = 0; unsigned int i; - if (stream->sink->link->public.psr_caps.psr_version != 0) { + if (stream->sink->link->psr_enabled) { vscPacketRevision = 2; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index a2a9e4ed393c..d12aa726164e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -82,6 +82,12 @@ struct dc_surface_dcc_cap { }; }; +struct dc_static_screen_events { + bool cursor_update; + bool surface_update; + bool overlay_update; +}; + /* Forward declaration*/ struct dc; struct dc_surface; @@ -102,10 +108,14 @@ struct dc_stream_funcs { const struct dc_stream *dc_stream, const struct rect *src, const struct rect *dst); + bool (*set_gamut_remap)(struct dc *dc, const struct dc_stream **stream, int num_streams); - bool (*set_psr_enable)(struct dc *dc, bool enable); - bool (*setup_psr)(struct dc *dc, const struct dc_stream *stream); + + void (*set_static_screen_events)(struct dc *dc, + const struct dc_stream **stream, + int num_streams, + const struct dc_static_screen_events *events); }; struct link_training_settings; @@ -604,7 +614,6 @@ struct dc_link { uint8_t ddc_hw_inst; uint8_t link_enc_hw_inst; - struct psr_caps psr_caps; bool test_pattern_enabled; union compliance_test_state compliance_test_state; @@ -657,7 +666,7 @@ bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable); bool dc_link_setup_psr(const struct dc_link *dc_link, - const struct dc_stream *stream); + const struct dc_stream *stream, struct psr_config *psr_config); /* Request DC to detect if there is a Panel connected. * boot - If this call is during initial boot. diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 2ba02b50bc18..d2f3b9fd7a30 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -484,6 +484,15 @@ struct freesync_context { unsigned int nominal_refresh_in_micro_hz; }; +struct psr_config { + unsigned char psr_version; + unsigned int psr_rfb_setup_time; + bool psr_exit_link_training_required; + + bool psr_frame_capture_indication_req; + unsigned int psr_sdp_transmit_line_num_deadline; +}; + struct colorspace_transform { struct fixed31_32 matrix[12]; bool enable_remap; @@ -494,21 +503,6 @@ struct csc_transform { bool enable_adjustment; }; -struct psr_caps { - /* These parameters are from PSR capabilities reported by Sink DPCD */ - unsigned char psr_version; - unsigned int psr_rfb_setup_time; - bool psr_exit_link_training_required; - - /* These parameters are calculated in Driver, - * based on display timing and Sink capabilities. - * If VBLANK region is too small and Sink takes a long time - * to set up RFB, it may take an extra frame to enter PSR state. - */ - bool psr_frame_capture_indication_req; - unsigned int psr_sdp_transmit_line_num_deadline; -}; - enum i2c_mot_mode { I2C_MOT_UNDEF, I2C_MOT_TRUE, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 6b249f5bf1da..6a93c96b9b26 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1005,6 +1005,10 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( pipe_ctx->tg, &stream->public.timing, true); + + pipe_ctx->tg->funcs->set_static_screen_control( + pipe_ctx->tg, + 0x182); } if (!pipe_ctx_old->stream) { @@ -1015,6 +1019,8 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( } } + + return DC_OK; } @@ -1114,6 +1120,8 @@ static enum dc_status apply_single_controller_ctx_to_hw( stream->public.timing.pix_clk_khz, context->stream_count); + pipe_ctx->stream->sink->link->psr_enabled = false; + return DC_OK; } @@ -1355,9 +1363,17 @@ static void set_drr(struct pipe_ctx **pipe_ctx, } static void set_static_screen_control(struct pipe_ctx **pipe_ctx, - int num_pipes, int value) + int num_pipes, const struct dc_static_screen_events *events) { unsigned int i; + unsigned int value = 0; + + if (events->overlay_update) + value |= 0x100; + if (events->surface_update) + value |= 0x80; + if (events->cursor_update) + value |= 0x2; for (i = 0; i < num_pipes; i++) pipe_ctx[i]->tg->funcs-> diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c index 7070aaf9e433..23760727f000 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c @@ -371,7 +371,6 @@ void dce110_timing_generator_set_drr( uint32_t v_total_min = 0; uint32_t v_total_max = 0; uint32_t v_total_cntl = 0; - uint32_t static_screen_cntl = 0; struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); uint32_t addr = 0; @@ -385,9 +384,6 @@ void dce110_timing_generator_set_drr( addr = CRTC_REG(mmCRTC_V_TOTAL_CONTROL); v_total_cntl = dm_read_reg(tg->ctx, addr); - addr = CRTC_REG(mmCRTC_STATIC_SCREEN_CONTROL); - static_screen_cntl = dm_read_reg(tg->ctx, addr); - if (params != NULL && params->vertical_total_max > 0 && params->vertical_total_min > 0) { @@ -430,20 +426,11 @@ void dce110_timing_generator_set_drr( 0, CRTC_V_TOTAL_CONTROL, CRTC_SET_V_TOTAL_MIN_MASK); - - set_reg_field_value(static_screen_cntl, - 0x180, - CRTC_STATIC_SCREEN_CONTROL, - CRTC_STATIC_SCREEN_EVENT_MASK); } else { set_reg_field_value(v_total_cntl, 0, CRTC_V_TOTAL_CONTROL, CRTC_SET_V_TOTAL_MIN_MASK); - set_reg_field_value(static_screen_cntl, - 0, - CRTC_STATIC_SCREEN_CONTROL, - CRTC_STATIC_SCREEN_EVENT_MASK); set_reg_field_value(v_total_min, 0, CRTC_V_TOTAL_MIN, @@ -478,9 +465,6 @@ void dce110_timing_generator_set_drr( addr = CRTC_REG(mmCRTC_V_TOTAL_CONTROL); dm_write_reg(tg->ctx, addr, v_total_cntl); - - addr = CRTC_REG(mmCRTC_STATIC_SCREEN_CONTROL); - dm_write_reg(tg->ctx, addr, static_screen_cntl); } void dce110_timing_generator_set_static_screen_control( diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 405608318ccc..2b43e18c65f5 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -156,6 +156,7 @@ struct core_link { unsigned int dpcd_sink_count; enum edp_revision edp_revision; + bool psr_enabled; /* MST record stream using this link */ struct link_flags { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 9bfaaad09bea..b42e4a0ef18a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -132,7 +132,7 @@ struct hw_sequencer_funcs { int vmin, int vmax); void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, - int num_pipes, int value); + int num_pipes, const struct dc_static_screen_events *events); enum dc_status (*prog_pixclk_crtc_otg)( struct pipe_ctx *pipe_ctx, diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 5c6de723da5d..78b4f28d862c 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -264,10 +264,10 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, enable_for_video = false; } - temp = core_stream->public.timing.pix_clk_khz; + temp = stream->timing.pix_clk_khz; temp *= 1000ULL * 1000ULL * 1000ULL; - temp = div_u64(temp, core_stream->public.timing.h_total); - temp = div_u64(temp, core_stream->public.timing.v_total); + temp = div_u64(temp, stream->timing.h_total); + temp = div_u64(temp, stream->timing.v_total); nom_refresh_rate_micro_hz = (unsigned int) temp; @@ -657,6 +657,7 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, unsigned int min_frame_duration_in_ns, vmax, vmin = 0; struct freesync_state *state; struct core_freesync *core_freesync = NULL; + struct dc_static_screen_events triggers = {0}; if (mod_freesync == NULL) return; @@ -749,6 +750,13 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, core_freesync->dc, streams, num_streams, v_total, v_total); + + triggers.overlay_update = true; + triggers.surface_update = true; + + core_freesync->dc->stream_funcs.set_static_screen_events( + core_freesync->dc, streams, num_streams, + &triggers); } } -- cgit v1.2.3 From 72ada5f76939ed00c07c584be7691a29d3c2c3da Mon Sep 17 00:00:00 2001 From: Eric Cook Date: Tue, 18 Apr 2017 15:24:50 -0400 Subject: drm/amd/display: FreeSync Auto Sweep Support Implement core support to allow for FreeSync Auto Sweep to work Signed-off-by: Eric Cook Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 28 +++ drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 5 +- drivers/gpu/drm/amd/display/dc/dc.h | 6 + .../amd/display/dc/dce110/dce110_hw_sequencer.c | 13 ++ .../display/dc/dce110/dce110_timing_generator.c | 61 +++--- .../display/dc/dce110/dce110_timing_generator.h | 9 +- .../display/dc/dce110/dce110_timing_generator_v.c | 23 +-- .../display/dc/dce120/dce120_timing_generator.c | 73 ++++++- .../amd/display/dc/dce80/dce80_timing_generator.c | 2 +- .../drm/amd/display/dc/inc/hw/timing_generator.h | 10 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 3 + .../drm/amd/display/modules/freesync/freesync.c | 227 ++++++++++++++++----- .../gpu/drm/amd/display/modules/inc/mod_freesync.h | 20 ++ 13 files changed, 357 insertions(+), 123 deletions(-) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 93c936d92f5a..2e74faef68e7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -175,6 +175,31 @@ static bool stream_adjust_vmin_vmax(struct dc *dc, return ret; } +static bool stream_get_crtc_position(struct dc *dc, + const struct dc_stream **stream, int num_streams, + unsigned int *v_pos, unsigned int *nom_v_pos) +{ + /* TODO: Support multiple streams */ + struct core_dc *core_dc = DC_TO_CORE(dc); + struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]); + int i = 0; + bool ret = false; + struct crtc_position position; + + for (i = 0; i < MAX_PIPES; i++) { + struct pipe_ctx *pipe = + &core_dc->current_context->res_ctx.pipe_ctx[i]; + + if (pipe->stream == core_stream && pipe->stream_enc) { + core_dc->hwss.get_position(&pipe, 1, &position); + + *v_pos = position.vertical_count; + *nom_v_pos = position.nominal_vcount; + ret = true; + } + } + return ret; +} static bool set_gamut_remap(struct dc *dc, const struct dc_stream **stream, int num_streams) @@ -349,6 +374,9 @@ static void allocate_dc_stream_funcs(struct core_dc *core_dc) core_dc->public.stream_funcs.set_static_screen_events = set_static_screen_events; + core_dc->public.stream_funcs.get_crtc_position = + stream_get_crtc_position; + core_dc->public.stream_funcs.set_gamut_remap = set_gamut_remap; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index fb48b8909e7f..ee840e75ee1f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -287,6 +287,7 @@ void context_timing_trace( struct core_dc *core_dc = DC_TO_CORE(dc); struct dal_logger *logger = core_dc->ctx->logger; int h_pos[MAX_PIPES], v_pos[MAX_PIPES]; + struct crtc_position position; for (i = 0; i < core_dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; @@ -294,7 +295,9 @@ void context_timing_trace( if (pipe_ctx->stream == NULL) continue; - pipe_ctx->tg->funcs->get_position(pipe_ctx->tg, &h_pos[i], &v_pos[i]); + pipe_ctx->tg->funcs->get_position(pipe_ctx->tg, &position); + h_pos[i] = position.horizontal_count; + v_pos[i] = position.vertical_count; } for (i = 0; i < core_dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d12aa726164e..647c095e0ae9 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -103,6 +103,12 @@ struct dc_stream_funcs { int num_streams, int vmin, int vmax); + bool (*get_crtc_position)(struct dc *dc, + const struct dc_stream **stream, + int num_streams, + unsigned int *v_pos, + unsigned int *nom_v_pos); + void (*stream_update_scaling)(const struct dc *dc, const struct dc_stream *dc_stream, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 6a93c96b9b26..0e69aceb0bad 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1362,6 +1362,18 @@ static void set_drr(struct pipe_ctx **pipe_ctx, } } +static void get_position(struct pipe_ctx **pipe_ctx, + int num_pipes, + struct crtc_position *position) +{ + int i = 0; + + /* TODO: handle pipes > 1 + */ + for (i = 0; i < num_pipes; i++) + pipe_ctx[i]->tg->funcs->get_position(pipe_ctx[i]->tg, position); +} + static void set_static_screen_control(struct pipe_ctx **pipe_ctx, int num_pipes, const struct dc_static_screen_events *events) { @@ -2486,6 +2498,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .pipe_control_lock = dce_pipe_control_lock, .set_bandwidth = dce110_set_bandwidth, .set_drr = set_drr, + .get_position = get_position, .set_static_screen_control = set_static_screen_control, .reset_hw_ctx_wrap = reset_hw_ctx_wrap, .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c index 23760727f000..ec599276ed2e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c @@ -518,34 +518,38 @@ uint32_t dce110_timing_generator_get_vblank_counter(struct timing_generator *tg) /** ***************************************************************************** - * Function: dce110_get_crtc_positions + * Function: dce110_timing_generator_get_position * * @brief * Returns CRTC vertical/horizontal counters * - * @param [out] v_position, h_position + * @param [out] position ***************************************************************************** */ - -void dce110_timing_generator_get_crtc_positions( - struct timing_generator *tg, - int32_t *h_position, - int32_t *v_position) +void dce110_timing_generator_get_position(struct timing_generator *tg, + struct crtc_position *position) { uint32_t value; struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_STATUS_POSITION)); - *h_position = get_reg_field_value( + position->horizontal_count = get_reg_field_value( value, CRTC_STATUS_POSITION, CRTC_HORZ_COUNT); - *v_position = get_reg_field_value( + position->vertical_count = get_reg_field_value( value, CRTC_STATUS_POSITION, CRTC_VERT_COUNT); + + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_NOM_VERT_POSITION)); + + position->nominal_vcount = get_reg_field_value( + value, + CRTC_NOM_VERT_POSITION, + CRTC_VERT_COUNT_NOM); } /** @@ -566,18 +570,23 @@ void dce110_timing_generator_get_crtc_scanoutpos( uint32_t *v_position) { struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + struct crtc_position position; - uint32_t v_blank_start_end = dm_read_reg(tg->ctx, + uint32_t value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_V_BLANK_START_END)); - *v_blank_start = get_reg_field_value(v_blank_start_end, + *v_blank_start = get_reg_field_value(value, CRTC_V_BLANK_START_END, CRTC_V_BLANK_START); - *v_blank_end = get_reg_field_value(v_blank_start_end, + *v_blank_end = get_reg_field_value(value, CRTC_V_BLANK_START_END, CRTC_V_BLANK_END); - dce110_timing_generator_get_crtc_positions(tg, h_position, v_position); + dce110_timing_generator_get_position( + tg, &position); + + *h_position = position.horizontal_count; + *v_position = position.vertical_count; } /* TODO: is it safe to assume that mask/shift of Primary and Underlay @@ -1344,15 +1353,13 @@ void dce110_timing_generator_tear_down_global_swap_lock( */ bool dce110_timing_generator_is_counter_moving(struct timing_generator *tg) { - uint32_t h1 = 0; - uint32_t h2 = 0; - uint32_t v1 = 0; - uint32_t v2 = 0; + struct crtc_position position1, position2; - tg->funcs->get_position(tg, &h1, &v1); - tg->funcs->get_position(tg, &h2, &v2); + tg->funcs->get_position(tg, &position1); + tg->funcs->get_position(tg, &position2); - if (h1 == h2 && v1 == v2) + if (position1.horizontal_count == position2.horizontal_count && + position1.vertical_count == position2.vertical_count) return false; else return true; @@ -1750,18 +1757,6 @@ void dce110_tg_set_overscan_color(struct timing_generator *tg, dm_write_reg(ctx, addr, value); } -void dce110_tg_get_position(struct timing_generator *tg, - struct crtc_position *position) -{ - int32_t h_position; - int32_t v_position; - - dce110_timing_generator_get_crtc_positions(tg, &h_position, &v_position); - - position->horizontal_count = (uint32_t)h_position; - position->vertical_count = (uint32_t)v_position; -} - void dce110_tg_program_timing(struct timing_generator *tg, const struct dc_crtc_timing *timing, bool use_vbios) @@ -1895,7 +1890,7 @@ static const struct timing_generator_funcs dce110_tg_funcs = { .enable_crtc = dce110_timing_generator_enable_crtc, .disable_crtc = dce110_timing_generator_disable_crtc, .is_counter_moving = dce110_timing_generator_is_counter_moving, - .get_position = dce110_timing_generator_get_crtc_positions, + .get_position = dce110_timing_generator_get_position, .get_frame_count = dce110_timing_generator_get_vblank_counter, .get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos, .set_early_control = dce110_timing_generator_set_early_control, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h index f14a4d91cd8e..a5d63c626ada 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h @@ -151,11 +151,9 @@ void dce110_timing_generator_set_early_control( uint32_t dce110_timing_generator_get_vblank_counter( struct timing_generator *tg); -/* Get current H and V position */ -void dce110_timing_generator_get_crtc_positions( +void dce110_timing_generator_get_position( struct timing_generator *tg, - int32_t *h_position, - int32_t *v_position); + struct crtc_position *position); /* return true if TG counter is moving. false if TG is stopped */ bool dce110_timing_generator_is_counter_moving(struct timing_generator *tg); @@ -251,9 +249,6 @@ void dce110_tg_program_blank_color(struct timing_generator *tg, void dce110_tg_set_overscan_color(struct timing_generator *tg, const struct tg_color *overscan_color); -void dce110_tg_get_position(struct timing_generator *tg, - struct crtc_position *position); - void dce110_tg_program_timing(struct timing_generator *tg, const struct dc_crtc_timing *timing, bool use_vbios); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c index c95b69446ced..759c55bb4d15 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c @@ -570,24 +570,11 @@ static void dce110_timing_generator_v_set_early_control( dm_write_reg(tg->ctx, address, regval); } -static void dce110_timing_generator_v_get_crtc_positions( - struct timing_generator *tg, - int32_t *h_position, - int32_t *v_position) +static void dce110_timing_generator_get_underlay_position(struct timing_generator *tg, + struct crtc_position *position) { - uint32_t value; - - value = dm_read_reg(tg->ctx, mmCRTCV_STATUS_POSITION); - - *h_position = get_reg_field_value( - value, - CRTCV_STATUS_POSITION, - CRTC_HORZ_COUNT); - - *v_position = get_reg_field_value( - value, - CRTCV_STATUS_POSITION, - CRTC_VERT_COUNT); + //Should never hit this case + ASSERT(false); } static uint32_t dce110_timing_generator_v_get_vblank_counter(struct timing_generator *tg) @@ -665,7 +652,7 @@ static const struct timing_generator_funcs dce110_tg_v_funcs = { .enable_crtc = dce110_timing_generator_v_enable_crtc, .disable_crtc = dce110_timing_generator_v_disable_crtc, .is_counter_moving = dce110_timing_generator_v_is_counter_moving, - .get_position = dce110_timing_generator_v_get_crtc_positions, + .get_position = dce110_timing_generator_get_underlay_position, .get_frame_count = dce110_timing_generator_v_get_vblank_counter, .set_early_control = dce110_timing_generator_v_set_early_control, .wait_for_state = dce110_timing_generator_v_wait_for_state, diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c index 1318df7ed47e..245356e72b36 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c @@ -180,10 +180,9 @@ uint32_t dce120_timing_generator_get_vblank_counter( } /* Get current H and V position */ -void dce120_timing_generator_get_crtc_positions( +void dce120_timing_generator_get_crtc_position( struct timing_generator *tg, - int32_t *h_position, - int32_t *v_position) + struct crtc_position *position) { struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); uint32_t value = dm_read_reg_soc15( @@ -191,11 +190,19 @@ void dce120_timing_generator_get_crtc_positions( mmCRTC0_CRTC_STATUS_POSITION, tg110->offsets.crtc); - *h_position = get_reg_field_value( - value, CRTC0_CRTC_STATUS_POSITION, CRTC_HORZ_COUNT); + position->horizontal_count = get_reg_field_value(value, + CRTC0_CRTC_STATUS_POSITION, CRTC_HORZ_COUNT); - *v_position = get_reg_field_value( - value, CRTC0_CRTC_STATUS_POSITION, CRTC_VERT_COUNT); + position->vertical_count = get_reg_field_value(value, + CRTC0_CRTC_STATUS_POSITION, CRTC_VERT_COUNT); + + value = dm_read_reg_soc15( + tg->ctx, + mmCRTC0_CRTC_NOM_VERT_POSITION, + tg110->offsets.crtc); + + position->nominal_vcount = get_reg_field_value(value, + CRTC0_CRTC_NOM_VERT_POSITION, CRTC_VERT_COUNT_NOM); } /* wait until TG is in beginning of vertical blank region */ @@ -576,6 +583,49 @@ void dce120_timing_generator_set_drr( } } +/** + ***************************************************************************** + * Function: dce120_timing_generator_get_position + * + * @brief + * Returns CRTC vertical/horizontal counters + * + * @param [out] position + ***************************************************************************** + */ +void dce120_timing_generator_get_position(struct timing_generator *tg, + struct crtc_position *position) +{ + uint32_t value; + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + + value = dm_read_reg_soc15( + tg->ctx, + mmCRTC0_CRTC_STATUS_POSITION, + tg110->offsets.crtc); + + position->horizontal_count = get_reg_field_value( + value, + CRTC0_CRTC_STATUS_POSITION, + CRTC_HORZ_COUNT); + + position->vertical_count = get_reg_field_value( + value, + CRTC0_CRTC_STATUS_POSITION, + CRTC_VERT_COUNT); + + value = dm_read_reg_soc15( + tg->ctx, + mmCRTC0_CRTC_NOM_VERT_POSITION, + tg110->offsets.crtc); + + position->nominal_vcount = get_reg_field_value( + value, + CRTC0_CRTC_NOM_VERT_POSITION, + CRTC_VERT_COUNT_NOM); +} + + void dce120_timing_generator_get_crtc_scanoutpos( struct timing_generator *tg, uint32_t *v_blank_start, @@ -584,6 +634,7 @@ void dce120_timing_generator_get_crtc_scanoutpos( uint32_t *v_position) { struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + struct crtc_position position; uint32_t v_blank_start_end = dm_read_reg_soc15( tg->ctx, @@ -597,7 +648,11 @@ void dce120_timing_generator_get_crtc_scanoutpos( CRTC0_CRTC_V_BLANK_START_END, CRTC_V_BLANK_END); - dce120_timing_generator_get_crtc_positions(tg, h_position, v_position); + dce120_timing_generator_get_crtc_position( + tg, &position); + + *h_position = position.horizontal_count; + *v_position = position.vertical_count; } void dce120_timing_generator_enable_advanced_request( @@ -1076,7 +1131,7 @@ static struct timing_generator_funcs dce120_tg_funcs = { /* used by enable_timing_synchronization. Not need for FPGA */ .is_counter_moving = dce110_timing_generator_is_counter_moving, /* never be called */ - .get_position = dce120_timing_generator_get_crtc_positions, + .get_position = dce120_timing_generator_get_crtc_position, .get_frame_count = dce120_timing_generator_get_vblank_counter, .get_scanoutpos = dce120_timing_generator_get_crtc_scanoutpos, .set_early_control = dce120_timing_generator_set_early_control, diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c index 1198f2fbf9c7..179a6d604838 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c @@ -121,7 +121,7 @@ static const struct timing_generator_funcs dce80_tg_funcs = { .enable_crtc = dce110_timing_generator_enable_crtc, .disable_crtc = dce110_timing_generator_disable_crtc, .is_counter_moving = dce110_timing_generator_is_counter_moving, - .get_position = dce110_timing_generator_get_crtc_positions, + .get_position = dce110_timing_generator_get_position, .get_frame_count = dce110_timing_generator_get_vblank_counter, .get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos, .set_early_control = dce110_timing_generator_set_early_control, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 235cfe8d1ad4..2c4a9d02b3c1 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -30,9 +30,9 @@ struct dc_bios; /* Contains CRTC vertical/horizontal pixel counters */ struct crtc_position { - uint32_t vertical_count; - uint32_t horizontal_count; - uint32_t nominal_vcount; + int32_t vertical_count; + int32_t horizontal_count; + int32_t nominal_vcount; }; struct dcp_gsl_params { @@ -105,8 +105,8 @@ struct timing_generator_funcs { bool (*disable_crtc)(struct timing_generator *tg); bool (*is_counter_moving)(struct timing_generator *tg); void (*get_position)(struct timing_generator *tg, - int32_t *h_position, - int32_t *v_position); + struct crtc_position *position); + uint32_t (*get_frame_count)(struct timing_generator *tg); void (*get_scanoutpos)( struct timing_generator *tg, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index b42e4a0ef18a..afdb8605a30f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -131,6 +131,9 @@ struct hw_sequencer_funcs { void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, int vmin, int vmax); + void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, + struct crtc_position *position); + void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, int num_pipes, const struct dc_static_screen_events *events); diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 78b4f28d862c..f6223e6b3536 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -76,6 +76,16 @@ struct fixed_refresh { bool program_fixed_refresh; }; +struct freesync_range { + unsigned int min_refresh; + unsigned int max_frame_duration; + unsigned int vmax; + + unsigned int max_refresh; + unsigned int min_frame_duration; + unsigned int vmin; +}; + struct freesync_state { bool fullscreen; bool static_screen; @@ -89,6 +99,7 @@ struct freesync_state { struct gradual_static_ramp static_ramp; struct below_the_range btr; struct fixed_refresh fixed_refresh; + struct freesync_range freesync_range; }; struct freesync_entity { @@ -342,8 +353,11 @@ static void update_stream(struct core_freesync *core_freesync, } } -static void calc_vmin_vmax(struct core_freesync *core_freesync, - const struct dc_stream *stream, int *vmin, int *vmax) +static void calc_freesync_range(struct core_freesync *core_freesync, + const struct dc_stream *stream, + struct freesync_state *state, + unsigned int min_refresh_in_uhz, + unsigned int max_refresh_in_uhz) { unsigned int min_frame_duration_in_ns = 0, max_frame_duration_in_ns = 0; unsigned int index = map_index_from_stream(core_freesync, stream); @@ -351,29 +365,50 @@ static void calc_vmin_vmax(struct core_freesync *core_freesync, min_frame_duration_in_ns = ((unsigned int) (div64_u64( (1000000000ULL * 1000000), - core_freesync->map[index].state. - nominal_refresh_rate_in_micro_hz))); + max_refresh_in_uhz))); max_frame_duration_in_ns = ((unsigned int) (div64_u64( - (1000000000ULL * 1000000), - core_freesync->map[index].caps->min_refresh_in_micro_hz))); + (1000000000ULL * 1000000), + min_refresh_in_uhz))); + + state->freesync_range.min_refresh = min_refresh_in_uhz; + state->freesync_range.max_refresh = max_refresh_in_uhz; - *vmax = div64_u64(div64_u64(((unsigned long long)( - max_frame_duration_in_ns) * stream->timing.pix_clk_khz), - stream->timing.h_total), 1000000); - *vmin = div64_u64(div64_u64(((unsigned long long)( - min_frame_duration_in_ns) * stream->timing.pix_clk_khz), - stream->timing.h_total), 1000000); + state->freesync_range.max_frame_duration = max_frame_duration_in_ns; + state->freesync_range.min_frame_duration = min_frame_duration_in_ns; + + state->freesync_range.vmax = div64_u64(div64_u64(((unsigned long long)( + max_frame_duration_in_ns) * stream->timing.pix_clk_khz), + stream->timing.h_total), 1000000); + state->freesync_range.vmin = div64_u64(div64_u64(((unsigned long long)( + min_frame_duration_in_ns) * stream->timing.pix_clk_khz), + stream->timing.h_total), 1000000); /* In case of 4k free sync monitor, vmin or vmax cannot be less than vtotal */ - if (*vmin < vtotal) { + if (state->freesync_range.vmin < vtotal) { ASSERT(false); - *vmin = vtotal; + state->freesync_range.vmin = vtotal; } - if (*vmax < vtotal) { + if (state->freesync_range.vmax < vtotal) { ASSERT(false); - *vmax = vtotal; + state->freesync_range.vmax = vtotal; } + + /* Determine whether BTR can be supported */ + if (max_frame_duration_in_ns >= + 2 * min_frame_duration_in_ns) + core_freesync->map[index].caps->btr_supported = true; + else + core_freesync->map[index].caps->btr_supported = false; + + /* Cache the time variables */ + state->time.max_render_time_in_us = + max_frame_duration_in_ns / 1000; + state->time.min_render_time_in_us = + min_frame_duration_in_ns / 1000; + state->btr.mid_point_in_us = + (max_frame_duration_in_ns + + min_frame_duration_in_ns) / 2000; } static void calc_v_total_from_duration(const struct dc_stream *stream, @@ -518,9 +553,8 @@ static bool set_freesync_on_streams(struct core_freesync *core_freesync, state->fixed_refresh.fixed_refresh_active == false) { /* Enable freesync */ - calc_vmin_vmax(core_freesync, - streams[stream_idx], - &v_total_min, &v_total_max); + v_total_min = state->freesync_range.vmin; + v_total_max = state->freesync_range.vmax; /* Update the freesync context for the stream */ update_stream_freesync_context(core_freesync, @@ -696,7 +730,7 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, (1000000000ULL * 1000000), state->nominal_refresh_rate_in_micro_hz))); - calc_vmin_vmax(core_freesync, *streams, &vmin, &vmax); + vmin = state->freesync_range.vmin; inserted_frame_v_total = vmin; @@ -941,11 +975,120 @@ bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, return true; } +bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, + const struct dc_stream *streams, + unsigned int min_refresh, + unsigned int max_refresh) +{ + unsigned int index = 0; + struct core_freesync *core_freesync; + struct freesync_state *state; + + if (mod_freesync == NULL) + return false; + + core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); + index = map_index_from_stream(core_freesync, streams); + state = &core_freesync->map[index].state; + + if (min_refresh == 0 || max_refresh == 0) { + /* Restore defaults */ + calc_freesync_range(core_freesync, streams, state, + core_freesync->map[index].caps-> + min_refresh_in_micro_hz, + state->nominal_refresh_rate_in_micro_hz); + } else { + calc_freesync_range(core_freesync, streams, + state, + min_refresh, + max_refresh); + + /* Program vtotal min/max */ + core_freesync->dc->stream_funcs.adjust_vmin_vmax( + core_freesync->dc, &streams, 1, + state->freesync_range.vmin, + state->freesync_range.vmax); + } + + return true; +} + +bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, + const struct dc_stream *stream, + unsigned int *min_refresh, + unsigned int *max_refresh) +{ + unsigned int index = 0; + struct core_freesync *core_freesync = NULL; + + if (mod_freesync == NULL) + return false; + + core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); + index = map_index_from_stream(core_freesync, stream); + + *min_refresh = + core_freesync->map[index].state.freesync_range.min_refresh; + *max_refresh = + core_freesync->map[index].state.freesync_range.max_refresh; + + return true; +} + +bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, + const struct dc_stream *stream, + unsigned int *vmin, + unsigned int *vmax) +{ + unsigned int index = 0; + struct core_freesync *core_freesync = NULL; + + if (mod_freesync == NULL) + return false; + + core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); + index = map_index_from_stream(core_freesync, stream); + + *vmin = + core_freesync->map[index].state.freesync_range.vmin; + *vmax = + core_freesync->map[index].state.freesync_range.vmax; + + return true; +} + +bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, + const struct dc_stream *stream, + unsigned int *nom_v_pos, + unsigned int *v_pos) +{ + unsigned int index = 0; + struct core_freesync *core_freesync = NULL; + struct crtc_position position; + + if (mod_freesync == NULL) + return false; + + core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); + index = map_index_from_stream(core_freesync, stream); + + if (core_freesync->dc->stream_funcs.get_crtc_position( + core_freesync->dc, &stream, 1, + &position.vertical_count, &position.nominal_vcount)) { + + *nom_v_pos = position.vertical_count; + *v_pos = position.nominal_vcount; + + return true; + } + + return false; +} + void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, const struct dc_stream **streams, int num_streams) { unsigned int stream_index, map_index; - unsigned min_frame_duration_in_ns, max_frame_duration_in_ns; struct freesync_state *state; struct core_freesync *core_freesync = NULL; @@ -965,37 +1108,23 @@ void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, unsigned long long temp; temp = streams[stream_index]->timing.pix_clk_khz; temp *= 1000ULL * 1000ULL * 1000ULL; - temp = div_u64(temp, streams[stream_index]->timing.h_total); - temp = div_u64(temp, streams[stream_index]->timing.v_total); - state->nominal_refresh_rate_in_micro_hz = (unsigned int) temp; + temp = div_u64(temp, + streams[stream_index]->timing.h_total); + temp = div_u64(temp, + streams[stream_index]->timing.v_total); + state->nominal_refresh_rate_in_micro_hz = + (unsigned int) temp; /* Update the stream */ update_stream(core_freesync, streams[stream_index]); - /* Determine whether BTR can be supported */ - min_frame_duration_in_ns = ((unsigned int) (div64_u64( - (1000000000ULL * 1000000), - state->nominal_refresh_rate_in_micro_hz))); - - max_frame_duration_in_ns = ((unsigned int) (div64_u64( - (1000000000ULL * 1000000), - core_freesync->map[map_index].caps->min_refresh_in_micro_hz))); - - if (max_frame_duration_in_ns >= - 2 * min_frame_duration_in_ns) - core_freesync->map[map_index].caps->btr_supported = true; - else - core_freesync->map[map_index].caps->btr_supported = false; - - /* Cache the time variables */ - state->time.max_render_time_in_us = - max_frame_duration_in_ns / 1000; - state->time.min_render_time_in_us = - min_frame_duration_in_ns / 1000; - state->btr.mid_point_in_us = - (max_frame_duration_in_ns + - min_frame_duration_in_ns) / 2000; - + /* Calculate vmin/vmax and refresh rate for + * current mode + */ + calc_freesync_range(core_freesync, *streams, state, + core_freesync->map[stream_index].caps-> + min_refresh_in_micro_hz, + state->nominal_refresh_rate_in_micro_hz); } } @@ -1178,7 +1307,7 @@ static void apply_fixed_refresh(struct core_freesync *core_freesync, /* Fixed Refresh set to "active" so engage (fix to max) */ } else { - calc_vmin_vmax(core_freesync, stream, &vmin, &vmax); + vmin = state->freesync_range.vmin; vmax = vmin; diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h index 783ff2ef3bee..3947cc412ad7 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h @@ -129,6 +129,26 @@ bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, const struct dc_stream *stream, struct mod_freesync_user_enable *user_enable); +bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, + const struct dc_stream *streams, + unsigned int min_refresh, + unsigned int max_refresh); + +bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, + const struct dc_stream *stream, + unsigned int *min_refresh, + unsigned int *max_refresh); + +bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, + const struct dc_stream *stream, + unsigned int *vmin, + unsigned int *vmax); + +bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, + const struct dc_stream *stream, + unsigned int *nom_v_pos, + unsigned int *v_pos); + void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, const struct dc_stream **streams, int num_streams); -- cgit v1.2.3 From 1c29313b96fbe9606ecaab540800d20f2ae88adc Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Wed, 26 Apr 2017 10:54:45 -0400 Subject: drm/amd/display: fix crash caused by incorrect index being used for array Signed-off-by: Dmytro Laktyushkin Acked-by: Harry Wentland Reviewed-by: Anthony Koo Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index f6223e6b3536..d3d57008271b 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -1122,7 +1122,7 @@ void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, * current mode */ calc_freesync_range(core_freesync, *streams, state, - core_freesync->map[stream_index].caps-> + core_freesync->map[map_index].caps-> min_refresh_in_micro_hz, state->nominal_refresh_rate_in_micro_hz); } -- cgit v1.2.3 From 7cc9e7a68abef8d1303700bac6f58ab76bc9db7b Mon Sep 17 00:00:00 2001 From: Eric Cook Date: Wed, 26 Apr 2017 11:51:38 -0400 Subject: drm/amd/display: Check for Zero Range in FreeSync Calc -check for min/max range in freesync calculation and handle it accordingly Signed-off-by: Eric Acked-by: Harry Wentland Reviewed-by: Anthony Koo Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index d3d57008271b..009cb797bcfa 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -363,6 +363,21 @@ static void calc_freesync_range(struct core_freesync *core_freesync, unsigned int index = map_index_from_stream(core_freesync, stream); uint32_t vtotal = stream->timing.v_total; + if ((min_refresh_in_uhz == 0) || (max_refresh_in_uhz == 0)) { + state->freesync_range.min_refresh = + state->nominal_refresh_rate_in_micro_hz; + state->freesync_range.max_refresh = + state->nominal_refresh_rate_in_micro_hz; + + state->freesync_range.max_frame_duration = 0; + state->freesync_range.min_frame_duration = 0; + + state->freesync_range.vmax = vtotal; + state->freesync_range.vmin = vtotal; + + return; + } + min_frame_duration_in_ns = ((unsigned int) (div64_u64( (1000000000ULL * 1000000), max_refresh_in_uhz))); -- cgit v1.2.3 From 9e594f4c3f30c8ba43a1601268e82177fbd737c1 Mon Sep 17 00:00:00 2001 From: Eric Cook Date: Thu, 27 Apr 2017 12:20:34 -0400 Subject: drm/amd/display: Add support for FreeSync on eDP to module Signed-off-by: Eric Acked-by: Harry Wentland Reviewed-by: Anthony Koo Signed-off-by: Alex Deucher --- .../drm/amd/display/modules/freesync/freesync.c | 42 +++++++++++++++++----- 1 file changed, 33 insertions(+), 9 deletions(-) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 009cb797bcfa..82086a129a3b 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -109,11 +109,16 @@ struct freesync_entity { struct mod_freesync_user_enable user_enable; }; +struct freesync_registry_options { + unsigned int min_refresh_from_edid; +}; + struct core_freesync { struct mod_freesync public; struct dc *dc; struct freesync_entity *map; int num_entities; + struct freesync_registry_options opts; }; #define MOD_FREESYNC_TO_CORE(mod_freesync)\ @@ -136,7 +141,7 @@ struct mod_freesync *mod_freesync_create(struct dc *dc) struct persistent_data_flag flag; - int i = 0; + int i, data = 0; if (core_freesync == NULL) goto fail_alloc_context; @@ -165,6 +170,12 @@ struct mod_freesync *mod_freesync_create(struct dc *dc) flag.save_per_link = false; dm_write_persistent_data(core_dc->ctx, NULL, FREESYNC_REGISTRY_NAME, NULL, NULL, 0, &flag); + flag.save_per_edid = false; + flag.save_per_link = false; + if (dm_read_persistent_data(core_dc->ctx, NULL, NULL, + "DalDrrSupport", &data, sizeof(data), &flag)) { + core_freesync->opts.min_refresh_from_edid = data; + } return &core_freesync->public; @@ -219,7 +230,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, struct core_stream *core_stream = NULL; struct core_dc *core_dc = NULL; struct core_freesync *core_freesync = NULL; - int persistent_freesync_enable = 0; + int persistent_freesync_enable, stream_index = 0; struct persistent_data_flag flag; unsigned int nom_refresh_rate_micro_hz; unsigned long long temp; @@ -238,6 +249,26 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, dc_stream_retain(stream); + stream_index = map_index_from_stream(core_freesync, stream); + + temp = stream->timing.pix_clk_khz; + temp *= 1000ULL * 1000ULL * 1000ULL; + temp = div_u64(temp, stream->timing.h_total); + temp = div_u64(temp, stream->timing.v_total); + + nom_refresh_rate_micro_hz = (unsigned int) temp; + + if (core_freesync->opts.min_refresh_from_edid != 0 && + dc_is_embedded_signal( + stream[stream_index].sink->sink_signal)) { + caps->supported = true; + caps->min_refresh_in_micro_hz = + core_freesync->opts.min_refresh_from_edid * + 1000000; + caps->max_refresh_in_micro_hz = + nom_refresh_rate_micro_hz; + } + core_freesync->map[core_freesync->num_entities].stream = stream; core_freesync->map[core_freesync->num_entities].caps = caps; @@ -275,13 +306,6 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, enable_for_video = false; } - temp = stream->timing.pix_clk_khz; - temp *= 1000ULL * 1000ULL * 1000ULL; - temp = div_u64(temp, stream->timing.h_total); - temp = div_u64(temp, stream->timing.v_total); - - nom_refresh_rate_micro_hz = (unsigned int) temp; - if (caps->supported && nom_refresh_rate_micro_hz >= caps->min_refresh_in_micro_hz && nom_refresh_rate_micro_hz <= caps->max_refresh_in_micro_hz) -- cgit v1.2.3 From ba624cddbc002816e376d588290a48f77ff4b06f Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Wed, 3 May 2017 13:58:45 -0400 Subject: drm/amd/display: Assign stream to map before we need it Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 82086a129a3b..c5330f3cc1de 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -230,7 +230,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, struct core_stream *core_stream = NULL; struct core_dc *core_dc = NULL; struct core_freesync *core_freesync = NULL; - int persistent_freesync_enable, stream_index = 0; + int persistent_freesync_enable = 0; struct persistent_data_flag flag; unsigned int nom_refresh_rate_micro_hz; unsigned long long temp; @@ -249,8 +249,6 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, dc_stream_retain(stream); - stream_index = map_index_from_stream(core_freesync, stream); - temp = stream->timing.pix_clk_khz; temp *= 1000ULL * 1000ULL * 1000ULL; temp = div_u64(temp, stream->timing.h_total); @@ -260,7 +258,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, if (core_freesync->opts.min_refresh_from_edid != 0 && dc_is_embedded_signal( - stream[stream_index].sink->sink_signal)) { + stream->sink->sink_signal)) { caps->supported = true; caps->min_refresh_in_micro_hz = core_freesync->opts.min_refresh_from_edid * -- cgit v1.2.3 From ac5c294719909bd5d2d3f8c74f894bdda5744916 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Fri, 5 May 2017 15:07:55 -0400 Subject: drm/amd/display: prevent assert on error of 1 in calc_freesync_range Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index c5330f3cc1de..05a086c7b31a 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -422,12 +422,14 @@ static void calc_freesync_range(struct core_freesync *core_freesync, /* In case of 4k free sync monitor, vmin or vmax cannot be less than vtotal */ if (state->freesync_range.vmin < vtotal) { - ASSERT(false); + /* Error of 1 is permissible */ + ASSERT((state->freesync_range.vmin + 1) >= vtotal); state->freesync_range.vmin = vtotal; } if (state->freesync_range.vmax < vtotal) { - ASSERT(false); + /* Error of 1 is permissible */ + ASSERT((state->freesync_range.vmax + 1) >= vtotal); state->freesync_range.vmax = vtotal; } -- cgit v1.2.3 From 6838161c723d061c85e20057dbf0a2a9378c4e59 Mon Sep 17 00:00:00 2001 From: Corbin McElhanney Date: Tue, 9 May 2017 12:00:24 -0400 Subject: drm/amd/display: fix freesync not working on raven Signed-off-by: Corbin McElhanney Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 05a086c7b31a..9a073bc55144 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -1130,6 +1130,7 @@ void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, unsigned int stream_index, map_index; struct freesync_state *state; struct core_freesync *core_freesync = NULL; + struct dc_static_screen_events triggers = {0}; if (mod_freesync == NULL) return; @@ -1157,6 +1158,7 @@ void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, /* Update the stream */ update_stream(core_freesync, streams[stream_index]); + /* Calculate vmin/vmax and refresh rate for * current mode */ @@ -1164,6 +1166,14 @@ void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, core_freesync->map[map_index].caps-> min_refresh_in_micro_hz, state->nominal_refresh_rate_in_micro_hz); + + /* Update mask */ + triggers.overlay_update = true; + triggers.surface_update = true; + + core_freesync->dc->stream_funcs.set_static_screen_events( + core_freesync->dc, streams, num_streams, + &triggers); } } -- cgit v1.2.3 From fc82c5cb306d6f201cdee2c4c092ff49c6929634 Mon Sep 17 00:00:00 2001 From: Amy Zhang Date: Fri, 2 Jun 2017 16:33:47 -0400 Subject: drm/amd/display: Fix DRR Enable on Desktop - Block PSR in Full screen apps to prevent incorrect static screen curser events - Reprogram static screen events when update freesync state - Program static ramp variable active after other values are programmed - Correct wrong assigning of the nominal and current vcount Signed-off-by: Amy Zhang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/modules/freesync/freesync.c | 89 ++++++++++++++-------- .../gpu/drm/amd/display/modules/inc/mod_freesync.h | 3 +- 2 files changed, 61 insertions(+), 31 deletions(-) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 9a073bc55144..f79c47951f90 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -257,8 +257,10 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, nom_refresh_rate_micro_hz = (unsigned int) temp; if (core_freesync->opts.min_refresh_from_edid != 0 && - dc_is_embedded_signal( - stream->sink->sink_signal)) { + dc_is_embedded_signal(stream->sink->sink_signal) + && (nom_refresh_rate_micro_hz - + core_freesync->opts.min_refresh_from_edid * + 1000000) >= 10000000) { caps->supported = true; caps->min_refresh_in_micro_hz = core_freesync->opts.min_refresh_from_edid * @@ -683,44 +685,47 @@ static void set_static_ramp_variables(struct core_freesync *core_freesync, unsigned int index, bool enable_static_screen) { unsigned int frame_duration = 0; - + unsigned int nominal_refresh_rate = core_freesync->map[index].state. + nominal_refresh_rate_in_micro_hz; + unsigned int min_refresh_rate= core_freesync->map[index].caps-> + min_refresh_in_micro_hz; struct gradual_static_ramp *static_ramp_variables = &core_freesync->map[index].state.static_ramp; + /* If we are ENABLING static screen, refresh rate should go DOWN. + * If we are DISABLING static screen, refresh rate should go UP. + */ + if (enable_static_screen) + static_ramp_variables->ramp_direction_is_up = false; + else + static_ramp_variables->ramp_direction_is_up = true; + /* If ramp is not active, set initial frame duration depending on * whether we are enabling/disabling static screen mode. If the ramp is * already active, ramp should continue in the opposite direction * starting with the current frame duration */ if (!static_ramp_variables->ramp_is_active) { - - static_ramp_variables->ramp_is_active = true; - if (enable_static_screen == true) { /* Going to lower refresh rate, so start from max * refresh rate (min frame duration) */ frame_duration = ((unsigned int) (div64_u64( (1000000000ULL * 1000000), - core_freesync->map[index].state. - nominal_refresh_rate_in_micro_hz))); + nominal_refresh_rate))); } else { /* Going to higher refresh rate, so start from min * refresh rate (max frame duration) */ frame_duration = ((unsigned int) (div64_u64( (1000000000ULL * 1000000), - core_freesync->map[index].caps->min_refresh_in_micro_hz))); + min_refresh_rate))); } - static_ramp_variables-> ramp_current_frame_duration_in_ns = frame_duration; - } - /* If we are ENABLING static screen, refresh rate should go DOWN. - * If we are DISABLING static screen, refresh rate should go UP. - */ - static_ramp_variables->ramp_direction_is_up = !enable_static_screen; + static_ramp_variables->ramp_is_active = true; + } } void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, @@ -841,6 +846,7 @@ void mod_freesync_update_state(struct mod_freesync *mod_freesync, unsigned int stream_index; struct freesync_state *state; struct core_freesync *core_freesync = NULL; + struct dc_static_screen_events triggers = {0}; if (mod_freesync == NULL) return; @@ -902,6 +908,14 @@ void mod_freesync_update_state(struct mod_freesync *mod_freesync, } } + /* Update mask */ + triggers.overlay_update = true; + triggers.surface_update = true; + + core_freesync->dc->stream_funcs.set_static_screen_events( + core_freesync->dc, streams, num_streams, + &triggers); + if (freesync_program_required) /* Program freesync according to current state*/ set_freesync_on_streams(core_freesync, streams, num_streams); @@ -1017,7 +1031,8 @@ bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, const struct dc_stream *streams, unsigned int min_refresh, - unsigned int max_refresh) + unsigned int max_refresh, + struct mod_freesync_caps *caps) { unsigned int index = 0; struct core_freesync *core_freesync; @@ -1030,7 +1045,10 @@ bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, index = map_index_from_stream(core_freesync, streams); state = &core_freesync->map[index].state; - if (min_refresh == 0 || max_refresh == 0) { + if (max_refresh == 0) + max_refresh = state->nominal_refresh_rate_in_micro_hz; + + if (min_refresh == 0) { /* Restore defaults */ calc_freesync_range(core_freesync, streams, state, core_freesync->map[index].caps-> @@ -1049,6 +1067,17 @@ bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, state->freesync_range.vmax); } + if (min_refresh != 0 && + dc_is_embedded_signal(streams->sink->sink_signal) && + (max_refresh - min_refresh >= 10000000)) { + caps->supported = true; + caps->min_refresh_in_micro_hz = min_refresh; + caps->max_refresh_in_micro_hz = max_refresh; + } + + /* Update the stream */ + update_stream(core_freesync, streams); + return true; } @@ -1115,8 +1144,8 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, core_freesync->dc, &stream, 1, &position.vertical_count, &position.nominal_vcount)) { - *nom_v_pos = position.vertical_count; - *v_pos = position.nominal_vcount; + *nom_v_pos = position.nominal_vcount; + *v_pos = position.vertical_count; return true; } @@ -1131,6 +1160,7 @@ void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, struct freesync_state *state; struct core_freesync *core_freesync = NULL; struct dc_static_screen_events triggers = {0}; + unsigned long long temp = 0; if (mod_freesync == NULL) return; @@ -1143,22 +1173,21 @@ void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, state = &core_freesync->map[map_index].state; + /* Update the field rate for new timing */ + temp = streams[stream_index]->timing.pix_clk_khz; + temp *= 1000ULL * 1000ULL * 1000ULL; + temp = div_u64(temp, + streams[stream_index]->timing.h_total); + temp = div_u64(temp, + streams[stream_index]->timing.v_total); + state->nominal_refresh_rate_in_micro_hz = + (unsigned int) temp; + if (core_freesync->map[map_index].caps->supported) { - /* Update the field rate for new timing */ - unsigned long long temp; - temp = streams[stream_index]->timing.pix_clk_khz; - temp *= 1000ULL * 1000ULL * 1000ULL; - temp = div_u64(temp, - streams[stream_index]->timing.h_total); - temp = div_u64(temp, - streams[stream_index]->timing.v_total); - state->nominal_refresh_rate_in_micro_hz = - (unsigned int) temp; /* Update the stream */ update_stream(core_freesync, streams[stream_index]); - /* Calculate vmin/vmax and refresh rate for * current mode */ diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h index 3947cc412ad7..f7f5a2cd7914 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h @@ -132,7 +132,8 @@ bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, const struct dc_stream *streams, unsigned int min_refresh, - unsigned int max_refresh); + unsigned int max_refresh, + struct mod_freesync_caps *caps); bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, const struct dc_stream *stream, -- cgit v1.2.3 From fea0f581ab529e194d424452a6f7ecd88c5a2116 Mon Sep 17 00:00:00 2001 From: Anthony Koo Date: Tue, 6 Jun 2017 16:30:51 -0400 Subject: drm/amd/display: Temporary disable BTR FreeSync support for now Reduce timer tick interval for the static screen Signed-off-by: Anthony Koo Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index f79c47951f90..7109742bd67c 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -436,11 +436,14 @@ static void calc_freesync_range(struct core_freesync *core_freesync, } /* Determine whether BTR can be supported */ - if (max_frame_duration_in_ns >= - 2 * min_frame_duration_in_ns) - core_freesync->map[index].caps->btr_supported = true; - else - core_freesync->map[index].caps->btr_supported = false; + //if (max_frame_duration_in_ns >= + // 2 * min_frame_duration_in_ns) + // core_freesync->map[index].caps->btr_supported = true; + //else + // core_freesync->map[index].caps->btr_supported = false; + + /* Temp, keep btr disabled */ + core_freesync->map[index].caps->btr_supported = false; /* Cache the time variables */ state->time.max_render_time_in_us = -- cgit v1.2.3 From d09fec0f94376b1c0048215e14838295730ed6d3 Mon Sep 17 00:00:00 2001 From: Anthony Koo Date: Tue, 27 Jun 2017 13:27:00 -0400 Subject: drm/amd/display: add hyst frames for fixed refresh Signed-off-by: Anthony Koo Reviewed-by: Anthony Koo Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/modules/freesync/freesync.c | 56 ++++++++++++++-------- 1 file changed, 36 insertions(+), 20 deletions(-) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 7109742bd67c..c7da90f2d8e7 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -37,6 +37,9 @@ #define RENDER_TIMES_MAX_COUNT 20 /* Threshold to exit BTR (to avoid frequent enter-exits at the lower limit) */ #define BTR_EXIT_MARGIN 2000 +/* Number of consecutive frames to check before entering/exiting fixed refresh*/ +#define FIXED_REFRESH_ENTER_FRAME_COUNT 5 +#define FIXED_REFRESH_EXIT_FRAME_COUNT 5 #define FREESYNC_REGISTRY_NAME "freesync_v1" @@ -72,8 +75,9 @@ struct below_the_range { }; struct fixed_refresh { - bool fixed_refresh_active; - bool program_fixed_refresh; + bool fixed_active; + bool program_fixed; + unsigned int frame_counter; }; struct freesync_range { @@ -168,8 +172,8 @@ struct mod_freesync *mod_freesync_create(struct dc *dc) /* Create initial module folder in registry for freesync enable data */ flag.save_per_edid = true; flag.save_per_link = false; - dm_write_persistent_data(core_dc->ctx, NULL, FREESYNC_REGISTRY_NAME, NULL, NULL, - 0, &flag); + dm_write_persistent_data(core_dc->ctx, NULL, FREESYNC_REGISTRY_NAME, + NULL, NULL, 0, &flag); flag.save_per_edid = false; flag.save_per_link = false; if (dm_read_persistent_data(core_dc->ctx, NULL, NULL, @@ -422,7 +426,7 @@ static void calc_freesync_range(struct core_freesync *core_freesync, min_frame_duration_in_ns) * stream->timing.pix_clk_khz), stream->timing.h_total), 1000000); - /* In case of 4k free sync monitor, vmin or vmax cannot be less than vtotal */ + /* vmin/vmax cannot be less than vtotal */ if (state->freesync_range.vmin < vtotal) { /* Error of 1 is permissible */ ASSERT((state->freesync_range.vmin + 1) >= vtotal); @@ -553,8 +557,8 @@ static void reset_freesync_state_variables(struct freesync_state* state) state->btr.inserted_frame_duration_in_us = 0; state->btr.program_btr = false; - state->fixed_refresh.fixed_refresh_active = false; - state->fixed_refresh.program_fixed_refresh = false; + state->fixed_refresh.fixed_active = false; + state->fixed_refresh.program_fixed = false; } /* * Sets freesync mode on a stream depending on current freesync state. @@ -594,7 +598,7 @@ static bool set_freesync_on_streams(struct core_freesync *core_freesync, if (core_freesync->map[map_index].user_enable. enable_for_gaming == true && state->fullscreen == true && - state->fixed_refresh.fixed_refresh_active == false) { + state->fixed_refresh.fixed_active == false) { /* Enable freesync */ v_total_min = state->freesync_range.vmin; @@ -1240,29 +1244,39 @@ static void update_timestamps(struct core_freesync *core_freesync, state->btr.frame_counter = 0; /* Exit Fixed Refresh mode */ - } else if (state->fixed_refresh.fixed_refresh_active) { + } else if (state->fixed_refresh.fixed_active) { - state->fixed_refresh.program_fixed_refresh = true; - state->fixed_refresh.fixed_refresh_active = false; + state->fixed_refresh.frame_counter++; + if (state->fixed_refresh.frame_counter > + FIXED_REFRESH_EXIT_FRAME_COUNT) { + state->fixed_refresh.frame_counter = 0; + state->fixed_refresh.program_fixed = true; + state->fixed_refresh.fixed_active = false; + } } } else if (last_render_time_in_us > state->time.max_render_time_in_us) { /* Enter Below the Range */ if (!state->btr.btr_active && - core_freesync->map[map_index].caps->btr_supported) { + core_freesync->map[map_index].caps->btr_supported) { state->btr.program_btr = true; state->btr.btr_active = true; /* Enter Fixed Refresh mode */ - } else if (!state->fixed_refresh.fixed_refresh_active && + } else if (!state->fixed_refresh.fixed_active && !core_freesync->map[map_index].caps->btr_supported) { - state->fixed_refresh.program_fixed_refresh = true; - state->fixed_refresh.fixed_refresh_active = true; + state->fixed_refresh.frame_counter++; + if (state->fixed_refresh.frame_counter > + FIXED_REFRESH_ENTER_FRAME_COUNT) { + state->fixed_refresh.frame_counter = 0; + state->fixed_refresh.program_fixed = true; + state->fixed_refresh.fixed_active = true; + } } } @@ -1316,7 +1330,8 @@ static void apply_below_the_range(struct core_freesync *core_freesync, frame_time_in_us = last_render_time_in_us / mid_point_frames_ceil; - delta_from_mid_point_in_us_1 = (state->btr.mid_point_in_us > + delta_from_mid_point_in_us_1 = + (state->btr.mid_point_in_us > frame_time_in_us) ? (state->btr.mid_point_in_us - frame_time_in_us): (frame_time_in_us - state->btr.mid_point_in_us); @@ -1332,7 +1347,8 @@ static void apply_below_the_range(struct core_freesync *core_freesync, frame_time_in_us = last_render_time_in_us / mid_point_frames_floor; - delta_from_mid_point_in_us_2 = (state->btr.mid_point_in_us > + delta_from_mid_point_in_us_2 = + (state->btr.mid_point_in_us > frame_time_in_us) ? (state->btr.mid_point_in_us - frame_time_in_us): (frame_time_in_us - state->btr.mid_point_in_us); @@ -1374,15 +1390,15 @@ static void apply_fixed_refresh(struct core_freesync *core_freesync, unsigned int vmin = 0, vmax = 0; struct freesync_state *state = &core_freesync->map[map_index].state; - if (!state->fixed_refresh.program_fixed_refresh) + if (!state->fixed_refresh.program_fixed) return; - state->fixed_refresh.program_fixed_refresh = false; + state->fixed_refresh.program_fixed = false; /* Program Fixed Refresh */ /* Fixed Refresh set to "not active" so disengage */ - if (!state->fixed_refresh.fixed_refresh_active) { + if (!state->fixed_refresh.fixed_active) { set_freesync_on_streams(core_freesync, &stream, 1); /* Fixed Refresh set to "active" so engage (fix to max) */ -- cgit v1.2.3 From 1a87fbfee0a0f96e8b482c2ac7eae113c9ca2497 Mon Sep 17 00:00:00 2001 From: Amy Zhang Date: Wed, 28 Jun 2017 18:14:09 -0400 Subject: drm/amd/display: Re-enable Vsync Interrupts for Gradual Refresh Ramp - Make sure Vsync interrupts are disabled in static screen case and enabled when not to save power - Create no_static_for_external_dp debug option Signed-off-by: Amy Zhang Reviewed-by: Anthony Koo Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + .../drm/amd/display/modules/freesync/freesync.c | 38 ++++++++++++++++------ .../gpu/drm/amd/display/modules/inc/mod_freesync.h | 5 +++ 3 files changed, 34 insertions(+), 10 deletions(-) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 3e2ed3d15379..93aff8269778 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -188,6 +188,7 @@ struct dc_debug { bool disable_dmcu; bool disable_psr; bool force_abm_enable; + bool no_static_for_external_dp; }; struct dc { diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index c7da90f2d8e7..4df79f7147f8 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -440,14 +440,11 @@ static void calc_freesync_range(struct core_freesync *core_freesync, } /* Determine whether BTR can be supported */ - //if (max_frame_duration_in_ns >= - // 2 * min_frame_duration_in_ns) - // core_freesync->map[index].caps->btr_supported = true; - //else - // core_freesync->map[index].caps->btr_supported = false; - - /* Temp, keep btr disabled */ - core_freesync->map[index].caps->btr_supported = false; + if (max_frame_duration_in_ns >= + 2 * min_frame_duration_in_ns) + core_freesync->map[index].caps->btr_supported = true; + else + core_freesync->map[index].caps->btr_supported = false; /* Cache the time variables */ state->time.max_render_time_in_us = @@ -882,8 +879,10 @@ void mod_freesync_update_state(struct mod_freesync *mod_freesync, * panels. Also change core variables only if there * is a change. */ - if (dc_is_embedded_signal( - streams[stream_index]->sink->sink_signal) && + if ((dc_is_embedded_signal( + streams[stream_index]->sink->sink_signal) || + core_freesync->map[map_index].caps-> + no_static_for_external_dp == false) && state->static_screen != freesync_params->enable) { @@ -1035,6 +1034,25 @@ bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, return true; } +bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync, + const struct dc_stream *stream, + bool *is_ramp_active) +{ + unsigned int index = 0; + struct core_freesync *core_freesync = NULL; + + if (mod_freesync == NULL) + return false; + + core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); + index = map_index_from_stream(core_freesync, stream); + + *is_ramp_active = + core_freesync->map[index].state.static_ramp.ramp_is_active; + + return true; +} + bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, const struct dc_stream *streams, unsigned int min_refresh, diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h index f7f5a2cd7914..eae1b348b0dd 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h @@ -88,6 +88,7 @@ struct mod_freesync_caps { unsigned int max_refresh_in_micro_hz; bool btr_supported; + bool no_static_for_external_dp; }; struct mod_freesync_params { @@ -129,6 +130,10 @@ bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, const struct dc_stream *stream, struct mod_freesync_user_enable *user_enable); +bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync, + const struct dc_stream *stream, + bool *is_ramp_active); + bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, const struct dc_stream *streams, unsigned int min_refresh, -- cgit v1.2.3 From 2233ec72b350fb8480f67b83f6a71ea422af60a3 Mon Sep 17 00:00:00 2001 From: Anthony Koo Date: Tue, 18 Jul 2017 10:21:43 -0400 Subject: drm/amd/display: Add regkey for DRR control for internal panel Also need to change default to off Signed-off-by: Anthony Koo Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 1 - .../drm/amd/display/modules/freesync/freesync.c | 74 ++++++++++++---------- .../gpu/drm/amd/display/modules/inc/mod_freesync.h | 1 - 3 files changed, 40 insertions(+), 36 deletions(-) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 6a22c91cbcef..07f064f53d85 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -188,7 +188,6 @@ struct dc_debug { bool disable_dmcu; bool disable_psr; bool force_abm_enable; - bool no_static_for_external_dp; }; struct dc { diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 4df79f7147f8..a989d5de9f3c 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -43,6 +43,10 @@ #define FREESYNC_REGISTRY_NAME "freesync_v1" +#define FREESYNC_NO_STATIC_FOR_EXTERNAL_DP_REGKEY "DalFreeSyncNoStaticForExternalDp" + +#define FREESYNC_NO_STATIC_FOR_INTERNAL_REGKEY "DalFreeSyncNoStaticForInternal" + struct gradual_static_ramp { bool ramp_is_active; bool ramp_direction_is_up; @@ -114,7 +118,8 @@ struct freesync_entity { }; struct freesync_registry_options { - unsigned int min_refresh_from_edid; + bool drr_external_supported; + bool drr_internal_supported; }; struct core_freesync { @@ -176,9 +181,19 @@ struct mod_freesync *mod_freesync_create(struct dc *dc) NULL, NULL, 0, &flag); flag.save_per_edid = false; flag.save_per_link = false; + if (dm_read_persistent_data(core_dc->ctx, NULL, NULL, - "DalDrrSupport", &data, sizeof(data), &flag)) { - core_freesync->opts.min_refresh_from_edid = data; + FREESYNC_NO_STATIC_FOR_INTERNAL_REGKEY, + &data, sizeof(data), &flag)) { + core_freesync->opts.drr_internal_supported = + (data & 1) ? false : true; + } + + if (dm_read_persistent_data(core_dc->ctx, NULL, NULL, + FREESYNC_NO_STATIC_FOR_EXTERNAL_DP_REGKEY, + &data, sizeof(data), &flag)) { + core_freesync->opts.drr_external_supported = + (data & 1) ? false : true; } return &core_freesync->public; @@ -236,7 +251,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, struct core_freesync *core_freesync = NULL; int persistent_freesync_enable = 0; struct persistent_data_flag flag; - unsigned int nom_refresh_rate_micro_hz; + unsigned int nom_refresh_rate_uhz; unsigned long long temp; if (mod_freesync == NULL) @@ -258,20 +273,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, temp = div_u64(temp, stream->timing.h_total); temp = div_u64(temp, stream->timing.v_total); - nom_refresh_rate_micro_hz = (unsigned int) temp; - - if (core_freesync->opts.min_refresh_from_edid != 0 && - dc_is_embedded_signal(stream->sink->sink_signal) - && (nom_refresh_rate_micro_hz - - core_freesync->opts.min_refresh_from_edid * - 1000000) >= 10000000) { - caps->supported = true; - caps->min_refresh_in_micro_hz = - core_freesync->opts.min_refresh_from_edid * - 1000000; - caps->max_refresh_in_micro_hz = - nom_refresh_rate_micro_hz; - } + nom_refresh_rate_uhz = (unsigned int) temp; core_freesync->map[core_freesync->num_entities].stream = stream; core_freesync->map[core_freesync->num_entities].caps = caps; @@ -311,8 +313,8 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, } if (caps->supported && - nom_refresh_rate_micro_hz >= caps->min_refresh_in_micro_hz && - nom_refresh_rate_micro_hz <= caps->max_refresh_in_micro_hz) + nom_refresh_rate_uhz >= caps->min_refresh_in_micro_hz && + nom_refresh_rate_uhz <= caps->max_refresh_in_micro_hz) core_stream->public.ignore_msa_timing_param = 1; core_freesync->num_entities++; @@ -865,6 +867,11 @@ void mod_freesync_update_state(struct mod_freesync *mod_freesync, unsigned int map_index = map_index_from_stream(core_freesync, streams[stream_index]); + bool is_embedded = dc_is_embedded_signal( + streams[stream_index]->sink->sink_signal); + + struct freesync_registry_options *opts = &core_freesync->opts; + state = &core_freesync->map[map_index].state; switch (freesync_params->state){ @@ -875,25 +882,24 @@ void mod_freesync_update_state(struct mod_freesync *mod_freesync, freesync_params->windowed_fullscreen; break; case FREESYNC_STATE_STATIC_SCREEN: - /* Static screen ramp is only enabled for embedded - * panels. Also change core variables only if there - * is a change. + /* Static screen ramp is disabled by default, but can + * be enabled through regkey. */ - if ((dc_is_embedded_signal( - streams[stream_index]->sink->sink_signal) || - core_freesync->map[map_index].caps-> - no_static_for_external_dp == false) && - state->static_screen != - freesync_params->enable) { + if ((is_embedded && opts->drr_internal_supported) || + (!is_embedded && opts->drr_external_supported)) - /* Change the state flag */ - state->static_screen = freesync_params->enable; + if (state->static_screen != + freesync_params->enable) { - /* Change static screen ramp variables */ - set_static_ramp_variables(core_freesync, + /* Change the state flag */ + state->static_screen = + freesync_params->enable; + + /* Update static screen ramp */ + set_static_ramp_variables(core_freesync, map_index, freesync_params->enable); - } + } /* We program the ramp starting next VUpdate */ break; case FREESYNC_STATE_VIDEO: diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h index eae1b348b0dd..53c428b97902 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h @@ -88,7 +88,6 @@ struct mod_freesync_caps { unsigned int max_refresh_in_micro_hz; bool btr_supported; - bool no_static_for_external_dp; }; struct mod_freesync_params { -- cgit v1.2.3 From 4fa086b9b6640818c053c79d4d7104790ba76cb7 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Tue, 25 Jul 2017 20:51:26 -0400 Subject: drm/amd/display: Roll core_stream into dc_stream Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 10 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h | 2 +- drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 16 +- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 92 ++++---- drivers/gpu/drm/amd/display/dc/core/dc.c | 107 ++++----- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 41 ++-- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 7 +- drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 259 ++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 118 +++++----- drivers/gpu/drm/amd/display/dc/dc.h | 71 +++--- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 10 +- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 2 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 12 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 176 +++++++------- .../drm/amd/display/dc/dce110/dce110_resource.c | 46 ++-- .../drm/amd/display/dc/dce112/dce112_resource.c | 16 +- .../drm/amd/display/dc/dce112/dce112_resource.h | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 12 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 72 +++--- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 36 +-- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 33 +-- drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 4 +- .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 3 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/resource.h | 14 +- .../amd/display/dc/virtual/virtual_link_encoder.c | 2 +- .../drm/amd/display/modules/freesync/freesync.c | 60 +++-- .../gpu/drm/amd/display/modules/inc/mod_freesync.h | 28 +-- 31 files changed, 612 insertions(+), 649 deletions(-) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 696a4112c8d9..c802437f4858 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1401,7 +1401,7 @@ static int amdgpu_notify_freesync(struct drm_device *dev, void *data, num_streams = dc_get_current_stream_count(adev->dm.dc); for (i = 0; i < num_streams; i++) { - const struct dc_stream *stream; + struct dc_stream *stream; stream = dc_get_stream_at_index(adev->dm.dc, i); mod_freesync_update_state(adev->dm.freesync_module, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 0fcd9b373172..80d4e2670cc2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -2196,7 +2196,7 @@ static bool is_scaling_state_different( static void remove_stream( struct amdgpu_device *adev, struct amdgpu_crtc *acrtc, - const struct dc_stream *stream) + struct dc_stream *stream) { /* this is the update mode case */ if (adev->dm.freesync_module) @@ -2351,7 +2351,7 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, uint32_t i; struct drm_plane *plane; struct drm_plane_state *old_plane_state; - const struct dc_stream *dc_stream_attach; + struct dc_stream *dc_stream_attach; struct dc_surface *dc_surfaces_constructed[MAX_SURFACES]; struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state); @@ -2487,7 +2487,7 @@ void amdgpu_dm_atomic_commit_tail( struct drm_crtc *crtc, *pcrtc; struct drm_crtc_state *old_crtc_state; struct amdgpu_crtc *new_crtcs[MAX_STREAMS]; - const struct dc_stream *new_stream; + struct dc_stream *new_stream = NULL; unsigned long flags; bool wait_for_vblank = true; struct drm_connector *connector; @@ -2822,8 +2822,8 @@ static uint32_t add_val_sets_surface( static uint32_t update_in_val_sets_stream( struct dc_validation_set *val_sets, uint32_t set_count, - const struct dc_stream *old_stream, - const struct dc_stream *new_stream, + struct dc_stream *old_stream, + struct dc_stream *new_stream, struct drm_crtc *crtc) { uint32_t i = 0; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h index c565787cd782..94de6a3736fc 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h @@ -45,7 +45,7 @@ struct dm_plane_state { struct dm_crtc_state { struct drm_crtc_state base; - const struct dc_stream *stream; + struct dc_stream *stream; }; #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c index 5ef44ff4bcf8..9a850227eeeb 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c @@ -2610,9 +2610,9 @@ static void populate_initial_data( data->fbc_en[num_displays + 4] = false; data->lpt_en[num_displays + 4] = false; - data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.h_total); - data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.v_total); - data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->public.timing.pix_clk_khz, 1000); + data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total); + data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total); + data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_khz, 1000); data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.width); data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4]; data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.height); @@ -2707,9 +2707,9 @@ static void populate_initial_data( data->fbc_en[num_displays + 4] = false; data->lpt_en[num_displays + 4] = false; - data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.h_total); - data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.v_total); - data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->public.timing.pix_clk_khz, 1000); + data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total); + data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total); + data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_khz, 1000); if (pipe[i].surface) { data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.width); data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4]; @@ -2759,9 +2759,9 @@ static void populate_initial_data( break; } } else { - data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.h_addressable); + data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_addressable); data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4]; - data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.v_addressable); + data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_addressable); data->h_taps[num_displays + 4] = bw_int_to_fixed(1); data->v_taps[num_displays + 4] = bw_int_to_fixed(1); data->h_scale_ratio[num_displays + 4] = bw_int_to_fixed(1); diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 1651b7548d40..ef10a8b49379 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -365,7 +365,7 @@ static void pipe_ctx_to_e2e_pipe_params ( } - input->dest.vactive = pipe->stream->public.timing.v_addressable; + input->dest.vactive = pipe->stream->timing.v_addressable; input->dest.recout_width = pipe->scl_data.recout.width; input->dest.recout_height = pipe->scl_data.recout.height; @@ -373,24 +373,24 @@ static void pipe_ctx_to_e2e_pipe_params ( input->dest.full_recout_width = pipe->scl_data.recout.width; input->dest.full_recout_height = pipe->scl_data.recout.height; - input->dest.htotal = pipe->stream->public.timing.h_total; - input->dest.hblank_start = input->dest.htotal - pipe->stream->public.timing.h_front_porch; + input->dest.htotal = pipe->stream->timing.h_total; + input->dest.hblank_start = input->dest.htotal - pipe->stream->timing.h_front_porch; input->dest.hblank_end = input->dest.hblank_start - - pipe->stream->public.timing.h_addressable - - pipe->stream->public.timing.h_border_left - - pipe->stream->public.timing.h_border_right; + - pipe->stream->timing.h_addressable + - pipe->stream->timing.h_border_left + - pipe->stream->timing.h_border_right; - input->dest.vtotal = pipe->stream->public.timing.v_total; - input->dest.vblank_start = input->dest.vtotal - pipe->stream->public.timing.v_front_porch; + input->dest.vtotal = pipe->stream->timing.v_total; + input->dest.vblank_start = input->dest.vtotal - pipe->stream->timing.v_front_porch; input->dest.vblank_end = input->dest.vblank_start - - pipe->stream->public.timing.v_addressable - - pipe->stream->public.timing.v_border_bottom - - pipe->stream->public.timing.v_border_top; - - input->dest.vsync_plus_back_porch = pipe->stream->public.timing.v_total - - pipe->stream->public.timing.v_addressable - - pipe->stream->public.timing.v_front_porch; - input->dest.pixel_rate_mhz = pipe->stream->public.timing.pix_clk_khz/1000.0; + - pipe->stream->timing.v_addressable + - pipe->stream->timing.v_border_bottom + - pipe->stream->timing.v_border_top; + + input->dest.vsync_plus_back_porch = pipe->stream->timing.v_total + - pipe->stream->timing.v_addressable + - pipe->stream->timing.v_front_porch; + input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_khz/1000.0; input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start; input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; @@ -851,14 +851,14 @@ bool dcn_validate_bandwidth( v->underscan_output[input_idx] = false; /* taken care of in recout already*/ v->interlace_output[input_idx] = false; - v->htotal[input_idx] = pipe->stream->public.timing.h_total; - v->vtotal[input_idx] = pipe->stream->public.timing.v_total; - v->v_sync_plus_back_porch[input_idx] = pipe->stream->public.timing.v_total - - pipe->stream->public.timing.v_addressable - - pipe->stream->public.timing.v_front_porch; - v->vactive[input_idx] = pipe->stream->public.timing.v_addressable; - v->pixel_clock[input_idx] = pipe->stream->public.timing.pix_clk_khz / 1000.0f; - if (pipe->stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) + v->htotal[input_idx] = pipe->stream->timing.h_total; + v->vtotal[input_idx] = pipe->stream->timing.v_total; + v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total + - pipe->stream->timing.v_addressable + - pipe->stream->timing.v_front_porch; + v->vactive[input_idx] = pipe->stream->timing.v_addressable; + v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_khz / 1000.0f; + if (pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) v->pixel_clock[input_idx] /= 2; @@ -867,10 +867,10 @@ bool dcn_validate_bandwidth( v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32; v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s; v->lb_bit_per_pixel[input_idx] = 30; - v->viewport_width[input_idx] = pipe->stream->public.timing.h_addressable; - v->viewport_height[input_idx] = pipe->stream->public.timing.v_addressable; - v->scaler_rec_out_width[input_idx] = pipe->stream->public.timing.h_addressable; - v->scaler_recout_height[input_idx] = pipe->stream->public.timing.v_addressable; + v->viewport_width[input_idx] = pipe->stream->timing.h_addressable; + v->viewport_height[input_idx] = pipe->stream->timing.v_addressable; + v->scaler_rec_out_width[input_idx] = pipe->stream->timing.h_addressable; + v->scaler_recout_height[input_idx] = pipe->stream->timing.v_addressable; v->override_hta_ps[input_idx] = 1; v->override_vta_ps[input_idx] = 1; v->override_hta_pschroma[input_idx] = 1; @@ -995,22 +995,22 @@ bool dcn_validate_bandwidth( pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx]; pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; - pipe->pipe_dlg_param.htotal = pipe->stream->public.timing.h_total; - pipe->pipe_dlg_param.vtotal = pipe->stream->public.timing.v_total; - vesa_sync_start = pipe->stream->public.timing.v_addressable + - pipe->stream->public.timing.v_border_bottom + - pipe->stream->public.timing.v_front_porch; + pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; + pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; + vesa_sync_start = pipe->stream->timing.v_addressable + + pipe->stream->timing.v_border_bottom + + pipe->stream->timing.v_front_porch; - asic_blank_end = (pipe->stream->public.timing.v_total - + asic_blank_end = (pipe->stream->timing.v_total - vesa_sync_start - - pipe->stream->public.timing.v_border_top) - * (pipe->stream->public.timing.flags.INTERLACE ? 1 : 0); + pipe->stream->timing.v_border_top) + * (pipe->stream->timing.flags.INTERLACE ? 1 : 0); asic_blank_start = asic_blank_end + - (pipe->stream->public.timing.v_border_top + - pipe->stream->public.timing.v_addressable + - pipe->stream->public.timing.v_border_bottom) - * (pipe->stream->public.timing.flags.INTERLACE ? 1 : 0); + (pipe->stream->timing.v_border_top + + pipe->stream->timing.v_addressable + + pipe->stream->timing.v_border_bottom) + * (pipe->stream->timing.flags.INTERLACE ? 1 : 0); pipe->pipe_dlg_param.vblank_start = asic_blank_start; pipe->pipe_dlg_param.vblank_end = asic_blank_end; @@ -1019,13 +1019,13 @@ bool dcn_validate_bandwidth( struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; if (v->dpp_per_plane[input_idx] == 2 || - ((pipe->stream->public.view_format == + ((pipe->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE || - pipe->stream->public.view_format == + pipe->stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) && - (pipe->stream->public.timing.timing_3d_format == + (pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM || - pipe->stream->public.timing.timing_3d_format == + pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE))) { if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) { /* update previously split pipe */ @@ -1034,8 +1034,8 @@ bool dcn_validate_bandwidth( hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx]; hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; - hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->public.timing.h_total; - hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->public.timing.v_total; + hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; + hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start; hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end; } else { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index bab07f8d4880..df8c5ca6b22a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -149,19 +149,19 @@ failed_alloc: } static bool stream_adjust_vmin_vmax(struct dc *dc, - const struct dc_stream **stream, int num_streams, + struct dc_stream **streams, int num_streams, int vmin, int vmax) { /* TODO: Support multiple streams */ struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]); + struct dc_stream *stream = streams[0]; int i = 0; bool ret = false; for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe = &core_dc->current_context->res_ctx.pipe_ctx[i]; - if (pipe->stream == core_stream && pipe->stream_enc) { + if (pipe->stream == stream && pipe->stream_enc) { core_dc->hwss.set_drr(&pipe, 1, vmin, vmax); /* build and update the info frame */ @@ -175,12 +175,12 @@ static bool stream_adjust_vmin_vmax(struct dc *dc, } static bool stream_get_crtc_position(struct dc *dc, - const struct dc_stream **stream, int num_streams, + struct dc_stream **streams, int num_streams, unsigned int *v_pos, unsigned int *nom_v_pos) { /* TODO: Support multiple streams */ struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]); + struct dc_stream *stream = streams[0]; int i = 0; bool ret = false; struct crtc_position position; @@ -189,7 +189,7 @@ static bool stream_get_crtc_position(struct dc *dc, struct pipe_ctx *pipe = &core_dc->current_context->res_ctx.pipe_ctx[i]; - if (pipe->stream == core_stream && pipe->stream_enc) { + if (pipe->stream == stream && pipe->stream_enc) { core_dc->hwss.get_position(&pipe, 1, &position); *v_pos = position.vertical_count; @@ -203,15 +203,12 @@ static bool stream_get_crtc_position(struct dc *dc, static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); int i = 0; bool ret = false; struct pipe_ctx *pipes; for (i = 0; i < MAX_PIPES; i++) { - if (core_dc->current_context->res_ctx.pipe_ctx[i].stream - == core_stream) { - + if (core_dc->current_context->res_ctx.pipe_ctx[i].stream == stream) { pipes = &core_dc->current_context->res_ctx.pipe_ctx[i]; core_dc->hwss.program_gamut_remap(pipes); ret = true; @@ -221,22 +218,21 @@ static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream) return ret; } -static bool program_csc_matrix(struct dc *dc, const struct dc_stream *stream) +static bool program_csc_matrix(struct dc *dc, struct dc_stream *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); int i = 0; bool ret = false; struct pipe_ctx *pipes; for (i = 0; i < MAX_PIPES; i++) { if (core_dc->current_context->res_ctx.pipe_ctx[i].stream - == core_stream) { + == stream) { pipes = &core_dc->current_context->res_ctx.pipe_ctx[i]; core_dc->hwss.program_csc_matrix(pipes, - core_stream->public.output_color_space, - core_stream->public.csc_color_matrix.matrix); + stream->output_color_space, + stream->csc_color_matrix.matrix); ret = true; } } @@ -245,7 +241,7 @@ static bool program_csc_matrix(struct dc *dc, const struct dc_stream *stream) } static void set_static_screen_events(struct dc *dc, - const struct dc_stream **stream, + struct dc_stream **streams, int num_streams, const struct dc_static_screen_events *events) { @@ -256,11 +252,11 @@ static void set_static_screen_events(struct dc *dc, int num_pipes_affected = 0; for (i = 0; i < num_streams; i++) { - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[i]); + struct dc_stream *stream = streams[i]; for (j = 0; j < MAX_PIPES; j++) { if (core_dc->current_context->res_ctx.pipe_ctx[j].stream - == core_stream) { + == stream) { pipes_affected[num_pipes_affected++] = &core_dc->current_context->res_ctx.pipe_ctx[j]; } @@ -337,10 +333,9 @@ static void set_test_pattern( cust_pattern_size); } -void set_dither_option(const struct dc_stream *dc_stream, +void set_dither_option(struct dc_stream *stream, enum dc_dither_option option) { - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct bit_depth_reduction_params params; struct dc_link *link = stream->status.link; struct pipe_ctx *pipes = link->dc->current_context->res_ctx.pipe_ctx; @@ -351,21 +346,21 @@ void set_dither_option(const struct dc_stream *dc_stream, if (option > DITHER_OPTION_MAX) return; if (option == DITHER_OPTION_DEFAULT) { - switch (stream->public.timing.display_color_depth) { + switch (stream->timing.display_color_depth) { case COLOR_DEPTH_666: - stream->public.dither_option = DITHER_OPTION_SPATIAL6; + stream->dither_option = DITHER_OPTION_SPATIAL6; break; case COLOR_DEPTH_888: - stream->public.dither_option = DITHER_OPTION_SPATIAL8; + stream->dither_option = DITHER_OPTION_SPATIAL8; break; case COLOR_DEPTH_101010: - stream->public.dither_option = DITHER_OPTION_SPATIAL10; + stream->dither_option = DITHER_OPTION_SPATIAL10; break; default: option = DITHER_OPTION_DISABLE; } } else { - stream->public.dither_option = option; + stream->dither_option = option; } resource_build_bit_depth_reduction_params(stream, ¶ms); @@ -644,7 +639,7 @@ static bool is_validation_required( if (set[i].surface_count != context->stream_status[i].surface_count) return true; - if (!is_stream_unchanged(DC_STREAM_TO_CORE(set[i].stream), context->streams[i])) + if (!is_stream_unchanged(set[i].stream, context->streams[i])) return true; for (j = 0; j < set[i].surface_count; j++) { @@ -754,7 +749,7 @@ context_alloc_fail: bool dc_validate_guaranteed( const struct dc *dc, - const struct dc_stream *stream) + struct dc_stream *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); enum dc_status result = DC_ERROR_UNEXPECTED; @@ -869,7 +864,7 @@ static bool context_changed( return true; for (i = 0; i < dc->current_context->stream_count; i++) { - if (&dc->current_context->streams[i]->public != &context->streams[i]->public) + if (dc->current_context->streams[i] != context->streams[i]) return true; } @@ -878,7 +873,7 @@ static bool context_changed( static bool streams_changed( struct core_dc *dc, - const struct dc_stream *streams[], + struct dc_stream *streams[], uint8_t stream_count) { uint8_t i; @@ -887,7 +882,7 @@ static bool streams_changed( return true; for (i = 0; i < dc->current_context->stream_count; i++) { - if (&dc->current_context->streams[i]->public != streams[i]) + if (dc->current_context->streams[i] != streams[i]) return true; } @@ -897,7 +892,7 @@ static bool streams_changed( bool dc_enable_stereo( struct dc *dc, struct validate_context *context, - const struct dc_stream *streams[], + struct dc_stream *streams[], uint8_t stream_count) { bool ret = true; @@ -915,7 +910,7 @@ bool dc_enable_stereo( else pipe = &core_dc->current_context->res_ctx.pipe_ctx[i]; for (j = 0 ; pipe && j < stream_count; j++) { - if (streams[j] && streams[j] == &pipe->stream->public && + if (streams[j] && streams[j] == pipe->stream && core_dc->hwss.setup_stereo) core_dc->hwss.setup_stereo(pipe, core_dc); } @@ -943,10 +938,10 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c enum dc_status result = DC_ERROR_UNEXPECTED; struct pipe_ctx *pipe; int i, j, k, l; - const struct dc_stream *dc_streams[MAX_STREAMS] = {0}; + struct dc_stream *dc_streams[MAX_STREAMS] = {0}; for (i = 0; i < context->stream_count; i++) - dc_streams[i] = &context->streams[i]->public; + dc_streams[i] = context->streams[i]; if (!dcb->funcs->is_accelerated_mode(dcb)) core_dc->hwss.enable_accelerated_mode(core_dc); @@ -985,11 +980,11 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c } CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}", - context->streams[i]->public.timing.h_addressable, - context->streams[i]->public.timing.v_addressable, - context->streams[i]->public.timing.h_total, - context->streams[i]->public.timing.v_total, - context->streams[i]->public.timing.pix_clk_khz); + context->streams[i]->timing.h_addressable, + context->streams[i]->timing.v_addressable, + context->streams[i]->timing.h_total, + context->streams[i]->timing.v_total, + context->streams[i]->timing.pix_clk_khz); } dc_enable_stereo(dc, context, dc_streams, context->stream_count); @@ -1016,7 +1011,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context) __func__, context->stream_count); for (i = 0; i < context->stream_count; i++) { - const struct dc_stream *stream = &context->streams[i]->public; + struct dc_stream *stream = context->streams[i]; dc_stream_log(stream, core_dc->ctx->logger, @@ -1031,7 +1026,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context) bool dc_commit_streams( struct dc *dc, - const struct dc_stream *streams[], + struct dc_stream *streams[], uint8_t stream_count) { struct core_dc *core_dc = DC_TO_CORE(dc); @@ -1047,8 +1042,8 @@ bool dc_commit_streams( __func__, stream_count); for (i = 0; i < stream_count; i++) { - const struct dc_stream *stream = streams[i]; - const struct dc_stream_status *status = dc_stream_get_status(stream); + struct dc_stream *stream = streams[i]; + struct dc_stream_status *status = dc_stream_get_status(stream); int j; dc_stream_log(stream, @@ -1120,7 +1115,7 @@ bool dc_commit_surfaces_to_stream( struct dc *dc, struct dc_surface **new_surfaces, uint8_t new_surface_count, - const struct dc_stream *dc_stream) + struct dc_stream *dc_stream) { struct dc_surface_update updates[MAX_SURFACES]; struct dc_flip_addrs flip_addr[MAX_SURFACES]; @@ -1377,7 +1372,7 @@ enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL; void dc_update_surfaces_and_stream(struct dc *dc, struct dc_surface_update *srf_updates, int surface_count, - const struct dc_stream *dc_stream, + struct dc_stream *stream, struct dc_stream_update *stream_update) { struct core_dc *core_dc = DC_TO_CORE(dc); @@ -1385,7 +1380,6 @@ void dc_update_surfaces_and_stream(struct dc *dc, int i, j; enum surface_update_type update_type; const struct dc_stream_status *stream_status; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct dc_context *dc_ctx = core_dc->ctx; /* Currently this function do not result in any HW programming @@ -1398,7 +1392,8 @@ void dc_update_surfaces_and_stream(struct dc *dc, if (surface_count == 0) return; - stream_status = dc_stream_get_status(dc_stream); + stream_status = dc_stream_get_status(stream); + ASSERT(stream_status); if (!stream_status) return; /* Cannot commit surface to stream that is not committed */ @@ -1415,19 +1410,19 @@ void dc_update_surfaces_and_stream(struct dc *dc, if (stream_update) { if ((stream_update->src.height != 0) && (stream_update->src.width != 0)) - stream->public.src = stream_update->src; + stream->src = stream_update->src; if ((stream_update->dst.height != 0) && (stream_update->dst.width != 0)) - stream->public.dst = stream_update->dst; + stream->dst = stream_update->dst; if (stream_update->out_transfer_func && stream_update->out_transfer_func != - dc_stream->out_transfer_func) { - if (dc_stream->out_transfer_func != NULL) - dc_transfer_func_release(dc_stream->out_transfer_func); + stream->out_transfer_func) { + if (stream->out_transfer_func != NULL) + dc_transfer_func_release(stream->out_transfer_func); dc_transfer_func_retain(stream_update->out_transfer_func); - stream->public.out_transfer_func = + stream->out_transfer_func = stream_update->out_transfer_func; } } @@ -1469,7 +1464,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* add surface to context */ if (!resource_attach_surfaces_to_context( - new_surfaces, surface_count, dc_stream, + new_surfaces, surface_count, stream, context, core_dc->res_pool)) { BREAK_TO_DEBUGGER(); goto fail; @@ -1617,7 +1612,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, core_dc, pipe_ctx->surface, context); /* TODO: this is a hack w/a for switching from mpo to pipe split */ - dc_stream_set_cursor_position(&pipe_ctx->stream->public, &position); + dc_stream_set_cursor_position(pipe_ctx->stream, &position); if (is_new_pipe_surface) { core_dc->hwss.update_plane_addr(core_dc, pipe_ctx); @@ -1712,7 +1707,7 @@ struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i) { struct core_dc *core_dc = DC_TO_CORE(dc); if (i < core_dc->current_context->stream_count) - return &(core_dc->current_context->streams[i]->public); + return core_dc->current_context->streams[i]; return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index 9a5df3a848b5..bf127a88e533 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -321,8 +321,8 @@ void context_timing_trace( TIMING_TRACE("OTG_%d H_tot:%d V_tot:%d H_pos:%d V_pos:%d\n", pipe_ctx->tg->inst, - pipe_ctx->stream->public.timing.h_total, - pipe_ctx->stream->public.timing.v_total, + pipe_ctx->stream->timing.h_total, + pipe_ctx->stream->timing.v_total, h_pos[i], v_pos[i]); } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index fd2ae181cff2..2487046457c8 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1143,7 +1143,7 @@ static void dpcd_configure_panel_mode( static void enable_stream_features(struct pipe_ctx *pipe_ctx) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; union down_spread_ctrl downspread; @@ -1151,7 +1151,7 @@ static void enable_stream_features(struct pipe_ctx *pipe_ctx) &downspread.raw, sizeof(downspread)); downspread.bits.IGNORE_MSA_TIMING_PARAM = - (stream->public.ignore_msa_timing_param) ? 1 : 0; + (stream->ignore_msa_timing_param) ? 1 : 0; core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, &downspread.raw, sizeof(downspread)); @@ -1159,7 +1159,7 @@ static void enable_stream_features(struct pipe_ctx *pipe_ctx) static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; enum dc_status status; bool skip_video_pattern; struct dc_link *link = stream->sink->link; @@ -1250,7 +1250,7 @@ static enum dc_status enable_link_dp_mst(struct pipe_ctx *pipe_ctx) static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; enum dc_color_depth display_color_depth; @@ -1258,13 +1258,13 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) dal_ddc_service_write_scdc_data( stream->sink->link->ddc, stream->phy_pix_clk, - stream->public.timing.flags.LTE_340MCSC_SCRAMBLE); + stream->timing.flags.LTE_340MCSC_SCRAMBLE); memset(&stream->sink->link->cur_link_settings, 0, sizeof(struct dc_link_settings)); - display_color_depth = stream->public.timing.display_color_depth; - if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) + display_color_depth = stream->timing.display_color_depth; + if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) display_color_depth = COLOR_DEPTH_888; link->link_enc->funcs->enable_tmds_output( @@ -1341,7 +1341,7 @@ static void disable_link(struct dc_link *link, enum signal_type signal) } enum dc_status dc_link_validate_mode_timing( - const struct core_stream *stream, + const struct dc_stream *stream, struct dc_link *link, const struct dc_crtc_timing *timing) { @@ -1377,7 +1377,6 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, uint32_t frame_ramp, const struct dc_stream *stream) { struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); - struct core_stream *core_stream = NULL; struct abm *abm = core_dc->res_pool->abm; unsigned int controller_id = 0; int i; @@ -1390,11 +1389,10 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, if (dc_is_embedded_signal(link->connector_signal)) { if (stream != NULL) { - core_stream = DC_STREAM_TO_CORE(stream); for (i = 0; i < MAX_PIPES; i++) { if (core_dc->current_context->res_ctx. pipe_ctx[i].stream - == core_stream) + == stream) /* DMCU -1 for all controller id values, * therefore +1 here */ @@ -1457,7 +1455,6 @@ bool dc_link_setup_psr(struct dc_link *link, { struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); struct dmcu *dmcu = core_dc->res_pool->dmcu; - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); int i; psr_context->controllerId = CONTROLLER_ID_UNDEFINED; @@ -1501,7 +1498,7 @@ bool dc_link_setup_psr(struct dc_link *link, for (i = 0; i < MAX_PIPES; i++) { if (core_dc->current_context->res_ctx.pipe_ctx[i].stream - == core_stream) { + == stream) { /* dmcu -1 for all controller id values, * therefore +1 here */ @@ -1590,7 +1587,7 @@ void core_link_resume(struct dc_link *link) program_hpd_filter(link); } -static struct fixed31_32 get_pbn_per_slot(struct core_stream *stream) +static struct fixed31_32 get_pbn_per_slot(struct dc_stream *stream) { struct dc_link_settings *link_settings = &stream->sink->link->cur_link_settings; @@ -1699,7 +1696,7 @@ static void update_mst_stream_alloc_table( */ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; struct link_encoder *link_encoder = link->link_enc; struct stream_encoder *stream_encoder = pipe_ctx->stream_enc; @@ -1717,7 +1714,7 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) /* get calculate VC payload for stream: stream_alloc */ if (dm_helpers_dp_mst_write_payload_allocation_table( stream->ctx, - &stream->public, + stream, &proposed_table, true)) { update_mst_stream_alloc_table( @@ -1759,11 +1756,11 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) /* send down message */ dm_helpers_dp_mst_poll_for_allocation_change_trigger( stream->ctx, - &stream->public); + stream); dm_helpers_dp_mst_send_payload_allocation( stream->ctx, - &stream->public, + stream, true); /* slot X.Y for only current stream */ @@ -1781,7 +1778,7 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; struct link_encoder *link_encoder = link->link_enc; struct stream_encoder *stream_encoder = pipe_ctx->stream_enc; @@ -1806,7 +1803,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) if (mst_mode) { if (dm_helpers_dp_mst_write_payload_allocation_table( stream->ctx, - &stream->public, + stream, &proposed_table, false)) { @@ -1848,11 +1845,11 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) if (mst_mode) { dm_helpers_dp_mst_poll_for_allocation_change_trigger( stream->ctx, - &stream->public); + stream); dm_helpers_dp_mst_send_payload_allocation( stream->ctx, - &stream->public, + stream, false); } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index c7b400786121..d9754b5f2543 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -1434,7 +1434,7 @@ bool dp_validate_mode_timing( return false; } -void decide_link_settings(struct core_stream *stream, +void decide_link_settings(struct dc_stream *stream, struct dc_link_settings *link_setting) { @@ -1446,8 +1446,7 @@ void decide_link_settings(struct core_stream *stream, uint32_t req_bw; uint32_t link_bw; - req_bw = bandwidth_in_kbps_from_timing( - &stream->public.timing); + req_bw = bandwidth_in_kbps_from_timing(&stream->timing); link = stream->sink->link; @@ -2327,7 +2326,7 @@ static void set_crtc_test_pattern(struct dc_link *link, { enum controller_dp_test_pattern controller_test_pattern; enum dc_color_depth color_depth = pipe_ctx-> - stream->public.timing.display_color_depth; + stream->timing.display_color_depth; struct bit_depth_reduction_params params; memset(¶ms, 0, sizeof(params)); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index 5bdcd5067116..76dc16916821 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -78,7 +78,7 @@ void dp_enable_link_phy( pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { pipes[i].clock_source = dp_cs; pipes[i].pix_clk_params.requested_pix_clk = - pipes[i].stream->public.timing.pix_clk_khz; + pipes[i].stream->timing.pix_clk_khz; pipes[i].clock_source->funcs->program_pix_clk( pipes[i].clock_source, &pipes[i].pix_clk_params, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index eeefc9c33633..ddbd3de63a8d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -294,25 +294,25 @@ void resource_reference_clock_source( } bool resource_are_streams_timing_synchronizable( - const struct core_stream *stream1, - const struct core_stream *stream2) + struct dc_stream *stream1, + struct dc_stream *stream2) { - if (stream1->public.timing.h_total != stream2->public.timing.h_total) + if (stream1->timing.h_total != stream2->timing.h_total) return false; - if (stream1->public.timing.v_total != stream2->public.timing.v_total) + if (stream1->timing.v_total != stream2->timing.v_total) return false; - if (stream1->public.timing.h_addressable - != stream2->public.timing.h_addressable) + if (stream1->timing.h_addressable + != stream2->timing.h_addressable) return false; - if (stream1->public.timing.v_addressable - != stream2->public.timing.v_addressable) + if (stream1->timing.v_addressable + != stream2->timing.v_addressable) return false; - if (stream1->public.timing.pix_clk_khz - != stream2->public.timing.pix_clk_khz) + if (stream1->timing.pix_clk_khz + != stream2->timing.pix_clk_khz) return false; if (stream1->phy_pix_clk != stream2->phy_pix_clk @@ -431,7 +431,7 @@ static void rect_swap_helper(struct rect *rect) static void calculate_viewport(struct pipe_ctx *pipe_ctx) { const struct dc_surface *surface = pipe_ctx->surface; - const struct dc_stream *stream = &pipe_ctx->stream->public; + const struct dc_stream *stream = pipe_ctx->stream; struct scaler_data *data = &pipe_ctx->scl_data; struct rect surf_src = surface->src_rect; struct rect clip = { 0 }; @@ -530,7 +530,7 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip) { const struct dc_surface *surface = pipe_ctx->surface; - struct core_stream *stream = pipe_ctx->stream; + const struct dc_stream *stream = pipe_ctx->stream; struct rect surf_src = surface->src_rect; struct rect surf_clip = surface->clip_rect; int recout_full_x, recout_full_y; @@ -539,38 +539,38 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip pipe_ctx->surface->rotation == ROTATION_ANGLE_270) rect_swap_helper(&surf_src); - pipe_ctx->scl_data.recout.x = stream->public.dst.x; - if (stream->public.src.x < surf_clip.x) + pipe_ctx->scl_data.recout.x = stream->dst.x; + if (stream->src.x < surf_clip.x) pipe_ctx->scl_data.recout.x += (surf_clip.x - - stream->public.src.x) * stream->public.dst.width - / stream->public.src.width; + - stream->src.x) * stream->dst.width + / stream->src.width; pipe_ctx->scl_data.recout.width = surf_clip.width * - stream->public.dst.width / stream->public.src.width; + stream->dst.width / stream->src.width; if (pipe_ctx->scl_data.recout.width + pipe_ctx->scl_data.recout.x > - stream->public.dst.x + stream->public.dst.width) + stream->dst.x + stream->dst.width) pipe_ctx->scl_data.recout.width = - stream->public.dst.x + stream->public.dst.width + stream->dst.x + stream->dst.width - pipe_ctx->scl_data.recout.x; - pipe_ctx->scl_data.recout.y = stream->public.dst.y; - if (stream->public.src.y < surf_clip.y) + pipe_ctx->scl_data.recout.y = stream->dst.y; + if (stream->src.y < surf_clip.y) pipe_ctx->scl_data.recout.y += (surf_clip.y - - stream->public.src.y) * stream->public.dst.height - / stream->public.src.height; + - stream->src.y) * stream->dst.height + / stream->src.height; pipe_ctx->scl_data.recout.height = surf_clip.height * - stream->public.dst.height / stream->public.src.height; + stream->dst.height / stream->src.height; if (pipe_ctx->scl_data.recout.height + pipe_ctx->scl_data.recout.y > - stream->public.dst.y + stream->public.dst.height) + stream->dst.y + stream->dst.height) pipe_ctx->scl_data.recout.height = - stream->public.dst.y + stream->public.dst.height + stream->dst.y + stream->dst.height - pipe_ctx->scl_data.recout.y; /* Handle h & vsplit */ if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface) { - if (stream->public.view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { + if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { pipe_ctx->scl_data.recout.height /= 2; pipe_ctx->scl_data.recout.y += pipe_ctx->scl_data.recout.height; /* Floor primary pipe, ceil 2ndary pipe */ @@ -582,7 +582,7 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip } } else if (pipe_ctx->bottom_pipe && pipe_ctx->bottom_pipe->surface == pipe_ctx->surface) { - if (stream->public.view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) + if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) pipe_ctx->scl_data.recout.height /= 2; else pipe_ctx->scl_data.recout.width /= 2; @@ -592,14 +592,14 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip * * 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl * ratio) */ - recout_full_x = stream->public.dst.x + (surface->dst_rect.x - stream->public.src.x) - * stream->public.dst.width / stream->public.src.width - + recout_full_x = stream->dst.x + (surface->dst_rect.x - stream->src.x) + * stream->dst.width / stream->src.width - surf_src.x * surface->dst_rect.width / surf_src.width - * stream->public.dst.width / stream->public.src.width; - recout_full_y = stream->public.dst.y + (surface->dst_rect.y - stream->public.src.y) - * stream->public.dst.height / stream->public.src.height - + * stream->dst.width / stream->src.width; + recout_full_y = stream->dst.y + (surface->dst_rect.y - stream->src.y) + * stream->dst.height / stream->src.height - surf_src.y * surface->dst_rect.height / surf_src.height - * stream->public.dst.height / stream->public.src.height; + * stream->dst.height / stream->src.height; recout_skip->width = pipe_ctx->scl_data.recout.x - recout_full_x; recout_skip->height = pipe_ctx->scl_data.recout.y - recout_full_y; @@ -608,12 +608,12 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) { const struct dc_surface *surface = pipe_ctx->surface; - struct core_stream *stream = pipe_ctx->stream; + const struct dc_stream *stream = pipe_ctx->stream; struct rect surf_src = surface->src_rect; - const int in_w = stream->public.src.width; - const int in_h = stream->public.src.height; - const int out_w = stream->public.dst.width; - const int out_h = stream->public.dst.height; + const int in_w = stream->src.width; + const int in_h = stream->src.height; + const int out_w = stream->dst.width; + const int out_h = stream->dst.height; if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 || pipe_ctx->surface->rotation == ROTATION_ANGLE_270) @@ -626,9 +626,9 @@ static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) surf_src.height, surface->dst_rect.height); - if (stream->public.view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) + if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) pipe_ctx->scl_data.ratios.horz.value *= 2; - else if (stream->public.view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) + else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) pipe_ctx->scl_data.ratios.vert.value *= 2; pipe_ctx->scl_data.ratios.vert.value = div64_s64( @@ -815,7 +815,7 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) { const struct dc_surface *surface = pipe_ctx->surface; - struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing; + struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; struct view recout_skip = { 0 }; bool res = false; @@ -920,7 +920,7 @@ struct pipe_ctx *find_idle_secondary_pipe( struct pipe_ctx *resource_get_head_pipe_for_stream( struct resource_context *res_ctx, - const struct core_stream *stream) + struct dc_stream *stream) { int i; for (i = 0; i < MAX_PIPES; i++) { @@ -940,11 +940,10 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( static struct pipe_ctx *acquire_free_pipe_for_stream( struct validate_context *context, const struct resource_pool *pool, - const struct dc_stream *dc_stream) + struct dc_stream *stream) { int i; struct resource_context *res_ctx = &context->res_ctx; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct pipe_ctx *head_pipe = NULL; @@ -980,10 +979,9 @@ static struct pipe_ctx *acquire_free_pipe_for_stream( static void release_free_pipes_for_stream( struct resource_context *res_ctx, - const struct dc_stream *dc_stream) + struct dc_stream *stream) { int i; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); for (i = MAX_PIPES - 1; i >= 0; i--) { /* never release the topmost pipe*/ @@ -999,7 +997,7 @@ static void release_free_pipes_for_stream( static int acquire_first_split_pipe( struct resource_context *res_ctx, const struct resource_pool *pool, - struct core_stream *stream) + struct dc_stream *stream) { int i; @@ -1033,14 +1031,13 @@ static int acquire_first_split_pipe( bool resource_attach_surfaces_to_context( struct dc_surface * const *surfaces, int surface_count, - const struct dc_stream *dc_stream, + struct dc_stream *stream, struct validate_context *context, const struct resource_pool *pool) { int i; struct pipe_ctx *tail_pipe; struct dc_stream_status *stream_status = NULL; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); if (surface_count > MAX_SURFACE_NUM) { @@ -1050,7 +1047,7 @@ bool resource_attach_surfaces_to_context( } for (i = 0; i < context->stream_count; i++) - if (&context->streams[i]->public == dc_stream) { + if (context->streams[i] == stream) { stream_status = &context->stream_status[i]; break; } @@ -1081,7 +1078,7 @@ bool resource_attach_surfaces_to_context( for (i = 0; i < surface_count; i++) { struct dc_surface *surface = surfaces[i]; struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream( - context, pool, dc_stream); + context, pool, stream); #if defined(CONFIG_DRM_AMD_DC_DCN1_0) if (!free_pipe) { @@ -1109,7 +1106,7 @@ bool resource_attach_surfaces_to_context( tail_pipe = free_pipe; } - release_free_pipes_for_stream(&context->res_ctx, dc_stream); + release_free_pipes_for_stream(&context->res_ctx, stream); /* assign new surfaces*/ for (i = 0; i < surface_count; i++) @@ -1121,8 +1118,8 @@ bool resource_attach_surfaces_to_context( } -static bool is_timing_changed(const struct core_stream *cur_stream, - const struct core_stream *new_stream) +static bool is_timing_changed(struct dc_stream *cur_stream, + struct dc_stream *new_stream) { if (cur_stream == NULL) return true; @@ -1134,18 +1131,17 @@ static bool is_timing_changed(const struct core_stream *cur_stream, return true; /* If output color space is changed, need to reprogram info frames */ - if (cur_stream->public.output_color_space != - new_stream->public.output_color_space) + if (cur_stream->output_color_space != new_stream->output_color_space) return true; return memcmp( - &cur_stream->public.timing, - &new_stream->public.timing, + &cur_stream->timing, + &new_stream->timing, sizeof(struct dc_crtc_timing)) != 0; } static bool are_stream_backends_same( - const struct core_stream *stream_a, const struct core_stream *stream_b) + struct dc_stream *stream_a, struct dc_stream *stream_b) { if (stream_a == stream_b) return true; @@ -1160,7 +1156,7 @@ static bool are_stream_backends_same( } bool is_stream_unchanged( - const struct core_stream *old_stream, const struct core_stream *stream) + struct dc_stream *old_stream, struct dc_stream *stream) { if (!are_stream_backends_same(old_stream, stream)) @@ -1186,7 +1182,7 @@ bool resource_validate_attach_surfaces( if (!resource_attach_surfaces_to_context( old_context->stream_status[j].surfaces, old_context->stream_status[j].surface_count, - &context->streams[i]->public, + context->streams[i], context, pool)) return false; context->stream_status[i] = old_context->stream_status[j]; @@ -1195,7 +1191,7 @@ bool resource_validate_attach_surfaces( if (!resource_attach_surfaces_to_context( set[i].surfaces, set[i].surface_count, - &context->streams[i]->public, + context->streams[i], context, pool)) return false; @@ -1237,7 +1233,7 @@ static void set_audio_in_use( static int acquire_first_free_pipe( struct resource_context *res_ctx, const struct resource_pool *pool, - struct core_stream *stream) + struct dc_stream *stream) { int i; @@ -1267,7 +1263,7 @@ static int acquire_first_free_pipe( static struct stream_encoder *find_first_free_match_stream_enc_for_link( struct resource_context *res_ctx, const struct resource_pool *pool, - struct core_stream *stream) + struct dc_stream *stream) { int i; int j = -1; @@ -1318,22 +1314,22 @@ static struct audio *find_first_free_audio( return 0; } -static void update_stream_signal(struct core_stream *stream) +static void update_stream_signal(struct dc_stream *stream) { - if (stream->public.output_signal == SIGNAL_TYPE_NONE) { - struct dc_sink *dc_sink = stream->public.sink; + if (stream->output_signal == SIGNAL_TYPE_NONE) { + struct dc_sink *dc_sink = stream->sink; if (dc_sink->sink_signal == SIGNAL_TYPE_NONE) stream->signal = stream->sink->link->connector_signal; else stream->signal = dc_sink->sink_signal; } else { - stream->signal = stream->public.output_signal; + stream->signal = stream->output_signal; } if (dc_is_dvi_signal(stream->signal)) { - if (stream->public.timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST && - stream->public.sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) + if (stream->timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST && + stream->sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK; else stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK; @@ -1341,12 +1337,12 @@ static void update_stream_signal(struct core_stream *stream) } bool resource_is_stream_unchanged( - const struct validate_context *old_context, const struct core_stream *stream) + struct validate_context *old_context, struct dc_stream *stream) { int i; for (i = 0; i < old_context->stream_count; i++) { - const struct core_stream *old_stream = old_context->streams[i]; + struct dc_stream *old_stream = old_context->streams[i]; if (are_stream_backends_same(old_stream, stream)) return true; @@ -1359,7 +1355,7 @@ static void copy_pipe_ctx( const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx) { struct dc_surface *surface = to_pipe_ctx->surface; - struct core_stream *stream = to_pipe_ctx->stream; + struct dc_stream *stream = to_pipe_ctx->stream; *to_pipe_ctx = *from_pipe_ctx; to_pipe_ctx->stream = stream; @@ -1367,14 +1363,14 @@ static void copy_pipe_ctx( to_pipe_ctx->surface = surface; } -static struct core_stream *find_pll_sharable_stream( - const struct core_stream *stream_needs_pll, +static struct dc_stream *find_pll_sharable_stream( + struct dc_stream *stream_needs_pll, struct validate_context *context) { int i; for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream_has_pll = context->streams[i]; + struct dc_stream *stream_has_pll = context->streams[i]; /* We are looking for non dp, non virtual stream */ if (resource_are_streams_timing_synchronizable( @@ -1418,17 +1414,17 @@ static int get_norm_pix_clk(const struct dc_crtc_timing *timing) return normalized_pix_clk; } -static void calculate_phy_pix_clks(struct core_stream *stream) +static void calculate_phy_pix_clks(struct dc_stream *stream) { update_stream_signal(stream); /* update actual pixel clock on all streams */ if (dc_is_hdmi_signal(stream->signal)) stream->phy_pix_clk = get_norm_pix_clk( - &stream->public.timing); + &stream->timing); else stream->phy_pix_clk = - stream->public.timing.pix_clk_khz; + stream->timing.pix_clk_khz; } enum dc_status resource_map_pool_resources( @@ -1440,7 +1436,7 @@ enum dc_status resource_map_pool_resources( int i, j; for (i = 0; old_context && i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (!resource_is_stream_unchanged(old_context, stream)) { if (stream != NULL && old_context->streams[i] != NULL) { @@ -1493,7 +1489,7 @@ enum dc_status resource_map_pool_resources( } for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; struct pipe_ctx *pipe_ctx = NULL; int pipe_idx = -1; @@ -1524,7 +1520,7 @@ enum dc_status resource_map_pool_resources( /* TODO: Add check if ASIC support and EDID audio */ if (!stream->sink->converter_disable_audio && dc_is_audio_capable_signal(pipe_ctx->stream->signal) && - stream->public.audio_info.mode_count) { + stream->audio_info.mode_count) { pipe_ctx->audio = find_first_free_audio( &context->res_ctx, pool); @@ -1560,7 +1556,7 @@ void validate_guaranteed_copy_streams( context->res_ctx.pipe_ctx[i].stream = context->res_ctx.pipe_ctx[0].stream; - dc_stream_retain(&context->streams[i]->public); + dc_stream_retain(context->streams[i]); context->stream_count++; } } @@ -1588,7 +1584,7 @@ static void set_avi_info_frame( struct encoder_info_packet *info_packet, struct pipe_ctx *pipe_ctx) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; enum dc_color_space color_space = COLOR_SPACE_UNKNOWN; struct info_frame info_frame = { {0} }; uint32_t pixel_encoding = 0; @@ -1602,12 +1598,12 @@ static void set_avi_info_frame( uint8_t byte_index = 0; union hdmi_info_packet *hdmi_info = &info_frame.avi_info_packet.info_packet_hdmi; union display_content_support support = {0}; - unsigned int vic = pipe_ctx->stream->public.timing.vic; + unsigned int vic = pipe_ctx->stream->timing.vic; enum dc_timing_3d_format format; - color_space = pipe_ctx->stream->public.output_color_space; + color_space = pipe_ctx->stream->output_color_space; if (color_space == COLOR_SPACE_UNKNOWN) - color_space = (stream->public.timing.pixel_encoding == PIXEL_ENCODING_RGB)? + color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709; /* Initialize header */ @@ -1622,7 +1618,7 @@ static void set_avi_info_frame( * according to HDMI 2.0 spec (Section 10.1) */ - switch (stream->public.timing.pixel_encoding) { + switch (stream->timing.pixel_encoding) { case PIXEL_ENCODING_YCBCR422: pixel_encoding = 1; break; @@ -1664,7 +1660,7 @@ static void set_avi_info_frame( color_space == COLOR_SPACE_YCBCR601_LIMITED) hdmi_info->bits.C0_C1 = COLORIMETRY_ITU601; else { - if (stream->public.timing.pixel_encoding != PIXEL_ENCODING_RGB) + if (stream->timing.pixel_encoding != PIXEL_ENCODING_RGB) BREAK_TO_DEBUGGER(); hdmi_info->bits.C0_C1 = COLORIMETRY_NO_DATA; } @@ -1679,7 +1675,7 @@ static void set_avi_info_frame( } /* TODO: un-hardcode aspect ratio */ - aspect = stream->public.timing.aspect_ratio; + aspect = stream->timing.aspect_ratio; switch (aspect) { case ASPECT_RATIO_4_3: @@ -1705,7 +1701,7 @@ static void set_avi_info_frame( itc = true; itc_value = 1; - support = stream->public.sink->edid_caps.content_support; + support = stream->sink->edid_caps.content_support; if (itc) { if (!support.bits.valid_content_type) { @@ -1744,8 +1740,8 @@ static void set_avi_info_frame( /* TODO : We should handle YCC quantization */ /* but we do not have matrix calculation */ - if (stream->public.sink->edid_caps.qs_bit == 1 && - stream->public.sink->edid_caps.qy_bit == 1) { + if (stream->sink->edid_caps.qs_bit == 1 && + stream->sink->edid_caps.qy_bit == 1) { if (color_space == COLOR_SPACE_SRGB || color_space == COLOR_SPACE_2020_RGB_FULLRANGE) { hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE; @@ -1764,11 +1760,11 @@ static void set_avi_info_frame( } ///VIC - format = stream->public.timing.timing_3d_format; + format = stream->timing.timing_3d_format; /*todo, add 3DStereo support*/ if (format != TIMING_3D_FORMAT_NONE) { // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled - switch (pipe_ctx->stream->public.timing.hdmi_vic) { + switch (pipe_ctx->stream->timing.hdmi_vic) { case 1: vic = 95; break; @@ -1797,12 +1793,12 @@ static void set_avi_info_frame( * barBottom: Line Number of Start of Bottom Bar. * barLeft: Pixel Number of End of Left Bar. * barRight: Pixel Number of Start of Right Bar. */ - hdmi_info->bits.bar_top = stream->public.timing.v_border_top; - hdmi_info->bits.bar_bottom = (stream->public.timing.v_total - - stream->public.timing.v_border_bottom + 1); - hdmi_info->bits.bar_left = stream->public.timing.h_border_left; - hdmi_info->bits.bar_right = (stream->public.timing.h_total - - stream->public.timing.h_border_right + 1); + hdmi_info->bits.bar_top = stream->timing.v_border_top; + hdmi_info->bits.bar_bottom = (stream->timing.v_total + - stream->timing.v_border_bottom + 1); + hdmi_info->bits.bar_left = stream->timing.h_border_left; + hdmi_info->bits.bar_right = (stream->timing.h_total + - stream->timing.h_border_right + 1); /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */ check_sum = &info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0]; @@ -1830,7 +1826,7 @@ static void set_avi_info_frame( static void set_vendor_info_packet( struct encoder_info_packet *info_packet, - struct core_stream *stream) + struct dc_stream *stream) { uint32_t length = 0; bool hdmi_vic_mode = false; @@ -1842,16 +1838,16 @@ static void set_vendor_info_packet( info_packet->valid = false; - format = stream->public.timing.timing_3d_format; - if (stream->public.view_format == VIEW_3D_FORMAT_NONE) + format = stream->timing.timing_3d_format; + if (stream->view_format == VIEW_3D_FORMAT_NONE) format = TIMING_3D_FORMAT_NONE; /* Can be different depending on packet content */ length = 5; - if (stream->public.timing.hdmi_vic != 0 - && stream->public.timing.h_total >= 3840 - && stream->public.timing.v_total >= 2160) + if (stream->timing.hdmi_vic != 0 + && stream->timing.h_total >= 3840 + && stream->timing.v_total >= 2160) hdmi_vic_mode = true; /* According to HDMI 1.4a CTS, VSIF should be sent @@ -1918,7 +1914,7 @@ static void set_vendor_info_packet( /*PB5: If PB4 is set to 0x1 (extended resolution format) * fill PB5 with the correct HDMI VIC code */ if (hdmi_vic_mode) - info_packet->sb[5] = stream->public.timing.hdmi_vic; + info_packet->sb[5] = stream->timing.hdmi_vic; /* Header */ info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; /* VSIF packet type. */ @@ -1943,7 +1939,7 @@ static void set_vendor_info_packet( static void set_spd_info_packet( struct encoder_info_packet *info_packet, - struct core_stream *stream) + struct dc_stream *stream) { /* SPD info packet for FreeSync */ @@ -1953,7 +1949,7 @@ static void set_spd_info_packet( /* Check if Freesync is supported. Return if false. If true, * set the corresponding bit in the info packet */ - if (stream->public.freesync_ctx.supported == false) + if (stream->freesync_ctx.supported == false) return; if (dc_is_hdmi_signal(stream->signal)) { @@ -2018,20 +2014,20 @@ static void set_spd_info_packet( /* PB6 = [Bits 7:3 = Reserved] */ info_packet->sb[6] = 0x00; - if (stream->public.freesync_ctx.supported == true) + if (stream->freesync_ctx.supported == true) /* PB6 = [Bit 0 = FreeSync Supported] */ info_packet->sb[6] |= 0x01; - if (stream->public.freesync_ctx.enabled == true) + if (stream->freesync_ctx.enabled == true) /* PB6 = [Bit 1 = FreeSync Enabled] */ info_packet->sb[6] |= 0x02; - if (stream->public.freesync_ctx.active == true) + if (stream->freesync_ctx.active == true) /* PB6 = [Bit 2 = FreeSync Active] */ info_packet->sb[6] |= 0x04; /* PB7 = FreeSync Minimum refresh rate (Hz) */ - info_packet->sb[7] = (unsigned char) (stream->public.freesync_ctx. + info_packet->sb[7] = (unsigned char) (stream->freesync_ctx. min_refresh_in_micro_hz / 1000000); /* PB8 = FreeSync Maximum refresh rate (Hz) @@ -2040,7 +2036,7 @@ static void set_spd_info_packet( * of the panel, because we should never go above the field * rate of the mode timing set. */ - info_packet->sb[8] = (unsigned char) (stream->public.freesync_ctx. + info_packet->sb[8] = (unsigned char) (stream->freesync_ctx. nominal_refresh_in_micro_hz / 1000000); /* PB9 - PB27 = Reserved */ @@ -2065,7 +2061,7 @@ static void set_spd_info_packet( static void set_hdr_static_info_packet( struct encoder_info_packet *info_packet, struct dc_surface *surface, - struct core_stream *stream) + struct dc_stream *stream) { uint16_t i = 0; enum signal_type signal = stream->signal; @@ -2168,7 +2164,7 @@ static void set_hdr_static_info_packet( static void set_vsc_info_packet( struct encoder_info_packet *info_packet, - struct core_stream *stream) + struct dc_stream *stream) { unsigned int vscPacketRevision = 0; unsigned int i; @@ -2218,7 +2214,7 @@ void dc_resource_validate_ctx_destruct(struct validate_context *context) context->stream_status[i].surfaces[j]); context->stream_status[i].surface_count = 0; - dc_stream_release(&context->streams[i]->public); + dc_stream_release(context->streams[i]); context->streams[i] = NULL; } } @@ -2248,7 +2244,7 @@ void dc_resource_validate_ctx_copy_construct( } for (i = 0; i < dst_ctx->stream_count; i++) { - dc_stream_retain(&dst_ctx->streams[i]->public); + dc_stream_retain(dst_ctx->streams[i]); for (j = 0; j < dst_ctx->stream_status[i].surface_count; j++) dc_surface_retain( dst_ctx->stream_status[i].surfaces[j]); @@ -2321,7 +2317,7 @@ enum dc_status resource_map_clock_resources( /* acquire new resources */ for (i = 0; i < context->stream_count; i++) { - const struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -2401,12 +2397,12 @@ bool pipe_need_reprogram( return false; } -void resource_build_bit_depth_reduction_params(const struct core_stream *stream, +void resource_build_bit_depth_reduction_params(struct dc_stream *stream, struct bit_depth_reduction_params *fmt_bit_depth) { - enum dc_dither_option option = stream->public.dither_option; + enum dc_dither_option option = stream->dither_option; enum dc_pixel_encoding pixel_encoding = - stream->public.timing.pixel_encoding; + stream->timing.pixel_encoding; memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth)); @@ -2511,31 +2507,30 @@ void resource_build_bit_depth_reduction_params(const struct core_stream *stream, fmt_bit_depth->pixel_encoding = pixel_encoding; } -bool dc_validate_stream(const struct dc *dc, const struct dc_stream *stream) +bool dc_validate_stream(const struct dc *dc, struct dc_stream *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); struct dc_context *dc_ctx = core_dc->ctx; - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); - struct dc_link *link = core_stream->sink->link; + struct dc_link *link = stream->sink->link; struct timing_generator *tg = core_dc->res_pool->timing_generators[0]; enum dc_status res = DC_OK; - calculate_phy_pix_clks(core_stream); + calculate_phy_pix_clks(stream); - if (!tg->funcs->validate_timing(tg, &core_stream->public.timing)) + if (!tg->funcs->validate_timing(tg, &stream->timing)) res = DC_FAIL_CONTROLLER_VALIDATE; if (res == DC_OK) if (!link->link_enc->funcs->validate_output_with_stream( - link->link_enc, core_stream)) + link->link_enc, stream)) res = DC_FAIL_ENC_VALIDATE; /* TODO: validate audio ASIC caps, encoder */ if (res == DC_OK) - res = dc_link_validate_mode_timing(core_stream, + res = dc_link_validate_mode_timing(stream, link, - &core_stream->public.timing); + &stream->timing); if (res != DC_OK) DC_ERROR("Failed validation for stream %p, err:%d, !\n", diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 5b356ddf5614..46ad1bc12f63 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -35,24 +35,24 @@ ******************************************************************************/ struct stream { - struct core_stream protected; + struct dc_stream protected; int ref_count; }; -#define DC_STREAM_TO_STREAM(dc_stream) container_of(dc_stream, struct stream, protected.public) +#define DC_STREAM_TO_STREAM(dc_stream) container_of(dc_stream, struct stream, protected) /******************************************************************************* * Private functions ******************************************************************************/ -static bool construct(struct core_stream *stream, +static bool construct(struct dc_stream *stream, struct dc_sink *dc_sink_data) { uint32_t i = 0; stream->sink = dc_sink_data; stream->ctx = stream->sink->ctx; - stream->public.sink = dc_sink_data; + stream->sink = dc_sink_data; dc_sink_retain(dc_sink_data); @@ -60,52 +60,52 @@ static bool construct(struct core_stream *stream, /* TODO - Remove this translation */ for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++) { - stream->public.audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count; - stream->public.audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code; - stream->public.audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate; - stream->public.audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size; + stream->audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count; + stream->audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code; + stream->audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate; + stream->audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size; } - stream->public.audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count; - stream->public.audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency; - stream->public.audio_info.video_latency = dc_sink_data->edid_caps.video_latency; + stream->audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count; + stream->audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency; + stream->audio_info.video_latency = dc_sink_data->edid_caps.video_latency; memmove( - stream->public.audio_info.display_name, + stream->audio_info.display_name, dc_sink_data->edid_caps.display_name, AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); - stream->public.audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id; - stream->public.audio_info.product_id = dc_sink_data->edid_caps.product_id; - stream->public.audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags; + stream->audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id; + stream->audio_info.product_id = dc_sink_data->edid_caps.product_id; + stream->audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags; if (dc_sink_data->dc_container_id != NULL) { struct dc_container_id *dc_container_id = dc_sink_data->dc_container_id; - stream->public.audio_info.port_id[0] = dc_container_id->portId[0]; - stream->public.audio_info.port_id[1] = dc_container_id->portId[1]; + stream->audio_info.port_id[0] = dc_container_id->portId[0]; + stream->audio_info.port_id[1] = dc_container_id->portId[1]; } else { /* TODO - WindowDM has implemented, other DMs need Unhardcode port_id */ - stream->public.audio_info.port_id[0] = 0x5558859e; - stream->public.audio_info.port_id[1] = 0xd989449; + stream->audio_info.port_id[0] = 0x5558859e; + stream->audio_info.port_id[1] = 0xd989449; } /* EDID CAP translation for HDMI 2.0 */ - stream->public.timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; + stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; stream->status.link = stream->sink->link; return true; } -static void destruct(struct core_stream *stream) +static void destruct(struct dc_stream *stream) { dc_sink_release(stream->sink); - if (stream->public.out_transfer_func != NULL) { + if (stream->out_transfer_func != NULL) { dc_transfer_func_release( - stream->public.out_transfer_func); - stream->public.out_transfer_func = NULL; + stream->out_transfer_func); + stream->out_transfer_func = NULL; } } -void dc_stream_retain(const struct dc_stream *dc_stream) +void dc_stream_retain(struct dc_stream *dc_stream) { struct stream *stream = DC_STREAM_TO_STREAM(dc_stream); @@ -113,17 +113,16 @@ void dc_stream_retain(const struct dc_stream *dc_stream) stream->ref_count++; } -void dc_stream_release(const struct dc_stream *public) +void dc_stream_release(struct dc_stream *public) { struct stream *stream = DC_STREAM_TO_STREAM(public); - struct core_stream *protected = DC_STREAM_TO_CORE(public); if (public != NULL) { ASSERT(stream->ref_count > 0); stream->ref_count--; if (stream->ref_count == 0) { - destruct(protected); + destruct(public); dm_free(stream); } } @@ -147,7 +146,7 @@ struct dc_stream *dc_create_stream_for_sink( stream->ref_count++; - return &stream->protected.public; + return &stream->protected; construct_fail: dm_free(stream); @@ -157,10 +156,9 @@ alloc_fail: } struct dc_stream_status *dc_stream_get_status( - const struct dc_stream *dc_stream) + struct dc_stream *stream) { uint8_t i; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); for (i = 0; i < dc->current_context->stream_count; i++) { @@ -176,15 +174,14 @@ struct dc_stream_status *dc_stream_get_status( * Update the cursor attributes and set cursor surface address */ bool dc_stream_set_cursor_attributes( - const struct dc_stream *dc_stream, + const struct dc_stream *stream, const struct dc_cursor_attributes *attributes) { int i; - struct core_stream *stream; struct core_dc *core_dc; struct resource_context *res_ctx; - if (NULL == dc_stream) { + if (NULL == stream) { dm_error("DC: dc_stream is NULL!\n"); return false; } @@ -193,7 +190,6 @@ bool dc_stream_set_cursor_attributes( return false; } - stream = DC_STREAM_TO_CORE(dc_stream); core_dc = DC_TO_CORE(stream->ctx->dc); res_ctx = &core_dc->current_context->res_ctx; @@ -213,15 +209,14 @@ bool dc_stream_set_cursor_attributes( } bool dc_stream_set_cursor_position( - const struct dc_stream *dc_stream, + struct dc_stream *stream, const struct dc_cursor_position *position) { int i; - struct core_stream *stream; struct core_dc *core_dc; struct resource_context *res_ctx; - if (NULL == dc_stream) { + if (NULL == stream) { dm_error("DC: dc_stream is NULL!\n"); return false; } @@ -231,7 +226,6 @@ bool dc_stream_set_cursor_position( return false; } - stream = DC_STREAM_TO_CORE(dc_stream); core_dc = DC_TO_CORE(stream->ctx->dc); res_ctx = &core_dc->current_context->res_ctx; @@ -240,7 +234,7 @@ bool dc_stream_set_cursor_position( struct input_pixel_processor *ipp = pipe_ctx->ipp; struct dc_cursor_position pos_cpy = *position; struct dc_cursor_mi_param param = { - .pixel_clk_khz = dc_stream->timing.pix_clk_khz, + .pixel_clk_khz = stream->timing.pix_clk_khz, .ref_clk_khz = core_dc->res_pool->ref_clock_inKhz, .viewport_x_start = pipe_ctx->scl_data.viewport.x, .viewport_width = pipe_ctx->scl_data.viewport.width, @@ -264,10 +258,9 @@ bool dc_stream_set_cursor_position( return true; } -uint32_t dc_stream_get_vblank_counter(const struct dc_stream *dc_stream) +uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream) { uint8_t i; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); struct resource_context *res_ctx = &core_dc->current_context->res_ctx; @@ -284,7 +277,7 @@ uint32_t dc_stream_get_vblank_counter(const struct dc_stream *dc_stream) return 0; } -bool dc_stream_get_scanoutpos(const struct dc_stream *dc_stream, +bool dc_stream_get_scanoutpos(const struct dc_stream *stream, uint32_t *v_blank_start, uint32_t *v_blank_end, uint32_t *h_position, @@ -292,7 +285,6 @@ bool dc_stream_get_scanoutpos(const struct dc_stream *dc_stream, { uint8_t i; bool ret = false; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); struct resource_context *res_ctx = &core_dc->current_context->res_ctx; @@ -322,37 +314,35 @@ void dc_stream_log( struct dal_logger *dm_logger, enum dc_log_type log_type) { - const struct core_stream *core_stream = - DC_STREAM_TO_CORE(stream); dm_logger_write(dm_logger, log_type, "core_stream 0x%x: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d\n", - core_stream, - core_stream->public.src.x, - core_stream->public.src.y, - core_stream->public.src.width, - core_stream->public.src.height, - core_stream->public.dst.x, - core_stream->public.dst.y, - core_stream->public.dst.width, - core_stream->public.dst.height, - core_stream->public.output_color_space); + stream, + stream->src.x, + stream->src.y, + stream->src.width, + stream->src.height, + stream->dst.x, + stream->dst.y, + stream->dst.width, + stream->dst.height, + stream->output_color_space); dm_logger_write(dm_logger, log_type, "\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n", - core_stream->public.timing.pix_clk_khz, - core_stream->public.timing.h_total, - core_stream->public.timing.v_total, - core_stream->public.timing.pixel_encoding, - core_stream->public.timing.display_color_depth); + stream->timing.pix_clk_khz, + stream->timing.h_total, + stream->timing.v_total, + stream->timing.pixel_encoding, + stream->timing.display_color_depth); dm_logger_write(dm_logger, log_type, "\tsink name: %s, serial: %d\n", - core_stream->sink->edid_caps.display_name, - core_stream->sink->edid_caps.serial_number); + stream->sink->edid_caps.display_name, + stream->sink->edid_caps.serial_number); dm_logger_write(dm_logger, log_type, "\tlink: %d\n", - core_stream->sink->link->link_index); + stream->sink->link->link_index); } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index f87f6c12494c..b20f7bfcdc1f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -32,6 +32,7 @@ #include "gpio_types.h" #include "link_service_types.h" #include "grph_object_ctrl_defs.h" +#include #define MAX_SURFACES 3 #define MAX_STREAMS 6 @@ -106,12 +107,12 @@ struct dc_cap_funcs { struct dc_stream_funcs { bool (*adjust_vmin_vmax)(struct dc *dc, - const struct dc_stream **stream, + struct dc_stream **stream, int num_streams, int vmin, int vmax); bool (*get_crtc_position)(struct dc *dc, - const struct dc_stream **stream, + struct dc_stream **stream, int num_streams, unsigned int *v_pos, unsigned int *nom_v_pos); @@ -120,14 +121,14 @@ struct dc_stream_funcs { const struct dc_stream *stream); bool (*program_csc_matrix)(struct dc *dc, - const struct dc_stream *stream); + struct dc_stream *stream); void (*set_static_screen_events)(struct dc *dc, - const struct dc_stream **stream, + struct dc_stream **stream, int num_streams, const struct dc_static_screen_events *events); - void (*set_dither_option)(const struct dc_stream *stream, + void (*set_dither_option)(struct dc_stream *stream, enum dc_dither_option option); }; @@ -428,7 +429,7 @@ bool dc_commit_surfaces_to_stream( struct dc *dc, struct dc_surface **dc_surfaces, uint8_t surface_count, - const struct dc_stream *stream); + struct dc_stream *stream); bool dc_post_update_surfaces_to_stream( struct dc *dc); @@ -468,6 +469,18 @@ enum surface_update_type { /******************************************************************************* * Stream Interfaces ******************************************************************************/ + +struct dc_stream_status { + int primary_otg_inst; + int surface_count; + struct dc_surface *surfaces[MAX_SURFACE_NUM]; + + /* + * link this stream passes through + */ + struct dc_link *link; +}; + struct dc_stream { struct dc_sink *sink; struct dc_crtc_timing timing; @@ -495,6 +508,21 @@ struct dc_stream { /* TODO: ABM info (DMCU) */ /* TODO: PSR info */ /* TODO: CEA VIC */ + + /* from core_stream struct */ + struct dc_context *ctx; + + /* used by DCP and FMT */ + struct bit_depth_reduction_params bit_depth_params; + struct clamping_and_pixel_encoding_params clamping; + + int phy_pix_clk; + enum signal_type signal; + + struct dc_stream_status status; + + /* from stream struct */ + int ref_count; }; struct dc_stream_update { @@ -521,7 +549,7 @@ struct dc_stream_update { void dc_update_surfaces_and_stream(struct dc *dc, struct dc_surface_update *surface_updates, int surface_count, - const struct dc_stream *dc_stream, + struct dc_stream *dc_stream, struct dc_stream_update *stream_update); /* @@ -554,12 +582,12 @@ bool dc_stream_get_scanoutpos(const struct dc_stream *stream, * Structure to store surface/stream associations for validation */ struct dc_validation_set { - const struct dc_stream *stream; + struct dc_stream *stream; struct dc_surface *surfaces[MAX_SURFACES]; uint8_t surface_count; }; -bool dc_validate_stream(const struct dc *dc, const struct dc_stream *stream); +bool dc_validate_stream(const struct dc *dc, struct dc_stream *stream); /* * This function takes a set of resources and checks that they are cofunctional. @@ -587,7 +615,7 @@ bool dc_validate_resources( bool dc_validate_guaranteed( const struct dc *dc, - const struct dc_stream *stream); + struct dc_stream *stream); void dc_resource_validate_ctx_copy_construct( const struct validate_context *src_ctx, @@ -616,7 +644,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context); */ bool dc_commit_streams( struct dc *dc, - const struct dc_stream *streams[], + struct dc_stream *streams[], uint8_t stream_count); /* * Enable stereo when commit_streams is not required, @@ -625,7 +653,7 @@ bool dc_commit_streams( bool dc_enable_stereo( struct dc *dc, struct validate_context *context, - const struct dc_stream *streams[], + struct dc_stream *streams[], uint8_t stream_count); /** @@ -633,22 +661,11 @@ bool dc_enable_stereo( */ struct dc_stream *dc_create_stream_for_sink(struct dc_sink *dc_sink); -void dc_stream_retain(const struct dc_stream *dc_stream); -void dc_stream_release(const struct dc_stream *dc_stream); - -struct dc_stream_status { - int primary_otg_inst; - int surface_count; - struct dc_surface *surfaces[MAX_SURFACE_NUM]; - - /* - * link this stream passes through - */ - struct dc_link *link; -}; +void dc_stream_retain(struct dc_stream *dc_stream); +void dc_stream_release(struct dc_stream *dc_stream); struct dc_stream_status *dc_stream_get_status( - const struct dc_stream *dc_stream); + struct dc_stream *dc_stream); enum surface_update_type dc_check_update_surfaces_for_stream( struct dc *dc, @@ -915,7 +932,7 @@ bool dc_stream_set_cursor_attributes( const struct dc_cursor_attributes *attributes); bool dc_stream_set_cursor_position( - const struct dc_stream *stream, + struct dc_stream *stream, const struct dc_cursor_position *position); /* Newer interfaces */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index aff0a440d4d3..24d0c48258ee 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -1009,7 +1009,7 @@ bool dce110_link_encoder_construct( bool dce110_link_encoder_validate_output_with_stream( struct link_encoder *enc, - const struct core_stream *stream) + const struct dc_stream *stream) { struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); bool is_valid; @@ -1021,22 +1021,22 @@ bool dce110_link_encoder_validate_output_with_stream( enc110, stream->sink->link->connector_signal, stream->signal, - &stream->public.timing); + &stream->timing); break; case SIGNAL_TYPE_HDMI_TYPE_A: is_valid = dce110_link_encoder_validate_hdmi_output( enc110, - &stream->public.timing, + &stream->timing, stream->phy_pix_clk); break; case SIGNAL_TYPE_DISPLAY_PORT: case SIGNAL_TYPE_DISPLAY_PORT_MST: is_valid = dce110_link_encoder_validate_dp_output( - enc110, &stream->public.timing); + enc110, &stream->timing); break; case SIGNAL_TYPE_EDP: is_valid = - (stream->public.timing. + (stream->timing. pixel_encoding == PIXEL_ENCODING_RGB) ? true : false; break; case SIGNAL_TYPE_VIRTUAL: diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index ded6c61304e6..a47b075f4869 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -199,7 +199,7 @@ bool dce110_link_encoder_validate_wireless_output( bool dce110_link_encoder_validate_output_with_stream( struct link_encoder *enc, - const struct core_stream *stream); + const struct dc_stream *stream); /****************** HW programming ************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 3d25a90e49b4..cf98f2471023 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -660,7 +660,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -734,8 +734,8 @@ enum dc_status dce100_validate_with_context( return DC_FAIL_SURFACE_VALIDATE; for (i = 0; i < set_count; i++) { - context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); - dc_stream_retain(&context->streams[i]->public); + context->streams[i] = set[i].stream; + dc_stream_retain(context->streams[i]); context->stream_count++; } @@ -765,13 +765,13 @@ enum dc_status dce100_validate_with_context( enum dc_status dce100_validate_guaranteed( const struct core_dc *dc, - const struct dc_stream *dc_stream, + struct dc_stream *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; - context->streams[0] = DC_STREAM_TO_CORE(dc_stream); - dc_stream_retain(&context->streams[0]->public); + context->streams[0] = dc_stream; + dc_stream_retain(context->streams[0]); context->stream_count++; result = resource_map_pool_resources(dc, context, NULL); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 119365960cd0..15f6eeef343d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -623,21 +623,21 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func static bool dce110_set_output_transfer_func( struct pipe_ctx *pipe_ctx, - const struct core_stream *stream) + const struct dc_stream *stream) { struct output_pixel_processor *opp = pipe_ctx->opp; opp->funcs->opp_power_on_regamma_lut(opp, true); opp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; - if (stream->public.out_transfer_func && - stream->public.out_transfer_func->type == + if (stream->out_transfer_func && + stream->out_transfer_func->type == TF_TYPE_PREDEFINED && - stream->public.out_transfer_func->tf == + stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB); } else if (dce110_translate_regamma_to_hw_format( - stream->public.out_transfer_func, &opp->regamma_params)) { + stream->out_transfer_func, &opp->regamma_params)) { opp->funcs->opp_program_regamma_pwl(opp, &opp->regamma_params); opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER); } else { @@ -702,7 +702,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) enum dc_lane_count lane_count = pipe_ctx->stream->sink->link->cur_link_settings.lane_count; - struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing; + struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; struct dc_link *link = pipe_ctx->stream->sink->link; /* 1. update AVI info frame (HDMI, DP) @@ -745,7 +745,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) void dce110_disable_stream(struct pipe_ctx *pipe_ctx) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; if (pipe_ctx->audio) { @@ -797,7 +797,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, /* only 3 items below are used by unblank */ params.pixel_clk_khz = - pipe_ctx->stream->public.timing.pix_clk_khz; + pipe_ctx->stream->timing.pix_clk_khz; params.link_settings.link_rate = link_settings->link_rate; pipe_ctx->stream_enc->funcs->dp_unblank(pipe_ctx->stream_enc, ¶ms); } @@ -833,7 +833,7 @@ static void build_audio_output( const struct pipe_ctx *pipe_ctx, struct audio_output *audio_output) { - const struct core_stream *stream = pipe_ctx->stream; + const struct dc_stream *stream = pipe_ctx->stream; audio_output->engine_id = pipe_ctx->stream_enc->id; audio_output->signal = pipe_ctx->stream->signal; @@ -841,33 +841,33 @@ static void build_audio_output( /* audio_crtc_info */ audio_output->crtc_info.h_total = - stream->public.timing.h_total; + stream->timing.h_total; /* * Audio packets are sent during actual CRTC blank physical signal, we * need to specify actual active signal portion */ audio_output->crtc_info.h_active = - stream->public.timing.h_addressable - + stream->public.timing.h_border_left - + stream->public.timing.h_border_right; + stream->timing.h_addressable + + stream->timing.h_border_left + + stream->timing.h_border_right; audio_output->crtc_info.v_active = - stream->public.timing.v_addressable - + stream->public.timing.v_border_top - + stream->public.timing.v_border_bottom; + stream->timing.v_addressable + + stream->timing.v_border_top + + stream->timing.v_border_bottom; audio_output->crtc_info.pixel_repetition = 1; audio_output->crtc_info.interlaced = - stream->public.timing.flags.INTERLACE; + stream->timing.flags.INTERLACE; audio_output->crtc_info.refresh_rate = - (stream->public.timing.pix_clk_khz*1000)/ - (stream->public.timing.h_total*stream->public.timing.v_total); + (stream->timing.pix_clk_khz*1000)/ + (stream->timing.h_total*stream->timing.v_total); audio_output->crtc_info.color_depth = - stream->public.timing.display_color_depth; + stream->timing.display_color_depth; audio_output->crtc_info.requested_pixel_clock = pipe_ctx->pix_clk_params.requested_pix_clk; @@ -878,7 +878,7 @@ static void build_audio_output( /*for HDMI, audio ACR is with deep color ratio factor*/ if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && audio_output->crtc_info.requested_pixel_clock == - stream->public.timing.pix_clk_khz) { + stream->timing.pix_clk_khz) { if (pipe_ctx->pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { audio_output->crtc_info.requested_pixel_clock = audio_output->crtc_info.requested_pixel_clock/2; @@ -959,7 +959,7 @@ static void program_scaler(const struct core_dc *dc, get_surface_visual_confirm_color(pipe_ctx, &color); else color_space_to_black_color(dc, - pipe_ctx->stream->public.output_color_space, + pipe_ctx->stream->output_color_space, &color); pipe_ctx->xfm->funcs->transform_set_pixel_storage_depth( @@ -981,7 +981,7 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( struct validate_context *context, struct core_dc *dc) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. pipe_ctx[pipe_ctx->pipe_idx]; struct tg_color black_color = {0}; @@ -990,7 +990,7 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( /* program blank color */ color_space_to_black_color(dc, - stream->public.output_color_space, &black_color); + stream->output_color_space, &black_color); pipe_ctx->tg->funcs->set_blank_color( pipe_ctx->tg, &black_color); @@ -1011,7 +1011,7 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( pipe_ctx->tg->funcs->program_timing( pipe_ctx->tg, - &stream->public.timing, + &stream->timing, true); pipe_ctx->tg->funcs->set_static_screen_control( @@ -1037,7 +1037,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( struct validate_context *context, struct core_dc *dc) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. pipe_ctx[pipe_ctx->pipe_idx]; @@ -1047,7 +1047,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( pipe_ctx->opp->funcs->opp_set_dyn_expansion( pipe_ctx->opp, COLOR_SPACE_YCBCR601, - stream->public.timing.display_color_depth, + stream->timing.display_color_depth, pipe_ctx->stream->signal); /* FPGA does not program backend */ @@ -1074,7 +1074,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( pipe_ctx->stream_enc->funcs->setup_stereo_sync( pipe_ctx->stream_enc, pipe_ctx->tg->inst, - stream->public.timing.timing_3d_format != TIMING_3D_FORMAT_NONE); + stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE); /*vbios crtc_source_selection and encoder_setup will override fmt_C*/ @@ -1086,20 +1086,20 @@ static enum dc_status apply_single_controller_ctx_to_hw( if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_enc->funcs->dp_set_stream_attribute( pipe_ctx->stream_enc, - &stream->public.timing, - stream->public.output_color_space); + &stream->timing, + stream->output_color_space); if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_enc->funcs->hdmi_set_stream_attribute( pipe_ctx->stream_enc, - &stream->public.timing, + &stream->timing, stream->phy_pix_clk, pipe_ctx->audio != NULL); if (dc_is_dvi_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_enc->funcs->dvi_set_stream_attribute( pipe_ctx->stream_enc, - &stream->public.timing, + &stream->timing, (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ? true : false); @@ -1129,9 +1129,9 @@ static enum dc_status apply_single_controller_ctx_to_hw( #endif pipe_ctx->mi->funcs->allocate_mem_input( pipe_ctx->mi, - stream->public.timing.h_total, - stream->public.timing.v_total, - stream->public.timing.pix_clk_khz, + stream->timing.h_total, + stream->timing.v_total, + stream->timing.pix_clk_khz, context->stream_count); pipe_ctx->stream->sink->link->psr_enabled = false; @@ -1228,7 +1228,7 @@ void dce110_enable_accelerated_mode(struct core_dc *dc) static uint32_t compute_pstate_blackout_duration( struct bw_fixed blackout_duration, - const struct core_stream *stream) + const struct dc_stream *stream) { uint32_t total_dest_line_time_ns; uint32_t pstate_blackout_duration_ns; @@ -1236,8 +1236,8 @@ static uint32_t compute_pstate_blackout_duration( pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; total_dest_line_time_ns = 1000000UL * - stream->public.timing.h_total / - stream->public.timing.pix_clk_khz + + stream->timing.h_total / + stream->timing.pix_clk_khz + pstate_blackout_duration_ns; return total_dest_line_time_ns; @@ -1805,19 +1805,19 @@ enum dc_status dce110_apply_ctx_to_hw( pipe_ctx->stream_enc->funcs->dp_audio_setup( pipe_ctx->stream_enc, pipe_ctx->audio->inst, - &pipe_ctx->stream->public.audio_info); + &pipe_ctx->stream->audio_info); else pipe_ctx->stream_enc->funcs->hdmi_audio_setup( pipe_ctx->stream_enc, pipe_ctx->audio->inst, - &pipe_ctx->stream->public.audio_info, + &pipe_ctx->stream->audio_info, &audio_output.crtc_info); pipe_ctx->audio->funcs->az_configure( pipe_ctx->audio, pipe_ctx->stream->signal, &audio_output.crtc_info, - &pipe_ctx->stream->public.audio_info); + &pipe_ctx->stream->audio_info); } status = apply_single_controller_ctx_to_hw( @@ -1862,13 +1862,13 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx) default_adjust.out_color_space = COLOR_SPACE_SRGB; else default_adjust.out_color_space = - pipe_ctx->stream->public.output_color_space; + pipe_ctx->stream->output_color_space; default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; default_adjust.surface_pixel_format = pipe_ctx->scl_data.format; /* display color depth */ default_adjust.color_depth = - pipe_ctx->stream->public.timing.display_color_depth; + pipe_ctx->stream->timing.display_color_depth; /* Lb color depth */ default_adjust.lb_color_depth = pipe_ctx->scl_data.lb_params.depth; @@ -1932,35 +1932,35 @@ static void program_gamut_remap(struct pipe_ctx *pipe_ctx) adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; - if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { + if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; adjust.temperature_matrix[0] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[0]; + gamut_remap_matrix.matrix[0]; adjust.temperature_matrix[1] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[1]; + gamut_remap_matrix.matrix[1]; adjust.temperature_matrix[2] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[2]; + gamut_remap_matrix.matrix[2]; adjust.temperature_matrix[3] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[4]; + gamut_remap_matrix.matrix[4]; adjust.temperature_matrix[4] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[5]; + gamut_remap_matrix.matrix[5]; adjust.temperature_matrix[5] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[6]; + gamut_remap_matrix.matrix[6]; adjust.temperature_matrix[6] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[8]; + gamut_remap_matrix.matrix[8]; adjust.temperature_matrix[7] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[9]; + gamut_remap_matrix.matrix[9]; adjust.temperature_matrix[8] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[10]; + gamut_remap_matrix.matrix[10]; } pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); @@ -1987,48 +1987,48 @@ static void set_plane_config( dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true); set_default_colors(pipe_ctx); - if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment + if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { tbl_entry.color_space = - pipe_ctx->stream->public.output_color_space; + pipe_ctx->stream->output_color_space; for (i = 0; i < 12; i++) tbl_entry.regval[i] = - pipe_ctx->stream->public.csc_color_matrix.matrix[i]; + pipe_ctx->stream->csc_color_matrix.matrix[i]; pipe_ctx->opp->funcs->opp_set_csc_adjustment (pipe_ctx->opp, &tbl_entry); } - if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { + if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; adjust.temperature_matrix[0] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[0]; + gamut_remap_matrix.matrix[0]; adjust.temperature_matrix[1] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[1]; + gamut_remap_matrix.matrix[1]; adjust.temperature_matrix[2] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[2]; + gamut_remap_matrix.matrix[2]; adjust.temperature_matrix[3] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[4]; + gamut_remap_matrix.matrix[4]; adjust.temperature_matrix[4] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[5]; + gamut_remap_matrix.matrix[5]; adjust.temperature_matrix[5] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[6]; + gamut_remap_matrix.matrix[6]; adjust.temperature_matrix[6] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[8]; + gamut_remap_matrix.matrix[8]; adjust.temperature_matrix[7] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[9]; + gamut_remap_matrix.matrix[9]; adjust.temperature_matrix[8] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[10]; + gamut_remap_matrix.matrix[10]; } pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); @@ -2260,7 +2260,7 @@ void dce110_fill_display_configs( for (j = 0; j < context->stream_count; j++) { int k; - const struct core_stream *stream = context->streams[j]; + const struct dc_stream *stream = context->streams[j]; struct dm_pp_single_disp_config *cfg = &pp_display_cfg->disp_configs[num_cfgs]; const struct pipe_ctx *pipe_ctx = NULL; @@ -2276,8 +2276,8 @@ void dce110_fill_display_configs( num_cfgs++; cfg->signal = pipe_ctx->stream->signal; cfg->pipe_idx = pipe_ctx->pipe_idx; - cfg->src_height = stream->public.src.height; - cfg->src_width = stream->public.src.width; + cfg->src_height = stream->src.height; + cfg->src_width = stream->src.width; cfg->ddi_channel_mapping = stream->sink->link->ddi_channel_mapping.raw; cfg->transmitter = @@ -2290,10 +2290,10 @@ void dce110_fill_display_configs( stream->sink->link->cur_link_settings.link_spread; cfg->sym_clock = stream->phy_pix_clk; /* Round v_refresh*/ - cfg->v_refresh = stream->public.timing.pix_clk_khz * 1000; - cfg->v_refresh /= stream->public.timing.h_total; - cfg->v_refresh = (cfg->v_refresh + stream->public.timing.v_total / 2) - / stream->public.timing.v_total; + cfg->v_refresh = stream->timing.pix_clk_khz * 1000; + cfg->v_refresh /= stream->timing.h_total; + cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) + / stream->timing.v_total; } pp_display_cfg->display_count = num_cfgs; @@ -2305,7 +2305,7 @@ uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context) uint32_t min_vertical_blank_time = -1; for (j = 0; j < context->stream_count; j++) { - const struct dc_stream *stream = &context->streams[j]->public; + struct dc_stream *stream = context->streams[j]; uint32_t vertical_blank_in_pixels = 0; uint32_t vertical_blank_time = 0; @@ -2388,7 +2388,7 @@ static void pplib_apply_display_requirements( /* TODO: is this still applicable?*/ if (pp_display_cfg->display_count == 1) { const struct dc_crtc_timing *timing = - &context->streams[0]->public.timing; + &context->streams[0]->timing; pp_display_cfg->crtc_index = pp_display_cfg->disp_configs[0].pipe_idx; @@ -2441,48 +2441,48 @@ static void dce110_program_front_end_for_pipe( dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true); set_default_colors(pipe_ctx); - if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment + if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { tbl_entry.color_space = - pipe_ctx->stream->public.output_color_space; + pipe_ctx->stream->output_color_space; for (i = 0; i < 12; i++) tbl_entry.regval[i] = - pipe_ctx->stream->public.csc_color_matrix.matrix[i]; + pipe_ctx->stream->csc_color_matrix.matrix[i]; pipe_ctx->opp->funcs->opp_set_csc_adjustment (pipe_ctx->opp, &tbl_entry); } - if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { + if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; adjust.temperature_matrix[0] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[0]; + gamut_remap_matrix.matrix[0]; adjust.temperature_matrix[1] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[1]; + gamut_remap_matrix.matrix[1]; adjust.temperature_matrix[2] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[2]; + gamut_remap_matrix.matrix[2]; adjust.temperature_matrix[3] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[4]; + gamut_remap_matrix.matrix[4]; adjust.temperature_matrix[4] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[5]; + gamut_remap_matrix.matrix[5]; adjust.temperature_matrix[5] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[6]; + gamut_remap_matrix.matrix[6]; adjust.temperature_matrix[6] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[8]; + gamut_remap_matrix.matrix[8]; adjust.temperature_matrix[7] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[9]; + gamut_remap_matrix.matrix[9]; adjust.temperature_matrix[8] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[10]; + gamut_remap_matrix.matrix[10]; } pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index c773351e93af..cc25c4b6c06f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -718,13 +718,13 @@ static void get_pixel_clock_parameters( const struct pipe_ctx *pipe_ctx, struct pixel_clk_params *pixel_clk_params) { - const struct core_stream *stream = pipe_ctx->stream; + const struct dc_stream *stream = pipe_ctx->stream; /*TODO: is this halved for YCbCr 420? in that case we might want to move * the pixel clock normalization for hdmi up to here instead of doing it * in pll_adjust_pix_clk */ - pixel_clk_params->requested_pix_clk = stream->public.timing.pix_clk_khz; + pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz; pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id; pixel_clk_params->signal_type = pipe_ctx->stream->signal; pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1; @@ -733,15 +733,15 @@ static void get_pixel_clock_parameters( LINK_RATE_REF_FREQ_IN_KHZ; pixel_clk_params->flags.ENABLE_SS = 0; pixel_clk_params->color_depth = - stream->public.timing.display_color_depth; + stream->timing.display_color_depth; pixel_clk_params->flags.DISPLAY_BLANKED = 1; - pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->public.timing.pixel_encoding == + pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420); - pixel_clk_params->pixel_encoding = stream->public.timing.pixel_encoding; - if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { + pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; + if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { pixel_clk_params->color_depth = COLOR_DEPTH_888; } - if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { + if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { pixel_clk_params->requested_pix_clk = pixel_clk_params->requested_pix_clk / 2; } } @@ -755,7 +755,7 @@ enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) &pipe_ctx->pll_settings); resource_build_bit_depth_reduction_params(pipe_ctx->stream, &pipe_ctx->stream->bit_depth_params); - pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->public.timing.pixel_encoding; + pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; return DC_OK; } @@ -780,7 +780,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -837,9 +837,9 @@ bool dce110_validate_bandwidth( dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION, "%s: %dx%d@%d Bandwidth validation failed!\n", __func__, - context->streams[0]->public.timing.h_addressable, - context->streams[0]->public.timing.v_addressable, - context->streams[0]->public.timing.pix_clk_khz); + context->streams[0]->timing.h_addressable, + context->streams[0]->timing.v_addressable, + context->streams[0]->timing.pix_clk_khz); if (memcmp(&dc->current_context->bw.dce, &context->bw.dce, sizeof(context->bw.dce))) { @@ -942,8 +942,8 @@ enum dc_status dce110_validate_with_context( return DC_FAIL_SURFACE_VALIDATE; for (i = 0; i < set_count; i++) { - context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); - dc_stream_retain(&context->streams[i]->public); + context->streams[i] = set[i].stream; + dc_stream_retain(context->streams[i]); context->stream_count++; } @@ -973,13 +973,13 @@ enum dc_status dce110_validate_with_context( enum dc_status dce110_validate_guaranteed( const struct core_dc *dc, - const struct dc_stream *dc_stream, + struct dc_stream *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; - context->streams[0] = DC_STREAM_TO_CORE(dc_stream); - dc_stream_retain(&context->streams[0]->public); + context->streams[0] = dc_stream; + dc_stream_retain(context->streams[0]); context->stream_count++; result = resource_map_pool_resources(dc, context, NULL); @@ -1006,7 +1006,7 @@ enum dc_status dce110_validate_guaranteed( static struct pipe_ctx *dce110_acquire_underlay( struct validate_context *context, const struct resource_pool *pool, - struct core_stream *stream) + struct dc_stream *stream) { struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); struct resource_context *res_ctx = &context->res_ctx; @@ -1041,18 +1041,18 @@ static struct pipe_ctx *dce110_acquire_underlay( */ pipe_ctx->tg->funcs->program_timing(pipe_ctx->tg, - &stream->public.timing, + &stream->timing, false); pipe_ctx->tg->funcs->enable_advanced_request( pipe_ctx->tg, true, - &stream->public.timing); + &stream->timing); pipe_ctx->mi->funcs->allocate_mem_input(pipe_ctx->mi, - stream->public.timing.h_total, - stream->public.timing.v_total, - stream->public.timing.pix_clk_khz, + stream->timing.h_total, + stream->timing.v_total, + stream->timing.pix_clk_khz, context->stream_count); color_space_to_black_color(dc, diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 19cd99923b24..9589208ea0c8 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -698,7 +698,7 @@ static void destruct(struct dce110_resource_pool *pool) static struct clock_source *find_matching_pll( struct resource_context *res_ctx, const struct resource_pool *pool, - const struct core_stream *const stream) + const struct dc_stream *const stream) { switch (stream->sink->link->link_enc->transmitter) { case TRANSMITTER_UNIPHY_A: @@ -729,7 +729,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -843,7 +843,7 @@ enum dc_status resource_map_phy_clock_resources( /* acquire new resources */ for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -916,8 +916,8 @@ enum dc_status dce112_validate_with_context( return DC_FAIL_SURFACE_VALIDATE; for (i = 0; i < set_count; i++) { - context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); - dc_stream_retain(&context->streams[i]->public); + context->streams[i] = set[i].stream; + dc_stream_retain(context->streams[i]); context->stream_count++; } @@ -947,13 +947,13 @@ enum dc_status dce112_validate_with_context( enum dc_status dce112_validate_guaranteed( const struct core_dc *dc, - const struct dc_stream *dc_stream, + struct dc_stream *stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; - context->streams[0] = DC_STREAM_TO_CORE(dc_stream); - dc_stream_retain(&context->streams[0]->public); + context->streams[0] = stream; + dc_stream_retain(context->streams[0]); context->stream_count++; result = resource_map_pool_resources(dc, context, NULL); diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h index c6c0bbac5335..cb2c69fb05a6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h @@ -44,7 +44,7 @@ enum dc_status dce112_validate_with_context( enum dc_status dce112_validate_guaranteed( const struct core_dc *dc, - const struct dc_stream *dc_stream, + struct dc_stream *dc_stream, struct validate_context *context); bool dce112_validate_bandwidth( diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 0123006e5360..2fde43c91ad0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -676,7 +676,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -750,8 +750,8 @@ enum dc_status dce80_validate_with_context( return DC_FAIL_SURFACE_VALIDATE; for (i = 0; i < set_count; i++) { - context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); - dc_stream_retain(&context->streams[i]->public); + context->streams[i] = set[i].stream; + dc_stream_retain(context->streams[i]); context->stream_count++; } @@ -780,13 +780,13 @@ enum dc_status dce80_validate_with_context( enum dc_status dce80_validate_guaranteed( const struct core_dc *dc, - const struct dc_stream *dc_stream, + struct dc_stream *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; - context->streams[0] = DC_STREAM_TO_CORE(dc_stream); - dc_stream_retain(&context->streams[0]->public); + context->streams[0] = dc_stream; + dc_stream_retain(context->streams[0]); context->stream_count++; result = resource_map_pool_resources(dc, context, NULL); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index e738387d8ba3..1531b52e61c2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -684,12 +684,12 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( struct validate_context *context, struct core_dc *dc) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; enum dc_color_space color_space; struct tg_color black_color = {0}; - bool enableStereo = stream->public.timing.timing_3d_format == TIMING_3D_FORMAT_NONE ? + bool enableStereo = stream->timing.timing_3d_format == TIMING_3D_FORMAT_NONE ? false:true; - bool rightEyePolarity = stream->public.timing.flags.RIGHT_EYE_3D_POLARITY; + bool rightEyePolarity = stream->timing.flags.RIGHT_EYE_3D_POLARITY; /* by upper caller loop, pipe0 is parent pipe and be called first. @@ -722,7 +722,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( pipe_ctx->tg->funcs->program_timing( pipe_ctx->tg, - &stream->public.timing, + &stream->timing, true); pipe_ctx->opp->funcs->opp_set_stereo_polarity( @@ -742,7 +742,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( &stream->clamping); #endif /* program otg blank color */ - color_space = stream->public.output_color_space; + color_space = stream->output_color_space; color_space_to_black_color(dc, color_space, &black_color); pipe_ctx->tg->funcs->set_blank_color( pipe_ctx->tg, @@ -1053,16 +1053,16 @@ static bool patch_address_for_sbs_tb_stereo( bool sec_split = pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface; if (sec_split && surface->address.type == PLN_ADDR_TYPE_GRPH_STEREO && - (pipe_ctx->stream->public.timing.timing_3d_format == + (pipe_ctx->stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE || - pipe_ctx->stream->public.timing.timing_3d_format == + pipe_ctx->stream->timing.timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { *addr = surface->address.grph_stereo.left_addr; surface->address.grph_stereo.left_addr = surface->address.grph_stereo.right_addr; return true; } else { - if (pipe_ctx->stream->public.view_format != VIEW_3D_FORMAT_NONE && + if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && surface->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { surface->address.type = PLN_ADDR_TYPE_GRPH_STEREO; surface->address.grph_stereo.right_addr = @@ -1456,7 +1456,7 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func static bool dcn10_set_output_transfer_func( struct pipe_ctx *pipe_ctx, - const struct core_stream *stream) + const struct dc_stream *stream) { struct transform *xfm = pipe_ctx->xfm; @@ -1465,14 +1465,14 @@ static bool dcn10_set_output_transfer_func( xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; - if (stream->public.out_transfer_func && - stream->public.out_transfer_func->type == + if (stream->out_transfer_func && + stream->out_transfer_func->type == TF_TYPE_PREDEFINED && - stream->public.out_transfer_func->tf == + stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); } else if (dcn10_translate_regamma_to_hw_format( - stream->public.out_transfer_func, &xfm->regamma_params)) { + stream->out_transfer_func, &xfm->regamma_params)) { xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); } else { @@ -1756,35 +1756,35 @@ static void program_gamut_remap(struct pipe_ctx *pipe_ctx) adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; - if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { + if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; adjust.temperature_matrix[0] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[0]; + gamut_remap_matrix.matrix[0]; adjust.temperature_matrix[1] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[1]; + gamut_remap_matrix.matrix[1]; adjust.temperature_matrix[2] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[2]; + gamut_remap_matrix.matrix[2]; adjust.temperature_matrix[3] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[4]; + gamut_remap_matrix.matrix[4]; adjust.temperature_matrix[4] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[5]; + gamut_remap_matrix.matrix[5]; adjust.temperature_matrix[5] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[6]; + gamut_remap_matrix.matrix[6]; adjust.temperature_matrix[6] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[8]; + gamut_remap_matrix.matrix[8]; adjust.temperature_matrix[7] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[9]; + gamut_remap_matrix.matrix[9]; adjust.temperature_matrix[8] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[10]; + gamut_remap_matrix.matrix[10]; } pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); @@ -1798,14 +1798,14 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, int i; struct out_csc_color_matrix tbl_entry; - if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment + if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { enum dc_color_space color_space = - pipe_ctx->stream->public.output_color_space; + pipe_ctx->stream->output_color_space; //uint16_t matrix[12]; for (i = 0; i < 12; i++) - tbl_entry.regval[i] = pipe_ctx->stream->public.csc_color_matrix.matrix[i]; + tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; tbl_entry.color_space = color_space; //tbl_entry.regval = matrix; @@ -1967,7 +1967,7 @@ static void update_dchubp_dpp( * pre-multiplied alpha. */ mpcc_cfg.pre_multiplied_alpha = is_rgb_cspace( - pipe_ctx->stream->public.output_color_space) + pipe_ctx->stream->output_color_space) && per_pixel_alpha; pipe_ctx->mpcc->funcs->set(pipe_ctx->mpcc, &mpcc_cfg); @@ -1975,7 +1975,7 @@ static void update_dchubp_dpp( dcn10_get_surface_visual_confirm_color(pipe_ctx, &black_color); } else { color_space_to_black_color( - dc, pipe_ctx->stream->public.output_color_space, + dc, pipe_ctx->stream->output_color_space, &black_color); } pipe_ctx->mpcc->funcs->set_bg_color(pipe_ctx->mpcc, &black_color); @@ -1991,7 +1991,7 @@ static void update_dchubp_dpp( program_gamut_remap(pipe_ctx); /*TODO add adjustments parameters*/ - ocsc.out_color_space = pipe_ctx->stream->public.output_color_space; + ocsc.out_color_space = pipe_ctx->stream->output_color_space; pipe_ctx->xfm->funcs->opp_set_csc_default(pipe_ctx->xfm, &ocsc); mi->funcs->mem_input_program_surface_config( @@ -2346,11 +2346,11 @@ static void set_plane_config( } static void dcn10_config_stereo_parameters( - struct core_stream *stream, struct crtc_stereo_flags *flags) + struct dc_stream *stream, struct crtc_stereo_flags *flags) { - enum view_3d_format view_format = stream->public.view_format; + enum view_3d_format view_format = stream->view_format; enum dc_timing_3d_format timing_3d_format =\ - stream->public.timing.timing_3d_format; + stream->timing.timing_3d_format; bool non_stereo_timing = false; if (timing_3d_format == TIMING_3D_FORMAT_NONE || @@ -2374,7 +2374,7 @@ static void dcn10_config_stereo_parameters( flags->DISABLE_STEREO_DP_SYNC = 1; } flags->RIGHT_EYE_POLARITY =\ - stream->public.timing.flags.RIGHT_EYE_3D_POLARITY; + stream->timing.flags.RIGHT_EYE_3D_POLARITY; if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) flags->FRAME_PACKED = 1; } @@ -2385,18 +2385,18 @@ static void dcn10_config_stereo_parameters( static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc) { struct crtc_stereo_flags flags = { 0 }; - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; dcn10_config_stereo_parameters(stream, &flags); pipe_ctx->opp->funcs->opp_set_stereo_polarity( pipe_ctx->opp, flags.PROGRAM_STEREO == 1 ? true:false, - stream->public.timing.flags.RIGHT_EYE_3D_POLARITY == 1 ? true:false); + stream->timing.flags.RIGHT_EYE_3D_POLARITY == 1 ? true:false); pipe_ctx->tg->funcs->program_stereo( pipe_ctx->tg, - &stream->public.timing, + &stream->timing, &flags); return; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index b901ef9689a6..33beb0bc3ddf 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -787,8 +787,8 @@ static void get_pixel_clock_parameters( const struct pipe_ctx *pipe_ctx, struct pixel_clk_params *pixel_clk_params) { - const struct core_stream *stream = pipe_ctx->stream; - pixel_clk_params->requested_pix_clk = stream->public.timing.pix_clk_khz; + const struct dc_stream *stream = pipe_ctx->stream; + pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz; pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id; pixel_clk_params->signal_type = pipe_ctx->stream->signal; pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1; @@ -797,23 +797,23 @@ static void get_pixel_clock_parameters( LINK_RATE_REF_FREQ_IN_KHZ; pixel_clk_params->flags.ENABLE_SS = 0; pixel_clk_params->color_depth = - stream->public.timing.display_color_depth; + stream->timing.display_color_depth; pixel_clk_params->flags.DISPLAY_BLANKED = 1; - pixel_clk_params->pixel_encoding = stream->public.timing.pixel_encoding; + pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; - if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) + if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) pixel_clk_params->color_depth = COLOR_DEPTH_888; - if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) + if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) pixel_clk_params->requested_pix_clk /= 2; } -static void build_clamping_params(struct core_stream *stream) +static void build_clamping_params(struct dc_stream *stream) { stream->clamping.clamping_level = CLAMPING_FULL_RANGE; - stream->clamping.c_depth = stream->public.timing.display_color_depth; - stream->clamping.pixel_encoding = stream->public.timing.pixel_encoding; + stream->clamping.c_depth = stream->timing.display_color_depth; + stream->clamping.pixel_encoding = stream->timing.pixel_encoding; } static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) @@ -826,7 +826,7 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) &pipe_ctx->pix_clk_params, &pipe_ctx->pll_settings); - pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->public.timing.pixel_encoding; + pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; resource_build_bit_depth_reduction_params(pipe_ctx->stream, &pipe_ctx->stream->bit_depth_params); @@ -844,7 +844,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) { if (stream != NULL && old_context->streams[i] != NULL) { @@ -852,7 +852,7 @@ static enum dc_status build_mapped_resource( resource_build_bit_depth_reduction_params(stream, &stream->bit_depth_params); stream->clamping.pixel_encoding = - stream->public.timing.pixel_encoding; + stream->timing.pixel_encoding; resource_build_bit_depth_reduction_params(stream, &stream->bit_depth_params); @@ -896,8 +896,8 @@ enum dc_status dcn10_validate_with_context( return result; for (i = 0; i < set_count; i++) { - context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); - dc_stream_retain(&context->streams[i]->public); + context->streams[i] = set[i].stream; + dc_stream_retain(context->streams[i]); context->stream_count++; } @@ -929,13 +929,13 @@ enum dc_status dcn10_validate_with_context( enum dc_status dcn10_validate_guaranteed( const struct core_dc *dc, - const struct dc_stream *dc_stream, + struct dc_stream *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; - context->streams[0] = DC_STREAM_TO_CORE(dc_stream); - dc_stream_retain(&context->streams[0]->public); + context->streams[0] = dc_stream; + dc_stream_retain(context->streams[0]); context->stream_count++; result = resource_map_pool_resources(dc, context, NULL); @@ -960,7 +960,7 @@ enum dc_status dcn10_validate_guaranteed( static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( struct validate_context *context, const struct resource_pool *pool, - struct core_stream *stream) + struct dc_stream *stream) { struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 5a47d4c94df6..2ae5a607fb5a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -36,41 +36,18 @@ #include "mpc.h" #endif -struct core_stream; - #define MAX_CLOCK_SOURCES 7 void enable_surface_flip_reporting(struct dc_surface *dc_surface, uint32_t controller_id); -/********* core_stream ************/ #include "grph_object_id.h" #include "link_encoder.h" #include "stream_encoder.h" #include "clock_source.h" #include "audio.h" #include "hw_sequencer_types.h" -#include "opp.h" - -#define DC_STREAM_TO_CORE(dc_stream) container_of( \ - dc_stream, struct core_stream, public) - -struct core_stream { - struct dc_stream public; - - /* field internal to DC */ - struct dc_context *ctx; - struct dc_sink *sink; - /* used by DCP and FMT */ - struct bit_depth_reduction_params bit_depth_params; - struct clamping_and_pixel_encoding_params clamping; - - int phy_pix_clk; - enum signal_type signal; - - struct dc_stream_status status; -}; /************ link *****************/ struct link_init_data { @@ -85,7 +62,7 @@ struct dc_link *link_create(const struct link_init_data *init_params); void link_destroy(struct dc_link **link); enum dc_status dc_link_validate_mode_timing( - const struct core_stream *stream, + const struct dc_stream *stream, struct dc_link *link, const struct dc_crtc_timing *timing); @@ -117,7 +94,7 @@ struct resource_funcs { enum dc_status (*validate_guaranteed)( const struct core_dc *dc, - const struct dc_stream *stream, + struct dc_stream *stream, struct validate_context *context); bool (*validate_bandwidth)( @@ -127,7 +104,7 @@ struct resource_funcs { struct pipe_ctx *(*acquire_idle_pipe_for_layer)( struct validate_context *context, const struct resource_pool *pool, - struct core_stream *stream); + struct dc_stream *stream); }; struct audio_support{ @@ -178,7 +155,7 @@ struct resource_pool { struct pipe_ctx { struct dc_surface *surface; - struct core_stream *stream; + struct dc_stream *stream; struct mem_input *mi; struct input_pixel_processor *ipp; @@ -264,7 +241,7 @@ union bw_context { }; struct validate_context { - struct core_stream *streams[MAX_PIPES]; + struct dc_stream *streams[MAX_PIPES]; struct dc_stream_status stream_status[MAX_PIPES]; uint8_t stream_count; diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h index d9af028a39df..5b4185053e9c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h @@ -30,7 +30,7 @@ #define LINK_TRAINING_RETRY_DELAY 50 /* ms */ struct dc_link; -struct core_stream; +struct dc_stream; struct dc_link_settings; bool dp_hbr_verify_link_cap( @@ -50,7 +50,7 @@ bool dp_validate_mode_timing( const struct dc_crtc_timing *timing); void decide_link_settings( - struct core_stream *stream, + struct dc_stream *stream, struct dc_link_settings *link_setting); bool perform_link_training_with_retries( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 0ee738774f9f..28fb02fb677e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -17,7 +17,6 @@ struct encoder_set_dp_phy_pattern_param; struct link_mst_stream_allocation_table; struct dc_link_settings; struct link_training_settings; -struct core_stream; struct pipe_ctx; struct encoder_init_data { @@ -94,7 +93,7 @@ struct link_encoder { struct link_encoder_funcs { bool (*validate_output_with_stream)( - struct link_encoder *enc, const struct core_stream *stream); + struct link_encoder *enc, const struct dc_stream *stream); void (*hw_init)(struct link_encoder *enc); void (*setup)(struct link_encoder *enc, enum signal_type signal); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index a3eec078dead..b2f7ba2115c9 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -92,7 +92,7 @@ struct hw_sequencer_funcs { bool (*set_output_transfer_func)( struct pipe_ctx *pipe_ctx, - const struct core_stream *stream); + const struct dc_stream *stream); void (*power_down)(struct core_dc *dc); diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index ed94df16a2d3..571bfae62a3c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -103,8 +103,8 @@ void resource_reference_clock_source( struct clock_source *clock_source); bool resource_are_streams_timing_synchronizable( - const struct core_stream *stream1, - const struct core_stream *stream2); + struct dc_stream *stream1, + struct dc_stream *stream2); struct clock_source *resource_find_used_clk_src_for_sharing( struct resource_context *res_ctx, @@ -116,12 +116,12 @@ struct clock_source *dc_resource_find_first_free_pll( struct pipe_ctx *resource_get_head_pipe_for_stream( struct resource_context *res_ctx, - const struct core_stream *stream); + struct dc_stream *stream); bool resource_attach_surfaces_to_context( struct dc_surface *const *surfaces, int surface_count, - const struct dc_stream *dc_stream, + struct dc_stream *dc_stream, struct validate_context *context, const struct resource_pool *pool); @@ -130,10 +130,10 @@ struct pipe_ctx *find_idle_secondary_pipe( const struct resource_pool *pool); bool resource_is_stream_unchanged( - const struct validate_context *old_context, const struct core_stream *stream); + struct validate_context *old_context, struct dc_stream *stream); bool is_stream_unchanged( - const struct core_stream *old_stream, const struct core_stream *stream); + struct dc_stream *old_stream, struct dc_stream *stream); bool resource_validate_attach_surfaces( const struct dc_validation_set set[], @@ -164,7 +164,7 @@ bool pipe_need_reprogram( struct pipe_ctx *pipe_ctx_old, struct pipe_ctx *pipe_ctx); -void resource_build_bit_depth_reduction_params(const struct core_stream *stream, +void resource_build_bit_depth_reduction_params(struct dc_stream *stream, struct bit_depth_reduction_params *fmt_bit_depth); #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c index d312874d95b5..dd024c99fb7e 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c @@ -30,7 +30,7 @@ static bool virtual_link_encoder_validate_output_with_stream( struct link_encoder *enc, - const struct core_stream *stream) { return true; } + const struct dc_stream *stream) { return true; } static void virtual_link_encoder_hw_init(struct link_encoder *enc) {} diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index a989d5de9f3c..358f8a855a59 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -111,7 +111,7 @@ struct freesync_state { }; struct freesync_entity { - const struct dc_stream *stream; + struct dc_stream *stream; struct mod_freesync_caps *caps; struct freesync_state state; struct mod_freesync_user_enable user_enable; @@ -229,7 +229,7 @@ void mod_freesync_destroy(struct mod_freesync *mod_freesync) * on the core_freesync->map and returns the corresponding index */ static unsigned int map_index_from_stream(struct core_freesync *core_freesync, - const struct dc_stream *stream) + struct dc_stream *stream) { unsigned int index = 0; @@ -244,9 +244,8 @@ static unsigned int map_index_from_stream(struct core_freesync *core_freesync, } bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, struct mod_freesync_caps *caps) + struct dc_stream *stream, struct mod_freesync_caps *caps) { - struct core_stream *core_stream = NULL; struct core_dc *core_dc = NULL; struct core_freesync *core_freesync = NULL; int persistent_freesync_enable = 0; @@ -258,7 +257,6 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, return false; core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); - core_stream = DC_STREAM_TO_CORE(stream); core_dc = DC_TO_CORE(core_freesync->dc); flag.save_per_edid = true; @@ -315,7 +313,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, if (caps->supported && nom_refresh_rate_uhz >= caps->min_refresh_in_micro_hz && nom_refresh_rate_uhz <= caps->max_refresh_in_micro_hz) - core_stream->public.ignore_msa_timing_param = 1; + stream->ignore_msa_timing_param = 1; core_freesync->num_entities++; return true; @@ -324,7 +322,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, } bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync, - const struct dc_stream *stream) + struct dc_stream *stream) { int i = 0; struct core_freesync *core_freesync = NULL; @@ -346,14 +344,12 @@ bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync, } static void update_stream_freesync_context(struct core_freesync *core_freesync, - const struct dc_stream *stream) + struct dc_stream *stream) { unsigned int index; struct freesync_context *ctx; - struct core_stream *core_stream; - core_stream = DC_STREAM_TO_CORE(stream); - ctx = &core_stream->public.freesync_ctx; + ctx = &stream->freesync_ctx; index = map_index_from_stream(core_freesync, stream); @@ -372,19 +368,17 @@ static void update_stream_freesync_context(struct core_freesync *core_freesync, } static void update_stream(struct core_freesync *core_freesync, - const struct dc_stream *stream) + struct dc_stream *stream) { - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); - unsigned int index = map_index_from_stream(core_freesync, stream); if (core_freesync->map[index].caps->supported) { - core_stream->public.ignore_msa_timing_param = 1; + stream->ignore_msa_timing_param = 1; update_stream_freesync_context(core_freesync, stream); } } static void calc_freesync_range(struct core_freesync *core_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, struct freesync_state *state, unsigned int min_refresh_in_uhz, unsigned int max_refresh_in_uhz) @@ -458,7 +452,7 @@ static void calc_freesync_range(struct core_freesync *core_freesync, min_frame_duration_in_ns) / 2000; } -static void calc_v_total_from_duration(const struct dc_stream *stream, +static void calc_v_total_from_duration(struct dc_stream *stream, unsigned int duration_in_ns, int *v_total_nominal) { *v_total_nominal = div64_u64(div64_u64(((unsigned long long)( @@ -467,7 +461,7 @@ static void calc_v_total_from_duration(const struct dc_stream *stream, } static void calc_v_total_for_static_ramp(struct core_freesync *core_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, unsigned int index, int *v_total) { unsigned int frame_duration = 0; @@ -563,7 +557,7 @@ static void reset_freesync_state_variables(struct freesync_state* state) * Sets freesync mode on a stream depending on current freesync state. */ static bool set_freesync_on_streams(struct core_freesync *core_freesync, - const struct dc_stream **streams, int num_streams) + struct dc_stream **streams, int num_streams) { int v_total_nominal = 0, v_total_min = 0, v_total_max = 0; unsigned int stream_idx, map_index = 0; @@ -735,7 +729,7 @@ static void set_static_ramp_variables(struct core_freesync *core_freesync, } void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams) + struct dc_stream **streams, int num_streams) { unsigned int index, v_total, inserted_frame_v_total = 0; unsigned int min_frame_duration_in_ns, vmax, vmin = 0; @@ -845,7 +839,7 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, } void mod_freesync_update_state(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams, + struct dc_stream **streams, int num_streams, struct mod_freesync_params *freesync_params) { bool freesync_program_required = false; @@ -935,7 +929,7 @@ void mod_freesync_update_state(struct mod_freesync *mod_freesync, bool mod_freesync_get_state(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, struct mod_freesync_params *freesync_params) { unsigned int index = 0; @@ -971,7 +965,7 @@ bool mod_freesync_get_state(struct mod_freesync *mod_freesync, } bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams, + struct dc_stream **streams, int num_streams, struct mod_freesync_user_enable *user_enable) { unsigned int stream_index, map_index; @@ -1023,7 +1017,7 @@ bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, } bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, struct mod_freesync_user_enable *user_enable) { unsigned int index = 0; @@ -1041,7 +1035,7 @@ bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, } bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, bool *is_ramp_active) { unsigned int index = 0; @@ -1060,7 +1054,7 @@ bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync, } bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, - const struct dc_stream *streams, + struct dc_stream *streams, unsigned int min_refresh, unsigned int max_refresh, struct mod_freesync_caps *caps) @@ -1113,7 +1107,7 @@ bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, } bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, unsigned int *min_refresh, unsigned int *max_refresh) { @@ -1135,7 +1129,7 @@ bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, } bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, unsigned int *vmin, unsigned int *vmax) { @@ -1157,7 +1151,7 @@ bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, } bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, unsigned int *nom_v_pos, unsigned int *v_pos) { @@ -1185,7 +1179,7 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, } void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams) + struct dc_stream **streams, int num_streams) { unsigned int stream_index, map_index; struct freesync_state *state; @@ -1310,7 +1304,7 @@ static void update_timestamps(struct core_freesync *core_freesync, } static void apply_below_the_range(struct core_freesync *core_freesync, - const struct dc_stream *stream, unsigned int map_index, + struct dc_stream *stream, unsigned int map_index, unsigned int last_render_time_in_us) { unsigned int inserted_frame_duration_in_us = 0; @@ -1409,7 +1403,7 @@ static void apply_below_the_range(struct core_freesync *core_freesync, } static void apply_fixed_refresh(struct core_freesync *core_freesync, - const struct dc_stream *stream, unsigned int map_index) + struct dc_stream *stream, unsigned int map_index) { unsigned int vmin = 0, vmax = 0; struct freesync_state *state = &core_freesync->map[map_index].state; @@ -1440,7 +1434,7 @@ static void apply_fixed_refresh(struct core_freesync *core_freesync, } void mod_freesync_pre_update_plane_addresses(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams, + struct dc_stream **streams, int num_streams, unsigned int curr_time_stamp_in_us) { unsigned int stream_index, map_index, last_render_time_in_us = 0; diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h index 53c428b97902..2b9d45100bdd 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h @@ -101,67 +101,67 @@ struct mod_freesync_params { * Add stream to be tracked by module */ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, struct mod_freesync_caps *caps); + struct dc_stream *stream, struct mod_freesync_caps *caps); /* * Remove stream to be tracked by module */ bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync, - const struct dc_stream *stream); + struct dc_stream *stream); /* * Update the freesync state flags for each display and program * freesync accordingly */ void mod_freesync_update_state(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams, + struct dc_stream **streams, int num_streams, struct mod_freesync_params *freesync_params); bool mod_freesync_get_state(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, struct mod_freesync_params *freesync_params); bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams, + struct dc_stream **streams, int num_streams, struct mod_freesync_user_enable *user_enable); bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, struct mod_freesync_user_enable *user_enable); bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, bool *is_ramp_active); bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, - const struct dc_stream *streams, + struct dc_stream *streams, unsigned int min_refresh, unsigned int max_refresh, struct mod_freesync_caps *caps); bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, unsigned int *min_refresh, unsigned int *max_refresh); bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, unsigned int *vmin, unsigned int *vmax); bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, unsigned int *nom_v_pos, unsigned int *v_pos); void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams); + struct dc_stream **streams, int num_streams); void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams); + struct dc_stream **streams, int num_streams); void mod_freesync_pre_update_plane_addresses(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams, + struct dc_stream **streams, int num_streams, unsigned int curr_time_stamp); #endif -- cgit v1.2.3 From 0971c40e180696c3512b9a63ca7ca5161cbfce32 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 27 Jul 2017 09:33:33 -0400 Subject: drm/amd/display: Rename dc_stream to dc_stream_state find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_stream/struct dc_stream_state/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_stream_state_update/struct dc_stream_update/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_stream_state_status/struct dc_stream_status/g' Plus some manual changes Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 42 ++++++------- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 6 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 38 ++++++------ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 18 +++--- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 68 +++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 26 ++++----- drivers/gpu/drm/amd/display/dc/dc.h | 58 +++++++++--------- drivers/gpu/drm/amd/display/dc/dc_types.h | 2 +- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 2 +- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 2 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 4 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 16 ++--- .../drm/amd/display/dc/dce110/dce110_resource.c | 8 +-- .../drm/amd/display/dc/dce112/dce112_resource.c | 8 +-- .../drm/amd/display/dc/dce112/dce112_resource.h | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 4 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 8 +-- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 10 ++-- drivers/gpu/drm/amd/display/dc/dm_helpers.h | 6 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 11 ++-- drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 4 +- .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/resource.h | 13 ++--- .../amd/display/dc/virtual/virtual_link_encoder.c | 2 +- .../drm/amd/display/modules/freesync/freesync.c | 50 ++++++++-------- .../gpu/drm/amd/display/modules/inc/mod_freesync.h | 28 ++++----- 29 files changed, 222 insertions(+), 222 deletions(-) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index af6bed907d10..497104a29d89 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -116,7 +116,8 @@ static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) if (acrtc_state->stream == NULL) { - DRM_ERROR("dc_stream is NULL for crtc '%d'!\n", crtc); + DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", + crtc); return 0; } @@ -137,7 +138,8 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, acrtc->base.state); if (acrtc_state->stream == NULL) { - DRM_ERROR("dc_stream is NULL for crtc '%d'!\n", crtc); + DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", + crtc); return 0; } @@ -1441,7 +1443,7 @@ static int amdgpu_notify_freesync(struct drm_device *dev, void *data, num_streams = dc_get_current_stream_count(adev->dm.dc); for (i = 0; i < num_streams; i++) { - struct dc_stream *stream; + struct dc_stream_state *stream; stream = dc_get_stream_at_index(adev->dm.dc, i); mod_freesync_update_state(adev->dm.freesync_module, @@ -1609,8 +1611,8 @@ struct dm_connector_state { container_of((x), struct dm_connector_state, base) static bool modeset_required(struct drm_crtc_state *crtc_state, - struct dc_stream *new_stream, - struct dc_stream *old_stream) + struct dc_stream_state *new_stream, + struct dc_stream_state *old_stream) { if (dc_is_stream_unchanged(new_stream, old_stream)) { crtc_state->mode_changed = false; @@ -2141,7 +2143,7 @@ struct amdgpu_connector *aconnector_from_drm_crtc_id( static void update_stream_scaling_settings( const struct drm_display_mode *mode, const struct dm_connector_state *dm_state, - struct dc_stream *stream) + struct dc_stream_state *stream) { enum amdgpu_rmx_type rmx_type; @@ -2285,7 +2287,7 @@ static enum dc_color_space get_output_color_space( /*****************************************************************************/ static void fill_stream_properties_from_drm_display_mode( - struct dc_stream *stream, + struct dc_stream_state *stream, const struct drm_display_mode *mode_in, const struct drm_connector *connector) { @@ -2426,14 +2428,14 @@ static void decide_crtc_timing_for_drm_display_mode( } } -static struct dc_stream *create_stream_for_sink( +static struct dc_stream_state *create_stream_for_sink( struct amdgpu_connector *aconnector, const struct drm_display_mode *drm_mode, const struct dm_connector_state *dm_state) { struct drm_display_mode *preferred_mode = NULL; const struct drm_connector *drm_connector; - struct dc_stream *stream = NULL; + struct dc_stream_state *stream = NULL; struct drm_display_mode mode = *drm_mode; bool native_mode_found = false; @@ -2842,7 +2844,7 @@ int amdgpu_dm_connector_mode_valid( struct dc_sink *dc_sink; struct amdgpu_device *adev = connector->dev->dev_private; /* TODO: Unhardcode stream count */ - struct dc_stream *stream; + struct dc_stream_state *stream; struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || @@ -3119,7 +3121,7 @@ int dm_create_validation_set_for_connector(struct drm_connector *connector, struct dc_sink *dc_sink = to_amdgpu_connector(connector)->dc_sink; /* TODO: Unhardcode stream count */ - struct dc_stream *stream; + struct dc_stream_state *stream; if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || (mode->flags & DRM_MODE_FLAG_DBLSCAN)) @@ -3770,7 +3772,7 @@ static bool is_scaling_state_different( static void remove_stream( struct amdgpu_device *adev, struct amdgpu_crtc *acrtc, - struct dc_stream *stream) + struct dc_stream_state *stream) { /* this is the update mode case */ if (adev->dm.freesync_module) @@ -3925,7 +3927,7 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, uint32_t i; struct drm_plane *plane; struct drm_plane_state *old_plane_state; - struct dc_stream *dc_stream_attach; + struct dc_stream_state *dc_stream_attach; struct dc_plane_state *dc_surfaces_constructed[MAX_SURFACES]; struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state); @@ -4061,7 +4063,7 @@ void amdgpu_dm_atomic_commit_tail( struct drm_crtc *crtc, *pcrtc; struct drm_crtc_state *old_crtc_state; struct amdgpu_crtc *new_crtcs[MAX_STREAMS]; - struct dc_stream *new_stream = NULL; + struct dc_stream_state *new_stream = NULL; unsigned long flags; bool wait_for_vblank = true; struct drm_connector *connector; @@ -4220,7 +4222,7 @@ void amdgpu_dm_atomic_commit_tail( new_acrtc_state = to_dm_crtc_state(acrtc->base.state); update_stream_scaling_settings(&con_new_state->base.crtc->mode, - con_new_state, (struct dc_stream *)new_acrtc_state->stream); + con_new_state, (struct dc_stream_state *)new_acrtc_state->stream); status = dc_stream_get_status(new_acrtc_state->stream); WARN_ON(!status); @@ -4376,7 +4378,7 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector static uint32_t add_val_sets_surface( struct dc_validation_set *val_sets, uint32_t set_count, - const struct dc_stream *stream, + const struct dc_stream_state *stream, struct dc_plane_state *surface) { uint32_t i = 0, j = 0; @@ -4399,8 +4401,8 @@ static uint32_t add_val_sets_surface( static uint32_t update_in_val_sets_stream( struct dc_validation_set *val_sets, uint32_t set_count, - struct dc_stream *old_stream, - struct dc_stream *new_stream, + struct dc_stream_state *old_stream, + struct dc_stream_state *new_stream, struct drm_crtc *crtc) { uint32_t i = 0; @@ -4423,7 +4425,7 @@ static uint32_t update_in_val_sets_stream( static uint32_t remove_from_val_sets( struct dc_validation_set *val_sets, uint32_t set_count, - const struct dc_stream *stream) + const struct dc_stream_state *stream) { int i; @@ -4545,7 +4547,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, for_each_crtc_in_state(state, crtc, crtc_state, i) { struct amdgpu_crtc *acrtc = NULL; struct amdgpu_connector *aconnector = NULL; - struct dc_stream *new_stream = NULL; + struct dc_stream_state *new_stream = NULL; struct drm_connector_state *conn_state = NULL; struct dm_connector_state *dm_conn_state = NULL; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index dcf1f77390a8..cca65a37b213 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -201,7 +201,7 @@ struct dm_plane_state { struct dm_crtc_state { struct drm_crtc_state base; - struct dc_stream *stream; + struct dc_stream_state *stream; }; #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 0a615583de63..4a124537dc9a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -174,7 +174,7 @@ static void get_payload_table( */ bool dm_helpers_dp_mst_write_payload_allocation_table( struct dc_context *ctx, - const struct dc_stream *stream, + const struct dc_stream_state *stream, struct dp_mst_stream_allocation_table *proposed_table, bool enable) { @@ -264,7 +264,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( */ bool dm_helpers_dp_mst_poll_for_allocation_change_trigger( struct dc_context *ctx, - const struct dc_stream *stream) + const struct dc_stream_state *stream) { struct amdgpu_connector *aconnector; struct drm_dp_mst_topology_mgr *mst_mgr; @@ -290,7 +290,7 @@ bool dm_helpers_dp_mst_poll_for_allocation_change_trigger( bool dm_helpers_dp_mst_send_payload_allocation( struct dc_context *ctx, - const struct dc_stream *stream, + const struct dc_stream_state *stream, bool enable) { struct amdgpu_connector *aconnector; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 500788c35d70..8b6b7631d776 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -149,12 +149,12 @@ failed_alloc: } static bool stream_adjust_vmin_vmax(struct dc *dc, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, int vmin, int vmax) { /* TODO: Support multiple streams */ struct core_dc *core_dc = DC_TO_CORE(dc); - struct dc_stream *stream = streams[0]; + struct dc_stream_state *stream = streams[0]; int i = 0; bool ret = false; @@ -175,12 +175,12 @@ static bool stream_adjust_vmin_vmax(struct dc *dc, } static bool stream_get_crtc_position(struct dc *dc, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, unsigned int *v_pos, unsigned int *nom_v_pos) { /* TODO: Support multiple streams */ struct core_dc *core_dc = DC_TO_CORE(dc); - struct dc_stream *stream = streams[0]; + struct dc_stream_state *stream = streams[0]; int i = 0; bool ret = false; struct crtc_position position; @@ -200,7 +200,7 @@ static bool stream_get_crtc_position(struct dc *dc, return ret; } -static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream) +static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); int i = 0; @@ -218,7 +218,7 @@ static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream) return ret; } -static bool program_csc_matrix(struct dc *dc, struct dc_stream *stream) +static bool program_csc_matrix(struct dc *dc, struct dc_stream_state *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); int i = 0; @@ -241,7 +241,7 @@ static bool program_csc_matrix(struct dc *dc, struct dc_stream *stream) } static void set_static_screen_events(struct dc *dc, - struct dc_stream **streams, + struct dc_stream_state **streams, int num_streams, const struct dc_static_screen_events *events) { @@ -252,7 +252,7 @@ static void set_static_screen_events(struct dc *dc, int num_pipes_affected = 0; for (i = 0; i < num_streams; i++) { - struct dc_stream *stream = streams[i]; + struct dc_stream_state *stream = streams[i]; for (j = 0; j < MAX_PIPES; j++) { if (core_dc->current_context->res_ctx.pipe_ctx[j].stream @@ -333,7 +333,7 @@ static void set_test_pattern( cust_pattern_size); } -void set_dither_option(struct dc_stream *stream, +void set_dither_option(struct dc_stream_state *stream, enum dc_dither_option option) { struct bit_depth_reduction_params params; @@ -769,7 +769,7 @@ context_alloc_fail: bool dc_validate_guaranteed( const struct dc *dc, - struct dc_stream *stream) + struct dc_stream_state *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); enum dc_status result = DC_ERROR_UNEXPECTED; @@ -893,7 +893,7 @@ static bool context_changed( static bool streams_changed( struct core_dc *dc, - struct dc_stream *streams[], + struct dc_stream_state *streams[], uint8_t stream_count) { uint8_t i; @@ -912,7 +912,7 @@ static bool streams_changed( bool dc_enable_stereo( struct dc *dc, struct validate_context *context, - struct dc_stream *streams[], + struct dc_stream_state *streams[], uint8_t stream_count) { bool ret = true; @@ -958,7 +958,7 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c enum dc_status result = DC_ERROR_UNEXPECTED; struct pipe_ctx *pipe; int i, j, k, l; - struct dc_stream *dc_streams[MAX_STREAMS] = {0}; + struct dc_stream_state *dc_streams[MAX_STREAMS] = {0}; for (i = 0; i < context->stream_count; i++) dc_streams[i] = context->streams[i]; @@ -1031,7 +1031,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context) __func__, context->stream_count); for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; dc_stream_log(stream, core_dc->ctx->logger, @@ -1046,7 +1046,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context) bool dc_commit_streams( struct dc *dc, - struct dc_stream *streams[], + struct dc_stream_state *streams[], uint8_t stream_count) { struct core_dc *core_dc = DC_TO_CORE(dc); @@ -1062,7 +1062,7 @@ bool dc_commit_streams( __func__, stream_count); for (i = 0; i < stream_count; i++) { - struct dc_stream *stream = streams[i]; + struct dc_stream_state *stream = streams[i]; struct dc_stream_status *status = dc_stream_get_status(stream); int j; @@ -1138,7 +1138,7 @@ bool dc_commit_surfaces_to_stream( struct dc *dc, struct dc_plane_state **new_surfaces, uint8_t new_surface_count, - struct dc_stream *dc_stream) + struct dc_stream_state *dc_stream) { struct dc_surface_update updates[MAX_SURFACES]; struct dc_flip_addrs flip_addr[MAX_SURFACES]; @@ -1395,7 +1395,7 @@ enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL; void dc_update_surfaces_and_stream(struct dc *dc, struct dc_surface_update *srf_updates, int surface_count, - struct dc_stream *stream, + struct dc_stream_state *stream, struct dc_stream_update *stream_update) { struct core_dc *core_dc = DC_TO_CORE(dc); @@ -1723,7 +1723,7 @@ uint8_t dc_get_current_stream_count(const struct dc *dc) return core_dc->current_context->stream_count; } -struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i) +struct dc_stream_state *dc_get_stream_at_index(const struct dc *dc, uint8_t i) { struct core_dc *core_dc = DC_TO_CORE(dc); if (i < core_dc->current_context->stream_count) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index a983a5ee3172..7a2fe2f3e65c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1143,7 +1143,7 @@ static void dpcd_configure_panel_mode( static void enable_stream_features(struct pipe_ctx *pipe_ctx) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; union down_spread_ctrl downspread; @@ -1159,7 +1159,7 @@ static void enable_stream_features(struct pipe_ctx *pipe_ctx) static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; enum dc_status status; bool skip_video_pattern; struct dc_link *link = stream->sink->link; @@ -1250,7 +1250,7 @@ static enum dc_status enable_link_dp_mst(struct pipe_ctx *pipe_ctx) static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; enum dc_color_depth display_color_depth; @@ -1341,7 +1341,7 @@ static void disable_link(struct dc_link *link, enum signal_type signal) } enum dc_status dc_link_validate_mode_timing( - const struct dc_stream *stream, + const struct dc_stream_state *stream, struct dc_link *link, const struct dc_crtc_timing *timing) { @@ -1374,7 +1374,7 @@ enum dc_status dc_link_validate_mode_timing( bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, - uint32_t frame_ramp, const struct dc_stream *stream) + uint32_t frame_ramp, const struct dc_stream_state *stream) { struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); struct abm *abm = core_dc->res_pool->abm; @@ -1450,7 +1450,7 @@ bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state) } bool dc_link_setup_psr(struct dc_link *link, - const struct dc_stream *stream, struct psr_config *psr_config, + const struct dc_stream_state *stream, struct psr_config *psr_config, struct psr_context *psr_context) { struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); @@ -1587,7 +1587,7 @@ void core_link_resume(struct dc_link *link) program_hpd_filter(link); } -static struct fixed31_32 get_pbn_per_slot(struct dc_stream *stream) +static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) { struct dc_link_settings *link_settings = &stream->sink->link->cur_link_settings; @@ -1696,7 +1696,7 @@ static void update_mst_stream_alloc_table( */ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; struct link_encoder *link_encoder = link->link_enc; struct stream_encoder *stream_encoder = pipe_ctx->stream_enc; @@ -1778,7 +1778,7 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; struct link_encoder *link_encoder = link->link_enc; struct stream_encoder *stream_encoder = pipe_ctx->stream_enc; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 17506345f97a..50724f9a8e2c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -1433,7 +1433,7 @@ bool dp_validate_mode_timing( return false; } -void decide_link_settings(struct dc_stream *stream, +void decide_link_settings(struct dc_stream_state *stream, struct dc_link_settings *link_setting) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index fd1d6be79fee..ce0415f26600 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -294,8 +294,8 @@ void resource_reference_clock_source( } bool resource_are_streams_timing_synchronizable( - struct dc_stream *stream1, - struct dc_stream *stream2) + struct dc_stream_state *stream1, + struct dc_stream_state *stream2) { if (stream1->timing.h_total != stream2->timing.h_total) return false; @@ -431,7 +431,7 @@ static void rect_swap_helper(struct rect *rect) static void calculate_viewport(struct pipe_ctx *pipe_ctx) { const struct dc_plane_state *surface = pipe_ctx->surface; - const struct dc_stream *stream = pipe_ctx->stream; + const struct dc_stream_state *stream = pipe_ctx->stream; struct scaler_data *data = &pipe_ctx->scl_data; struct rect surf_src = surface->src_rect; struct rect clip = { 0 }; @@ -530,7 +530,7 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip) { const struct dc_plane_state *surface = pipe_ctx->surface; - const struct dc_stream *stream = pipe_ctx->stream; + const struct dc_stream_state *stream = pipe_ctx->stream; struct rect surf_src = surface->src_rect; struct rect surf_clip = surface->clip_rect; int recout_full_x, recout_full_y; @@ -608,7 +608,7 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) { const struct dc_plane_state *surface = pipe_ctx->surface; - const struct dc_stream *stream = pipe_ctx->stream; + const struct dc_stream_state *stream = pipe_ctx->stream; struct rect surf_src = surface->src_rect; const int in_w = stream->src.width; const int in_h = stream->src.height; @@ -920,7 +920,7 @@ struct pipe_ctx *find_idle_secondary_pipe( struct pipe_ctx *resource_get_head_pipe_for_stream( struct resource_context *res_ctx, - struct dc_stream *stream) + struct dc_stream_state *stream) { int i; for (i = 0; i < MAX_PIPES; i++) { @@ -940,7 +940,7 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( static struct pipe_ctx *acquire_free_pipe_for_stream( struct validate_context *context, const struct resource_pool *pool, - struct dc_stream *stream) + struct dc_stream_state *stream) { int i; struct resource_context *res_ctx = &context->res_ctx; @@ -979,7 +979,7 @@ static struct pipe_ctx *acquire_free_pipe_for_stream( static void release_free_pipes_for_stream( struct resource_context *res_ctx, - struct dc_stream *stream) + struct dc_stream_state *stream) { int i; @@ -997,7 +997,7 @@ static void release_free_pipes_for_stream( static int acquire_first_split_pipe( struct resource_context *res_ctx, const struct resource_pool *pool, - struct dc_stream *stream) + struct dc_stream_state *stream) { int i; @@ -1030,7 +1030,7 @@ static int acquire_first_split_pipe( bool resource_attach_surfaces_to_context( struct dc_plane_state * const *surfaces, int surface_count, - struct dc_stream *stream, + struct dc_stream_state *stream, struct validate_context *context, const struct resource_pool *pool) { @@ -1118,8 +1118,8 @@ bool resource_attach_surfaces_to_context( } -static bool is_timing_changed(struct dc_stream *cur_stream, - struct dc_stream *new_stream) +static bool is_timing_changed(struct dc_stream_state *cur_stream, + struct dc_stream_state *new_stream) { if (cur_stream == NULL) return true; @@ -1141,7 +1141,7 @@ static bool is_timing_changed(struct dc_stream *cur_stream, } static bool are_stream_backends_same( - struct dc_stream *stream_a, struct dc_stream *stream_b) + struct dc_stream_state *stream_a, struct dc_stream_state *stream_b) { if (stream_a == stream_b) return true; @@ -1156,7 +1156,7 @@ static bool are_stream_backends_same( } bool dc_is_stream_unchanged( - struct dc_stream *old_stream, struct dc_stream *stream) + struct dc_stream_state *old_stream, struct dc_stream_state *stream) { if (!are_stream_backends_same(old_stream, stream)) @@ -1233,7 +1233,7 @@ static void set_audio_in_use( static int acquire_first_free_pipe( struct resource_context *res_ctx, const struct resource_pool *pool, - struct dc_stream *stream) + struct dc_stream_state *stream) { int i; @@ -1260,7 +1260,7 @@ static int acquire_first_free_pipe( static struct stream_encoder *find_first_free_match_stream_enc_for_link( struct resource_context *res_ctx, const struct resource_pool *pool, - struct dc_stream *stream) + struct dc_stream_state *stream) { int i; int j = -1; @@ -1311,7 +1311,7 @@ static struct audio *find_first_free_audio( return 0; } -static void update_stream_signal(struct dc_stream *stream) +static void update_stream_signal(struct dc_stream_state *stream) { if (stream->output_signal == SIGNAL_TYPE_NONE) { struct dc_sink *dc_sink = stream->sink; @@ -1334,12 +1334,12 @@ static void update_stream_signal(struct dc_stream *stream) } bool resource_is_stream_unchanged( - struct validate_context *old_context, struct dc_stream *stream) + struct validate_context *old_context, struct dc_stream_state *stream) { int i; for (i = 0; i < old_context->stream_count; i++) { - struct dc_stream *old_stream = old_context->streams[i]; + struct dc_stream_state *old_stream = old_context->streams[i]; if (are_stream_backends_same(old_stream, stream)) return true; @@ -1352,7 +1352,7 @@ static void copy_pipe_ctx( const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx) { struct dc_plane_state *surface = to_pipe_ctx->surface; - struct dc_stream *stream = to_pipe_ctx->stream; + struct dc_stream_state *stream = to_pipe_ctx->stream; *to_pipe_ctx = *from_pipe_ctx; to_pipe_ctx->stream = stream; @@ -1360,14 +1360,14 @@ static void copy_pipe_ctx( to_pipe_ctx->surface = surface; } -static struct dc_stream *find_pll_sharable_stream( - struct dc_stream *stream_needs_pll, +static struct dc_stream_state *find_pll_sharable_stream( + struct dc_stream_state *stream_needs_pll, struct validate_context *context) { int i; for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream_has_pll = context->streams[i]; + struct dc_stream_state *stream_has_pll = context->streams[i]; /* We are looking for non dp, non virtual stream */ if (resource_are_streams_timing_synchronizable( @@ -1411,7 +1411,7 @@ static int get_norm_pix_clk(const struct dc_crtc_timing *timing) return normalized_pix_clk; } -static void calculate_phy_pix_clks(struct dc_stream *stream) +static void calculate_phy_pix_clks(struct dc_stream_state *stream) { update_stream_signal(stream); @@ -1433,7 +1433,7 @@ enum dc_status resource_map_pool_resources( int i, j; for (i = 0; old_context && i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (!resource_is_stream_unchanged(old_context, stream)) { if (stream != NULL && old_context->streams[i] != NULL) { @@ -1486,7 +1486,7 @@ enum dc_status resource_map_pool_resources( } for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; struct pipe_ctx *pipe_ctx = NULL; int pipe_idx = -1; @@ -1581,7 +1581,7 @@ static void set_avi_info_frame( struct encoder_info_packet *info_packet, struct pipe_ctx *pipe_ctx) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; enum dc_color_space color_space = COLOR_SPACE_UNKNOWN; struct info_frame info_frame = { {0} }; uint32_t pixel_encoding = 0; @@ -1821,7 +1821,7 @@ static void set_avi_info_frame( static void set_vendor_info_packet( struct encoder_info_packet *info_packet, - struct dc_stream *stream) + struct dc_stream_state *stream) { uint32_t length = 0; bool hdmi_vic_mode = false; @@ -1934,7 +1934,7 @@ static void set_vendor_info_packet( static void set_spd_info_packet( struct encoder_info_packet *info_packet, - struct dc_stream *stream) + struct dc_stream_state *stream) { /* SPD info packet for FreeSync */ @@ -2056,7 +2056,7 @@ static void set_spd_info_packet( static void set_hdr_static_info_packet( struct encoder_info_packet *info_packet, struct dc_plane_state *surface, - struct dc_stream *stream) + struct dc_stream_state *stream) { uint16_t i = 0; enum signal_type signal = stream->signal; @@ -2159,7 +2159,7 @@ static void set_hdr_static_info_packet( static void set_vsc_info_packet( struct encoder_info_packet *info_packet, - struct dc_stream *stream) + struct dc_stream_state *stream) { unsigned int vscPacketRevision = 0; unsigned int i; @@ -2312,7 +2312,7 @@ enum dc_status resource_map_clock_resources( /* acquire new resources */ for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -2392,7 +2392,7 @@ bool pipe_need_reprogram( return false; } -void resource_build_bit_depth_reduction_params(struct dc_stream *stream, +void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, struct bit_depth_reduction_params *fmt_bit_depth) { enum dc_dither_option option = stream->dither_option; @@ -2502,7 +2502,7 @@ void resource_build_bit_depth_reduction_params(struct dc_stream *stream, fmt_bit_depth->pixel_encoding = pixel_encoding; } -bool dc_validate_stream(const struct dc *dc, struct dc_stream *stream) +bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); struct dc_context *dc_ctx = core_dc->ctx; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index a77e1e80d7c2..7a87f38f2324 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -34,7 +34,7 @@ * Private functions ******************************************************************************/ -static bool construct(struct dc_stream *stream, +static bool construct(struct dc_stream_state *stream, struct dc_sink *dc_sink_data) { uint32_t i = 0; @@ -84,7 +84,7 @@ static bool construct(struct dc_stream *stream, return true; } -static void destruct(struct dc_stream *stream) +static void destruct(struct dc_stream_state *stream) { dc_sink_release(stream->sink); if (stream->out_transfer_func != NULL) { @@ -94,14 +94,14 @@ static void destruct(struct dc_stream *stream) } } -void dc_stream_retain(struct dc_stream *stream) +void dc_stream_retain(struct dc_stream_state *stream) { ASSERT(stream->ref_count > 0); stream->ref_count++; } -void dc_stream_release(struct dc_stream *stream) +void dc_stream_release(struct dc_stream_state *stream) { if (stream != NULL) { @@ -115,15 +115,15 @@ void dc_stream_release(struct dc_stream *stream) } } -struct dc_stream *dc_create_stream_for_sink( +struct dc_stream_state *dc_create_stream_for_sink( struct dc_sink *sink) { - struct dc_stream *stream; + struct dc_stream_state *stream; if (sink == NULL) goto alloc_fail; - stream = dm_alloc(sizeof(struct dc_stream)); + stream = dm_alloc(sizeof(struct dc_stream_state)); if (NULL == stream) goto alloc_fail; @@ -143,7 +143,7 @@ alloc_fail: } struct dc_stream_status *dc_stream_get_status( - struct dc_stream *stream) + struct dc_stream_state *stream) { uint8_t i; struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); @@ -161,7 +161,7 @@ struct dc_stream_status *dc_stream_get_status( * Update the cursor attributes and set cursor surface address */ bool dc_stream_set_cursor_attributes( - const struct dc_stream *stream, + const struct dc_stream_state *stream, const struct dc_cursor_attributes *attributes) { int i; @@ -196,7 +196,7 @@ bool dc_stream_set_cursor_attributes( } bool dc_stream_set_cursor_position( - struct dc_stream *stream, + struct dc_stream_state *stream, const struct dc_cursor_position *position) { int i; @@ -245,7 +245,7 @@ bool dc_stream_set_cursor_position( return true; } -uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream) +uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) { uint8_t i; struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); @@ -264,7 +264,7 @@ uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream) return 0; } -bool dc_stream_get_scanoutpos(const struct dc_stream *stream, +bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, uint32_t *v_blank_start, uint32_t *v_blank_end, uint32_t *h_position, @@ -297,7 +297,7 @@ bool dc_stream_get_scanoutpos(const struct dc_stream *stream, void dc_stream_log( - const struct dc_stream *stream, + const struct dc_stream_state *stream, struct dal_logger *dm_logger, enum dc_log_type log_type) { diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d1943b9644d4..ab805965e321 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -101,30 +101,30 @@ struct dc_cap_funcs { struct dc_surface_dcc_cap *output); }; -struct dc_stream_funcs { +struct dc_stream_state_funcs { bool (*adjust_vmin_vmax)(struct dc *dc, - struct dc_stream **stream, + struct dc_stream_state **stream, int num_streams, int vmin, int vmax); bool (*get_crtc_position)(struct dc *dc, - struct dc_stream **stream, + struct dc_stream_state **stream, int num_streams, unsigned int *v_pos, unsigned int *nom_v_pos); bool (*set_gamut_remap)(struct dc *dc, - const struct dc_stream *stream); + const struct dc_stream_state *stream); bool (*program_csc_matrix)(struct dc *dc, - struct dc_stream *stream); + struct dc_stream_state *stream); void (*set_static_screen_events)(struct dc *dc, - struct dc_stream **stream, + struct dc_stream_state **stream, int num_streams, const struct dc_static_screen_events *events); - void (*set_dither_option)(struct dc_stream *stream, + void (*set_dither_option)(struct dc_stream_state *stream, enum dc_dither_option option); }; @@ -190,7 +190,7 @@ struct dc_debug { struct dc { struct dc_caps caps; struct dc_cap_funcs cap_funcs; - struct dc_stream_funcs stream_funcs; + struct dc_stream_state_funcs stream_funcs; struct dc_link_funcs link_funcs; struct dc_config config; struct dc_debug debug; @@ -426,7 +426,7 @@ bool dc_commit_surfaces_to_stream( struct dc *dc, struct dc_plane_state **dc_surfaces, uint8_t surface_count, - struct dc_stream *stream); + struct dc_stream_state *stream); bool dc_post_update_surfaces_to_stream( struct dc *dc); @@ -478,7 +478,7 @@ struct dc_stream_status { struct dc_link *link; }; -struct dc_stream { +struct dc_stream_state { struct dc_sink *sink; struct dc_crtc_timing timing; @@ -529,7 +529,7 @@ struct dc_stream_update { }; bool dc_is_stream_unchanged( - struct dc_stream *old_stream, struct dc_stream *stream); + struct dc_stream_state *old_stream, struct dc_stream_state *stream); /* * Setup stream attributes if no stream updates are provided @@ -548,30 +548,30 @@ bool dc_is_stream_unchanged( void dc_update_surfaces_and_stream(struct dc *dc, struct dc_surface_update *surface_updates, int surface_count, - struct dc_stream *dc_stream, + struct dc_stream_state *dc_stream, struct dc_stream_update *stream_update); /* * Log the current stream state. */ void dc_stream_log( - const struct dc_stream *stream, + const struct dc_stream_state *stream, struct dal_logger *dc_logger, enum dc_log_type log_type); uint8_t dc_get_current_stream_count(const struct dc *dc); -struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i); +struct dc_stream_state *dc_get_stream_at_index(const struct dc *dc, uint8_t i); /* * Return the current frame counter. */ -uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream); +uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream); /* TODO: Return parsed values rather than direct register read * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos) * being refactored properly to be dce-specific */ -bool dc_stream_get_scanoutpos(const struct dc_stream *stream, +bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, uint32_t *v_blank_start, uint32_t *v_blank_end, uint32_t *h_position, @@ -581,12 +581,12 @@ bool dc_stream_get_scanoutpos(const struct dc_stream *stream, * Structure to store surface/stream associations for validation */ struct dc_validation_set { - struct dc_stream *stream; + struct dc_stream_state *stream; struct dc_plane_state *surfaces[MAX_SURFACES]; uint8_t surface_count; }; -bool dc_validate_stream(const struct dc *dc, struct dc_stream *stream); +bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream); bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_state); /* @@ -615,7 +615,7 @@ bool dc_validate_resources( bool dc_validate_guaranteed( const struct dc *dc, - struct dc_stream *stream); + struct dc_stream_state *stream); void dc_resource_validate_ctx_copy_construct( const struct validate_context *src_ctx, @@ -644,7 +644,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context); */ bool dc_commit_streams( struct dc *dc, - struct dc_stream *streams[], + struct dc_stream_state *streams[], uint8_t stream_count); /* * Enable stereo when commit_streams is not required, @@ -653,19 +653,19 @@ bool dc_commit_streams( bool dc_enable_stereo( struct dc *dc, struct validate_context *context, - struct dc_stream *streams[], + struct dc_stream_state *streams[], uint8_t stream_count); /** * Create a new default stream for the requested sink */ -struct dc_stream *dc_create_stream_for_sink(struct dc_sink *dc_sink); +struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink); -void dc_stream_retain(struct dc_stream *dc_stream); -void dc_stream_release(struct dc_stream *dc_stream); +void dc_stream_retain(struct dc_stream_state *dc_stream); +void dc_stream_release(struct dc_stream_state *dc_stream); struct dc_stream_status *dc_stream_get_status( - struct dc_stream *dc_stream); + struct dc_stream_state *dc_stream); enum surface_update_type dc_check_update_surfaces_for_stream( struct dc *dc, @@ -804,7 +804,7 @@ const struct graphics_object_id dc_get_link_id_at_index( /* Set backlight level of an embedded panel (eDP, LVDS). */ bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, - uint32_t frame_ramp, const struct dc_stream *stream); + uint32_t frame_ramp, const struct dc_stream_state *stream); bool dc_link_set_abm_disable(const struct dc_link *dc_link); @@ -813,7 +813,7 @@ bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable); bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state); bool dc_link_setup_psr(struct dc_link *dc_link, - const struct dc_stream *stream, struct psr_config *psr_config, + const struct dc_stream_state *stream, struct psr_config *psr_config, struct psr_context *psr_context); /* Request DC to detect if there is a Panel connected. @@ -927,11 +927,11 @@ bool dc_sink_set_container_id(struct dc_sink *dc_sink, const struct dc_container ******************************************************************************/ /* TODO: Deprecated once we switch to dc_set_cursor_position */ bool dc_stream_set_cursor_attributes( - const struct dc_stream *stream, + const struct dc_stream_state *stream, const struct dc_cursor_attributes *attributes); bool dc_stream_set_cursor_position( - struct dc_stream *stream, + struct dc_stream_state *stream, const struct dc_cursor_position *position); /* Newer interfaces */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 4fb9584452a4..a47f7472ea92 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -35,7 +35,7 @@ /* forward declarations */ struct dc_plane_state; -struct dc_stream; +struct dc_stream_state; struct dc_link; struct dc_sink; struct dal; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index 24d0c48258ee..5bb2ac71f297 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -1009,7 +1009,7 @@ bool dce110_link_encoder_construct( bool dce110_link_encoder_validate_output_with_stream( struct link_encoder *enc, - const struct dc_stream *stream) + const struct dc_stream_state *stream) { struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); bool is_valid; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index 5f05ca65281e..5960fb933f1f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -196,7 +196,7 @@ bool dce110_link_encoder_validate_wireless_output( bool dce110_link_encoder_validate_output_with_stream( struct link_encoder *enc, - const struct dc_stream *stream); + const struct dc_stream_state *stream); /****************** HW programming ************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 2cf2fefc3d79..98fb7f02a6fe 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -660,7 +660,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -765,7 +765,7 @@ enum dc_status dce100_validate_with_context( enum dc_status dce100_validate_guaranteed( const struct core_dc *dc, - struct dc_stream *dc_stream, + struct dc_stream_state *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 84dc8916de96..e4310a376116 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -623,7 +623,7 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func static bool dce110_set_output_transfer_func( struct pipe_ctx *pipe_ctx, - const struct dc_stream *stream) + const struct dc_stream_state *stream) { struct transform *xfm = pipe_ctx->xfm; @@ -745,7 +745,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) void dce110_disable_stream(struct pipe_ctx *pipe_ctx) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; if (pipe_ctx->audio) { @@ -833,7 +833,7 @@ static void build_audio_output( const struct pipe_ctx *pipe_ctx, struct audio_output *audio_output) { - const struct dc_stream *stream = pipe_ctx->stream; + const struct dc_stream_state *stream = pipe_ctx->stream; audio_output->engine_id = pipe_ctx->stream_enc->id; audio_output->signal = pipe_ctx->stream->signal; @@ -981,7 +981,7 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( struct validate_context *context, struct core_dc *dc) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. pipe_ctx[pipe_ctx->pipe_idx]; struct tg_color black_color = {0}; @@ -1037,7 +1037,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( struct validate_context *context, struct core_dc *dc) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. pipe_ctx[pipe_ctx->pipe_idx]; @@ -1229,7 +1229,7 @@ void dce110_enable_accelerated_mode(struct core_dc *dc) static uint32_t compute_pstate_blackout_duration( struct bw_fixed blackout_duration, - const struct dc_stream *stream) + const struct dc_stream_state *stream) { uint32_t total_dest_line_time_ns; uint32_t pstate_blackout_duration_ns; @@ -2325,7 +2325,7 @@ void dce110_fill_display_configs( for (j = 0; j < context->stream_count; j++) { int k; - const struct dc_stream *stream = context->streams[j]; + const struct dc_stream_state *stream = context->streams[j]; struct dm_pp_single_disp_config *cfg = &pp_display_cfg->disp_configs[num_cfgs]; const struct pipe_ctx *pipe_ctx = NULL; @@ -2370,7 +2370,7 @@ uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context) uint32_t min_vertical_blank_time = -1; for (j = 0; j < context->stream_count; j++) { - struct dc_stream *stream = context->streams[j]; + struct dc_stream_state *stream = context->streams[j]; uint32_t vertical_blank_in_pixels = 0; uint32_t vertical_blank_time = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 5c1790b61290..89b21bd57a35 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -718,7 +718,7 @@ static void get_pixel_clock_parameters( const struct pipe_ctx *pipe_ctx, struct pixel_clk_params *pixel_clk_params) { - const struct dc_stream *stream = pipe_ctx->stream; + const struct dc_stream_state *stream = pipe_ctx->stream; /*TODO: is this halved for YCbCr 420? in that case we might want to move * the pixel clock normalization for hdmi up to here instead of doing it @@ -780,7 +780,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -973,7 +973,7 @@ enum dc_status dce110_validate_with_context( enum dc_status dce110_validate_guaranteed( const struct core_dc *dc, - struct dc_stream *dc_stream, + struct dc_stream_state *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; @@ -1006,7 +1006,7 @@ enum dc_status dce110_validate_guaranteed( static struct pipe_ctx *dce110_acquire_underlay( struct validate_context *context, const struct resource_pool *pool, - struct dc_stream *stream) + struct dc_stream_state *stream) { struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); struct resource_context *res_ctx = &context->res_ctx; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index c68372fa1292..68554d6edd94 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -700,7 +700,7 @@ static void destruct(struct dce110_resource_pool *pool) static struct clock_source *find_matching_pll( struct resource_context *res_ctx, const struct resource_pool *pool, - const struct dc_stream *const stream) + const struct dc_stream_state *const stream) { switch (stream->sink->link->link_enc->transmitter) { case TRANSMITTER_UNIPHY_A: @@ -731,7 +731,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -845,7 +845,7 @@ enum dc_status resource_map_phy_clock_resources( /* acquire new resources */ for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -949,7 +949,7 @@ enum dc_status dce112_validate_with_context( enum dc_status dce112_validate_guaranteed( const struct core_dc *dc, - struct dc_stream *stream, + struct dc_stream_state *stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h index cb2c69fb05a6..feef559f1ecd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h @@ -44,7 +44,7 @@ enum dc_status dce112_validate_with_context( enum dc_status dce112_validate_guaranteed( const struct core_dc *dc, - struct dc_stream *dc_stream, + struct dc_stream_state *dc_stream, struct validate_context *context); bool dce112_validate_bandwidth( diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index bcb66447b558..734b35eddeed 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -677,7 +677,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -781,7 +781,7 @@ enum dc_status dce80_validate_with_context( enum dc_status dce80_validate_guaranteed( const struct core_dc *dc, - struct dc_stream *dc_stream, + struct dc_stream_state *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 3979cb03cf8d..866f63d1259d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -679,7 +679,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( struct validate_context *context, struct core_dc *dc) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; enum dc_color_space color_space; struct tg_color black_color = {0}; bool enableStereo = stream->timing.timing_3d_format == TIMING_3D_FORMAT_NONE ? @@ -1445,7 +1445,7 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func static bool dcn10_set_output_transfer_func( struct pipe_ctx *pipe_ctx, - const struct dc_stream *stream) + const struct dc_stream_state *stream) { struct transform *xfm = pipe_ctx->xfm; @@ -2321,7 +2321,7 @@ static void set_plane_config( } static void dcn10_config_stereo_parameters( - struct dc_stream *stream, struct crtc_stereo_flags *flags) + struct dc_stream_state *stream, struct crtc_stereo_flags *flags) { enum view_3d_format view_format = stream->view_format; enum dc_timing_3d_format timing_3d_format =\ @@ -2360,7 +2360,7 @@ static void dcn10_config_stereo_parameters( static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc) { struct crtc_stereo_flags flags = { 0 }; - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; dcn10_config_stereo_parameters(stream, &flags); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 9d44f42cbf96..5a9fcbc22d04 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -774,7 +774,7 @@ static void get_pixel_clock_parameters( const struct pipe_ctx *pipe_ctx, struct pixel_clk_params *pixel_clk_params) { - const struct dc_stream *stream = pipe_ctx->stream; + const struct dc_stream_state *stream = pipe_ctx->stream; pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz; pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id; pixel_clk_params->signal_type = pipe_ctx->stream->signal; @@ -796,7 +796,7 @@ static void get_pixel_clock_parameters( } -static void build_clamping_params(struct dc_stream *stream) +static void build_clamping_params(struct dc_stream_state *stream) { stream->clamping.clamping_level = CLAMPING_FULL_RANGE; stream->clamping.c_depth = stream->timing.display_color_depth; @@ -831,7 +831,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) { if (stream != NULL && old_context->streams[i] != NULL) { @@ -916,7 +916,7 @@ enum dc_status dcn10_validate_with_context( enum dc_status dcn10_validate_guaranteed( const struct core_dc *dc, - struct dc_stream *dc_stream, + struct dc_stream_state *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; @@ -947,7 +947,7 @@ enum dc_status dcn10_validate_guaranteed( static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( struct validate_context *context, const struct resource_pool *pool, - struct dc_stream *stream) + struct dc_stream_state *stream) { struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h index e8bd501feb48..39010325cef9 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h +++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h @@ -45,7 +45,7 @@ enum dc_edid_status dm_helpers_parse_edid_caps( */ bool dm_helpers_dp_mst_write_payload_allocation_table( struct dc_context *ctx, - const struct dc_stream *stream, + const struct dc_stream_state *stream, struct dp_mst_stream_allocation_table *proposed_table, bool enable); @@ -54,13 +54,13 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( */ bool dm_helpers_dp_mst_poll_for_allocation_change_trigger( struct dc_context *ctx, - const struct dc_stream *stream); + const struct dc_stream_state *stream); /* * Sends ALLOCATE_PAYLOAD message. */ bool dm_helpers_dp_mst_send_payload_allocation( struct dc_context *ctx, - const struct dc_stream *stream, + const struct dc_stream_state *stream, bool enable); bool dm_helpers_dp_mst_start_top_mgr( diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 44a87c9427f7..d5c0f9e34ce9 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -60,7 +60,7 @@ struct dc_link *link_create(const struct link_init_data *init_params); void link_destroy(struct dc_link **link); enum dc_status dc_link_validate_mode_timing( - const struct dc_stream *stream, + const struct dc_stream_state *stream, struct dc_link *link, const struct dc_crtc_timing *timing); @@ -92,7 +92,7 @@ struct resource_funcs { enum dc_status (*validate_guaranteed)( const struct core_dc *dc, - struct dc_stream *stream, + struct dc_stream_state *stream, struct validate_context *context); bool (*validate_bandwidth)( @@ -102,8 +102,7 @@ struct resource_funcs { struct pipe_ctx *(*acquire_idle_pipe_for_layer)( struct validate_context *context, const struct resource_pool *pool, - struct dc_stream *stream); - + struct dc_stream_state *stream); enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state); }; @@ -155,7 +154,7 @@ struct resource_pool { struct pipe_ctx { struct dc_plane_state *surface; - struct dc_stream *stream; + struct dc_stream_state *stream; struct mem_input *mi; struct input_pixel_processor *ipp; @@ -240,7 +239,7 @@ union bw_context { }; struct validate_context { - struct dc_stream *streams[MAX_PIPES]; + struct dc_stream_state *streams[MAX_PIPES]; struct dc_stream_status stream_status[MAX_PIPES]; uint8_t stream_count; diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h index 1a4a605cb449..7168dcc70ae7 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h @@ -30,7 +30,7 @@ #define LINK_TRAINING_RETRY_DELAY 50 /* ms */ struct dc_link; -struct dc_stream; +struct dc_stream_state; struct dc_link_settings; bool dp_hbr_verify_link_cap( @@ -50,7 +50,7 @@ bool dp_validate_mode_timing( const struct dc_crtc_timing *timing); void decide_link_settings( - struct dc_stream *stream, + struct dc_stream_state *stream, struct dc_link_settings *link_setting); bool perform_link_training_with_retries( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 28fb02fb677e..38e4070806cb 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -93,7 +93,7 @@ struct link_encoder { struct link_encoder_funcs { bool (*validate_output_with_stream)( - struct link_encoder *enc, const struct dc_stream *stream); + struct link_encoder *enc, const struct dc_stream_state *stream); void (*hw_init)(struct link_encoder *enc); void (*setup)(struct link_encoder *enc, enum signal_type signal); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index c529ddd2e0d5..7e03f8d45b2b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -92,7 +92,7 @@ struct hw_sequencer_funcs { bool (*set_output_transfer_func)( struct pipe_ctx *pipe_ctx, - const struct dc_stream *stream); + const struct dc_stream_state *stream); void (*power_down)(struct core_dc *dc); diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index bfd7cfc86df0..aef1197cf749 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -103,8 +103,8 @@ void resource_reference_clock_source( struct clock_source *clock_source); bool resource_are_streams_timing_synchronizable( - struct dc_stream *stream1, - struct dc_stream *stream2); + struct dc_stream_state *stream1, + struct dc_stream_state *stream2); struct clock_source *resource_find_used_clk_src_for_sharing( struct resource_context *res_ctx, @@ -116,12 +116,12 @@ struct clock_source *dc_resource_find_first_free_pll( struct pipe_ctx *resource_get_head_pipe_for_stream( struct resource_context *res_ctx, - struct dc_stream *stream); + struct dc_stream_state *stream); bool resource_attach_surfaces_to_context( struct dc_plane_state *const *surfaces, int surface_count, - struct dc_stream *dc_stream, + struct dc_stream_state *dc_stream, struct validate_context *context, const struct resource_pool *pool); @@ -130,8 +130,7 @@ struct pipe_ctx *find_idle_secondary_pipe( const struct resource_pool *pool); bool resource_is_stream_unchanged( - struct validate_context *old_context, struct dc_stream *stream); - + struct validate_context *old_context, struct dc_stream_state *stream); bool resource_validate_attach_surfaces( const struct dc_validation_set set[], @@ -162,7 +161,7 @@ bool pipe_need_reprogram( struct pipe_ctx *pipe_ctx_old, struct pipe_ctx *pipe_ctx); -void resource_build_bit_depth_reduction_params(struct dc_stream *stream, +void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, struct bit_depth_reduction_params *fmt_bit_depth); #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c index dd024c99fb7e..57b5a3babdf8 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c @@ -30,7 +30,7 @@ static bool virtual_link_encoder_validate_output_with_stream( struct link_encoder *enc, - const struct dc_stream *stream) { return true; } + const struct dc_stream_state *stream) { return true; } static void virtual_link_encoder_hw_init(struct link_encoder *enc) {} diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 358f8a855a59..f0a3e4332a09 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -111,7 +111,7 @@ struct freesync_state { }; struct freesync_entity { - struct dc_stream *stream; + struct dc_stream_state *stream; struct mod_freesync_caps *caps; struct freesync_state state; struct mod_freesync_user_enable user_enable; @@ -229,7 +229,7 @@ void mod_freesync_destroy(struct mod_freesync *mod_freesync) * on the core_freesync->map and returns the corresponding index */ static unsigned int map_index_from_stream(struct core_freesync *core_freesync, - struct dc_stream *stream) + struct dc_stream_state *stream) { unsigned int index = 0; @@ -244,7 +244,7 @@ static unsigned int map_index_from_stream(struct core_freesync *core_freesync, } bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, - struct dc_stream *stream, struct mod_freesync_caps *caps) + struct dc_stream_state *stream, struct mod_freesync_caps *caps) { struct core_dc *core_dc = NULL; struct core_freesync *core_freesync = NULL; @@ -322,7 +322,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, } bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync, - struct dc_stream *stream) + struct dc_stream_state *stream) { int i = 0; struct core_freesync *core_freesync = NULL; @@ -344,7 +344,7 @@ bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync, } static void update_stream_freesync_context(struct core_freesync *core_freesync, - struct dc_stream *stream) + struct dc_stream_state *stream) { unsigned int index; struct freesync_context *ctx; @@ -368,7 +368,7 @@ static void update_stream_freesync_context(struct core_freesync *core_freesync, } static void update_stream(struct core_freesync *core_freesync, - struct dc_stream *stream) + struct dc_stream_state *stream) { unsigned int index = map_index_from_stream(core_freesync, stream); if (core_freesync->map[index].caps->supported) { @@ -378,7 +378,7 @@ static void update_stream(struct core_freesync *core_freesync, } static void calc_freesync_range(struct core_freesync *core_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, struct freesync_state *state, unsigned int min_refresh_in_uhz, unsigned int max_refresh_in_uhz) @@ -452,7 +452,7 @@ static void calc_freesync_range(struct core_freesync *core_freesync, min_frame_duration_in_ns) / 2000; } -static void calc_v_total_from_duration(struct dc_stream *stream, +static void calc_v_total_from_duration(struct dc_stream_state *stream, unsigned int duration_in_ns, int *v_total_nominal) { *v_total_nominal = div64_u64(div64_u64(((unsigned long long)( @@ -461,7 +461,7 @@ static void calc_v_total_from_duration(struct dc_stream *stream, } static void calc_v_total_for_static_ramp(struct core_freesync *core_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, unsigned int index, int *v_total) { unsigned int frame_duration = 0; @@ -557,7 +557,7 @@ static void reset_freesync_state_variables(struct freesync_state* state) * Sets freesync mode on a stream depending on current freesync state. */ static bool set_freesync_on_streams(struct core_freesync *core_freesync, - struct dc_stream **streams, int num_streams) + struct dc_stream_state **streams, int num_streams) { int v_total_nominal = 0, v_total_min = 0, v_total_max = 0; unsigned int stream_idx, map_index = 0; @@ -729,7 +729,7 @@ static void set_static_ramp_variables(struct core_freesync *core_freesync, } void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams) + struct dc_stream_state **streams, int num_streams) { unsigned int index, v_total, inserted_frame_v_total = 0; unsigned int min_frame_duration_in_ns, vmax, vmin = 0; @@ -839,7 +839,7 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, } void mod_freesync_update_state(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, struct mod_freesync_params *freesync_params) { bool freesync_program_required = false; @@ -929,7 +929,7 @@ void mod_freesync_update_state(struct mod_freesync *mod_freesync, bool mod_freesync_get_state(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, struct mod_freesync_params *freesync_params) { unsigned int index = 0; @@ -965,7 +965,7 @@ bool mod_freesync_get_state(struct mod_freesync *mod_freesync, } bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, struct mod_freesync_user_enable *user_enable) { unsigned int stream_index, map_index; @@ -1017,7 +1017,7 @@ bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, } bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, struct mod_freesync_user_enable *user_enable) { unsigned int index = 0; @@ -1035,7 +1035,7 @@ bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, } bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, bool *is_ramp_active) { unsigned int index = 0; @@ -1054,7 +1054,7 @@ bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync, } bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, - struct dc_stream *streams, + struct dc_stream_state *streams, unsigned int min_refresh, unsigned int max_refresh, struct mod_freesync_caps *caps) @@ -1107,7 +1107,7 @@ bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, } bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, unsigned int *min_refresh, unsigned int *max_refresh) { @@ -1129,7 +1129,7 @@ bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, } bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, unsigned int *vmin, unsigned int *vmax) { @@ -1151,7 +1151,7 @@ bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, } bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, unsigned int *nom_v_pos, unsigned int *v_pos) { @@ -1179,7 +1179,7 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, } void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams) + struct dc_stream_state **streams, int num_streams) { unsigned int stream_index, map_index; struct freesync_state *state; @@ -1239,7 +1239,7 @@ void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, * is required, depending on the times calculated */ static void update_timestamps(struct core_freesync *core_freesync, - const struct dc_stream *stream, unsigned int map_index, + const struct dc_stream_state *stream, unsigned int map_index, unsigned int last_render_time_in_us) { struct freesync_state *state = &core_freesync->map[map_index].state; @@ -1304,7 +1304,7 @@ static void update_timestamps(struct core_freesync *core_freesync, } static void apply_below_the_range(struct core_freesync *core_freesync, - struct dc_stream *stream, unsigned int map_index, + struct dc_stream_state *stream, unsigned int map_index, unsigned int last_render_time_in_us) { unsigned int inserted_frame_duration_in_us = 0; @@ -1403,7 +1403,7 @@ static void apply_below_the_range(struct core_freesync *core_freesync, } static void apply_fixed_refresh(struct core_freesync *core_freesync, - struct dc_stream *stream, unsigned int map_index) + struct dc_stream_state *stream, unsigned int map_index) { unsigned int vmin = 0, vmax = 0; struct freesync_state *state = &core_freesync->map[map_index].state; @@ -1434,7 +1434,7 @@ static void apply_fixed_refresh(struct core_freesync *core_freesync, } void mod_freesync_pre_update_plane_addresses(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, unsigned int curr_time_stamp_in_us) { unsigned int stream_index, map_index, last_render_time_in_us = 0; diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h index 2b9d45100bdd..84b53425f2c8 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h @@ -101,67 +101,67 @@ struct mod_freesync_params { * Add stream to be tracked by module */ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, - struct dc_stream *stream, struct mod_freesync_caps *caps); + struct dc_stream_state *stream, struct mod_freesync_caps *caps); /* * Remove stream to be tracked by module */ bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync, - struct dc_stream *stream); + struct dc_stream_state *stream); /* * Update the freesync state flags for each display and program * freesync accordingly */ void mod_freesync_update_state(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, struct mod_freesync_params *freesync_params); bool mod_freesync_get_state(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, struct mod_freesync_params *freesync_params); bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, struct mod_freesync_user_enable *user_enable); bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, struct mod_freesync_user_enable *user_enable); bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, bool *is_ramp_active); bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, - struct dc_stream *streams, + struct dc_stream_state *streams, unsigned int min_refresh, unsigned int max_refresh, struct mod_freesync_caps *caps); bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, unsigned int *min_refresh, unsigned int *max_refresh); bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, unsigned int *vmin, unsigned int *vmax); bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, unsigned int *nom_v_pos, unsigned int *v_pos); void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams); + struct dc_stream_state **streams, int num_streams); void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams); + struct dc_stream_state **streams, int num_streams); void mod_freesync_pre_update_plane_addresses(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, unsigned int curr_time_stamp); #endif -- cgit v1.2.3 From fb3466a450cc4684654367ae2f47fc3fc7846574 Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Tue, 1 Aug 2017 15:00:25 -0400 Subject: drm/amd/display: Flattening core_dc to dc -Flattening core_dc to dc Signed-off-by: Bhawanpreet Lakha Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 73 +++++----- drivers/gpu/drm/amd/display/dc/core/dc.c | 162 ++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 20 +-- .../gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 3 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 19 ++- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 1 - drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 22 +-- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 14 +- drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 10 +- drivers/gpu/drm/amd/display/dc/dc.h | 71 +++++++-- .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 5 +- drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 10 +- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 4 +- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 2 +- .../amd/display/dc/dce100/dce100_hw_sequencer.c | 9 +- .../amd/display/dc/dce100/dce100_hw_sequencer.h | 6 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 22 +-- .../drm/amd/display/dc/dce100/dce100_resource.h | 4 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 72 ++++----- .../amd/display/dc/dce110/dce110_hw_sequencer.h | 12 +- .../drm/amd/display/dc/dce110/dce110_resource.c | 26 ++-- .../drm/amd/display/dc/dce110/dce110_resource.h | 4 +- .../amd/display/dc/dce112/dce112_hw_sequencer.c | 5 +- .../amd/display/dc/dce112/dce112_hw_sequencer.h | 4 +- .../drm/amd/display/dc/dce112/dce112_resource.c | 26 ++-- .../drm/amd/display/dc/dce112/dce112_resource.h | 10 +- .../amd/display/dc/dce120/dce120_hw_sequencer.c | 5 +- .../amd/display/dc/dce120/dce120_hw_sequencer.h | 4 +- .../drm/amd/display/dc/dce120/dce120_resource.c | 18 +-- .../drm/amd/display/dc/dce120/dce120_resource.h | 4 +- .../drm/amd/display/dc/dce80/dce80_hw_sequencer.c | 5 +- .../drm/amd/display/dc/dce80/dce80_hw_sequencer.h | 4 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 46 +++--- .../gpu/drm/amd/display/dc/dce80/dce80_resource.h | 8 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c | 1 - .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 108 +++++++------- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 4 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 34 ++--- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.h | 4 +- drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 55 ------- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 8 +- drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 12 +- drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 1 + drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 50 ++++--- drivers/gpu/drm/amd/display/dc/inc/resource.h | 15 +- .../amd/display/dc/irq/dce110/irq_service_dce110.c | 6 +- .../amd/display/dc/irq/dce80/irq_service_dce80.c | 1 - .../gpu/drm/amd/display/include/logger_interface.h | 10 +- .../drm/amd/display/modules/freesync/freesync.c | 11 +- 51 files changed, 507 insertions(+), 527 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/dc/inc/core_dc.h (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 6fb1b9a91993..f0dfd3c3c12c 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -27,7 +27,6 @@ #include "dcn_calcs.h" #include "dcn_calc_auto.h" #include "dc.h" -#include "core_dc.h" #include "dal_asic_id.h" #include "resource.h" @@ -399,7 +398,7 @@ static void pipe_ctx_to_e2e_pipe_params ( } static void dcn_bw_calc_rq_dlg_ttu( - const struct core_dc *dc, + const struct dc *dc, const struct dcn_bw_internal_vars *v, struct pipe_ctx *pipe, int in_idx) @@ -674,45 +673,45 @@ static void calc_wm_sets_and_perf_params( context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a; } -static bool dcn_bw_apply_registry_override(struct core_dc *dc) +static bool dcn_bw_apply_registry_override(struct dc *dc) { bool updated = false; kernel_fpu_begin(); - if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->public.debug.sr_exit_time_ns - && dc->public.debug.sr_exit_time_ns) { + if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns + && dc->debug.sr_exit_time_ns) { updated = true; - dc->dcn_soc->sr_exit_time = dc->public.debug.sr_exit_time_ns / 1000.0; + dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0; } if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000) - != dc->public.debug.sr_enter_plus_exit_time_ns - && dc->public.debug.sr_enter_plus_exit_time_ns) { + != dc->debug.sr_enter_plus_exit_time_ns + && dc->debug.sr_enter_plus_exit_time_ns) { updated = true; dc->dcn_soc->sr_enter_plus_exit_time = - dc->public.debug.sr_enter_plus_exit_time_ns / 1000.0; + dc->debug.sr_enter_plus_exit_time_ns / 1000.0; } - if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->public.debug.urgent_latency_ns - && dc->public.debug.urgent_latency_ns) { + if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->debug.urgent_latency_ns + && dc->debug.urgent_latency_ns) { updated = true; - dc->dcn_soc->urgent_latency = dc->public.debug.urgent_latency_ns / 1000.0; + dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0; } if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000) - != dc->public.debug.percent_of_ideal_drambw - && dc->public.debug.percent_of_ideal_drambw) { + != dc->debug.percent_of_ideal_drambw + && dc->debug.percent_of_ideal_drambw) { updated = true; dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency = - dc->public.debug.percent_of_ideal_drambw; + dc->debug.percent_of_ideal_drambw; } if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000) - != dc->public.debug.dram_clock_change_latency_ns - && dc->public.debug.dram_clock_change_latency_ns) { + != dc->debug.dram_clock_change_latency_ns + && dc->debug.dram_clock_change_latency_ns) { updated = true; dc->dcn_soc->dram_clock_change_latency = - dc->public.debug.dram_clock_change_latency_ns / 1000.0; + dc->debug.dram_clock_change_latency_ns / 1000.0; } kernel_fpu_end(); @@ -720,7 +719,7 @@ static bool dcn_bw_apply_registry_override(struct core_dc *dc) } bool dcn_validate_bandwidth( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context) { const struct resource_pool *pool = dc->res_pool; @@ -730,8 +729,8 @@ bool dcn_validate_bandwidth( bool bw_limit_pass; float bw_limit; - if (dcn_bw_apply_registry_override(DC_TO_CORE(&dc->public))) - dcn_bw_sync_calcs_and_dml(DC_TO_CORE(&dc->public)); + if (dcn_bw_apply_registry_override(dc)) + dcn_bw_sync_calcs_and_dml(dc); memset(v, 0, sizeof(*v)); kernel_fpu_begin(); @@ -850,7 +849,7 @@ bool dcn_validate_bandwidth( v->phyclk_per_state[1] = v->phyclkv_mid0p72; v->phyclk_per_state[0] = v->phyclkv_min0p65; - if (dc->public.debug.disable_pipe_split) { + if (dc->debug.disable_pipe_split) { v->max_dispclk[0] = v->max_dppclk_vmin0p65; } @@ -982,15 +981,15 @@ bool dcn_validate_bandwidth( mode_support_and_system_configuration(v); if (v->voltage_level == 0 && - (dc->public.debug.sr_exit_time_dpm0_ns - || dc->public.debug.sr_enter_plus_exit_time_dpm0_ns)) { - struct core_dc *dc_core = DC_TO_CORE(&dc->public); + (dc->debug.sr_exit_time_dpm0_ns + || dc->debug.sr_enter_plus_exit_time_dpm0_ns)) { + struct dc *dc_core = dc; - if (dc->public.debug.sr_enter_plus_exit_time_dpm0_ns) + if (dc->debug.sr_enter_plus_exit_time_dpm0_ns) v->sr_enter_plus_exit_time = - dc->public.debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f; - if (dc->public.debug.sr_exit_time_dpm0_ns) - v->sr_exit_time = dc->public.debug.sr_exit_time_dpm0_ns / 1000.0f; + dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f; + if (dc->debug.sr_exit_time_dpm0_ns) + v->sr_exit_time = dc->debug.sr_exit_time_dpm0_ns / 1000.0f; dc_core->dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time; dc_core->dml.soc.sr_exit_time_us = v->sr_exit_time; mode_support_and_system_configuration(v); @@ -1020,7 +1019,7 @@ bool dcn_validate_bandwidth( context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000); context->bw.dcn.calc_clk.dcfclk_khz = (int)(v->dcfclk * 1000); context->bw.dcn.calc_clk.dispclk_khz = (int)(v->dispclk * 1000); - if (dc->public.debug.max_disp_clk == true) + if (dc->debug.max_disp_clk == true) context->bw.dcn.calc_clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000); context->bw.dcn.calc_clk.dppclk_div = (int)(v->dispclk_dppclk_ratio) == 2; @@ -1109,13 +1108,13 @@ bool dcn_validate_bandwidth( input_idx++; } - if (dc->public.debug.use_dml_wm) + if (dc->debug.use_dml_wm) dcn_dml_wm_override(v, (struct display_mode_lib *) &dc->dml, context, pool); } if (v->voltage_level == 0) { - struct core_dc *dc_core = DC_TO_CORE(&dc->public); + struct dc *dc_core = dc; dc_core->dml.soc.sr_enter_plus_exit_time_us = dc_core->dcn_soc->sr_enter_plus_exit_time; @@ -1138,7 +1137,7 @@ bool dcn_validate_bandwidth( } unsigned int dcn_find_normalized_clock_vdd_Level( - const struct core_dc *dc, + const struct dc *dc, enum dm_pp_clock_type clocks_type, int clocks_in_khz) { @@ -1228,7 +1227,7 @@ unsigned int dcn_find_normalized_clock_vdd_Level( } unsigned int dcn_find_dcfclk_suits_all( - const struct core_dc *dc, + const struct dc *dc, struct clocks_value *clocks) { unsigned vdd_level, vdd_level_temp; @@ -1270,7 +1269,7 @@ unsigned int dcn_find_dcfclk_suits_all( return dcf_clk; } -void dcn_bw_update_from_pplib(struct core_dc *dc) +void dcn_bw_update_from_pplib(struct dc *dc) { struct dc_context *ctx = dc->ctx; struct dm_pp_clock_levels_with_voltage clks = {0}; @@ -1310,7 +1309,7 @@ void dcn_bw_update_from_pplib(struct core_dc *dc) kernel_fpu_end(); } -void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc) +void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc) { struct dm_pp_wm_sets_with_clock_ranges_soc15 clk_ranges = {0}; int max_fclk_khz, nom_fclk_khz, min_fclk_khz, max_dcfclk_khz, @@ -1388,7 +1387,7 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc) dm_pp_notify_wm_clock_changes_soc15(dc->ctx, &clk_ranges); } -void dcn_bw_sync_calcs_and_dml(struct core_dc *dc) +void dcn_bw_sync_calcs_and_dml(struct dc *dc) { kernel_fpu_begin(); dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 40d65b758994..44c7b52e4a00 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -35,7 +35,6 @@ #include "clock_source.h" #include "dc_bios_types.h" -#include "dce_calcs.h" #include "bios_parser_interface.h" #include "include/irq_service_interface.h" #include "transform.h" @@ -52,7 +51,7 @@ /******************************************************************************* * Private functions ******************************************************************************/ -static void destroy_links(struct core_dc *dc) +static void destroy_links(struct dc *dc) { uint32_t i; @@ -63,7 +62,7 @@ static void destroy_links(struct core_dc *dc) } static bool create_links( - struct core_dc *dc, + struct dc *dc, uint32_t num_virtual_links) { int i; @@ -153,7 +152,7 @@ static bool stream_adjust_vmin_vmax(struct dc *dc, int vmin, int vmax) { /* TODO: Support multiple streams */ - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_stream_state *stream = streams[0]; int i = 0; bool ret = false; @@ -179,7 +178,7 @@ static bool stream_get_crtc_position(struct dc *dc, unsigned int *v_pos, unsigned int *nom_v_pos) { /* TODO: Support multiple streams */ - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_stream_state *stream = streams[0]; int i = 0; bool ret = false; @@ -202,7 +201,7 @@ static bool stream_get_crtc_position(struct dc *dc, static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; int i = 0; bool ret = false; struct pipe_ctx *pipes; @@ -220,7 +219,7 @@ static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) static bool program_csc_matrix(struct dc *dc, struct dc_stream_state *stream) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; int i = 0; bool ret = false; struct pipe_ctx *pipes; @@ -245,7 +244,7 @@ static void set_static_screen_events(struct dc *dc, int num_streams, const struct dc_static_screen_events *events) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; int i = 0; int j = 0; struct pipe_ctx *pipes_affected[MAX_PIPES]; @@ -270,7 +269,7 @@ static void set_drive_settings(struct dc *dc, struct link_training_settings *lt_settings, const struct dc_link *link) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; int i; for (i = 0; i < core_dc->link_count; i++) { @@ -288,7 +287,7 @@ static void perform_link_training(struct dc *dc, struct dc_link_settings *link_setting, bool skip_video_pattern) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; int i; for (i = 0; i < core_dc->link_count; i++) @@ -369,48 +368,48 @@ void set_dither_option(struct dc_stream_state *stream, opp_program_bit_depth_reduction(pipes->stream_res.opp, ¶ms); } -static void allocate_dc_stream_funcs(struct core_dc *core_dc) +static void allocate_dc_stream_funcs(struct dc *core_dc) { if (core_dc->hwss.set_drr != NULL) { - core_dc->public.stream_funcs.adjust_vmin_vmax = + core_dc->stream_funcs.adjust_vmin_vmax = stream_adjust_vmin_vmax; } - core_dc->public.stream_funcs.set_static_screen_events = + core_dc->stream_funcs.set_static_screen_events = set_static_screen_events; - core_dc->public.stream_funcs.get_crtc_position = + core_dc->stream_funcs.get_crtc_position = stream_get_crtc_position; - core_dc->public.stream_funcs.set_gamut_remap = + core_dc->stream_funcs.set_gamut_remap = set_gamut_remap; - core_dc->public.stream_funcs.program_csc_matrix = + core_dc->stream_funcs.program_csc_matrix = program_csc_matrix; - core_dc->public.stream_funcs.set_dither_option = + core_dc->stream_funcs.set_dither_option = set_dither_option; - core_dc->public.link_funcs.set_drive_settings = + core_dc->link_funcs.set_drive_settings = set_drive_settings; - core_dc->public.link_funcs.perform_link_training = + core_dc->link_funcs.perform_link_training = perform_link_training; - core_dc->public.link_funcs.set_preferred_link_settings = + core_dc->link_funcs.set_preferred_link_settings = set_preferred_link_settings; - core_dc->public.link_funcs.enable_hpd = + core_dc->link_funcs.enable_hpd = enable_hpd; - core_dc->public.link_funcs.disable_hpd = + core_dc->link_funcs.disable_hpd = disable_hpd; - core_dc->public.link_funcs.set_test_pattern = + core_dc->link_funcs.set_test_pattern = set_test_pattern; } -static void destruct(struct core_dc *dc) +static void destruct(struct dc *dc) { dc_release_validate_context(dc->current_context); dc->current_context = NULL; @@ -446,10 +445,11 @@ static void destruct(struct core_dc *dc) dm_free(dc->dcn_ip); dc->dcn_ip = NULL; + #endif } -static bool construct(struct core_dc *dc, +static bool construct(struct dc *dc, const struct dc_init_data *init_params) { struct dal_logger *logger; @@ -508,7 +508,7 @@ static bool construct(struct core_dc *dc, dc_ctx->cgs_device = init_params->cgs_device; dc_ctx->driver_context = init_params->driver; - dc_ctx->dc = &dc->public; + dc_ctx->dc = dc; dc_ctx->asic_id = init_params->asic_id; /* Create logger */ @@ -621,7 +621,7 @@ void ProgramPixelDurationV(unsigned int pixelClockInKHz ) struct dc *dc_create(const struct dc_init_data *init_params) { - struct core_dc *core_dc = dm_alloc(sizeof(*core_dc)); + struct dc *core_dc = dm_alloc(sizeof(*core_dc)); unsigned int full_pipe_count; if (NULL == core_dc) @@ -636,23 +636,23 @@ struct dc *dc_create(const struct dc_init_data *init_params) full_pipe_count = core_dc->res_pool->pipe_count; if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE) full_pipe_count--; - core_dc->public.caps.max_streams = min( + core_dc->caps.max_streams = min( full_pipe_count, core_dc->res_pool->stream_enc_count); - core_dc->public.caps.max_links = core_dc->link_count; - core_dc->public.caps.max_audios = core_dc->res_pool->audio_count; + core_dc->caps.max_links = core_dc->link_count; + core_dc->caps.max_audios = core_dc->res_pool->audio_count; - core_dc->public.config = init_params->flags; + core_dc->config = init_params->flags; dm_logger_write(core_dc->ctx->logger, LOG_DC, "Display Core initialized\n"); /* TODO: missing feature to be enabled */ - core_dc->public.debug.disable_dfs_bypass = true; + core_dc->debug.disable_dfs_bypass = true; - return &core_dc->public; + return core_dc; construct_fail: dm_free(core_dc); @@ -663,14 +663,14 @@ alloc_fail: void dc_destroy(struct dc **dc) { - struct core_dc *core_dc = DC_TO_CORE(*dc); + struct dc *core_dc = *dc; destruct(core_dc); dm_free(core_dc); *dc = NULL; } static bool is_validation_required( - const struct core_dc *dc, + const struct dc *dc, const struct dc_validation_set set[], int set_count) { @@ -705,7 +705,7 @@ static bool is_validation_required( } static bool validate_streams ( - const struct dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count) { @@ -719,7 +719,7 @@ static bool validate_streams ( } static bool validate_surfaces( - const struct dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count) { @@ -734,11 +734,11 @@ static bool validate_surfaces( } struct validate_context *dc_get_validate_context( - const struct dc *dc, + struct dc *dc, const struct dc_validation_set set[], uint8_t set_count) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; enum dc_status result = DC_ERROR_UNEXPECTED; struct validate_context *context; @@ -773,11 +773,11 @@ context_alloc_fail: } bool dc_validate_resources( - const struct dc *dc, + struct dc *dc, const struct dc_validation_set set[], uint8_t set_count) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; enum dc_status result = DC_ERROR_UNEXPECTED; struct validate_context *context; @@ -811,10 +811,10 @@ context_alloc_fail: } bool dc_validate_guaranteed( - const struct dc *dc, + struct dc *dc, struct dc_stream_state *stream) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; enum dc_status result = DC_ERROR_UNEXPECTED; struct validate_context *context; @@ -844,7 +844,7 @@ context_alloc_fail: } static void program_timing_sync( - struct core_dc *core_dc, + struct dc *core_dc, struct validate_context *ctx) { int i, j; @@ -918,7 +918,7 @@ static void program_timing_sync( } static bool context_changed( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { uint8_t i; @@ -935,7 +935,7 @@ static bool context_changed( } static bool streams_changed( - struct core_dc *dc, + struct dc *dc, struct dc_stream_state *streams[], uint8_t stream_count) { @@ -961,7 +961,7 @@ bool dc_enable_stereo( bool ret = true; int i, j; struct pipe_ctx *pipe; - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; #ifdef ENABLE_FBC struct compressor *fbc_compressor = core_dc->fbc_compressor; @@ -996,7 +996,7 @@ bool dc_enable_stereo( */ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *context) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_bios *dcb = core_dc->ctx->dc_bios; enum dc_status result = DC_ERROR_UNEXPECTED; struct pipe_ctx *pipe; @@ -1064,7 +1064,7 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c bool dc_commit_context(struct dc *dc, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; int i; if (false == context_changed(core_dc, context)) @@ -1092,7 +1092,7 @@ bool dc_commit_streams( struct dc_stream_state *streams[], uint8_t stream_count) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; enum dc_status result = DC_ERROR_UNEXPECTED; struct validate_context *context; struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } }; @@ -1158,7 +1158,7 @@ context_alloc_fail: bool dc_post_update_surfaces_to_stream(struct dc *dc) { int i; - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct validate_context *context = core_dc->current_context; post_surface_trace(dc); @@ -1375,7 +1375,7 @@ static enum surface_update_type get_scaling_info_update_type( } static enum surface_update_type det_surface_update( - const struct core_dc *dc, + const struct dc *dc, const struct dc_surface_update *u, int surface_index) { @@ -1410,7 +1410,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream( struct dc_stream_update *stream_update, const struct dc_stream_status *stream_status) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; int i; enum surface_update_type overall_type = UPDATE_TYPE_FAST; @@ -1456,7 +1456,7 @@ void dc_update_planes_and_stream(struct dc *dc, struct dc_stream_state *stream, struct dc_stream_update *stream_update) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct validate_context *context; int i, j; enum surface_update_type update_type; @@ -1781,29 +1781,29 @@ context_alloc_fail: DC_ERROR("Failed to allocate new validate context!\n"); } -uint8_t dc_get_current_stream_count(const struct dc *dc) +uint8_t dc_get_current_stream_count(struct dc *dc) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; return core_dc->current_context->stream_count; } -struct dc_stream_state *dc_get_stream_at_index(const struct dc *dc, uint8_t i) +struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; if (i < core_dc->current_context->stream_count) return core_dc->current_context->streams[i]; return NULL; } -struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index) +struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; return core_dc->links[link_index]; } -struct dwbc *dc_get_dwb_at_pipe(const struct dc *dc, uint32_t pipe) +struct dwbc *dc_get_dwb_at_pipe(struct dc *dc, uint32_t pipe) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; if ((pipe >= dwb_pipe0) && (pipe < dwb_pipe_max_num)) { return core_dc->res_pool->dwbc[(int)pipe]; } else { @@ -1814,20 +1814,20 @@ struct dwbc *dc_get_dwb_at_pipe(const struct dc *dc, uint32_t pipe) const struct graphics_object_id dc_get_link_id_at_index( struct dc *dc, uint32_t link_index) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; return core_dc->links[link_index]->link_id; } enum dc_irq_source dc_get_hpd_irq_source_at_index( struct dc *dc, uint32_t link_index) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; return core_dc->links[link_index]->irq_source_hpd; } const struct audio **dc_get_audios(struct dc *dc) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; return (const struct audio **)core_dc->res_pool->audios; } @@ -1836,24 +1836,24 @@ enum dc_irq_source dc_interrupt_to_irq_source( uint32_t src_id, uint32_t ext_id) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; return dal_irq_service_to_irq_source(core_dc->res_pool->irqs, src_id, ext_id); } -void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable) +void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable) { - struct core_dc *core_dc; + struct dc *core_dc; if (dc == NULL) return; - core_dc = DC_TO_CORE(dc); + core_dc = dc; dal_irq_service_set(core_dc->res_pool->irqs, src, enable); } void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; dal_irq_service_ack(core_dc->res_pool->irqs, src); } @@ -1861,7 +1861,7 @@ void dc_set_power_state( struct dc *dc, enum dc_acpi_cm_power_state power_state) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; atomic_t ref_count; switch (power_state) { @@ -1889,9 +1889,9 @@ void dc_set_power_state( } -void dc_resume(const struct dc *dc) +void dc_resume(struct dc *dc) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; uint32_t i; @@ -1906,7 +1906,7 @@ bool dc_read_aux_dpcd( uint8_t *data, uint32_t size) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_link *link = core_dc->links[link_index]; enum ddc_result r = dal_ddc_service_read_dpcd_data( @@ -1926,7 +1926,7 @@ bool dc_write_aux_dpcd( const uint8_t *data, uint32_t size) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_link *link = core_dc->links[link_index]; enum ddc_result r = dal_ddc_service_write_dpcd_data( @@ -1947,7 +1947,7 @@ bool dc_read_aux_i2c( uint8_t *data, uint32_t size) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_link *link = core_dc->links[link_index]; enum ddc_result r = dal_ddc_service_read_dpcd_data( @@ -1968,7 +1968,7 @@ bool dc_write_aux_i2c( const uint8_t *data, uint32_t size) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_link *link = core_dc->links[link_index]; enum ddc_result r = dal_ddc_service_write_dpcd_data( @@ -1990,7 +1990,7 @@ bool dc_query_ddc_data( uint8_t *read_buf, uint32_t read_size) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_link *link = core_dc->links[link_index]; @@ -2010,7 +2010,7 @@ bool dc_submit_i2c( uint32_t link_index, struct i2c_command *cmd) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_link *link = core_dc->links[link_index]; struct ddc_service *ddc = link->ddc; @@ -2129,7 +2129,7 @@ void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) { int i; - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct mem_input *mi = NULL; for (i = 0; i < core_dc->res_pool->pipe_count; i++) { @@ -2155,7 +2155,7 @@ bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) void dc_log_hw_state(struct dc *dc) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; if (core_dc->hwss.log_hw_state) core_dc->hwss.log_hw_state(core_dc); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index 21af3bc057c7..d74eed8f9b96 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -37,12 +37,12 @@ } while (0) void pre_surface_trace( - const struct dc *dc, + struct dc *dc, const struct dc_plane_state *const *plane_states, int surface_count) { int i; - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dal_logger *logger = core_dc->ctx->logger; for (i = 0; i < surface_count; i++) { @@ -158,12 +158,12 @@ void pre_surface_trace( } void update_surface_trace( - const struct dc *dc, + struct dc *dc, const struct dc_surface_update *updates, int surface_count) { int i; - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dal_logger *logger = core_dc->ctx->logger; for (i = 0; i < surface_count; i++) { @@ -279,9 +279,9 @@ void update_surface_trace( SURFACE_TRACE("\n"); } -void post_surface_trace(const struct dc *dc) +void post_surface_trace(struct dc *dc) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dal_logger *logger = core_dc->ctx->logger; SURFACE_TRACE("post surface process.\n"); @@ -289,11 +289,11 @@ void post_surface_trace(const struct dc *dc) } void context_timing_trace( - const struct dc *dc, + struct dc *dc, struct resource_context *res_ctx) { int i; - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dal_logger *logger = core_dc->ctx->logger; int h_pos[MAX_PIPES], v_pos[MAX_PIPES]; struct crtc_position position; @@ -328,11 +328,11 @@ void context_timing_trace( } void context_clock_trace( - const struct dc *dc, + struct dc *dc, struct validate_context *context) { #if defined(CONFIG_DRM_AMD_DC_DCN1_0) - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dal_logger *logger = core_dc->ctx->logger; CLOCK_TRACE("Current: dispclk_khz:%d dppclk_div:%d dcfclk_khz:%d\n" diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index 7b1f2493cbc9..71993d5983bf 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -25,7 +25,6 @@ #include "dm_services.h" #include "core_types.h" -#include "core_dc.h" #include "timing_generator.h" #include "hw_sequencer.h" @@ -55,7 +54,7 @@ static const struct tg_color black_color_format[] = { }; void color_space_to_black_color( - const struct core_dc *dc, + const struct dc *dc, enum dc_color_space colorspace, struct tg_color *black_color) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index b858fec72bd7..1888bf4d2c3f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -26,14 +26,13 @@ #include "dm_services.h" #include "dm_helpers.h" #include "dc.h" -#include "core_dc.h" #include "grph_object_id.h" #include "gpio_service_interface.h" #include "core_status.h" #include "dc_link_dp.h" #include "dc_link_ddc.h" #include "link_hwss.h" -#include "stream_encoder.h" + #include "link_encoder.h" #include "hw_sequencer.h" #include "resource.h" @@ -1392,7 +1391,7 @@ enum dc_status dc_link_validate_mode_timing( bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, uint32_t frame_ramp, const struct dc_stream_state *stream) { - struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); + struct dc *core_dc = link->ctx->dc; struct abm *abm = core_dc->res_pool->abm; unsigned int controller_id = 0; int i; @@ -1431,7 +1430,7 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, bool dc_link_set_abm_disable(const struct dc_link *link) { - struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); + struct dc *core_dc = link->ctx->dc; struct abm *abm = core_dc->res_pool->abm; if ((abm == NULL) || (abm->funcs->set_backlight_level == NULL)) @@ -1445,7 +1444,7 @@ bool dc_link_set_abm_disable(const struct dc_link *link) bool dc_link_set_psr_enable(const struct dc_link *link, bool enable) { - struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); + struct dc *core_dc = link->ctx->dc; struct dmcu *dmcu = core_dc->res_pool->dmcu; if (dmcu != NULL && link->psr_enabled) @@ -1456,7 +1455,7 @@ bool dc_link_set_psr_enable(const struct dc_link *link, bool enable) bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state) { - struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); + struct dc *core_dc = link->ctx->dc; struct dmcu *dmcu = core_dc->res_pool->dmcu; if (dmcu != NULL && link->psr_enabled) @@ -1469,7 +1468,7 @@ bool dc_link_setup_psr(struct dc_link *link, const struct dc_stream_state *stream, struct psr_config *psr_config, struct psr_context *psr_context) { - struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); + struct dc *core_dc = link->ctx->dc; struct dmcu *dmcu = core_dc->res_pool->dmcu; int i; @@ -1874,7 +1873,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) void core_link_enable_stream(struct pipe_ctx *pipe_ctx) { - struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc); + struct dc *core_dc = pipe_ctx->stream->ctx->dc; enum dc_status status = enable_link(pipe_ctx); @@ -1907,7 +1906,7 @@ void core_link_enable_stream(struct pipe_ctx *pipe_ctx) void core_link_disable_stream(struct pipe_ctx *pipe_ctx) { - struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc); + struct dc *core_dc = pipe_ctx->stream->ctx->dc; if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) deallocate_mst_payload(pipe_ctx); @@ -1919,7 +1918,7 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx) void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) { - struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc); + struct dc *core_dc = pipe_ctx->stream->ctx->dc; if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) return; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 9d5fe658d14c..0144c98fd0d5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -10,7 +10,6 @@ #include "core_status.h" #include "dpcd_defs.h" -#include "core_dc.h" #include "resource.h" /* maximum pre emphasis level allowed for each voltage swing level*/ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index d19c663c257f..da880bd02ad7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -3,7 +3,7 @@ #include "dm_services.h" #include "dc.h" -#include "inc/core_dc.h" +#include "inc/core_types.h" #include "include/ddc_service_types.h" #include "include/i2caux_interface.h" #include "link_hwss.h" diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index d2b8f27416d6..2b357318f945 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -92,7 +92,7 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) } struct resource_pool *dc_create_resource_pool( - struct core_dc *dc, + struct dc *dc, int num_virtual_links, enum dce_version dc_version, struct hw_asic_id asic_id) @@ -153,7 +153,7 @@ struct resource_pool *dc_create_resource_pool( return res_pool; } -void dc_destroy_resource_pool(struct core_dc *dc) +void dc_destroy_resource_pool(struct dc *dc) { if (dc) { if (dc->res_pool) @@ -193,7 +193,7 @@ static void update_num_audio( bool resource_construct( unsigned int num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct resource_pool *pool, const struct resource_create_funcs *create_funcs) { @@ -892,7 +892,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) enum dc_status resource_build_scaling_params_for_context( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context) { int i; @@ -1438,7 +1438,7 @@ static void calculate_phy_pix_clks(struct dc_stream_state *stream) } enum dc_status resource_map_pool_resources( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -2316,7 +2316,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) } enum dc_status resource_map_clock_resources( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -2343,7 +2343,7 @@ enum dc_status resource_map_clock_resources( else { pipe_ctx->clock_source = NULL; - if (!dc->public.config.disable_disp_pll_sharing) + if (!dc->config.disable_disp_pll_sharing) resource_find_used_clk_src_for_sharing( &context->res_ctx, pipe_ctx); @@ -2515,9 +2515,9 @@ void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, fmt_bit_depth->pixel_encoding = pixel_encoding; } -bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream) +bool dc_validate_stream(struct dc *dc, struct dc_stream_state *stream) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_context *dc_ctx = core_dc->ctx; struct dc_link *link = stream->sink->link; struct timing_generator *tg = core_dc->res_pool->timing_generators[0]; @@ -2547,9 +2547,9 @@ bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream) return res == DC_OK; } -bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_state) +bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; /* TODO For now validates pixel format only */ if (core_dc->res_pool->funcs->validate_plane) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 47e407dab4a3..5e4f7f08e3db 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -144,7 +144,7 @@ struct dc_stream_status *dc_stream_get_status( struct dc_stream_state *stream) { uint8_t i; - struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); + struct dc *dc = stream->ctx->dc; for (i = 0; i < dc->current_context->stream_count; i++) { if (stream == dc->current_context->streams[i]) { @@ -163,7 +163,7 @@ bool dc_stream_set_cursor_attributes( const struct dc_cursor_attributes *attributes) { int i; - struct core_dc *core_dc; + struct dc *core_dc; struct resource_context *res_ctx; if (NULL == stream) { @@ -175,7 +175,7 @@ bool dc_stream_set_cursor_attributes( return false; } - core_dc = DC_TO_CORE(stream->ctx->dc); + core_dc = stream->ctx->dc; res_ctx = &core_dc->current_context->res_ctx; for (i = 0; i < MAX_PIPES; i++) { @@ -198,7 +198,7 @@ bool dc_stream_set_cursor_position( const struct dc_cursor_position *position) { int i; - struct core_dc *core_dc; + struct dc *core_dc; struct resource_context *res_ctx; if (NULL == stream) { @@ -211,7 +211,7 @@ bool dc_stream_set_cursor_position( return false; } - core_dc = DC_TO_CORE(stream->ctx->dc); + core_dc = stream->ctx->dc; res_ctx = &core_dc->current_context->res_ctx; for (i = 0; i < MAX_PIPES; i++) { @@ -246,7 +246,7 @@ bool dc_stream_set_cursor_position( uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) { uint8_t i; - struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); + struct dc *core_dc = stream->ctx->dc; struct resource_context *res_ctx = &core_dc->current_context->res_ctx; @@ -270,7 +270,7 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, { uint8_t i; bool ret = false; - struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); + struct dc *core_dc = stream->ctx->dc; struct resource_context *res_ctx = &core_dc->current_context->res_ctx; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index da19c7fa5151..0b6410fb2f3e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -28,7 +28,7 @@ #include "dc.h" /* DC core (private) */ -#include "core_dc.h" +#include "core_types.h" #include "transform.h" /******************************************************************************* @@ -64,9 +64,9 @@ void enable_surface_flip_reporting(struct dc_plane_state *plane_state, /*register_flip_interrupt(surface);*/ } -struct dc_plane_state *dc_create_plane_state(const struct dc *dc) +struct dc_plane_state *dc_create_plane_state(struct dc *dc) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct dc_plane_state *plane_state = dm_alloc(sizeof(*plane_state)); @@ -91,7 +91,7 @@ const struct dc_plane_status *dc_plane_get_status( const struct dc_plane_state *plane_state) { const struct dc_plane_status *plane_status; - struct core_dc *core_dc; + struct dc *core_dc; int i; if (!plane_state || @@ -102,7 +102,7 @@ const struct dc_plane_status *dc_plane_get_status( } plane_status = &plane_state->status; - core_dc = DC_TO_CORE(plane_state->ctx->dc); + core_dc = plane_state->ctx->dc; if (core_dc->current_context == NULL) return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e62d15d90fdb..68056d888def 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -34,14 +34,19 @@ #include "grph_object_ctrl_defs.h" #include +#include "inc/hw_sequencer.h" +#include "dml/display_mode_lib.h" + + + #define MAX_SURFACES 3 #define MAX_STREAMS 6 #define MAX_SINKS_PER_LINK 4 + /******************************************************************************* * Display Core Interfaces ******************************************************************************/ - struct dc_caps { uint32_t max_streams; uint32_t max_links; @@ -186,7 +191,9 @@ struct dc_debug { bool disable_psr; bool force_abm_enable; }; - +struct validate_context; +struct resource_pool; +struct dce_hwseq; struct dc { struct dc_caps caps; struct dc_cap_funcs cap_funcs; @@ -194,6 +201,40 @@ struct dc { struct dc_link_funcs link_funcs; struct dc_config config; struct dc_debug debug; + + struct dc_context *ctx; + + uint8_t link_count; + struct dc_link *links[MAX_PIPES * 2]; + + struct validate_context *current_context; + struct resource_pool *res_pool; + + /* Display Engine Clock levels */ + struct dm_pp_clock_levels sclk_lvls; + + /* Inputs into BW and WM calculations. */ + struct bw_calcs_dceip *bw_dceip; + struct bw_calcs_vbios *bw_vbios; +#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + struct dcn_soc_bounding_box *dcn_soc; + struct dcn_ip_params *dcn_ip; + struct display_mode_lib dml; +#endif + + /* HW functions */ + struct hw_sequencer_funcs hwss; + struct dce_hwseq *hwseq; + + /* temp store of dm_pp_display_configuration + * to compare to see if display config changed + */ + struct dm_pp_display_configuration prev_display_config; + + /* FBC compressor */ +#ifdef ENABLE_FBC + struct compressor *fbc_compressor; +#endif }; enum frame_buffer_mode { @@ -384,7 +425,7 @@ struct dc_surface_update { /* * Create a new surface with default parameters; */ -struct dc_plane_state *dc_create_plane_state(const struct dc *dc); +struct dc_plane_state *dc_create_plane_state(struct dc *dc); const struct dc_plane_status *dc_plane_get_status( const struct dc_plane_state *plane_state); @@ -558,8 +599,8 @@ void dc_stream_log( struct dal_logger *dc_logger, enum dc_log_type log_type); -uint8_t dc_get_current_stream_count(const struct dc *dc); -struct dc_stream_state *dc_get_stream_at_index(const struct dc *dc, uint8_t i); +uint8_t dc_get_current_stream_count(struct dc *dc); +struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i); /* * Return the current frame counter. @@ -585,9 +626,9 @@ struct dc_validation_set { uint8_t plane_count; }; -bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream); +bool dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); -bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_state); +bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); /* * This function takes a set of resources and checks that they are cofunctional. * @@ -595,12 +636,12 @@ bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_s * No hardware is programmed for call. Only validation is done. */ struct validate_context *dc_get_validate_context( - const struct dc *dc, + struct dc *dc, const struct dc_validation_set set[], uint8_t set_count); bool dc_validate_resources( - const struct dc *dc, + struct dc *dc, const struct dc_validation_set set[], uint8_t set_count); @@ -613,7 +654,7 @@ bool dc_validate_resources( */ bool dc_validate_guaranteed( - const struct dc *dc, + struct dc *dc, struct dc_stream_state *stream); void dc_resource_validate_ctx_copy_construct( @@ -764,7 +805,7 @@ struct dc_link { /* Private to DC core */ - const struct core_dc *dc; + const struct dc *dc; struct dc_context *ctx; @@ -795,9 +836,9 @@ const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link); * boot time. They cannot be created or destroyed. * Use dc_get_caps() to get number of links. */ -struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index); +struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); -struct dwbc *dc_get_dwb_at_pipe(const struct dc *dc, uint32_t pipe); +struct dwbc *dc_get_dwb_at_pipe(struct dc *dc, uint32_t pipe); /* Return id of physical connector represented by a dc_link at link_index.*/ const struct graphics_object_id dc_get_link_id_at_index( @@ -948,7 +989,7 @@ enum dc_irq_source dc_interrupt_to_irq_source( struct dc *dc, uint32_t src_id, uint32_t ext_id); -void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable); +void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); enum dc_irq_source dc_get_hpd_irq_source_at_index( struct dc *dc, uint32_t link_index); @@ -960,7 +1001,7 @@ enum dc_irq_source dc_get_hpd_irq_source_at_index( void dc_set_power_state( struct dc *dc, enum dc_acpi_cm_power_state power_state); -void dc_resume(const struct dc *dc); +void dc_resume(struct dc *dc); /* * DPCD access interfaces diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 922af2d1b91a..0654fe34627c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -34,7 +34,6 @@ #include "dce_clock_source.h" -#include "core_dc.h" #include "reg_helper.h" #define REG(reg)\ @@ -609,7 +608,7 @@ static uint32_t dce110_get_pll_pixel_rate_in_hz( struct pll_settings *pll_settings) { uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; - struct core_dc *dc_core = DC_TO_CORE(cs->ctx->dc); + struct dc *dc_core = cs->ctx->dc; struct validate_context *context = dc_core->current_context; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst]; @@ -624,7 +623,7 @@ static uint32_t dce110_get_dp_pixel_rate_from_combo_phy_pll( struct pll_settings *pll_settings) { uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; - struct core_dc *dc_core = DC_TO_CORE(cs->ctx->dc); + struct dc *dc_core = cs->ctx->dc; struct validate_context *context = dc_core->current_context; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst]; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c index 7bb2eaf07da5..9d67340a6b8b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c @@ -29,14 +29,12 @@ #include "fixed32_32.h" #include "bios_parser_interface.h" #include "dc.h" -#include "core_dc.h" #include "dce_abm.h" #include "dmcu.h" #if defined(CONFIG_DRM_AMD_DC_DCN1_0) #include "dcn_calcs.h" -#include "core_dc.h" #endif - +#include "core_types.h" #define TO_DCE_CLOCKS(clocks)\ @@ -368,7 +366,7 @@ static int dce_psr_set_clock( { struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk); struct dc_context *ctx = clk_dce->base.ctx; - struct core_dc *core_dc = DC_TO_CORE(ctx->dc); + struct dc *core_dc = ctx->dc; struct dmcu *dmcu = core_dc->res_pool->dmcu; int actual_clk_khz = requested_clk_khz; @@ -385,7 +383,7 @@ static int dce112_set_clock( struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk); struct bp_set_dce_clock_parameters dce_clk_params; struct dc_bios *bp = clk->ctx->dc_bios; - struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc); + struct dc *core_dc = clk->ctx->dc; struct abm *abm = core_dc->res_pool->abm; struct dmcu *dmcu = core_dc->res_pool->dmcu; int actual_clock = requested_clk_khz; @@ -621,7 +619,7 @@ static bool dce_apply_clock_voltage_request( if (send_request) { #if defined(CONFIG_DRM_AMD_DC_DCN1_0) if (clk->ctx->dce_version >= DCN_VERSION_1_0) { - struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc); + struct dc *core_dc = clk->ctx->dc; /*use dcfclk request voltage*/ clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; clock_voltage_req.clocks_in_khz = diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c index 4894e1755d84..d2e66b1bc0ef 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c @@ -26,7 +26,7 @@ #include "dce_hwseq.h" #include "reg_helper.h" #include "hw_sequencer.h" -#include "core_dc.h" +#include "core_types.h" #define CTX \ hws->ctx @@ -44,7 +44,7 @@ void dce_enable_fe_clock(struct dce_hwseq *hws, DCFE_CLOCK_ENABLE, enable); } -void dce_pipe_control_lock(struct core_dc *dc, +void dce_pipe_control_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock) { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index 9a97d8ee7971..3a1eb6a79d66 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -528,7 +528,7 @@ enum blnd_mode { void dce_enable_fe_clock(struct dce_hwseq *hwss, unsigned int inst, bool enable); -void dce_pipe_control_lock(struct core_dc *dc, +void dce_pipe_control_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock); diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c index c638f47acefc..b7e51c5ed1b1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c @@ -24,7 +24,6 @@ */ #include "dm_services.h" #include "dc.h" -#include "core_dc.h" #include "core_types.h" #include "hw_sequencer.h" #include "dce100_hw_sequencer.h" @@ -71,7 +70,7 @@ static const struct dce100_hw_seq_reg_offsets reg_offsets[] = { /***************************PIPE_CONTROL***********************************/ static bool dce100_enable_display_power_gating( - struct core_dc *dc, + struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating) @@ -107,7 +106,7 @@ static bool dce100_enable_display_power_gating( } static void dce100_pplib_apply_display_requirements( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; @@ -127,7 +126,7 @@ static void dce100_pplib_apply_display_requirements( } void dce100_set_bandwidth( - struct core_dc *dc, + struct dc *dc, struct validate_context *context, bool decrease_allowed) { @@ -143,7 +142,7 @@ void dce100_set_bandwidth( /**************************************************************************/ -bool dce100_hw_sequencer_construct(struct core_dc *dc) +bool dce100_hw_sequencer_construct(struct dc *dc) { dce110_hw_sequencer_construct(dc); diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h index 24433f0e770b..c04aa15cd656 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h @@ -28,13 +28,13 @@ #include "core_types.h" -struct core_dc; +struct dc; struct validate_context; -bool dce100_hw_sequencer_construct(struct core_dc *dc); +bool dce100_hw_sequencer_construct(struct dc *dc); void dce100_set_bandwidth( - struct core_dc *dc, + struct dc *dc, struct validate_context *context, bool decrease_allowed); diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 46f0c71fbac4..b2b03633eb4f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -652,7 +652,7 @@ static void destruct(struct dce110_resource_pool *pool) } static enum dc_status build_mapped_resource( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -688,7 +688,7 @@ static enum dc_status build_mapped_resource( } bool dce100_validate_bandwidth( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context) { /* TODO implement when needed but for now hardcode max value*/ @@ -720,7 +720,7 @@ static bool dce100_validate_surface_sets( } enum dc_status dce100_validate_with_context( - const struct core_dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count, struct validate_context *context, @@ -764,7 +764,7 @@ enum dc_status dce100_validate_with_context( } enum dc_status dce100_validate_guaranteed( - const struct core_dc *dc, + struct dc *dc, struct dc_stream_state *dc_stream, struct validate_context *context) { @@ -784,7 +784,7 @@ enum dc_status dce100_validate_guaranteed( if (result == DC_OK) { validate_guaranteed_copy_streams( - context, dc->public.caps.max_streams); + context, dc->caps.max_streams); result = resource_build_scaling_params_for_context(dc, context); } @@ -824,7 +824,7 @@ static const struct resource_funcs dce100_res_pool_funcs = { static bool construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dce110_resource_pool *pool) { unsigned int i; @@ -909,9 +909,9 @@ static bool construct( *************************************************/ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = res_cap.num_timing_generator; - dc->public.caps.max_downscale_ratio = 200; - dc->public.caps.i2c_speed_in_khz = 40; - dc->public.caps.max_cursor_size = 128; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 40; + dc->caps.max_cursor_size = 128; for (i = 0; i < pool->base.pipe_count; i++) { pool->base.timing_generators[i] = @@ -958,7 +958,7 @@ static bool construct( } } - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) @@ -978,7 +978,7 @@ res_create_fail: struct resource_pool *dce100_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc) + struct dc *dc) { struct dce110_resource_pool *pool = dm_alloc(sizeof(struct dce110_resource_pool)); diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h index edc50caf04d1..ca7b2b7c1a48 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h @@ -8,13 +8,13 @@ #ifndef DCE100_RESOURCE_H_ #define DCE100_RESOURCE_H_ -struct core_dc; +struct dc; struct resource_pool; struct dc_validation_set; struct resource_pool *dce100_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc); + struct dc *dc); enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index ccde7c80d658..e6c6f1108078 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -164,7 +164,7 @@ static void enable_display_pipe_clock_gating( } static bool dce110_enable_display_power_gating( - struct core_dc *dc, + struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating) @@ -944,7 +944,7 @@ static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, } } -static void program_scaler(const struct core_dc *dc, +static void program_scaler(const struct dc *dc, const struct pipe_ctx *pipe_ctx) { struct tg_color color = {0}; @@ -955,7 +955,7 @@ static void program_scaler(const struct core_dc *dc, return; #endif - if (dc->public.debug.surface_visual_confirm) + if (dc->debug.surface_visual_confirm) get_surface_visual_confirm_color(pipe_ctx, &color); else color_space_to_black_color(dc, @@ -979,7 +979,7 @@ static void program_scaler(const struct core_dc *dc, static enum dc_status dce110_prog_pixclk_crtc_otg( struct pipe_ctx *pipe_ctx, struct validate_context *context, - struct core_dc *dc) + struct dc *dc) { struct dc_stream_state *stream = pipe_ctx->stream; struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. @@ -1035,7 +1035,7 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( static enum dc_status apply_single_controller_ctx_to_hw( struct pipe_ctx *pipe_ctx, struct validate_context *context, - struct core_dc *dc) + struct dc *dc) { struct dc_stream_state *stream = pipe_ctx->stream; struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. @@ -1146,7 +1146,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( /******************************************************************************/ -static void power_down_encoders(struct core_dc *dc) +static void power_down_encoders(struct dc *dc) { int i; @@ -1156,7 +1156,7 @@ static void power_down_encoders(struct core_dc *dc) } } -static void power_down_controllers(struct core_dc *dc) +static void power_down_controllers(struct dc *dc) { int i; @@ -1166,7 +1166,7 @@ static void power_down_controllers(struct core_dc *dc) } } -static void power_down_clock_sources(struct core_dc *dc) +static void power_down_clock_sources(struct dc *dc) { int i; @@ -1181,7 +1181,7 @@ static void power_down_clock_sources(struct core_dc *dc) } } -static void power_down_all_hw_blocks(struct core_dc *dc) +static void power_down_all_hw_blocks(struct dc *dc) { power_down_encoders(dc); @@ -1196,7 +1196,7 @@ static void power_down_all_hw_blocks(struct core_dc *dc) } static void disable_vga_and_power_gate_all_controllers( - struct core_dc *dc) + struct dc *dc) { int i; struct timing_generator *tg; @@ -1224,7 +1224,7 @@ static void disable_vga_and_power_gate_all_controllers( * 3. Enable power gating for controller * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) */ -void dce110_enable_accelerated_mode(struct core_dc *dc) +void dce110_enable_accelerated_mode(struct dc *dc) { power_down_all_hw_blocks(dc); @@ -1250,7 +1250,7 @@ static uint32_t compute_pstate_blackout_duration( } void dce110_set_displaymarks( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context) { uint8_t i, num_pipes; @@ -1316,7 +1316,7 @@ static void set_safe_displaymarks( } static void switch_dp_clock_sources( - const struct core_dc *dc, + const struct dc *dc, struct resource_context *res_ctx) { uint8_t i; @@ -1408,7 +1408,7 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx, * may read PLL register to get pixel clock */ static uint32_t get_max_pixel_clock_for_all_paths( - struct core_dc *dc, + struct dc *dc, struct validate_context *context, bool pre_mode_set) { @@ -1449,7 +1449,7 @@ static uint32_t get_max_pixel_clock_for_all_paths( * etc support for dcn1.0 */ static void apply_min_clocks( - struct core_dc *dc, + struct dc *dc, struct validate_context *context, enum dm_pp_clocks_state *clocks_state, bool pre_mode_set) @@ -1538,7 +1538,7 @@ static void apply_min_clocks( /* * Check if FBC can be enabled */ -static enum dc_status validate_fbc(struct core_dc *dc, +static enum dc_status validate_fbc(struct dc *dc, struct validate_context *context) { struct pipe_ctx *pipe_ctx = @@ -1568,7 +1568,7 @@ static enum dc_status validate_fbc(struct core_dc *dc, /* * Enable FBC */ -static enum dc_status enable_fbc(struct core_dc *dc, +static enum dc_status enable_fbc(struct dc *dc, struct validate_context *context) { enum dc_status status = validate_fbc(dc, context); @@ -1597,7 +1597,7 @@ static enum dc_status enable_fbc(struct core_dc *dc, #endif static enum dc_status apply_ctx_to_hw_fpga( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { enum dc_status status = DC_ERROR_UNEXPECTED; @@ -1627,7 +1627,7 @@ static enum dc_status apply_ctx_to_hw_fpga( } static void dce110_reset_hw_ctx_wrap( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { int i; @@ -1672,7 +1672,7 @@ static void dce110_reset_hw_ctx_wrap( enum dc_status dce110_apply_ctx_to_hw( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { struct dc_bios *dcb = dc->ctx->dc_bios; @@ -1965,7 +1965,7 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx) * -------------------------------------------------| * ******************************************************************************/ -static void program_surface_visibility(const struct core_dc *dc, +static void program_surface_visibility(const struct dc *dc, struct pipe_ctx *pipe_ctx) { enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; @@ -2038,7 +2038,7 @@ static void program_gamut_remap(struct pipe_ctx *pipe_ctx) * TODO REMOVE, USE UPDATE INSTEAD */ static void set_plane_config( - const struct core_dc *dc, + const struct dc *dc, struct pipe_ctx *pipe_ctx, struct resource_context *res_ctx) { @@ -2117,7 +2117,7 @@ static void set_plane_config( if (mi->funcs->set_blank) mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); - if (dc->public.config.gpu_vm_support) + if (dc->config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( pipe_ctx->plane_res.mi, plane_state->format, @@ -2125,7 +2125,7 @@ static void set_plane_config( plane_state->rotation); } -static void update_plane_addr(const struct core_dc *dc, +static void update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) { struct dc_plane_state *plane_state = pipe_ctx->plane_state; @@ -2163,7 +2163,7 @@ void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) } } -void dce110_power_down(struct core_dc *dc) +void dce110_power_down(struct dc *dc) { power_down_all_hw_blocks(dc); disable_vga_and_power_gate_all_controllers(dc); @@ -2208,7 +2208,7 @@ static bool wait_for_reset_trigger_to_occur( /* Enable timing synchronization for a group of Timing Generators. */ static void dce110_enable_timing_synchronization( - struct core_dc *dc, + struct dc *dc, int group_index, int group_size, struct pipe_ctx *grouped_pipes[]) @@ -2257,7 +2257,7 @@ static void dce110_enable_timing_synchronization( DC_SYNC_INFO("GSL: Set-up complete.\n"); } -static void init_hw(struct core_dc *dc) +static void init_hw(struct dc *dc) { int i; struct dc_bios *bp; @@ -2394,7 +2394,7 @@ uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context) } static int determine_sclk_from_bounding_box( - const struct core_dc *dc, + const struct dc *dc, int required_sclk) { int i; @@ -2420,7 +2420,7 @@ static int determine_sclk_from_bounding_box( } static void pplib_apply_display_requirements( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; @@ -2474,7 +2474,7 @@ static void pplib_apply_display_requirements( } static void dce110_set_bandwidth( - struct core_dc *dc, + struct dc *dc, struct validate_context *context, bool decrease_allowed) { @@ -2491,7 +2491,7 @@ static void dce110_set_bandwidth( } static void dce110_program_front_end_for_pipe( - struct core_dc *dc, struct pipe_ctx *pipe_ctx) + struct dc *dc, struct pipe_ctx *pipe_ctx) { struct mem_input *mi = pipe_ctx->plane_res.mi; struct pipe_ctx *old_pipe = NULL; @@ -2572,7 +2572,7 @@ static void dce110_program_front_end_for_pipe( if (mi->funcs->set_blank) mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); - if (dc->public.config.gpu_vm_support) + if (dc->config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( pipe_ctx->plane_res.mi, plane_state->format, @@ -2618,7 +2618,7 @@ static void dce110_program_front_end_for_pipe( } static void dce110_apply_ctx_for_surface( - struct core_dc *dc, + struct dc *dc, const struct dc_stream_state *stream, int num_planes, struct validate_context *context) @@ -2648,7 +2648,7 @@ static void dce110_apply_ctx_for_surface( } } -static void dce110_power_down_fe(struct core_dc *dc, int fe_idx) +static void dce110_power_down_fe(struct dc *dc, int fe_idx) { /* Do not power down fe when stream is active on dce*/ if (dc->current_context->res_ctx.pipe_ctx[fe_idx].stream) @@ -2662,7 +2662,7 @@ static void dce110_power_down_fe(struct core_dc *dc, int fe_idx) } static void dce110_wait_for_mpcc_disconnect( - struct core_dc *dc, + struct dc *dc, struct resource_pool *res_pool, struct pipe_ctx *pipe_ctx) { @@ -2724,7 +2724,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect }; -bool dce110_hw_sequencer_construct(struct core_dc *dc) +bool dce110_hw_sequencer_construct(struct dc *dc) { dc->hwss = dce110_funcs; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h index 89782ca1917f..d710f6e6dc07 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h @@ -29,20 +29,20 @@ #include "core_types.h" #define GAMMA_HW_POINTS_NUM 256 -struct core_dc; +struct dc; struct validate_context; struct dm_pp_display_configuration; -bool dce110_hw_sequencer_construct(struct core_dc *dc); +bool dce110_hw_sequencer_construct(struct dc *dc); enum dc_status dce110_apply_ctx_to_hw( - struct core_dc *dc, + struct dc *dc, struct validate_context *context); void dce110_set_display_clock(struct validate_context *context); void dce110_set_displaymarks( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context); void dce110_enable_stream(struct pipe_ctx *pipe_ctx); @@ -55,9 +55,9 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, void dce110_update_info_frame(struct pipe_ctx *pipe_ctx); void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); -void dce110_enable_accelerated_mode(struct core_dc *dc); +void dce110_enable_accelerated_mode(struct dc *dc); -void dce110_power_down(struct core_dc *dc); +void dce110_power_down(struct dc *dc); void dce110_update_pending_status(struct pipe_ctx *pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 56be84ce5a0d..2154c2e567f2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -772,7 +772,7 @@ static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigne } static enum dc_status build_mapped_resource( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -814,7 +814,7 @@ static enum dc_status build_mapped_resource( } static bool dce110_validate_bandwidth( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context) { bool result = false; @@ -928,7 +928,7 @@ static bool dce110_validate_surface_sets( } static enum dc_status dce110_validate_with_context( - const struct core_dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count, struct validate_context *context, @@ -972,7 +972,7 @@ static enum dc_status dce110_validate_with_context( } static enum dc_status dce110_validate_guaranteed( - const struct core_dc *dc, + struct dc *dc, struct dc_stream_state *dc_stream, struct validate_context *context) { @@ -992,7 +992,7 @@ static enum dc_status dce110_validate_guaranteed( if (result == DC_OK) { validate_guaranteed_copy_streams( - context, dc->public.caps.max_streams); + context, dc->caps.max_streams); result = resource_build_scaling_params_for_context(dc, context); } @@ -1008,7 +1008,7 @@ static struct pipe_ctx *dce110_acquire_underlay( const struct resource_pool *pool, struct dc_stream_state *stream) { - struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); + struct dc *dc = stream->ctx->dc; struct resource_context *res_ctx = &context->res_ctx; unsigned int underlay_idx = pool->underlay_pipe_index; struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; @@ -1117,7 +1117,7 @@ static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) return true; } -static void bw_calcs_data_update_from_pplib(struct core_dc *dc) +static void bw_calcs_data_update_from_pplib(struct dc *dc) { struct dm_pp_clock_levels clks = {0}; @@ -1184,7 +1184,7 @@ const struct resource_caps *dce110_resource_cap( static bool construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dce110_resource_pool *pool, struct hw_asic_id asic_id) { @@ -1206,9 +1206,9 @@ static bool construct( pool->base.pipe_count = pool->base.res_cap->num_timing_generator; pool->base.underlay_pipe_index = pool->base.pipe_count; - dc->public.caps.max_downscale_ratio = 150; - dc->public.caps.i2c_speed_in_khz = 100; - dc->public.caps.max_cursor_size = 128; + dc->caps.max_downscale_ratio = 150; + dc->caps.i2c_speed_in_khz = 100; + dc->caps.max_cursor_size = 128; /************************************************* * Create resources * @@ -1351,7 +1351,7 @@ static bool construct( if (!dce110_hw_sequencer_construct(dc)) goto res_create_fail; - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); @@ -1366,7 +1366,7 @@ res_create_fail: struct resource_pool *dce110_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct hw_asic_id asic_id) { struct dce110_resource_pool *pool = diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h index 8e2e85dd30b9..5bb692d037d9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h @@ -28,7 +28,7 @@ #include "core_types.h" -struct core_dc; +struct dc; struct resource_pool; #define TO_DCE110_RES_POOL(pool)\ @@ -42,7 +42,7 @@ enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx); struct resource_pool *dce110_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct hw_asic_id asic_id); #endif /* __DC_RESOURCE_DCE110_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c index 204f613467b7..8816e09110e1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c @@ -25,7 +25,6 @@ #include "dm_services.h" #include "dc.h" -#include "core_dc.h" #include "core_types.h" #include "dce112_hw_sequencer.h" @@ -112,7 +111,7 @@ static void dce112_init_pte(struct dc_context *ctx) } static bool dce112_enable_display_power_gating( - struct core_dc *dc, + struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating) @@ -153,7 +152,7 @@ static bool dce112_enable_display_power_gating( return false; } -bool dce112_hw_sequencer_construct(struct core_dc *dc) +bool dce112_hw_sequencer_construct(struct dc *dc) { /* All registers used by dce11.2 match those in dce11 in offset and * structure diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h index d96c582da45c..37bd60cc93f9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h @@ -28,9 +28,9 @@ #include "core_types.h" -struct core_dc; +struct dc; -bool dce112_hw_sequencer_construct(struct core_dc *dc); +bool dce112_hw_sequencer_construct(struct dc *dc); #endif /* __DC_HWSS_DCE112_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index d6e58a25f3d0..89a8dfa68c01 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -723,7 +723,7 @@ static struct clock_source *find_matching_pll( } static enum dc_status build_mapped_resource( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -759,7 +759,7 @@ static enum dc_status build_mapped_resource( } bool dce112_validate_bandwidth( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context) { bool result = false; @@ -837,7 +837,7 @@ bool dce112_validate_bandwidth( } enum dc_status resource_map_phy_clock_resources( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -904,7 +904,7 @@ static bool dce112_validate_surface_sets( } enum dc_status dce112_validate_with_context( - const struct core_dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count, struct validate_context *context, @@ -948,7 +948,7 @@ enum dc_status dce112_validate_with_context( } enum dc_status dce112_validate_guaranteed( - const struct core_dc *dc, + struct dc *dc, struct dc_stream_state *stream, struct validate_context *context) { @@ -968,7 +968,7 @@ enum dc_status dce112_validate_guaranteed( if (result == DC_OK) { validate_guaranteed_copy_streams( - context, dc->public.caps.max_streams); + context, dc->caps.max_streams); result = resource_build_scaling_params_for_context(dc, context); } @@ -997,7 +997,7 @@ static const struct resource_funcs dce112_res_pool_funcs = { .validate_plane = dce100_validate_plane }; -static void bw_calcs_data_update_from_pplib(struct core_dc *dc) +static void bw_calcs_data_update_from_pplib(struct dc *dc) { struct dm_pp_clock_levels_with_latency eng_clks = {0}; struct dm_pp_clock_levels_with_latency mem_clks = {0}; @@ -1153,7 +1153,7 @@ const struct resource_caps *dce112_resource_cap( static bool construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dce110_resource_pool *pool) { unsigned int i; @@ -1170,9 +1170,9 @@ static bool construct( *************************************************/ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = pool->base.res_cap->num_timing_generator; - dc->public.caps.max_downscale_ratio = 200; - dc->public.caps.i2c_speed_in_khz = 100; - dc->public.caps.max_cursor_size = 128; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 100; + dc->caps.max_cursor_size = 128; /************************************************* * Create resources * @@ -1319,7 +1319,7 @@ static bool construct( &res_create_funcs)) goto res_create_fail; - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; /* Create hardware sequencer */ if (!dce112_hw_sequencer_construct(dc)) @@ -1338,7 +1338,7 @@ res_create_fail: struct resource_pool *dce112_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc) + struct dc *dc) { struct dce110_resource_pool *pool = dm_alloc(sizeof(struct dce110_resource_pool)); diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h index feef559f1ecd..69f8f689196d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h @@ -28,27 +28,27 @@ #include "core_types.h" -struct core_dc; +struct dc; struct resource_pool; struct resource_pool *dce112_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc); + struct dc *dc); enum dc_status dce112_validate_with_context( - const struct core_dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count, struct validate_context *context, struct validate_context *old_context); enum dc_status dce112_validate_guaranteed( - const struct core_dc *dc, + struct dc *dc, struct dc_stream_state *dc_stream, struct validate_context *context); bool dce112_validate_bandwidth( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context); diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c index 91301b412aa0..d6225f332431 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c @@ -25,7 +25,6 @@ #include "dm_services.h" #include "dc.h" -#include "core_dc.h" #include "core_types.h" #include "dce120_hw_sequencer.h" #include "dce/dce_hwseq.h" @@ -149,7 +148,7 @@ static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id) #endif static bool dce120_enable_display_power_gating( - struct core_dc *dc, + struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating) @@ -247,7 +246,7 @@ static void dce120_update_dchub( -bool dce120_hw_sequencer_construct(struct core_dc *dc) +bool dce120_hw_sequencer_construct(struct dc *dc) { /* All registers used by dce11.2 match those in dce11 in offset and * structure diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h index 3402413c7156..6448a17c2fde 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h @@ -28,9 +28,9 @@ #include "core_types.h" -struct core_dc; +struct dc; -bool dce120_hw_sequencer_construct(struct core_dc *dc); +bool dce120_hw_sequencer_construct(struct dc *dc); #endif /* __DC_HWSS_DCE112_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index 562ae2205a90..b8fcdff40db3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -410,7 +410,7 @@ void dce120_clock_source_destroy(struct clock_source **clk_src) } -bool dce120_hw_sequencer_create(struct core_dc *dc) +bool dce120_hw_sequencer_create(struct dc *dc) { /* All registers used by dce11.2 match those in dce11 in offset and * structure @@ -704,7 +704,7 @@ static const struct resource_funcs dce120_res_pool_funcs = { .validate_plane = dce100_validate_plane }; -static void bw_calcs_data_update_from_pplib(struct core_dc *dc) +static void bw_calcs_data_update_from_pplib(struct dc *dc) { struct dm_pp_clock_levels_with_latency eng_clks = {0}; struct dm_pp_clock_levels_with_latency mem_clks = {0}; @@ -831,7 +831,7 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) static bool construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dce110_resource_pool *pool) { unsigned int i; @@ -847,10 +847,10 @@ static bool construct( pool->base.pipe_count = res_cap.num_timing_generator; pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; - dc->public.caps.max_downscale_ratio = 200; - dc->public.caps.i2c_speed_in_khz = 100; - dc->public.caps.max_cursor_size = 128; - dc->public.debug = debug_defaults; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 100; + dc->caps.max_cursor_size = 128; + dc->debug = debug_defaults; /************************************************* * Create resources * @@ -982,7 +982,7 @@ static bool construct( if (!dce120_hw_sequencer_create(dc)) goto controller_create_fail; - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); @@ -1003,7 +1003,7 @@ res_create_fail: struct resource_pool *dce120_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc) + struct dc *dc) { struct dce110_resource_pool *pool = dm_alloc(sizeof(struct dce110_resource_pool)); diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h index 038c78dcc247..3d1f3cf012f4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h @@ -28,12 +28,12 @@ #include "core_types.h" -struct core_dc; +struct dc; struct resource_pool; struct resource_pool *dce120_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc); + struct dc *dc); #endif /* __DC_RESOURCE_DCE120_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c index 4cba80ff6ca4..28fe3824441f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c @@ -25,7 +25,6 @@ #include "dm_services.h" #include "dc.h" -#include "core_dc.h" #include "core_types.h" #include "dce80_hw_sequencer.h" @@ -72,7 +71,7 @@ static const struct dce80_hw_seq_reg_offsets reg_offsets[] = { /***************************PIPE_CONTROL***********************************/ static bool dce80_enable_display_power_gating( - struct core_dc *dc, + struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating) @@ -107,7 +106,7 @@ static bool dce80_enable_display_power_gating( return false; } -bool dce80_hw_sequencer_construct(struct core_dc *dc) +bool dce80_hw_sequencer_construct(struct dc *dc) { dce110_hw_sequencer_construct(dc); diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h index 7cc203f433d3..9d6dd05bd596 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h @@ -28,9 +28,9 @@ #include "core_types.h" -struct core_dc; +struct dc; -bool dce80_hw_sequencer_construct(struct core_dc *dc); +bool dce80_hw_sequencer_construct(struct dc *dc); #endif /* __DC_HWSS_DCE80_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 132117e8bb77..838bfdaee009 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -684,7 +684,7 @@ static void destruct(struct dce110_resource_pool *pool) } static enum dc_status build_mapped_resource( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -720,7 +720,7 @@ static enum dc_status build_mapped_resource( } bool dce80_validate_bandwidth( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context) { /* TODO implement when needed but for now hardcode max value*/ @@ -752,7 +752,7 @@ static bool dce80_validate_surface_sets( } enum dc_status dce80_validate_with_context( - const struct core_dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count, struct validate_context *context, @@ -795,7 +795,7 @@ enum dc_status dce80_validate_with_context( } enum dc_status dce80_validate_guaranteed( - const struct core_dc *dc, + struct dc *dc, struct dc_stream_state *dc_stream, struct validate_context *context) { @@ -815,7 +815,7 @@ enum dc_status dce80_validate_guaranteed( if (result == DC_OK) { validate_guaranteed_copy_streams( - context, dc->public.caps.max_streams); + context, dc->caps.max_streams); result = resource_build_scaling_params_for_context(dc, context); } @@ -845,7 +845,7 @@ static const struct resource_funcs dce80_res_pool_funcs = { static bool dce80_construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dce110_resource_pool *pool) { unsigned int i; @@ -865,9 +865,9 @@ static bool dce80_construct( *************************************************/ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = res_cap.num_timing_generator; - dc->public.caps.max_downscale_ratio = 200; - dc->public.caps.i2c_speed_in_khz = 40; - dc->public.caps.max_cursor_size = 128; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 40; + dc->caps.max_cursor_size = 128; /************************************************* * Create resources * @@ -974,7 +974,7 @@ static bool dce80_construct( } } - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) @@ -993,7 +993,7 @@ res_create_fail: struct resource_pool *dce80_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc) + struct dc *dc) { struct dce110_resource_pool *pool = dm_alloc(sizeof(struct dce110_resource_pool)); @@ -1010,7 +1010,7 @@ struct resource_pool *dce80_create_resource_pool( static bool dce81_construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dce110_resource_pool *pool) { unsigned int i; @@ -1030,9 +1030,9 @@ static bool dce81_construct( *************************************************/ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = res_cap_81.num_timing_generator; - dc->public.caps.max_downscale_ratio = 200; - dc->public.caps.i2c_speed_in_khz = 40; - dc->public.caps.max_cursor_size = 128; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 40; + dc->caps.max_cursor_size = 128; /************************************************* * Create resources * @@ -1139,7 +1139,7 @@ static bool dce81_construct( } } - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) @@ -1158,7 +1158,7 @@ res_create_fail: struct resource_pool *dce81_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc) + struct dc *dc) { struct dce110_resource_pool *pool = dm_alloc(sizeof(struct dce110_resource_pool)); @@ -1175,7 +1175,7 @@ struct resource_pool *dce81_create_resource_pool( static bool dce83_construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dce110_resource_pool *pool) { unsigned int i; @@ -1195,9 +1195,9 @@ static bool dce83_construct( *************************************************/ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = res_cap_83.num_timing_generator; - dc->public.caps.max_downscale_ratio = 200; - dc->public.caps.i2c_speed_in_khz = 40; - dc->public.caps.max_cursor_size = 128; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 40; + dc->caps.max_cursor_size = 128; /************************************************* * Create resources * @@ -1300,7 +1300,7 @@ static bool dce83_construct( } } - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) @@ -1319,7 +1319,7 @@ res_create_fail: struct resource_pool *dce83_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc) + struct dc *dc) { struct dce110_resource_pool *pool = dm_alloc(sizeof(struct dce110_resource_pool)); diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h index 04f0cfe24ef2..eff31ab83a39 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h @@ -28,20 +28,20 @@ #include "core_types.h" -struct core_dc; +struct dc; struct resource_pool; struct resource_pool *dce80_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc); + struct dc *dc); struct resource_pool *dce81_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc); + struct dc *dc); struct resource_pool *dce83_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc); + struct dc *dc); #endif /* __DC_RESOURCE_DCE80_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c index 11386121f8ed..684241cb40d7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c @@ -26,7 +26,6 @@ #if defined(CONFIG_DRM_AMD_DC_DCN1_0) #include "reg_helper.h" -#include "core_dc.h" #include "resource.h" #include "dwb.h" #include "dcn10_dwb.h" diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 184627c8685e..d5d2398d92b8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -52,7 +52,7 @@ #define FN(reg_name, field_name) \ hws->shifts->field_name, hws->masks->field_name -static void log_mpc_crc(struct core_dc *dc) +static void log_mpc_crc(struct dc *dc) { struct dc_context *dc_ctx = dc->ctx; struct dce_hwseq *hws = dc->hwseq; @@ -130,7 +130,7 @@ static void dcn10_hubbub_wm_read_state(struct dce_hwseq *hws, s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); } -static void dcn10_log_hubbub_state(struct core_dc *dc) +static void dcn10_log_hubbub_state(struct dc *dc) { struct dc_context *dc_ctx = dc->ctx; struct dcn_hubbub_wm wm; @@ -157,7 +157,7 @@ static void dcn10_log_hubbub_state(struct core_dc *dc) DTN_INFO("\n"); } -static void dcn10_log_hw_state(struct core_dc *dc) +static void dcn10_log_hw_state(struct dc *dc) { struct dc_context *dc_ctx = dc->ctx; struct resource_pool *pool = dc->res_pool; @@ -273,7 +273,7 @@ static void verify_allow_pstate_change_high( forced_pstate_allow = true; if (should_log_hw_state) { - dcn10_log_hw_state(DC_TO_CORE(hws->ctx->dc)); + dcn10_log_hw_state(hws->ctx->dc); } BREAK_TO_DEBUGGER(); @@ -746,7 +746,7 @@ static void power_on_plane( "Un-gated front end for pipe %d\n", plane_id); } -static void bios_golden_init(struct core_dc *dc) +static void bios_golden_init(struct dc *dc) { struct dc_bios *bp = dc->ctx->dc_bios; int i; @@ -762,7 +762,7 @@ static void bios_golden_init(struct core_dc *dc) } } -static void dcn10_init_hw(struct core_dc *dc) +static void dcn10_init_hw(struct dc *dc) { int i; struct abm *abm = dc->res_pool->abm; @@ -773,7 +773,7 @@ static void dcn10_init_hw(struct core_dc *dc) REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); REG_WRITE(DIO_MEM_PWR_CTRL, 0); - if (!dc->public.debug.disable_clock_gate) { + if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); @@ -830,7 +830,7 @@ static void dcn10_init_hw(struct core_dc *dc) /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ REG_WRITE(DIO_MEM_PWR_CTRL, 0); - if (!dc->public.debug.disable_clock_gate) { + if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); @@ -845,7 +845,7 @@ static void dcn10_init_hw(struct core_dc *dc) static enum dc_status dcn10_prog_pixclk_crtc_otg( struct pipe_ctx *pipe_ctx, struct validate_context *context, - struct core_dc *dc) + struct dc *dc) { struct dc_stream_state *stream = pipe_ctx->stream; enum dc_color_space color_space; @@ -932,7 +932,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( } static void reset_back_end_for_pipe( - struct core_dc *dc, + struct dc *dc, struct pipe_ctx *pipe_ctx, struct validate_context *context) { @@ -979,7 +979,7 @@ static void reset_back_end_for_pipe( } /* trigger HW to start disconnect plane from stream on the next vsync */ -static void plane_atomic_disconnect(struct core_dc *dc, +static void plane_atomic_disconnect(struct dc *dc, int fe_idx) { struct mem_input *mi = dc->res_pool->mis[fe_idx]; @@ -1004,10 +1004,10 @@ static void plane_atomic_disconnect(struct core_dc *dc, if (opp_id == dc->res_pool->pipe_count) return; - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); mi->funcs->dcc_control(mi, false, false); - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); mpc->funcs->remove(mpc, dc->res_pool->opps[opp_id], fe_idx); @@ -1015,7 +1015,7 @@ static void plane_atomic_disconnect(struct core_dc *dc, /* disable HW used by plane. * note: cannot disable until disconnect is complete */ -static void plane_atomic_disable(struct core_dc *dc, +static void plane_atomic_disable(struct dc *dc, int fe_idx) { struct dce_hwseq *hws = dc->hwseq; @@ -1037,7 +1037,7 @@ static void plane_atomic_disable(struct core_dc *dc, mi->opp_id = 0xf; mi->mpcc_id = 0xf; - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); REG_UPDATE(HUBP_CLK_CNTL[fe_idx], @@ -1049,7 +1049,7 @@ static void plane_atomic_disable(struct core_dc *dc, REG_UPDATE(OPP_PIPE_CONTROL[opp_id], OPP_PIPE_CLOCK_EN, 0); - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); } @@ -1057,7 +1057,7 @@ static void plane_atomic_disable(struct core_dc *dc, * kill power to plane hw * note: cannot power down until plane is disable */ -static void plane_atomic_power_down(struct core_dc *dc, int fe_idx) +static void plane_atomic_power_down(struct dc *dc, int fe_idx) { struct dce_hwseq *hws = dc->hwseq; struct transform *xfm = dc->res_pool->transforms[fe_idx]; @@ -1072,13 +1072,13 @@ static void plane_atomic_power_down(struct core_dc *dc, int fe_idx) dm_logger_write(dc->ctx->logger, LOG_DC, "Power gated front end %d\n", fe_idx); - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); } static void reset_front_end( - struct core_dc *dc, + struct dc *dc, int fe_idx) { struct dce_hwseq *hws = dc->hwseq; @@ -1097,7 +1097,7 @@ static void reset_front_end( REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst], VUPDATE_NO_LOCK_EVENT_CLEAR, 1); tg->funcs->unlock(tg); - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(hws); if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) @@ -1112,7 +1112,7 @@ static void reset_front_end( fe_idx); } -static void dcn10_power_down_fe(struct core_dc *dc, int fe_idx) +static void dcn10_power_down_fe(struct dc *dc, int fe_idx) { struct dce_hwseq *hws = dc->hwseq; struct transform *xfm = dc->res_pool->transforms[fe_idx]; @@ -1129,12 +1129,12 @@ static void dcn10_power_down_fe(struct core_dc *dc, int fe_idx) dm_logger_write(dc->ctx->logger, LOG_DC, "Power gated front end %d\n", fe_idx); - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); } static void reset_hw_ctx_wrap( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { int i; @@ -1246,7 +1246,7 @@ static void toggle_watermark_change_req(struct dce_hwseq *hws) DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req); } -static void dcn10_update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ctx) +static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) { bool addr_patched = false; PHYSICAL_ADDRESS_LOC addr; @@ -1657,7 +1657,7 @@ static bool dcn10_set_output_transfer_func( } static void dcn10_pipe_control_lock( - struct core_dc *dc, + struct dc *dc, struct pipe_ctx *pipe, bool lock) { @@ -1669,7 +1669,7 @@ static void dcn10_pipe_control_lock( if (pipe->top_pipe) return; - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); if (lock) @@ -1677,7 +1677,7 @@ static void dcn10_pipe_control_lock( else pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); } @@ -1719,7 +1719,7 @@ static bool wait_for_reset_trigger_to_occur( } static void dcn10_enable_timing_synchronization( - struct core_dc *dc, + struct dc *dc, int group_index, int group_size, struct pipe_ctx *grouped_pipes[]) @@ -1748,7 +1748,7 @@ static void dcn10_enable_timing_synchronization( } static void print_rq_dlg_ttu( - struct core_dc *core_dc, + struct dc *core_dc, struct pipe_ctx *pipe_ctx) { dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS, @@ -1870,14 +1870,14 @@ static void print_rq_dlg_ttu( } static void dcn10_power_on_fe( - struct core_dc *dc, + struct dc *dc, struct pipe_ctx *pipe_ctx, struct validate_context *context) { struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct dce_hwseq *hws = dc->hwseq; - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { verify_allow_pstate_change_high(dc->hwseq); } @@ -1928,7 +1928,7 @@ static void dcn10_power_on_fe( print_rq_dlg_ttu(dc, pipe_ctx); } - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { verify_allow_pstate_change_high(dc->hwseq); } } @@ -2084,7 +2084,7 @@ static void dcn10_get_surface_visual_confirm_color( } static void update_dchubp_dpp( - struct core_dc *dc, + struct dc *dc, struct pipe_ctx *pipe_ctx, struct validate_context *context) { @@ -2126,7 +2126,7 @@ static void update_dchubp_dpp( size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport; - if (dc->public.config.gpu_vm_support) + if (dc->config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( pipe_ctx->plane_res.mi, plane_state->format, @@ -2142,7 +2142,7 @@ static void update_dchubp_dpp( mpcc_cfg.opp = pipe_ctx->stream_res.opp; for (top_pipe = pipe_ctx->top_pipe; top_pipe; top_pipe = top_pipe->top_pipe) mpcc_cfg.z_index++; - if (dc->public.debug.surface_visual_confirm) + if (dc->debug.surface_visual_confirm) dcn10_get_surface_visual_confirm_color( pipe_ctx, &mpcc_cfg.black_color); else @@ -2187,7 +2187,7 @@ static void update_dchubp_dpp( static void program_all_pipe_in_tree( - struct core_dc *dc, + struct dc *dc, struct pipe_ctx *pipe_ctx, struct validate_context *context) { @@ -2201,7 +2201,7 @@ static void program_all_pipe_in_tree( /* watermark is for all pipes */ program_watermarks(dc->hwseq, &context->bw.dcn.watermarks, ref_clk_mhz); - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { /* pstate stuck check after watermark update */ verify_allow_pstate_change_high(dc->hwseq); } @@ -2236,7 +2236,7 @@ static void program_all_pipe_in_tree( update_dchubp_dpp(dc, pipe_ctx, context); } - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { /* pstate stuck check after each pipe is programmed */ verify_allow_pstate_change_high(dc->hwseq); } @@ -2246,7 +2246,7 @@ static void program_all_pipe_in_tree( } static void dcn10_pplib_apply_display_requirements( - struct core_dc *dc, + struct dc *dc, struct validate_context *context) { struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; @@ -2273,14 +2273,14 @@ static void dcn10_pplib_apply_display_requirements( } static void dcn10_apply_ctx_for_surface( - struct core_dc *dc, + struct dc *dc, const struct dc_stream_state *stream, int num_planes, struct validate_context *context) { int i, be_idx; - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); be_idx = -1; @@ -2351,7 +2351,7 @@ static void dcn10_apply_ctx_for_surface( "[debug_mpo: apply_ctx disconnect pending on mpcc %d]\n", old_pipe_ctx->mpcc->inst);*/ - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); old_pipe_ctx->top_pipe = NULL; @@ -2422,18 +2422,18 @@ static void dcn10_apply_ctx_for_surface( context->bw.dcn.watermarks.d.pte_meta_urgent_ns ); - if (dc->public.debug.sanity_checks) + if (dc->debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); } static void dcn10_set_bandwidth( - struct core_dc *dc, + struct dc *dc, struct validate_context *context, bool decrease_allowed) { struct dm_pp_clock_for_voltage_req clock; - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { verify_allow_pstate_change_high(dc->hwseq); } @@ -2488,7 +2488,7 @@ static void dcn10_set_bandwidth( } dcn10_pplib_apply_display_requirements(dc, context); - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { verify_allow_pstate_change_high(dc->hwseq); } @@ -2541,7 +2541,7 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx, } static void set_plane_config( - const struct core_dc *dc, + const struct dc *dc, struct pipe_ctx *pipe_ctx, struct resource_context *res_ctx) { @@ -2586,7 +2586,7 @@ static void dcn10_config_stereo_parameters( return; } -static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc) +static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc) { struct crtc_stereo_flags flags = { 0 }; struct dc_stream_state *stream = pipe_ctx->stream; @@ -2607,13 +2607,13 @@ static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc) } static void dcn10_wait_for_mpcc_disconnect( - struct core_dc *dc, + struct dc *dc, struct resource_pool *res_pool, struct pipe_ctx *pipe_ctx) { int i; - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { verify_allow_pstate_change_high(dc->hwseq); } @@ -2631,14 +2631,14 @@ static void dcn10_wait_for_mpcc_disconnect( } } - if (dc->public.debug.sanity_checks) { + if (dc->debug.sanity_checks) { verify_allow_pstate_change_high(dc->hwseq); } } static bool dcn10_dummy_display_power_gating( - struct core_dc *dc, + struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating) @@ -2652,7 +2652,7 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) struct timing_generator *tg = pipe_ctx->stream_res.tg; if (plane_state->ctx->dc->debug.sanity_checks) { - struct core_dc *dc = DC_TO_CORE(plane_state->ctx->dc); + struct dc *dc = plane_state->ctx->dc; verify_allow_pstate_change_high(dc->hwseq); } @@ -2716,7 +2716,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { }; -void dcn10_hw_sequencer_construct(struct core_dc *dc) +void dcn10_hw_sequencer_construct(struct dc *dc) { dc->hwss = dcn10_funcs; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h index 28218dc43522..8bb09de8dcd7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h @@ -28,9 +28,9 @@ #include "core_types.h" -struct core_dc; +struct dc; -void dcn10_hw_sequencer_construct(struct core_dc *dc); +void dcn10_hw_sequencer_construct(struct dc *dc); extern void fill_display_configs( const struct validate_context *context, struct dm_pp_display_configuration *pp_display_cfg); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index c36843d497ac..2d9e88f08abb 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -825,7 +825,7 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) } static enum dc_status build_mapped_resource( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context) { @@ -872,7 +872,7 @@ static enum dc_status build_mapped_resource( } enum dc_status dcn10_validate_with_context( - const struct core_dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count, struct validate_context *context, @@ -917,7 +917,7 @@ enum dc_status dcn10_validate_with_context( } enum dc_status dcn10_validate_guaranteed( - const struct core_dc *dc, + struct dc *dc, struct dc_stream_state *dc_stream, struct validate_context *context) { @@ -937,7 +937,7 @@ enum dc_status dcn10_validate_guaranteed( if (result == DC_OK) { validate_guaranteed_copy_streams( - context, dc->public.caps.max_streams); + context, dc->caps.max_streams); result = resource_build_scaling_params_for_context(dc, context); } if (result == DC_OK && !dcn_validate_bandwidth(dc, context)) @@ -1221,7 +1221,7 @@ static struct resource_funcs dcn10_res_pool_funcs = { static bool construct( uint8_t num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct dcn10_resource_pool *pool) { int i; @@ -1244,16 +1244,16 @@ static bool construct( /* TODO: Hardcode to correct number of functional controllers */ pool->base.pipe_count = 4; - dc->public.caps.max_downscale_ratio = 200; - dc->public.caps.i2c_speed_in_khz = 100; - dc->public.caps.max_cursor_size = 256; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 100; + dc->caps.max_cursor_size = 256; - dc->public.caps.max_slave_planes = 1; + dc->caps.max_slave_planes = 1; if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) - dc->public.debug = debug_defaults_drv; + dc->debug = debug_defaults_drv; else - dc->public.debug = debug_defaults_diags; + dc->debug = debug_defaults_diags; /************************************************* * Create resources * @@ -1327,7 +1327,7 @@ static bool construct( if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { dc->dcn_soc->urgent_latency = 3; - dc->public.debug.disable_dmcu = true; + dc->debug.disable_dmcu = true; dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; } @@ -1347,10 +1347,10 @@ static bool construct( } } - if (!dc->public.debug.disable_pplib_clock_request) + if (!dc->debug.disable_pplib_clock_request) dcn_bw_update_from_pplib(dc); dcn_bw_sync_calcs_and_dml(dc); - if (!dc->public.debug.disable_pplib_wm_range) + if (!dc->debug.disable_pplib_wm_range) dcn_bw_notify_pplib_of_wm_ranges(dc); { @@ -1424,9 +1424,9 @@ static bool construct( goto res_create_fail; dcn10_hw_sequencer_construct(dc); - dc->public.caps.max_planes = pool->base.pipe_count; + dc->caps.max_planes = pool->base.pipe_count; - dc->public.cap_funcs = cap_funcs; + dc->cap_funcs = cap_funcs; return true; @@ -1449,7 +1449,7 @@ dwbc_create_fail: struct resource_pool *dcn10_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc) + struct dc *dc) { struct dcn10_resource_pool *pool = dm_alloc(sizeof(struct dcn10_resource_pool)); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h index 5f84dbd0bdea..8f71225bc61b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h @@ -31,7 +31,7 @@ #define TO_DCN10_RES_POOL(pool)\ container_of(pool, struct dcn10_resource_pool, base) -struct core_dc; +struct dc; struct resource_pool; struct _vcs_dpi_display_pipe_params_st; @@ -40,7 +40,7 @@ struct dcn10_resource_pool { }; struct resource_pool *dcn10_create_resource_pool( uint8_t num_virtual_links, - struct core_dc *dc); + struct dc *dc); #endif /* __DC_RESOURCE_DCN10_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h deleted file mode 100644 index ebe1fd78a92a..000000000000 --- a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * core_dc.h - * - * Created on: Nov 13, 2015 - * Author: yonsun - */ - -#ifndef __CORE_DC_H__ -#define __CORE_DC_H__ - -#include "core_types.h" -#include "hw_sequencer.h" -#include "compressor.h" - -#define DC_TO_CORE(dc)\ - container_of(dc, struct core_dc, public) - -struct core_dc { - struct dc public; - struct dc_context *ctx; - - uint8_t link_count; - struct dc_link *links[MAX_PIPES * 2]; - - struct validate_context *current_context; - struct resource_pool *res_pool; - - /* Display Engine Clock levels */ - struct dm_pp_clock_levels sclk_lvls; - - /* Inputs into BW and WM calculations. */ - struct bw_calcs_dceip *bw_dceip; - struct bw_calcs_vbios *bw_vbios; -#ifdef CONFIG_DRM_AMD_DC_DCN1_0 - struct dcn_soc_bounding_box *dcn_soc; - struct dcn_ip_params *dcn_ip; - struct display_mode_lib dml; -#endif - - /* HW functions */ - struct hw_sequencer_funcs hwss; - struct dce_hwseq *hwseq; - - /* temp store of dm_pp_display_configuration - * to compare to see if display config changed - */ - struct dm_pp_display_configuration prev_display_config; - - /* FBC compressor */ -#ifdef ENABLE_FBC - struct compressor *fbc_compressor; -#endif -}; - -#endif /* __CORE_DC_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 28454028434c..f8ade552c595 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -52,7 +52,7 @@ void enable_surface_flip_reporting(struct dc_plane_state *plane_state, /************ link *****************/ struct link_init_data { - const struct core_dc *dc; + const struct dc *dc; struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ uint32_t connector_index; /* this will be mapped to the HPD pins */ uint32_t link_index; /* this is mapped to DAL display_index @@ -87,19 +87,19 @@ struct resource_funcs { struct link_encoder *(*link_enc_create)( const struct encoder_init_data *init); enum dc_status (*validate_with_context)( - const struct core_dc *dc, + struct dc *dc, const struct dc_validation_set set[], int set_count, struct validate_context *context, struct validate_context *old_context); enum dc_status (*validate_guaranteed)( - const struct core_dc *dc, + struct dc *dc, struct dc_stream_state *stream, struct validate_context *context); bool (*validate_bandwidth)( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context); struct pipe_ctx *(*acquire_idle_pipe_for_layer)( diff --git a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h index 36c48f7d3f56..6a205b010084 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h @@ -33,7 +33,7 @@ #include "bw_fixed.h" struct pipe_ctx; -struct core_dc; +struct dc; struct validate_context; struct dce_bw_output; diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h index 7e8abcd60d12..58744fe87ed8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h @@ -34,7 +34,7 @@ #include "display_clock.h" #include "../dml/display_mode_lib.h" -struct core_dc; +struct dc; struct validate_context; /******************************************************************************* @@ -620,16 +620,16 @@ struct dcn_ip_params { extern const struct dcn_ip_params dcn10_ip_defaults; bool dcn_validate_bandwidth( - const struct core_dc *dc, + struct dc *dc, struct validate_context *context); unsigned int dcn_find_dcfclk_suits_all( - const struct core_dc *dc, + const struct dc *dc, struct clocks_value *clocks); -void dcn_bw_update_from_pplib(struct core_dc *dc); -void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc); -void dcn_bw_sync_calcs_and_dml(struct core_dc *dc); +void dcn_bw_update_from_pplib(struct dc *dc); +void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc); +void dcn_bw_sync_calcs_and_dml(struct dc *dc); #endif /* __DCN_CALCS_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index a02f18ae527d..f876a11c903f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -30,6 +30,7 @@ #include "dml/display_mode_structs.h" +struct dchub_init_data; struct cstate_pstate_watermarks_st { uint32_t cstate_exit_ns; uint32_t cstate_enter_plus_exit_ns; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 7689e372b9da..c73dca9f6d46 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -25,8 +25,10 @@ #ifndef __DC_HW_SEQUENCER_H__ #define __DC_HW_SEQUENCER_H__ -#include "core_types.h" -#include "timing_generator.h" +#include "dc_types.h" +#include "clock_source.h" +#include "inc/hw/timing_generator.h" +#include "core_status.h" enum pipe_gating_control { PIPE_GATING_CONTROL_DISABLE = 0, @@ -46,25 +48,31 @@ struct dce_hwseq { struct dce_hwseq_wa wa; }; +struct pipe_ctx; +struct validate_context; +struct dchub_init_data; +struct dc_static_screen_events; +struct resource_pool; +struct resource_context; struct hw_sequencer_funcs { - void (*init_hw)(struct core_dc *dc); + void (*init_hw)(struct dc *dc); enum dc_status (*apply_ctx_to_hw)( - struct core_dc *dc, struct validate_context *context); + struct dc *dc, struct validate_context *context); void (*reset_hw_ctx_wrap)( - struct core_dc *dc, struct validate_context *context); + struct dc *dc, struct validate_context *context); void (*apply_ctx_for_surface)( - struct core_dc *dc, + struct dc *dc, const struct dc_stream_state *stream, int num_planes, struct validate_context *context); void (*set_plane_config)( - const struct core_dc *dc, + const struct dc *dc, struct pipe_ctx *pipe_ctx, struct resource_context *res_ctx); @@ -77,7 +85,7 @@ struct hw_sequencer_funcs { uint16_t *matrix); void (*update_plane_addr)( - const struct core_dc *dc, + const struct dc *dc, struct pipe_ctx *pipe_ctx); void (*update_dchub)( @@ -95,12 +103,12 @@ struct hw_sequencer_funcs { struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream); - void (*power_down)(struct core_dc *dc); + void (*power_down)(struct dc *dc); - void (*enable_accelerated_mode)(struct core_dc *dc); + void (*enable_accelerated_mode)(struct dc *dc); void (*enable_timing_synchronization)( - struct core_dc *dc, + struct dc *dc, int group_index, int group_size, struct pipe_ctx *grouped_pipes[]); @@ -110,14 +118,14 @@ struct hw_sequencer_funcs { bool clock_gating); bool (*enable_display_power_gating)( - struct core_dc *dc, + struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating); - void (*power_down_front_end)(struct core_dc *dc, int fe_idx); + void (*power_down_front_end)(struct dc *dc, int fe_idx); - void (*power_on_front_end)(struct core_dc *dc, + void (*power_on_front_end)(struct dc *dc, struct pipe_ctx *pipe, struct validate_context *context); @@ -131,12 +139,12 @@ struct hw_sequencer_funcs { struct dc_link_settings *link_settings); void (*pipe_control_lock)( - struct core_dc *dc, + struct dc *dc, struct pipe_ctx *pipe, bool lock); void (*set_bandwidth)( - struct core_dc *dc, + struct dc *dc, struct validate_context *context, bool decrease_allowed); @@ -152,23 +160,23 @@ struct hw_sequencer_funcs { enum dc_status (*prog_pixclk_crtc_otg)( struct pipe_ctx *pipe_ctx, struct validate_context *context, - struct core_dc *dc); + struct dc *dc); void (*setup_stereo)( struct pipe_ctx *pipe_ctx, - struct core_dc *dc); + struct dc *dc); void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); - void (*log_hw_state)(struct core_dc *dc); + void (*log_hw_state)(struct dc *dc); - void (*wait_for_mpcc_disconnect)(struct core_dc *dc, + void (*wait_for_mpcc_disconnect)(struct dc *dc, struct resource_pool *res_pool, struct pipe_ctx *pipe_ctx); }; void color_space_to_black_color( - const struct core_dc *dc, + const struct dc *dc, enum dc_color_space colorspace, struct tg_color *black_color); diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index 7f30d9937d10..13218a52e2fa 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -27,7 +27,6 @@ #include "core_types.h" #include "core_status.h" -#include "core_dc.h" #include "dal_asic_id.h" /* TODO unhardcode, 4 for CZ*/ @@ -67,27 +66,27 @@ struct resource_create_funcs { bool resource_construct( unsigned int num_virtual_links, - struct core_dc *dc, + struct dc *dc, struct resource_pool *pool, const struct resource_create_funcs *create_funcs); struct resource_pool *dc_create_resource_pool( - struct core_dc *dc, + struct dc *dc, int num_virtual_links, enum dce_version dc_version, struct hw_asic_id asic_id); -void dc_destroy_resource_pool(struct core_dc *dc); +void dc_destroy_resource_pool(struct dc *dc); enum dc_status resource_map_pool_resources( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context); bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx); enum dc_status resource_build_scaling_params_for_context( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context); void resource_build_info_frame(struct pipe_ctx *pipe_ctx); @@ -148,12 +147,12 @@ void resource_validate_ctx_update_pointer_after_copy( struct validate_context *dst_ctx); enum dc_status resource_map_clock_resources( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context); enum dc_status resource_map_phy_clock_resources( - const struct core_dc *dc, + const struct dc *dc, struct validate_context *context, struct validate_context *old_context); diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c index 24e47eb8cf3f..e3a12f3e0642 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c @@ -34,8 +34,8 @@ #include "ivsrcid/ivsrcid_vislands30.h" -#include "core_dc.h" - +#include "dc.h" +#include "core_types.h" static bool hpd_ack( struct irq_service *irq_service, const struct irq_source_info *info) @@ -206,7 +206,7 @@ bool dce110_vblank_set( bool enable) { struct dc_context *dc_ctx = irq_service->ctx; - struct core_dc *core_dc = DC_TO_CORE(irq_service->ctx->dc); + struct dc *core_dc = irq_service->ctx->dc; enum dc_irq_source dal_irq_src = dc_interrupt_to_irq_source( irq_service->ctx->dc, info->src_id, diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c index 7e8cb22f280f..f458ef8e4c57 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c @@ -36,7 +36,6 @@ #include "ivsrcid/ivsrcid_vislands30.h" #include "dc_types.h" -#include "inc/core_dc.h" static bool hpd_ack( struct irq_service *irq_service, diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index beb790937769..93c8556358f0 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -76,23 +76,23 @@ void logger_write(struct dal_logger *logger, void *paralist); void pre_surface_trace( - const struct dc *dc, + struct dc *dc, const struct dc_plane_state *const *plane_states, int surface_count); void update_surface_trace( - const struct dc *dc, + struct dc *dc, const struct dc_surface_update *updates, int surface_count); -void post_surface_trace(const struct dc *dc); +void post_surface_trace(struct dc *dc); void context_timing_trace( - const struct dc *dc, + struct dc *dc, struct resource_context *res_ctx); void context_clock_trace( - const struct dc *dc, + struct dc *dc, struct validate_context *context); /* Any function which is empty or have incomplete implementation should be diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index f0a3e4332a09..f49203b3eb94 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -27,7 +27,6 @@ #include "dc.h" #include "mod_freesync.h" #include "core_types.h" -#include "core_dc.h" #define MOD_FREESYNC_MAX_CONCURRENT_STREAMS 32 @@ -146,7 +145,7 @@ struct mod_freesync *mod_freesync_create(struct dc *dc) struct core_freesync *core_freesync = dm_alloc(sizeof(struct core_freesync)); - struct core_dc *core_dc = DC_TO_CORE(dc); + struct dc *core_dc = dc; struct persistent_data_flag flag; @@ -246,7 +245,7 @@ static unsigned int map_index_from_stream(struct core_freesync *core_freesync, bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, struct dc_stream_state *stream, struct mod_freesync_caps *caps) { - struct core_dc *core_dc = NULL; + struct dc *core_dc = NULL; struct core_freesync *core_freesync = NULL; int persistent_freesync_enable = 0; struct persistent_data_flag flag; @@ -257,7 +256,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, return false; core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); - core_dc = DC_TO_CORE(core_freesync->dc); + core_dc = core_freesync->dc; flag.save_per_edid = true; flag.save_per_link = false; @@ -971,14 +970,14 @@ bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, unsigned int stream_index, map_index; int persistent_data = 0; struct persistent_data_flag flag; - struct core_dc *core_dc = NULL; + struct dc *core_dc = NULL; struct core_freesync *core_freesync = NULL; if (mod_freesync == NULL) return false; core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); - core_dc = DC_TO_CORE(core_freesync->dc); + core_dc = core_freesync->dc; flag.save_per_edid = true; flag.save_per_link = false; -- cgit v1.2.3 From 156590454259a19d1709fab2ff7d59870574e822 Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Wed, 23 Aug 2017 15:44:42 -0400 Subject: drm/amd/display: Clean up flattening core_dc to dc Clean up some code related to flattening core_dc commit (Remove redundent dc = dc, which was the result of removing DC_TO_CORE() macro) Signed-off-by: Bhawanpreet Lakha Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 12 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 335 +++++++++------------ .../drm/amd/display/modules/freesync/freesync.c | 19 +- 3 files changed, 164 insertions(+), 202 deletions(-) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index afd403ceb2a7..5e5766a63a47 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -983,15 +983,14 @@ bool dcn_validate_bandwidth( if (v->voltage_level == 0 && (dc->debug.sr_exit_time_dpm0_ns || dc->debug.sr_enter_plus_exit_time_dpm0_ns)) { - struct dc *dc_core = dc; if (dc->debug.sr_enter_plus_exit_time_dpm0_ns) v->sr_enter_plus_exit_time = dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f; if (dc->debug.sr_exit_time_dpm0_ns) v->sr_exit_time = dc->debug.sr_exit_time_dpm0_ns / 1000.0f; - dc_core->dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time; - dc_core->dml.soc.sr_exit_time_us = v->sr_exit_time; + dc->dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time; + dc->dml.soc.sr_exit_time_us = v->sr_exit_time; mode_support_and_system_configuration(v); } @@ -1114,11 +1113,10 @@ bool dcn_validate_bandwidth( } if (v->voltage_level == 0) { - struct dc *dc_core = dc; - dc_core->dml.soc.sr_enter_plus_exit_time_us = - dc_core->dcn_soc->sr_enter_plus_exit_time; - dc_core->dml.soc.sr_exit_time_us = dc_core->dcn_soc->sr_exit_time; + dc->dml.soc.sr_enter_plus_exit_time_us = + dc->dcn_soc->sr_enter_plus_exit_time; + dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time; } /* diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 79980cb0900c..dc1b7d061be2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -155,20 +155,19 @@ static bool stream_adjust_vmin_vmax(struct dc *dc, int vmin, int vmax) { /* TODO: Support multiple streams */ - struct dc *core_dc = dc; struct dc_stream_state *stream = streams[0]; int i = 0; bool ret = false; for (i = 0; i < MAX_PIPES; i++) { - struct pipe_ctx *pipe = &core_dc->current_context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe = &dc->current_context->res_ctx.pipe_ctx[i]; if (pipe->stream == stream && pipe->stream_res.stream_enc) { - core_dc->hwss.set_drr(&pipe, 1, vmin, vmax); + dc->hwss.set_drr(&pipe, 1, vmin, vmax); /* build and update the info frame */ resource_build_info_frame(pipe); - core_dc->hwss.update_info_frame(pipe); + dc->hwss.update_info_frame(pipe); ret = true; } @@ -181,7 +180,6 @@ static bool stream_get_crtc_position(struct dc *dc, unsigned int *v_pos, unsigned int *nom_v_pos) { /* TODO: Support multiple streams */ - struct dc *core_dc = dc; struct dc_stream_state *stream = streams[0]; int i = 0; bool ret = false; @@ -189,10 +187,10 @@ static bool stream_get_crtc_position(struct dc *dc, for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe = - &core_dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_context->res_ctx.pipe_ctx[i]; if (pipe->stream == stream && pipe->stream_res.stream_enc) { - core_dc->hwss.get_position(&pipe, 1, &position); + dc->hwss.get_position(&pipe, 1, &position); *v_pos = position.vertical_count; *nom_v_pos = position.nominal_vcount; @@ -204,15 +202,14 @@ static bool stream_get_crtc_position(struct dc *dc, static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) { - struct dc *core_dc = dc; int i = 0; bool ret = false; struct pipe_ctx *pipes; for (i = 0; i < MAX_PIPES; i++) { - if (core_dc->current_context->res_ctx.pipe_ctx[i].stream == stream) { - pipes = &core_dc->current_context->res_ctx.pipe_ctx[i]; - core_dc->hwss.program_gamut_remap(pipes); + if (dc->current_context->res_ctx.pipe_ctx[i].stream == stream) { + pipes = &dc->current_context->res_ctx.pipe_ctx[i]; + dc->hwss.program_gamut_remap(pipes); ret = true; } } @@ -222,17 +219,16 @@ static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) static bool program_csc_matrix(struct dc *dc, struct dc_stream_state *stream) { - struct dc *core_dc = dc; int i = 0; bool ret = false; struct pipe_ctx *pipes; for (i = 0; i < MAX_PIPES; i++) { - if (core_dc->current_context->res_ctx.pipe_ctx[i].stream + if (dc->current_context->res_ctx.pipe_ctx[i].stream == stream) { - pipes = &core_dc->current_context->res_ctx.pipe_ctx[i]; - core_dc->hwss.program_csc_matrix(pipes, + pipes = &dc->current_context->res_ctx.pipe_ctx[i]; + dc->hwss.program_csc_matrix(pipes, stream->output_color_space, stream->csc_color_matrix.matrix); ret = true; @@ -247,7 +243,6 @@ static void set_static_screen_events(struct dc *dc, int num_streams, const struct dc_static_screen_events *events) { - struct dc *core_dc = dc; int i = 0; int j = 0; struct pipe_ctx *pipes_affected[MAX_PIPES]; @@ -257,45 +252,44 @@ static void set_static_screen_events(struct dc *dc, struct dc_stream_state *stream = streams[i]; for (j = 0; j < MAX_PIPES; j++) { - if (core_dc->current_context->res_ctx.pipe_ctx[j].stream + if (dc->current_context->res_ctx.pipe_ctx[j].stream == stream) { pipes_affected[num_pipes_affected++] = - &core_dc->current_context->res_ctx.pipe_ctx[j]; + &dc->current_context->res_ctx.pipe_ctx[j]; } } } - core_dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events); + dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events); } static void set_drive_settings(struct dc *dc, struct link_training_settings *lt_settings, const struct dc_link *link) { - struct dc *core_dc = dc; + int i; - for (i = 0; i < core_dc->link_count; i++) { - if (core_dc->links[i] == link) + for (i = 0; i < dc->link_count; i++) { + if (dc->links[i] == link) break; } - if (i >= core_dc->link_count) + if (i >= dc->link_count) ASSERT_CRITICAL(false); - dc_link_dp_set_drive_settings(core_dc->links[i], lt_settings); + dc_link_dp_set_drive_settings(dc->links[i], lt_settings); } static void perform_link_training(struct dc *dc, struct dc_link_settings *link_setting, bool skip_video_pattern) { - struct dc *core_dc = dc; int i; - for (i = 0; i < core_dc->link_count; i++) + for (i = 0; i < dc->link_count; i++) dc_link_dp_perform_link_training( - core_dc->links[i], + dc->links[i], link_setting, skip_video_pattern); } @@ -371,44 +365,44 @@ void set_dither_option(struct dc_stream_state *stream, opp_program_bit_depth_reduction(pipes->stream_res.opp, ¶ms); } -static void allocate_dc_stream_funcs(struct dc *core_dc) +static void allocate_dc_stream_funcs(struct dc *dc) { - if (core_dc->hwss.set_drr != NULL) { - core_dc->stream_funcs.adjust_vmin_vmax = + if (dc->hwss.set_drr != NULL) { + dc->stream_funcs.adjust_vmin_vmax = stream_adjust_vmin_vmax; } - core_dc->stream_funcs.set_static_screen_events = + dc->stream_funcs.set_static_screen_events = set_static_screen_events; - core_dc->stream_funcs.get_crtc_position = + dc->stream_funcs.get_crtc_position = stream_get_crtc_position; - core_dc->stream_funcs.set_gamut_remap = + dc->stream_funcs.set_gamut_remap = set_gamut_remap; - core_dc->stream_funcs.program_csc_matrix = + dc->stream_funcs.program_csc_matrix = program_csc_matrix; - core_dc->stream_funcs.set_dither_option = + dc->stream_funcs.set_dither_option = set_dither_option; - core_dc->link_funcs.set_drive_settings = + dc->link_funcs.set_drive_settings = set_drive_settings; - core_dc->link_funcs.perform_link_training = + dc->link_funcs.perform_link_training = perform_link_training; - core_dc->link_funcs.set_preferred_link_settings = + dc->link_funcs.set_preferred_link_settings = set_preferred_link_settings; - core_dc->link_funcs.enable_hpd = + dc->link_funcs.enable_hpd = enable_hpd; - core_dc->link_funcs.disable_hpd = + dc->link_funcs.disable_hpd = disable_hpd; - core_dc->link_funcs.set_test_pattern = + dc->link_funcs.set_test_pattern = set_test_pattern; } @@ -622,41 +616,41 @@ void ProgramPixelDurationV(unsigned int pixelClockInKHz ) struct dc *dc_create(const struct dc_init_data *init_params) { - struct dc *core_dc = dm_alloc(sizeof(*core_dc)); + struct dc *dc = dm_alloc(sizeof(*dc)); unsigned int full_pipe_count; - if (NULL == core_dc) + if (NULL == dc) goto alloc_fail; - if (false == construct(core_dc, init_params)) + if (false == construct(dc, init_params)) goto construct_fail; /*TODO: separate HW and SW initialization*/ - core_dc->hwss.init_hw(core_dc); + dc->hwss.init_hw(dc); - full_pipe_count = core_dc->res_pool->pipe_count; - if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE) + full_pipe_count = dc->res_pool->pipe_count; + if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE) full_pipe_count--; - core_dc->caps.max_streams = min( + dc->caps.max_streams = min( full_pipe_count, - core_dc->res_pool->stream_enc_count); + dc->res_pool->stream_enc_count); - core_dc->caps.max_links = core_dc->link_count; - core_dc->caps.max_audios = core_dc->res_pool->audio_count; + dc->caps.max_links = dc->link_count; + dc->caps.max_audios = dc->res_pool->audio_count; - core_dc->config = init_params->flags; + dc->config = init_params->flags; - dm_logger_write(core_dc->ctx->logger, LOG_DC, + dm_logger_write(dc->ctx->logger, LOG_DC, "Display Core initialized\n"); /* TODO: missing feature to be enabled */ - core_dc->debug.disable_dfs_bypass = true; + dc->debug.disable_dfs_bypass = true; - return core_dc; + return dc; construct_fail: - dm_free(core_dc); + dm_free(dc); alloc_fail: return NULL; @@ -664,9 +658,8 @@ alloc_fail: void dc_destroy(struct dc **dc) { - struct dc *core_dc = *dc; - destruct(core_dc); - dm_free(core_dc); + destruct(*dc); + dm_free(*dc); *dc = NULL; } @@ -674,7 +667,6 @@ bool dc_validate_guaranteed( struct dc *dc, struct dc_stream_state *stream) { - struct dc *core_dc = dc; enum dc_status result = DC_ERROR_UNEXPECTED; struct validate_context *context; @@ -687,14 +679,14 @@ bool dc_validate_guaranteed( atomic_inc(&context->ref_count); - result = core_dc->res_pool->funcs->validate_guaranteed( - core_dc, stream, context); + result = dc->res_pool->funcs->validate_guaranteed( + dc, stream, context); dc_release_validate_context(context); context_alloc_fail: if (result != DC_OK) { - dm_logger_write(core_dc->ctx->logger, LOG_WARNING, + dm_logger_write(dc->ctx->logger, LOG_WARNING, "%s:guaranteed validation failed, dc_status:%d\n", __func__, result); @@ -704,12 +696,12 @@ context_alloc_fail: } static void program_timing_sync( - struct dc *core_dc, + struct dc *dc, struct validate_context *ctx) { int i, j; int group_index = 0; - int pipe_count = core_dc->res_pool->pipe_count; + int pipe_count = dc->res_pool->pipe_count; struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL }; for (i = 0; i < pipe_count; i++) { @@ -770,8 +762,8 @@ static void program_timing_sync( } if (group_size > 1) { - core_dc->hwss.enable_timing_synchronization( - core_dc, group_index, group_size, pipe_set); + dc->hwss.enable_timing_synchronization( + dc, group_index, group_size, pipe_set); group_index++; } } @@ -803,17 +795,16 @@ bool dc_enable_stereo( bool ret = true; int i, j; struct pipe_ctx *pipe; - struct dc *core_dc = dc; for (i = 0; i < MAX_PIPES; i++) { if (context != NULL) pipe = &context->res_ctx.pipe_ctx[i]; else - pipe = &core_dc->current_context->res_ctx.pipe_ctx[i]; + pipe = &dc->current_context->res_ctx.pipe_ctx[i]; for (j = 0 ; pipe && j < stream_count; j++) { if (streams[j] && streams[j] == pipe->stream && - core_dc->hwss.setup_stereo) - core_dc->hwss.setup_stereo(pipe, core_dc); + dc->hwss.setup_stereo) + dc->hwss.setup_stereo(pipe, dc); } } @@ -827,8 +818,7 @@ bool dc_enable_stereo( */ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *context) { - struct dc *core_dc = dc; - struct dc_bios *dcb = core_dc->ctx->dc_bios; + struct dc_bios *dcb = dc->ctx->dc_bios; enum dc_status result = DC_ERROR_UNEXPECTED; struct pipe_ctx *pipe; int i, j, k, l; @@ -838,22 +828,22 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c dc_streams[i] = context->streams[i]; if (!dcb->funcs->is_accelerated_mode(dcb)) - core_dc->hwss.enable_accelerated_mode(core_dc); + dc->hwss.enable_accelerated_mode(dc); - for (i = 0; i < core_dc->res_pool->pipe_count; i++) { + for (i = 0; i < dc->res_pool->pipe_count; i++) { pipe = &context->res_ctx.pipe_ctx[i]; - core_dc->hwss.wait_for_mpcc_disconnect(core_dc, core_dc->res_pool, pipe); + dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe); } - result = core_dc->hwss.apply_ctx_to_hw(core_dc, context); + result = dc->hwss.apply_ctx_to_hw(dc, context); - program_timing_sync(core_dc, context); + program_timing_sync(dc, context); for (i = 0; i < context->stream_count; i++) { const struct dc_sink *sink = context->streams[i]->sink; for (j = 0; j < context->stream_status[i].plane_count; j++) { - core_dc->hwss.apply_ctx_for_surface( - core_dc, context->streams[i], + dc->hwss.apply_ctx_for_surface( + dc, context->streams[i], context->stream_status[i].plane_count, context); @@ -867,8 +857,8 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c for (l = 0 ; pipe && l < context->stream_count; l++) { if (context->streams[l] && context->streams[l] == pipe->stream && - core_dc->hwss.setup_stereo) - core_dc->hwss.setup_stereo(pipe, core_dc); + dc->hwss.setup_stereo) + dc->hwss.setup_stereo(pipe, dc); } } } @@ -883,11 +873,11 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c dc_enable_stereo(dc, context, dc_streams, context->stream_count); - dc_release_validate_context(core_dc->current_context); + dc_release_validate_context(dc->current_context); - core_dc->current_context = context; + dc->current_context = context; - dc_retain_validate_context(core_dc->current_context); + dc_retain_validate_context(dc->current_context); return (result == DC_OK); } @@ -895,20 +885,19 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c bool dc_commit_context(struct dc *dc, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; - struct dc *core_dc = dc; int i; - if (false == context_changed(core_dc, context)) + if (false == context_changed(dc, context)) return DC_OK; - dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n", + dm_logger_write(dc->ctx->logger, LOG_DC, "%s: %d streams\n", __func__, context->stream_count); for (i = 0; i < context->stream_count; i++) { struct dc_stream_state *stream = context->streams[i]; dc_stream_log(stream, - core_dc->ctx->logger, + dc->ctx->logger, LOG_DC); } @@ -921,21 +910,20 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context) bool dc_post_update_surfaces_to_stream(struct dc *dc) { int i; - struct dc *core_dc = dc; - struct validate_context *context = core_dc->current_context; + struct validate_context *context = dc->current_context; post_surface_trace(dc); - for (i = 0; i < core_dc->res_pool->pipe_count; i++) + for (i = 0; i < dc->res_pool->pipe_count; i++) if (context->res_ctx.pipe_ctx[i].stream == NULL || context->res_ctx.pipe_ctx[i].plane_state == NULL) - core_dc->hwss.power_down_front_end(core_dc, i); + dc->hwss.power_down_front_end(dc, i); /* 3rd param should be true, temp w/a for RV*/ #if defined(CONFIG_DRM_AMD_DC_DCN1_0) - core_dc->hwss.set_bandwidth(core_dc, context, core_dc->ctx->dce_version < DCN_VERSION_1_0); + dc->hwss.set_bandwidth(dc, context, dc->ctx->dce_version < DCN_VERSION_1_0); #else - core_dc->hwss.set_bandwidth(core_dc, context, true); + dc->hwss.set_bandwidth(dc, context, true); #endif return true; } @@ -1184,7 +1172,6 @@ enum surface_update_type dc_check_update_surfaces_for_stream( struct dc_stream_update *stream_update, const struct dc_stream_status *stream_status) { - struct dc *core_dc = dc; int i; enum surface_update_type overall_type = UPDATE_TYPE_FAST; @@ -1196,7 +1183,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream( for (i = 0 ; i < surface_count; i++) { enum surface_update_type type = - det_surface_update(core_dc, &updates[i], i); + det_surface_update(dc, &updates[i], i); if (type == UPDATE_TYPE_FULL) return type; @@ -1230,12 +1217,11 @@ void dc_update_planes_and_stream(struct dc *dc, struct dc_stream_state *stream, struct dc_stream_update *stream_update) { - struct dc *core_dc = dc; struct validate_context *context; int i, j; enum surface_update_type update_type; const struct dc_stream_status *stream_status; - struct dc_context *dc_ctx = core_dc->ctx; + struct dc_context *dc_ctx = dc->ctx; stream_status = dc_stream_get_status(stream); @@ -1249,7 +1235,7 @@ void dc_update_planes_and_stream(struct dc *dc, ASSERT(0); } #endif - context = core_dc->current_context; + context = dc->current_context; /* update current stream with the new updates */ if (stream_update) { @@ -1303,7 +1289,7 @@ void dc_update_planes_and_stream(struct dc *dc, goto context_alloc_fail; dc_resource_validate_ctx_copy_construct( - core_dc->current_context, context); + dc->current_context, context); /*remove old surfaces from context */ if (!dc_rem_all_planes_for_stream(dc, stream, context)) { @@ -1365,7 +1351,7 @@ void dc_update_planes_and_stream(struct dc *dc, } if (update_type >= UPDATE_TYPE_MED) { - for (j = 0; j < core_dc->res_pool->pipe_count; j++) { + for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; if (pipe_ctx->plane_state != surface) @@ -1403,31 +1389,31 @@ void dc_update_planes_and_stream(struct dc *dc, } if (update_type == UPDATE_TYPE_FULL) { - if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) { + if (!dc->res_pool->funcs->validate_bandwidth(dc, context)) { BREAK_TO_DEBUGGER(); goto fail; } else { - core_dc->hwss.set_bandwidth(core_dc, context, false); + dc->hwss.set_bandwidth(dc, context, false); context_clock_trace(dc, context); } } if (update_type > UPDATE_TYPE_FAST) { - for (j = 0; j < core_dc->res_pool->pipe_count; j++) { + for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - core_dc->hwss.wait_for_mpcc_disconnect(core_dc, core_dc->res_pool, pipe_ctx); + dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); } } if (surface_count == 0) - core_dc->hwss.apply_ctx_for_surface(core_dc, stream, surface_count, context); + dc->hwss.apply_ctx_for_surface(dc, stream, surface_count, context); /* Lock pipes for provided surfaces, or all active if full update*/ for (i = 0; i < surface_count; i++) { struct dc_plane_state *plane_state = srf_updates[i].surface; - for (j = 0; j < core_dc->res_pool->pipe_count; j++) { + for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; if (update_type != UPDATE_TYPE_FULL && pipe_ctx->plane_state != plane_state) @@ -1435,8 +1421,8 @@ void dc_update_planes_and_stream(struct dc *dc, if (!pipe_ctx->plane_state || pipe_ctx->top_pipe) continue; - core_dc->hwss.pipe_control_lock( - core_dc, + dc->hwss.pipe_control_lock( + dc, pipe_ctx, true); } @@ -1445,9 +1431,9 @@ void dc_update_planes_and_stream(struct dc *dc, } /* Full fe update*/ - for (j = 0; j < core_dc->res_pool->pipe_count; j++) { + for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - struct pipe_ctx *cur_pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[j]; + struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[j]; bool is_new_pipe_surface = cur_pipe_ctx->plane_state != pipe_ctx->plane_state; struct dc_cursor_position position = { 0 }; @@ -1458,18 +1444,18 @@ void dc_update_planes_and_stream(struct dc *dc, if (!pipe_ctx->top_pipe && pipe_ctx->stream) { struct dc_stream_status *stream_status = stream_get_status(context, pipe_ctx->stream); - core_dc->hwss.apply_ctx_for_surface( - core_dc, pipe_ctx->stream, stream_status->plane_count, context); + dc->hwss.apply_ctx_for_surface( + dc, pipe_ctx->stream, stream_status->plane_count, context); } /* TODO: this is a hack w/a for switching from mpo to pipe split */ dc_stream_set_cursor_position(pipe_ctx->stream, &position); if (is_new_pipe_surface) { - core_dc->hwss.update_plane_addr(core_dc, pipe_ctx); - core_dc->hwss.set_input_transfer_func( + dc->hwss.update_plane_addr(dc, pipe_ctx); + dc->hwss.set_input_transfer_func( pipe_ctx, pipe_ctx->plane_state); - core_dc->hwss.set_output_transfer_func( + dc->hwss.set_output_transfer_func( pipe_ctx, pipe_ctx->stream); } } @@ -1482,40 +1468,40 @@ void dc_update_planes_and_stream(struct dc *dc, struct dc_plane_state *plane_state = srf_updates[i].surface; if (update_type == UPDATE_TYPE_MED) - core_dc->hwss.apply_ctx_for_surface( - core_dc, stream, surface_count, context); + dc->hwss.apply_ctx_for_surface( + dc, stream, surface_count, context); - for (j = 0; j < core_dc->res_pool->pipe_count; j++) { + for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; if (pipe_ctx->plane_state != plane_state) continue; if (srf_updates[i].flip_addr) - core_dc->hwss.update_plane_addr(core_dc, pipe_ctx); + dc->hwss.update_plane_addr(dc, pipe_ctx); if (update_type == UPDATE_TYPE_FAST) continue; if (srf_updates[i].in_transfer_func) - core_dc->hwss.set_input_transfer_func( + dc->hwss.set_input_transfer_func( pipe_ctx, pipe_ctx->plane_state); if (stream_update != NULL && stream_update->out_transfer_func != NULL) { - core_dc->hwss.set_output_transfer_func( + dc->hwss.set_output_transfer_func( pipe_ctx, pipe_ctx->stream); } if (srf_updates[i].hdr_static_metadata) { resource_build_info_frame(pipe_ctx); - core_dc->hwss.update_info_frame(pipe_ctx); + dc->hwss.update_info_frame(pipe_ctx); } } } /* Unlock pipes */ - for (i = core_dc->res_pool->pipe_count - 1; i >= 0; i--) { + for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; for (j = 0; j < surface_count; j++) { @@ -1525,8 +1511,8 @@ void dc_update_planes_and_stream(struct dc *dc, if (!pipe_ctx->plane_state || pipe_ctx->top_pipe) continue; - core_dc->hwss.pipe_control_lock( - core_dc, + dc->hwss.pipe_control_lock( + dc, pipe_ctx, false); @@ -1534,7 +1520,7 @@ void dc_update_planes_and_stream(struct dc *dc, } } - if (core_dc->current_context != context) { + if (dc->current_context != context) { /* Since memory free requires elevated IRQL, an interrupt * request is generated by mem free. If this happens @@ -1544,9 +1530,9 @@ void dc_update_planes_and_stream(struct dc *dc, * then free the old context. */ - struct validate_context *old = core_dc->current_context; + struct validate_context *old = dc->current_context; - core_dc->current_context = context; + dc->current_context = context; dc_release_validate_context(old); } @@ -1561,29 +1547,25 @@ context_alloc_fail: uint8_t dc_get_current_stream_count(struct dc *dc) { - struct dc *core_dc = dc; - return core_dc->current_context->stream_count; + return dc->current_context->stream_count; } struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i) { - struct dc *core_dc = dc; - if (i < core_dc->current_context->stream_count) - return core_dc->current_context->streams[i]; + if (i < dc->current_context->stream_count) + return dc->current_context->streams[i]; return NULL; } struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index) { - struct dc *core_dc = dc; - return core_dc->links[link_index]; + return dc->links[link_index]; } struct dwbc *dc_get_dwb_at_pipe(struct dc *dc, uint32_t pipe) { - struct dc *core_dc = dc; if ((pipe >= dwb_pipe0) && (pipe < dwb_pipe_max_num)) { - return core_dc->res_pool->dwbc[(int)pipe]; + return dc->res_pool->dwbc[(int)pipe]; } else { return NULL; } @@ -1592,21 +1574,18 @@ struct dwbc *dc_get_dwb_at_pipe(struct dc *dc, uint32_t pipe) const struct graphics_object_id dc_get_link_id_at_index( struct dc *dc, uint32_t link_index) { - struct dc *core_dc = dc; - return core_dc->links[link_index]->link_id; + return dc->links[link_index]->link_id; } enum dc_irq_source dc_get_hpd_irq_source_at_index( struct dc *dc, uint32_t link_index) { - struct dc *core_dc = dc; - return core_dc->links[link_index]->irq_source_hpd; + return dc->links[link_index]->irq_source_hpd; } const struct audio **dc_get_audios(struct dc *dc) { - struct dc *core_dc = dc; - return (const struct audio **)core_dc->res_pool->audios; + return (const struct audio **)dc->res_pool->audios; } enum dc_irq_source dc_interrupt_to_irq_source( @@ -1614,41 +1593,36 @@ enum dc_irq_source dc_interrupt_to_irq_source( uint32_t src_id, uint32_t ext_id) { - struct dc *core_dc = dc; - return dal_irq_service_to_irq_source(core_dc->res_pool->irqs, src_id, ext_id); + return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id); } void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable) { - struct dc *core_dc; if (dc == NULL) return; - core_dc = dc; - dal_irq_service_set(core_dc->res_pool->irqs, src, enable); + dal_irq_service_set(dc->res_pool->irqs, src, enable); } void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src) { - struct dc *core_dc = dc; - dal_irq_service_ack(core_dc->res_pool->irqs, src); + dal_irq_service_ack(dc->res_pool->irqs, src); } void dc_set_power_state( struct dc *dc, enum dc_acpi_cm_power_state power_state) { - struct dc *core_dc = dc; atomic_t ref_count; switch (power_state) { case DC_ACPI_CM_POWER_STATE_D0: - core_dc->hwss.init_hw(core_dc); + dc->hwss.init_hw(dc); break; default: - core_dc->hwss.power_down(core_dc); + dc->hwss.power_down(dc); /* Zero out the current context so that on resume we start with * clean state, and dc hw programming optimizations will not @@ -1656,11 +1630,11 @@ void dc_set_power_state( */ /* Preserve refcount */ - ref_count = core_dc->current_context->ref_count; - dc_resource_validate_ctx_destruct(core_dc->current_context); - memset(core_dc->current_context, 0, - sizeof(*core_dc->current_context)); - core_dc->current_context->ref_count = ref_count; + ref_count = dc->current_context->ref_count; + dc_resource_validate_ctx_destruct(dc->current_context); + memset(dc->current_context, 0, + sizeof(*dc->current_context)); + dc->current_context->ref_count = ref_count; break; } @@ -1669,12 +1643,11 @@ void dc_set_power_state( void dc_resume(struct dc *dc) { - struct dc *core_dc = dc; uint32_t i; - for (i = 0; i < core_dc->link_count; i++) - core_link_resume(core_dc->links[i]); + for (i = 0; i < dc->link_count; i++) + core_link_resume(dc->links[i]); } bool dc_read_aux_dpcd( @@ -1684,9 +1657,8 @@ bool dc_read_aux_dpcd( uint8_t *data, uint32_t size) { - struct dc *core_dc = dc; - struct dc_link *link = core_dc->links[link_index]; + struct dc_link *link = dc->links[link_index]; enum ddc_result r = dal_ddc_service_read_dpcd_data( link->ddc, false, @@ -1704,8 +1676,7 @@ bool dc_write_aux_dpcd( const uint8_t *data, uint32_t size) { - struct dc *core_dc = dc; - struct dc_link *link = core_dc->links[link_index]; + struct dc_link *link = dc->links[link_index]; enum ddc_result r = dal_ddc_service_write_dpcd_data( link->ddc, @@ -1725,9 +1696,8 @@ bool dc_read_aux_i2c( uint8_t *data, uint32_t size) { - struct dc *core_dc = dc; - struct dc_link *link = core_dc->links[link_index]; + struct dc_link *link = dc->links[link_index]; enum ddc_result r = dal_ddc_service_read_dpcd_data( link->ddc, true, @@ -1746,8 +1716,7 @@ bool dc_write_aux_i2c( const uint8_t *data, uint32_t size) { - struct dc *core_dc = dc; - struct dc_link *link = core_dc->links[link_index]; + struct dc_link *link = dc->links[link_index]; enum ddc_result r = dal_ddc_service_write_dpcd_data( link->ddc, @@ -1768,9 +1737,8 @@ bool dc_query_ddc_data( uint8_t *read_buf, uint32_t read_size) { - struct dc *core_dc = dc; - struct dc_link *link = core_dc->links[link_index]; + struct dc_link *link = dc->links[link_index]; bool result = dal_ddc_service_query_ddc_data( link->ddc, @@ -1788,9 +1756,8 @@ bool dc_submit_i2c( uint32_t link_index, struct i2c_command *cmd) { - struct dc *core_dc = dc; - struct dc_link *link = core_dc->links[link_index]; + struct dc_link *link = dc->links[link_index]; struct ddc_service *ddc = link->ddc; return dal_i2caux_submit_i2c_command( @@ -1907,12 +1874,11 @@ void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) { int i; - struct dc *core_dc = dc; struct mem_input *mi = NULL; - for (i = 0; i < core_dc->res_pool->pipe_count; i++) { - if (core_dc->res_pool->mis[i] != NULL) { - mi = core_dc->res_pool->mis[i]; + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (dc->res_pool->mis[i] != NULL) { + mi = dc->res_pool->mis[i]; break; } } @@ -1921,10 +1887,10 @@ bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) return false; } - if (core_dc->hwss.update_dchub) - core_dc->hwss.update_dchub(core_dc->hwseq, dh_data); + if (dc->hwss.update_dchub) + dc->hwss.update_dchub(dc->hwseq, dh_data); else - ASSERT(core_dc->hwss.update_dchub); + ASSERT(dc->hwss.update_dchub); return true; @@ -1933,9 +1899,8 @@ bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) void dc_log_hw_state(struct dc *dc) { - struct dc *core_dc = dc; - if (core_dc->hwss.log_hw_state) - core_dc->hwss.log_hw_state(core_dc); + if (dc->hwss.log_hw_state) + dc->hwss.log_hw_state(dc); } diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index f49203b3eb94..52350d0e68d0 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -145,7 +145,6 @@ struct mod_freesync *mod_freesync_create(struct dc *dc) struct core_freesync *core_freesync = dm_alloc(sizeof(struct core_freesync)); - struct dc *core_dc = dc; struct persistent_data_flag flag; @@ -176,19 +175,19 @@ struct mod_freesync *mod_freesync_create(struct dc *dc) /* Create initial module folder in registry for freesync enable data */ flag.save_per_edid = true; flag.save_per_link = false; - dm_write_persistent_data(core_dc->ctx, NULL, FREESYNC_REGISTRY_NAME, + dm_write_persistent_data(dc->ctx, NULL, FREESYNC_REGISTRY_NAME, NULL, NULL, 0, &flag); flag.save_per_edid = false; flag.save_per_link = false; - if (dm_read_persistent_data(core_dc->ctx, NULL, NULL, + if (dm_read_persistent_data(dc->ctx, NULL, NULL, FREESYNC_NO_STATIC_FOR_INTERNAL_REGKEY, &data, sizeof(data), &flag)) { core_freesync->opts.drr_internal_supported = (data & 1) ? false : true; } - if (dm_read_persistent_data(core_dc->ctx, NULL, NULL, + if (dm_read_persistent_data(dc->ctx, NULL, NULL, FREESYNC_NO_STATIC_FOR_EXTERNAL_DP_REGKEY, &data, sizeof(data), &flag)) { core_freesync->opts.drr_external_supported = @@ -245,7 +244,7 @@ static unsigned int map_index_from_stream(struct core_freesync *core_freesync, bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, struct dc_stream_state *stream, struct mod_freesync_caps *caps) { - struct dc *core_dc = NULL; + struct dc *dc = NULL; struct core_freesync *core_freesync = NULL; int persistent_freesync_enable = 0; struct persistent_data_flag flag; @@ -256,7 +255,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, return false; core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); - core_dc = core_freesync->dc; + dc = core_freesync->dc; flag.save_per_edid = true; flag.save_per_link = false; @@ -287,7 +286,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, static_ramp.ramp_is_active = false; /* get persistent data from registry */ - if (dm_read_persistent_data(core_dc->ctx, stream->sink, + if (dm_read_persistent_data(dc->ctx, stream->sink, FREESYNC_REGISTRY_NAME, "userenable", &persistent_freesync_enable, sizeof(int), &flag)) { @@ -970,14 +969,14 @@ bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, unsigned int stream_index, map_index; int persistent_data = 0; struct persistent_data_flag flag; - struct dc *core_dc = NULL; + struct dc *dc = NULL; struct core_freesync *core_freesync = NULL; if (mod_freesync == NULL) return false; core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); - core_dc = core_freesync->dc; + dc = core_freesync->dc; flag.save_per_edid = true; flag.save_per_link = false; @@ -1001,7 +1000,7 @@ bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, enable_for_video) persistent_data = persistent_data | 4; - dm_write_persistent_data(core_dc->ctx, + dm_write_persistent_data(dc->ctx, streams[stream_index]->sink, FREESYNC_REGISTRY_NAME, "userenable", -- cgit v1.2.3 From 2004f45ef83f07f43f5da6ede780b08068c7583d Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Wed, 27 Sep 2017 10:53:50 -0400 Subject: drm/amd/display: Use kernel alloc/free Abstractions are frowned upon. cocci script: virtual context virtual patch virtual org virtual report @@ expression ptr; @@ - dm_alloc(ptr) + kzalloc(ptr, GFP_KERNEL) @@ expression ptr, size; @@ - dm_realloc(ptr, size) + krealloc(ptr, size, GFP_KERNEL) @@ expression ptr; @@ - dm_free(ptr) + kfree(ptr) v2: use GFP_KERNEL, not GFP_ATOMIC. add cocci script Reviewed-by: Alex Deucher Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/amd/display/dc/basics/logger.c | 18 ++++--- drivers/gpu/drm/amd/display/dc/basics/vector.c | 19 +++---- drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 17 +++--- drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 14 ++--- drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 5 +- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 6 +-- drivers/gpu/drm/amd/display/dc/core/dc.c | 42 ++++++++------- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 +-- drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 18 +++---- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_sink.c | 11 ++-- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 6 +-- drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 15 +++--- drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 4 +- drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 4 +- .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 12 +++-- drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 10 ++-- drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 6 +-- drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c | 2 +- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 2 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 43 +++++++-------- .../drm/amd/display/dc/dce110/dce110_compressor.c | 6 +-- .../drm/amd/display/dc/dce110/dce110_resource.c | 61 ++++++++++++---------- .../drm/amd/display/dc/dce112/dce112_compressor.c | 6 +-- .../drm/amd/display/dc/dce112/dce112_resource.c | 43 +++++++-------- .../drm/amd/display/dc/dce120/dce120_resource.c | 43 +++++++-------- .../drm/amd/display/dc/dce80/dce80_compressor.c | 6 +-- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 47 +++++++++-------- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 2 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 2 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 56 ++++++++++---------- drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c | 4 +- drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c | 21 ++++---- drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c | 6 +-- drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 2 +- drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c | 6 +-- .../amd/display/dc/i2caux/dce100/i2caux_dce100.c | 4 +- .../display/dc/i2caux/dce110/aux_engine_dce110.c | 6 +-- .../dc/i2caux/dce110/i2c_hw_engine_dce110.c | 7 +-- .../dc/i2caux/dce110/i2c_sw_engine_dce110.c | 7 +-- .../amd/display/dc/i2caux/dce110/i2caux_dce110.c | 6 +-- .../amd/display/dc/i2caux/dce112/i2caux_dce112.c | 4 +- .../amd/display/dc/i2caux/dce120/i2caux_dce120.c | 4 +- .../display/dc/i2caux/dce80/i2c_hw_engine_dce80.c | 6 +-- .../display/dc/i2caux/dce80/i2c_sw_engine_dce80.c | 6 +-- .../drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c | 6 +-- .../drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c | 4 +- .../display/dc/i2caux/diagnostics/i2caux_diag.c | 7 +-- .../gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c | 6 +-- .../amd/display/dc/irq/dce110/irq_service_dce110.c | 5 +- .../amd/display/dc/irq/dce120/irq_service_dce120.c | 5 +- .../amd/display/dc/irq/dce80/irq_service_dce80.c | 5 +- .../amd/display/dc/irq/dcn10/irq_service_dcn10.c | 5 +- drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 2 +- .../amd/display/dc/virtual/virtual_link_encoder.c | 2 +- .../display/dc/virtual/virtual_stream_encoder.c | 4 +- .../drm/amd/display/modules/freesync/freesync.c | 14 ++--- 59 files changed, 362 insertions(+), 330 deletions(-) (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 36635486b937..dba54c0a7b5f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2429,7 +2429,7 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc) if (WARN_ON(!crtc->state)) return NULL; - state = dm_alloc(sizeof(*state)); + state = kzalloc(sizeof(*state), GFP_KERNEL); __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); diff --git a/drivers/gpu/drm/amd/display/dc/basics/logger.c b/drivers/gpu/drm/amd/display/dc/basics/logger.c index 5895dd3903a3..afb6d2d80e0c 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/logger.c +++ b/drivers/gpu/drm/amd/display/dc/basics/logger.c @@ -70,8 +70,8 @@ static bool construct(struct dc_context *ctx, struct dal_logger *logger, { /* malloc buffer and init offsets */ logger->log_buffer_size = DAL_LOGGER_BUFFER_MAX_SIZE; - logger->log_buffer = (char *)dm_alloc(logger->log_buffer_size * - sizeof(char)); + logger->log_buffer = (char *)kzalloc(logger->log_buffer_size * sizeof(char), + GFP_KERNEL); if (!logger->log_buffer) return false; @@ -97,7 +97,7 @@ static bool construct(struct dc_context *ctx, struct dal_logger *logger, static void destruct(struct dal_logger *logger) { if (logger->log_buffer) { - dm_free(logger->log_buffer); + kfree(logger->log_buffer); logger->log_buffer = NULL; } } @@ -105,12 +105,13 @@ static void destruct(struct dal_logger *logger) struct dal_logger *dal_logger_create(struct dc_context *ctx, uint32_t log_mask) { /* malloc struct */ - struct dal_logger *logger = dm_alloc(sizeof(struct dal_logger)); + struct dal_logger *logger = kzalloc(sizeof(struct dal_logger), + GFP_KERNEL); if (!logger) return NULL; if (!construct(ctx, logger, log_mask)) { - dm_free(logger); + kfree(logger); return NULL; } @@ -122,7 +123,7 @@ uint32_t dal_logger_destroy(struct dal_logger **logger) if (logger == NULL || *logger == NULL) return 1; destruct(*logger); - dm_free(*logger); + kfree(*logger); *logger = NULL; return 0; @@ -390,7 +391,8 @@ void dm_logger_open( entry->type = log_type; entry->logger = logger; - entry->buf = dm_alloc(DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char)); + entry->buf = kzalloc(DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char), + GFP_KERNEL); entry->buf_offset = 0; entry->max_buf_bytes = DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char); @@ -421,7 +423,7 @@ void dm_logger_close(struct log_entry *entry) cleanup: if (entry->buf) { - dm_free(entry->buf); + kfree(entry->buf); entry->buf = NULL; entry->buf_offset = 0; entry->max_buf_bytes = 0; diff --git a/drivers/gpu/drm/amd/display/dc/basics/vector.c b/drivers/gpu/drm/amd/display/dc/basics/vector.c index bb72a1857160..e00fc4db3ac4 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/vector.c +++ b/drivers/gpu/drm/amd/display/dc/basics/vector.c @@ -40,7 +40,7 @@ bool dal_vector_construct( return false; } - vector->container = dm_alloc(struct_size * capacity); + vector->container = kzalloc(struct_size * capacity, GFP_KERNEL); if (vector->container == NULL) return false; vector->capacity = capacity; @@ -67,7 +67,7 @@ bool dal_vector_presized_costruct( return false; } - vector->container = dm_alloc(struct_size * count); + vector->container = kzalloc(struct_size * count, GFP_KERNEL); if (vector->container == NULL) return false; @@ -95,7 +95,7 @@ struct vector *dal_vector_presized_create( void *initial_value, uint32_t struct_size) { - struct vector *vector = dm_alloc(sizeof(struct vector)); + struct vector *vector = kzalloc(sizeof(struct vector), GFP_KERNEL); if (vector == NULL) return NULL; @@ -105,7 +105,7 @@ struct vector *dal_vector_presized_create( return vector; BREAK_TO_DEBUGGER(); - dm_free(vector); + kfree(vector); return NULL; } @@ -114,7 +114,7 @@ struct vector *dal_vector_create( uint32_t capacity, uint32_t struct_size) { - struct vector *vector = dm_alloc(sizeof(struct vector)); + struct vector *vector = kzalloc(sizeof(struct vector), GFP_KERNEL); if (vector == NULL) return NULL; @@ -123,7 +123,7 @@ struct vector *dal_vector_create( return vector; BREAK_TO_DEBUGGER(); - dm_free(vector); + kfree(vector); return NULL; } @@ -131,7 +131,7 @@ void dal_vector_destruct( struct vector *vector) { if (vector->container != NULL) - dm_free(vector->container); + kfree(vector->container); vector->count = 0; vector->capacity = 0; } @@ -142,7 +142,7 @@ void dal_vector_destroy( if (vector == NULL || *vector == NULL) return; dal_vector_destruct(*vector); - dm_free(*vector); + kfree(*vector); *vector = NULL; } @@ -290,7 +290,8 @@ bool dal_vector_reserve(struct vector *vector, uint32_t capacity) if (capacity <= vector->capacity) return true; - new_container = dm_realloc(vector->container, capacity * vector->struct_size); + new_container = krealloc(vector->container, + capacity * vector->struct_size, GFP_KERNEL); if (new_container) { vector->container = new_container; diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c index 2c411441771b..47d673a1f688 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c @@ -116,14 +116,14 @@ struct dc_bios *bios_parser_create( { struct bios_parser *bp = NULL; - bp = dm_alloc(sizeof(struct bios_parser)); + bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL); if (!bp) return NULL; if (bios_parser_construct(bp, init, dce_version)) return &bp->base; - dm_free(bp); + kfree(bp); BREAK_TO_DEBUGGER(); return NULL; } @@ -131,10 +131,10 @@ struct dc_bios *bios_parser_create( static void destruct(struct bios_parser *bp) { if (bp->base.bios_local_image) - dm_free(bp->base.bios_local_image); + kfree(bp->base.bios_local_image); if (bp->base.integrated_info) - dm_free(bp->base.integrated_info); + kfree(bp->base.integrated_info); } static void bios_parser_destroy(struct dc_bios **dcb) @@ -148,7 +148,7 @@ static void bios_parser_destroy(struct dc_bios **dcb) destruct(bp); - dm_free(bp); + kfree(bp); *dcb = NULL; } @@ -3531,7 +3531,8 @@ static void process_ext_display_connection_info(struct bios_parser *bp) uint8_t *original_bios; /* Step 1: Replace bios image with the new copy which will be * patched */ - bp->base.bios_local_image = dm_alloc(bp->base.bios_size); + bp->base.bios_local_image = kzalloc(bp->base.bios_size, + GFP_KERNEL); if (bp->base.bios_local_image == NULL) { BREAK_TO_DEBUGGER(); /* Failed to alloc bp->base.bios_local_image */ @@ -3965,7 +3966,7 @@ static struct integrated_info *bios_parser_create_integrated_info( struct bios_parser *bp = BP_FROM_DCB(dcb); struct integrated_info *info = NULL; - info = dm_alloc(sizeof(struct integrated_info)); + info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL); if (info == NULL) { ASSERT_CRITICAL(0); @@ -3975,7 +3976,7 @@ static struct integrated_info *bios_parser_create_integrated_info( if (construct_integrated_info(bp, info) == BP_RESULT_OK) return info; - dm_free(info); + kfree(info); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c index 95fe50f62c57..3f8e605efde9 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c @@ -107,10 +107,10 @@ static struct atom_encoder_caps_record *get_encoder_cap_record( static void destruct(struct bios_parser *bp) { if (bp->base.bios_local_image) - dm_free(bp->base.bios_local_image); + kfree(bp->base.bios_local_image); if (bp->base.integrated_info) - dm_free(bp->base.integrated_info); + kfree(bp->base.integrated_info); } static void firmware_parser_destroy(struct dc_bios **dcb) @@ -124,7 +124,7 @@ static void firmware_parser_destroy(struct dc_bios **dcb) destruct(bp); - dm_free(bp); + kfree(bp); *dcb = NULL; } @@ -2030,7 +2030,7 @@ static struct integrated_info *bios_parser_create_integrated_info( struct bios_parser *bp = BP_FROM_DCB(dcb); struct integrated_info *info = NULL; - info = dm_alloc(sizeof(struct integrated_info)); + info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL); if (info == NULL) { ASSERT_CRITICAL(0); @@ -2040,7 +2040,7 @@ static struct integrated_info *bios_parser_create_integrated_info( if (construct_integrated_info(bp, info) == BP_RESULT_OK) return info; - dm_free(info); + kfree(info); return NULL; } @@ -2205,14 +2205,14 @@ struct dc_bios *firmware_parser_create( { struct bios_parser *bp = NULL; - bp = dm_alloc(sizeof(struct bios_parser)); + bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL); if (!bp) return NULL; if (bios_parser_construct(bp, init, dce_version)) return &bp->base; - dm_free(bp); + kfree(bp); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c index dba25853f7f9..15cbfc400633 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c @@ -2792,7 +2792,8 @@ bool bw_calcs(struct dc_context *ctx, int pipe_count, struct dce_bw_output *calcs_output) { - struct bw_calcs_data *data = dm_alloc(sizeof(struct bw_calcs_data)); + struct bw_calcs_data *data = kzalloc(sizeof(struct bw_calcs_data), + GFP_KERNEL); populate_initial_data(pipe, pipe_count, data); @@ -3248,7 +3249,7 @@ bool bw_calcs(struct dc_context *ctx, calcs_output->sclk_khz = 0; } - dm_free(data); + kfree(data); return is_display_configuration_supported(vbios, calcs_output); } diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 1b0f64756be6..91f43a1b88ee 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -481,8 +481,8 @@ static void dcn_dml_wm_override( { int i, in_idx, active_count; - struct _vcs_dpi_display_e2e_pipe_params_st *input = dm_alloc(pool->pipe_count * - sizeof(struct _vcs_dpi_display_e2e_pipe_params_st)); + struct _vcs_dpi_display_e2e_pipe_params_st *input = kzalloc(pool->pipe_count * sizeof(struct _vcs_dpi_display_e2e_pipe_params_st), + GFP_KERNEL); struct wm { double urgent; struct _vcs_dpi_cstate_pstate_watermarks_st cpstate; @@ -560,7 +560,7 @@ static void dcn_dml_wm_override( pipe->plane_state->flip_immediate); in_idx++; } - dm_free(input); + kfree(input); } static void split_stream_across_pipes( diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 58c5083bef2a..d86d9796e4cc 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -113,7 +113,7 @@ static bool create_links( } for (i = 0; i < num_virtual_links; i++) { - struct dc_link *link = dm_alloc(sizeof(*link)); + struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL); struct encoder_init_data enc_init = {0}; if (link == NULL) { @@ -127,7 +127,7 @@ static bool create_links( link->link_id.type = OBJECT_TYPE_CONNECTOR; link->link_id.id = CONNECTOR_ID_VIRTUAL; link->link_id.enum_id = ENUM_ID_1; - link->link_enc = dm_alloc(sizeof(*link->link_enc)); + link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL); enc_init.ctx = dc->ctx; enc_init.channel = CHANNEL_ID_UNKNOWN; @@ -413,20 +413,20 @@ static void destruct(struct dc *dc) if (dc->ctx->logger) dal_logger_destroy(&dc->ctx->logger); - dm_free(dc->ctx); + kfree(dc->ctx); dc->ctx = NULL; - dm_free(dc->bw_vbios); + kfree(dc->bw_vbios); dc->bw_vbios = NULL; - dm_free(dc->bw_dceip); + kfree(dc->bw_dceip); dc->bw_dceip = NULL; #ifdef CONFIG_DRM_AMD_DC_DCN1_0 - dm_free(dc->dcn_soc); + kfree(dc->dcn_soc); dc->dcn_soc = NULL; - dm_free(dc->dcn_ip); + kfree(dc->dcn_ip); dc->dcn_ip = NULL; #endif @@ -436,12 +436,15 @@ static bool construct(struct dc *dc, const struct dc_init_data *init_params) { struct dal_logger *logger; - struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx)); - struct bw_calcs_dceip *dc_dceip = dm_alloc(sizeof(*dc_dceip)); - struct bw_calcs_vbios *dc_vbios = dm_alloc(sizeof(*dc_vbios)); + struct dc_context *dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL); + struct bw_calcs_dceip *dc_dceip = kzalloc(sizeof(*dc_dceip), + GFP_KERNEL); + struct bw_calcs_vbios *dc_vbios = kzalloc(sizeof(*dc_vbios), + GFP_KERNEL); #ifdef CONFIG_DRM_AMD_DC_DCN1_0 - struct dcn_soc_bounding_box *dcn_soc = dm_alloc(sizeof(*dcn_soc)); - struct dcn_ip_params *dcn_ip = dm_alloc(sizeof(*dcn_ip)); + struct dcn_soc_bounding_box *dcn_soc = kzalloc(sizeof(*dcn_soc), + GFP_KERNEL); + struct dcn_ip_params *dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL); #endif enum dce_version dc_version = DCE_VERSION_UNKNOWN; @@ -604,7 +607,7 @@ void ProgramPixelDurationV(unsigned int pixelClockInKHz ) struct dc *dc_create(const struct dc_init_data *init_params) { - struct dc *dc = dm_alloc(sizeof(*dc)); + struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL); unsigned int full_pipe_count; if (NULL == dc) @@ -638,7 +641,7 @@ struct dc *dc_create(const struct dc_init_data *init_params) return dc; construct_fail: - dm_free(dc); + kfree(dc); alloc_fail: return NULL; @@ -647,7 +650,7 @@ alloc_fail: void dc_destroy(struct dc **dc) { destruct(*dc); - dm_free(*dc); + kfree(*dc); *dc = NULL; } @@ -900,7 +903,7 @@ bool dc_commit_planes_to_stream( struct dc_scaling_info scaling_info[MAX_SURFACES]; int i; struct dc_stream_update *stream_update = - dm_alloc(sizeof(struct dc_stream_update)); + kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL); if (!stream_update) { BREAK_TO_DEBUGGER(); @@ -951,13 +954,14 @@ bool dc_commit_planes_to_stream( dc_post_update_surfaces_to_stream(dc); - dm_free(stream_update); + kfree(stream_update); return true; } struct dc_state *dc_create_state(void) { - struct dc_state *context = dm_alloc(sizeof(struct dc_state)); + struct dc_state *context = kzalloc(sizeof(struct dc_state), + GFP_KERNEL); if (!context) return NULL; @@ -979,7 +983,7 @@ void dc_release_state(struct dc_state *context) if (atomic_read(&context->ref_count) == 0) { dc_resource_state_destruct(context); - dm_free(context); + kfree(context); } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 845ec421d861..43ebd8941b77 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1100,7 +1100,7 @@ create_fail: struct dc_link *link_create(const struct link_init_data *init_params) { struct dc_link *link = - dm_alloc(sizeof(*link)); + kzalloc(sizeof(*link), GFP_KERNEL); if (NULL == link) goto alloc_fail; @@ -1111,7 +1111,7 @@ struct dc_link *link_create(const struct link_init_data *init_params) return link; construct_fail: - dm_free(link); + kfree(link); alloc_fail: return NULL; @@ -1120,7 +1120,7 @@ alloc_fail: void link_destroy(struct dc_link **link) { destruct(*link); - dm_free(*link); + kfree(*link); *link = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c index d09e539397ea..226512c11ab7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c @@ -130,7 +130,7 @@ struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, uint32_ { struct i2c_payloads *payloads; - payloads = dm_alloc(sizeof(struct i2c_payloads)); + payloads = kzalloc(sizeof(struct i2c_payloads), GFP_KERNEL); if (!payloads) return NULL; @@ -139,7 +139,7 @@ struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, uint32_ &payloads->payloads, ctx, count, sizeof(struct i2c_payload))) return payloads; - dm_free(payloads); + kfree(payloads); return NULL; } @@ -159,7 +159,7 @@ void dal_ddc_i2c_payloads_destroy(struct i2c_payloads **p) if (!p || !*p) return; dal_vector_destruct(&(*p)->payloads); - dm_free(*p); + kfree(*p); *p = NULL; } @@ -168,7 +168,7 @@ struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, uint32_ { struct aux_payloads *payloads; - payloads = dm_alloc(sizeof(struct aux_payloads)); + payloads = kzalloc(sizeof(struct aux_payloads), GFP_KERNEL); if (!payloads) return NULL; @@ -177,7 +177,7 @@ struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, uint32_ &payloads->payloads, ctx, count, sizeof(struct aux_payload))) return payloads; - dm_free(payloads); + kfree(payloads); return NULL; } @@ -197,7 +197,7 @@ void dal_ddc_aux_payloads_destroy(struct aux_payloads **p) return; dal_vector_destruct(&(*p)->payloads); - dm_free(*p); + kfree(*p); *p = NULL; } @@ -290,7 +290,7 @@ struct ddc_service *dal_ddc_service_create( { struct ddc_service *ddc_service; - ddc_service = dm_alloc(sizeof(struct ddc_service)); + ddc_service = kzalloc(sizeof(struct ddc_service), GFP_KERNEL); if (!ddc_service) return NULL; @@ -298,7 +298,7 @@ struct ddc_service *dal_ddc_service_create( if (construct(ddc_service, init_data)) return ddc_service; - dm_free(ddc_service); + kfree(ddc_service); return NULL; } @@ -315,7 +315,7 @@ void dal_ddc_service_destroy(struct ddc_service **ddc) return; } destruct(*ddc); - dm_free(*ddc); + kfree(*ddc); *ddc = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index dcfdfebd5c62..1832f252edab 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -160,7 +160,7 @@ void dc_destroy_resource_pool(struct dc *dc) dc->res_pool->funcs->destroy(&dc->res_pool); if (dc->hwseq) - dm_free(dc->hwseq); + kfree(dc->hwseq); } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c index 7717350297a5..b3bbafc8fd6a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c @@ -34,7 +34,7 @@ static void destruct(struct dc_sink *sink) { if (sink->dc_container_id) { - dm_free(sink->dc_container_id); + kfree(sink->dc_container_id); sink->dc_container_id = NULL; } } @@ -74,13 +74,13 @@ void dc_sink_release(struct dc_sink *sink) if (atomic_read(&sink->ref_count) == 0) { destruct(sink); - dm_free(sink); + kfree(sink); } } struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params) { - struct dc_sink *sink = dm_alloc(sizeof(*sink)); + struct dc_sink *sink = kzalloc(sizeof(*sink), GFP_KERNEL); if (NULL == sink) goto alloc_fail; @@ -93,7 +93,7 @@ struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params) return sink; construct_fail: - dm_free(sink); + kfree(sink); alloc_fail: return NULL; @@ -117,7 +117,8 @@ bool dc_sink_set_container_id(struct dc_sink *dc_sink, const struct dc_container { if (dc_sink && container_id) { if (!dc_sink->dc_container_id) - dc_sink->dc_container_id = dm_alloc(sizeof(*dc_sink->dc_container_id)); + dc_sink->dc_container_id = kzalloc(sizeof(*dc_sink->dc_container_id), + GFP_KERNEL); if (dc_sink->dc_container_id) { memmove(&dc_sink->dc_container_id->guid, &container_id->guid, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index a421779093d9..d5da847ffad6 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -131,7 +131,7 @@ void dc_stream_release(struct dc_stream_state *stream) if (atomic_read(&stream->ref_count) == 0) { destruct(stream); - dm_free(stream); + kfree(stream); } } } @@ -144,7 +144,7 @@ struct dc_stream_state *dc_create_stream_for_sink( if (sink == NULL) goto alloc_fail; - stream = dm_alloc(sizeof(struct dc_stream_state)); + stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL); if (NULL == stream) goto alloc_fail; @@ -157,7 +157,7 @@ struct dc_stream_state *dc_create_stream_for_sink( return stream; construct_fail: - dm_free(stream); + kfree(stream); alloc_fail: return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index e96f63eed070..511ada94530e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -68,7 +68,8 @@ struct dc_plane_state *dc_create_plane_state(struct dc *dc) { struct dc *core_dc = dc; - struct dc_plane_state *plane_state = dm_alloc(sizeof(*plane_state)); + struct dc_plane_state *plane_state = kzalloc(sizeof(*plane_state), + GFP_KERNEL); if (NULL == plane_state) goto alloc_fail; @@ -81,7 +82,7 @@ struct dc_plane_state *dc_create_plane_state(struct dc *dc) return plane_state; construct_fail: - dm_free(plane_state); + kfree(plane_state); alloc_fail: return NULL; @@ -133,7 +134,7 @@ void dc_plane_state_release(struct dc_plane_state *plane_state) if (atomic_read(&plane_state->ref_count) == 0) { destruct(plane_state); - dm_free(plane_state); + kfree(plane_state); } } @@ -149,14 +150,14 @@ void dc_gamma_release(struct dc_gamma **gamma) atomic_dec(&(*gamma)->ref_count); if (atomic_read(&(*gamma)->ref_count) == 0) - dm_free((*gamma)); + kfree((*gamma)); *gamma = NULL; } struct dc_gamma *dc_create_gamma() { - struct dc_gamma *gamma = dm_alloc(sizeof(*gamma)); + struct dc_gamma *gamma = kzalloc(sizeof(*gamma), GFP_KERNEL); if (gamma == NULL) goto alloc_fail; @@ -181,12 +182,12 @@ void dc_transfer_func_release(struct dc_transfer_func *tf) atomic_dec(&tf->ref_count); if (atomic_read(&tf->ref_count) == 0) - dm_free(tf); + kfree(tf); } struct dc_transfer_func *dc_create_transfer_func() { - struct dc_transfer_func *tf = dm_alloc(sizeof(*tf)); + struct dc_transfer_func *tf = kzalloc(sizeof(*tf), GFP_KERNEL); if (tf == NULL) goto alloc_fail; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c index 0e9d914e1a8f..0e0336c5af4e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c @@ -462,7 +462,7 @@ struct abm *dce_abm_create( const struct dce_abm_shift *abm_shift, const struct dce_abm_mask *abm_mask) { - struct dce_abm *abm_dce = dm_alloc(sizeof(*abm_dce)); + struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL); if (abm_dce == NULL) { BREAK_TO_DEBUGGER(); @@ -480,6 +480,6 @@ void dce_abm_destroy(struct abm **abm) { struct dce_abm *abm_dce = TO_DCE_ABM(*abm); - dm_free(abm_dce); + kfree(abm_dce); *abm = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c index b94c1e5d85cb..198f4532e100 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c @@ -897,7 +897,7 @@ void dce_aud_destroy(struct audio **audio) { struct dce_audio *aud = DCE_AUD(*audio); - dm_free(aud); + kfree(aud); *audio = NULL; } @@ -909,7 +909,7 @@ struct audio *dce_audio_create( const struct dce_aduio_mask *masks ) { - struct dce_audio *audio = dm_alloc(sizeof(*audio)); + struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL); if (audio == NULL) { ASSERT_CRITICAL(audio); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index d3b61b92ebec..31280d252753 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -1084,12 +1084,14 @@ static void get_ss_info_from_atombios( if (*ss_entries_num == 0) return; - ss_info = dm_alloc(sizeof(struct spread_spectrum_info) * (*ss_entries_num)); + ss_info = kzalloc(sizeof(struct spread_spectrum_info) * (*ss_entries_num), + GFP_KERNEL); ss_info_cur = ss_info; if (ss_info == NULL) return; - ss_data = dm_alloc(sizeof(struct spread_spectrum_data) * (*ss_entries_num)); + ss_data = kzalloc(sizeof(struct spread_spectrum_data) * (*ss_entries_num), + GFP_KERNEL); if (ss_data == NULL) goto out_free_info; @@ -1157,14 +1159,14 @@ static void get_ss_info_from_atombios( } *spread_spectrum_data = ss_data; - dm_free(ss_info); + kfree(ss_info); return; out_free_data: - dm_free(ss_data); + kfree(ss_data); *ss_entries_num = 0; out_free_info: - dm_free(ss_info); + kfree(ss_info); } static void ss_info_from_atombios_create( diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c index 06d9a3e7c8a2..3e9ff2f5472d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c @@ -719,7 +719,7 @@ struct display_clock *dce_disp_clk_create( const struct dce_disp_clk_shift *clk_shift, const struct dce_disp_clk_mask *clk_mask) { - struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce)); + struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL); if (clk_dce == NULL) { BREAK_TO_DEBUGGER(); @@ -742,7 +742,7 @@ struct display_clock *dce110_disp_clk_create( const struct dce_disp_clk_shift *clk_shift, const struct dce_disp_clk_mask *clk_mask) { - struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce)); + struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL); if (clk_dce == NULL) { BREAK_TO_DEBUGGER(); @@ -767,7 +767,7 @@ struct display_clock *dce112_disp_clk_create( const struct dce_disp_clk_shift *clk_shift, const struct dce_disp_clk_mask *clk_mask) { - struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce)); + struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL); if (clk_dce == NULL) { BREAK_TO_DEBUGGER(); @@ -788,7 +788,7 @@ struct display_clock *dce112_disp_clk_create( struct display_clock *dce120_disp_clk_create(struct dc_context *ctx) { - struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce)); + struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL); struct dm_pp_clock_levels_with_voltage clk_level_info = {0}; if (clk_dce == NULL) { @@ -822,6 +822,6 @@ void dce_disp_clk_destroy(struct display_clock **disp_clk) { struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(*disp_clk); - dm_free(clk_dce); + kfree(clk_dce); *disp_clk = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c index 313f61bf06e1..f9873cad40e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c @@ -573,7 +573,7 @@ struct dmcu *dce_dmcu_create( const struct dce_dmcu_shift *dmcu_shift, const struct dce_dmcu_mask *dmcu_mask) { - struct dce_dmcu *dmcu_dce = dm_alloc(sizeof(*dmcu_dce)); + struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); if (dmcu_dce == NULL) { BREAK_TO_DEBUGGER(); @@ -595,7 +595,7 @@ struct dmcu *dcn10_dmcu_create( const struct dce_dmcu_shift *dmcu_shift, const struct dce_dmcu_mask *dmcu_mask) { - struct dce_dmcu *dmcu_dce = dm_alloc(sizeof(*dmcu_dce)); + struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); if (dmcu_dce == NULL) { BREAK_TO_DEBUGGER(); @@ -615,6 +615,6 @@ void dce_dmcu_destroy(struct dmcu **dmcu) { struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu); - dm_free(dmcu_dce); + kfree(dmcu_dce); *dmcu = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c index e010cf10d605..fa481d481132 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c @@ -261,6 +261,6 @@ void dce_ipp_construct( void dce_ipp_destroy(struct input_pixel_processor **ipp) { - dm_free(TO_DCE_IPP(*ipp)); + kfree(TO_DCE_IPP(*ipp)); *ipp = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index 0ce94ede80bf..2ce730de0dc3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -1108,7 +1108,7 @@ void dce110_link_encoder_hw_init( void dce110_link_encoder_destroy(struct link_encoder **enc) { - dm_free(TO_DCE110_LINK_ENC(*enc)); + kfree(TO_DCE110_LINK_ENC(*enc)); *enc = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c index 348e4b7047f1..c0736aeabd85 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c @@ -563,7 +563,7 @@ bool dce110_opp_construct(struct dce110_opp *opp110, void dce110_opp_destroy(struct output_pixel_processor **opp) { if (*opp) - dm_free(FROM_DCE11_OPP(*opp)); + kfree(FROM_DCE11_OPP(*opp)); *opp = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index ca6c7c2a1b4c..9a75bde32611 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -370,7 +370,7 @@ static struct timing_generator *dce100_timing_generator_create( const struct dce110_timing_generator_offsets *offsets) { struct dce110_timing_generator *tg110 = - dm_alloc(sizeof(struct dce110_timing_generator)); + kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); if (!tg110) return NULL; @@ -380,7 +380,7 @@ static struct timing_generator *dce100_timing_generator_create( return &tg110->base; BREAK_TO_DEBUGGER(); - dm_free(tg110); + kfree(tg110); return NULL; } @@ -389,7 +389,7 @@ static struct stream_encoder *dce100_stream_encoder_create( struct dc_context *ctx) { struct dce110_stream_encoder *enc110 = - dm_alloc(sizeof(struct dce110_stream_encoder)); + kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -400,7 +400,7 @@ static struct stream_encoder *dce100_stream_encoder_create( return &enc110->base; BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -422,7 +422,7 @@ static const struct dce_hwseq_mask hwseq_mask = { static struct dce_hwseq *dce100_hwseq_create( struct dc_context *ctx) { - struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); if (hws) { hws->ctx = ctx; @@ -467,7 +467,8 @@ static struct mem_input *dce100_mem_input_create( struct dc_context *ctx, uint32_t inst) { - struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); + struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), + GFP_KERNEL); if (!dce_mi) { BREAK_TO_DEBUGGER(); @@ -481,7 +482,7 @@ static struct mem_input *dce100_mem_input_create( static void dce100_transform_destroy(struct transform **xfm) { - dm_free(TO_DCE_TRANSFORM(*xfm)); + kfree(TO_DCE_TRANSFORM(*xfm)); *xfm = NULL; } @@ -490,7 +491,7 @@ static struct transform *dce100_transform_create( uint32_t inst) { struct dce_transform *transform = - dm_alloc(sizeof(struct dce_transform)); + kzalloc(sizeof(struct dce_transform), GFP_KERNEL); if (!transform) return NULL; @@ -501,14 +502,14 @@ static struct transform *dce100_transform_create( } BREAK_TO_DEBUGGER(); - dm_free(transform); + kfree(transform); return NULL; } static struct input_pixel_processor *dce100_ipp_create( struct dc_context *ctx, uint32_t inst) { - struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); + struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); if (!ipp) { BREAK_TO_DEBUGGER(); @@ -532,7 +533,7 @@ struct link_encoder *dce100_link_encoder_create( const struct encoder_init_data *enc_init_data) { struct dce110_link_encoder *enc110 = - dm_alloc(sizeof(struct dce110_link_encoder)); + kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -549,7 +550,7 @@ struct link_encoder *dce100_link_encoder_create( } BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -558,7 +559,7 @@ struct output_pixel_processor *dce100_opp_create( uint32_t inst) { struct dce110_opp *opp = - dm_alloc(sizeof(struct dce110_opp)); + kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); if (!opp) return NULL; @@ -568,7 +569,7 @@ struct output_pixel_processor *dce100_opp_create( return &opp->base; BREAK_TO_DEBUGGER(); - dm_free(opp); + kfree(opp); return NULL; } @@ -580,7 +581,7 @@ struct clock_source *dce100_clock_source_create( bool dp_clk_src) { struct dce110_clk_src *clk_src = - dm_alloc(sizeof(struct dce110_clk_src)); + kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); if (!clk_src) return NULL; @@ -597,7 +598,7 @@ struct clock_source *dce100_clock_source_create( void dce100_clock_source_destroy(struct clock_source **clk_src) { - dm_free(TO_DCE110_CLK_SRC(*clk_src)); + kfree(TO_DCE110_CLK_SRC(*clk_src)); *clk_src = NULL; } @@ -616,19 +617,19 @@ static void destruct(struct dce110_resource_pool *pool) dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); + kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } if (pool->base.timing_generators[i] != NULL) { - dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i])); + kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } for (i = 0; i < pool->base.stream_enc_count; i++) { if (pool->base.stream_enc[i] != NULL) - dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); + kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); } for (i = 0; i < pool->base.clk_src_count; i++) { @@ -768,7 +769,7 @@ static void dce100_destroy_resource_pool(struct resource_pool **pool) struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); destruct(dce110_pool); - dm_free(dce110_pool); + kfree(dce110_pool); *pool = NULL; } @@ -950,7 +951,7 @@ struct resource_pool *dce100_create_resource_pool( struct dc *dc) { struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); + kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); if (!pool) return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c index f82c26995609..90770cb2ffcd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c @@ -388,7 +388,7 @@ void dce110_compressor_set_fbc_invalidation_triggers( struct compressor *dce110_compressor_create(struct dc_context *ctx) { struct dce110_compressor *cp110 = - dm_alloc(sizeof(struct dce110_compressor)); + kzalloc(sizeof(struct dce110_compressor), GFP_KERNEL); if (!cp110) return NULL; @@ -397,13 +397,13 @@ struct compressor *dce110_compressor_create(struct dc_context *ctx) return &cp110->base; BREAK_TO_DEBUGGER(); - dm_free(cp110); + kfree(cp110); return NULL; } void dce110_compressor_destroy(struct compressor **compressor) { - dm_free(TO_DCE110_COMPRESSOR(*compressor)); + kfree(TO_DCE110_COMPRESSOR(*compressor)); *compressor = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 25eda52c32ef..787e20e15221 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -405,7 +405,7 @@ static struct timing_generator *dce110_timing_generator_create( const struct dce110_timing_generator_offsets *offsets) { struct dce110_timing_generator *tg110 = - dm_alloc(sizeof(struct dce110_timing_generator)); + kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); if (!tg110) return NULL; @@ -414,7 +414,7 @@ static struct timing_generator *dce110_timing_generator_create( return &tg110->base; BREAK_TO_DEBUGGER(); - dm_free(tg110); + kfree(tg110); return NULL; } @@ -423,7 +423,7 @@ static struct stream_encoder *dce110_stream_encoder_create( struct dc_context *ctx) { struct dce110_stream_encoder *enc110 = - dm_alloc(sizeof(struct dce110_stream_encoder)); + kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -434,7 +434,7 @@ static struct stream_encoder *dce110_stream_encoder_create( return &enc110->base; BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -460,7 +460,7 @@ static const struct dce_hwseq_mask hwseq_mask = { static struct dce_hwseq *dce110_hwseq_create( struct dc_context *ctx) { - struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); if (hws) { hws->ctx = ctx; @@ -505,7 +505,8 @@ static struct mem_input *dce110_mem_input_create( struct dc_context *ctx, uint32_t inst) { - struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); + struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), + GFP_KERNEL); if (!dce_mi) { BREAK_TO_DEBUGGER(); @@ -519,7 +520,7 @@ static struct mem_input *dce110_mem_input_create( static void dce110_transform_destroy(struct transform **xfm) { - dm_free(TO_DCE_TRANSFORM(*xfm)); + kfree(TO_DCE_TRANSFORM(*xfm)); *xfm = NULL; } @@ -528,7 +529,7 @@ static struct transform *dce110_transform_create( uint32_t inst) { struct dce_transform *transform = - dm_alloc(sizeof(struct dce_transform)); + kzalloc(sizeof(struct dce_transform), GFP_KERNEL); if (!transform) return NULL; @@ -538,14 +539,14 @@ static struct transform *dce110_transform_create( return &transform->base; BREAK_TO_DEBUGGER(); - dm_free(transform); + kfree(transform); return NULL; } static struct input_pixel_processor *dce110_ipp_create( struct dc_context *ctx, uint32_t inst) { - struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); + struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); if (!ipp) { BREAK_TO_DEBUGGER(); @@ -569,7 +570,7 @@ static struct link_encoder *dce110_link_encoder_create( const struct encoder_init_data *enc_init_data) { struct dce110_link_encoder *enc110 = - dm_alloc(sizeof(struct dce110_link_encoder)); + kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -586,7 +587,7 @@ static struct link_encoder *dce110_link_encoder_create( } BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -595,7 +596,7 @@ static struct output_pixel_processor *dce110_opp_create( uint32_t inst) { struct dce110_opp *opp = - dm_alloc(sizeof(struct dce110_opp)); + kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); if (!opp) return NULL; @@ -605,7 +606,7 @@ static struct output_pixel_processor *dce110_opp_create( return &opp->base; BREAK_TO_DEBUGGER(); - dm_free(opp); + kfree(opp); return NULL; } @@ -617,7 +618,7 @@ struct clock_source *dce110_clock_source_create( bool dp_clk_src) { struct dce110_clk_src *clk_src = - dm_alloc(sizeof(struct dce110_clk_src)); + kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); if (!clk_src) return NULL; @@ -642,15 +643,15 @@ void dce110_clock_source_destroy(struct clock_source **clk_src) dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src); if (dce110_clk_src->dp_ss_params) - dm_free(dce110_clk_src->dp_ss_params); + kfree(dce110_clk_src->dp_ss_params); if (dce110_clk_src->hdmi_ss_params) - dm_free(dce110_clk_src->hdmi_ss_params); + kfree(dce110_clk_src->hdmi_ss_params); if (dce110_clk_src->dvi_ss_params) - dm_free(dce110_clk_src->dvi_ss_params); + kfree(dce110_clk_src->dvi_ss_params); - dm_free(dce110_clk_src); + kfree(dce110_clk_src); *clk_src = NULL; } @@ -669,19 +670,19 @@ static void destruct(struct dce110_resource_pool *pool) dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); + kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } if (pool->base.timing_generators[i] != NULL) { - dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i])); + kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } for (i = 0; i < pool->base.stream_enc_count; i++) { if (pool->base.stream_enc[i] != NULL) - dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); + kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); } for (i = 0; i < pool->base.clk_src_count; i++) { @@ -1031,7 +1032,7 @@ static void dce110_destroy_resource_pool(struct resource_pool **pool) struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); destruct(dce110_pool); - dm_free(dce110_pool); + kfree(dce110_pool); *pool = NULL; } @@ -1048,10 +1049,14 @@ static const struct resource_funcs dce110_res_pool_funcs = { static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) { - struct dce110_timing_generator *dce110_tgv = dm_alloc(sizeof (*dce110_tgv)); - struct dce_transform *dce110_xfmv = dm_alloc(sizeof (*dce110_xfmv)); - struct dce_mem_input *dce110_miv = dm_alloc(sizeof (*dce110_miv)); - struct dce110_opp *dce110_oppv = dm_alloc(sizeof (*dce110_oppv)); + struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv), + GFP_KERNEL); + struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv), + GFP_KERNEL); + struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv), + GFP_KERNEL); + struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv), + GFP_KERNEL); if ((dce110_tgv == NULL) || (dce110_xfmv == NULL) || @@ -1332,7 +1337,7 @@ struct resource_pool *dce110_create_resource_pool( struct hw_asic_id asic_id) { struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); + kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); if (!pool) return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c index 75af2125344b..e75895baa132 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c @@ -839,7 +839,7 @@ bool dce112_compressor_construct(struct dce112_compressor *compressor, struct compressor *dce112_compressor_create(struct dc_context *ctx) { struct dce112_compressor *cp110 = - dm_alloc(sizeof(struct dce112_compressor)); + kzalloc(sizeof(struct dce112_compressor), GFP_KERNEL); if (!cp110) return NULL; @@ -848,12 +848,12 @@ struct compressor *dce112_compressor_create(struct dc_context *ctx) return &cp110->base; BREAK_TO_DEBUGGER(); - dm_free(cp110); + kfree(cp110); return NULL; } void dce112_compressor_destroy(struct compressor **compressor) { - dm_free(TO_DCE112_COMPRESSOR(*compressor)); + kfree(TO_DCE112_COMPRESSOR(*compressor)); *compressor = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index de6f71d8a89b..4e2ed3429a90 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -410,7 +410,7 @@ static struct timing_generator *dce112_timing_generator_create( const struct dce110_timing_generator_offsets *offsets) { struct dce110_timing_generator *tg110 = - dm_alloc(sizeof(struct dce110_timing_generator)); + kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); if (!tg110) return NULL; @@ -419,7 +419,7 @@ static struct timing_generator *dce112_timing_generator_create( return &tg110->base; BREAK_TO_DEBUGGER(); - dm_free(tg110); + kfree(tg110); return NULL; } @@ -428,7 +428,7 @@ static struct stream_encoder *dce112_stream_encoder_create( struct dc_context *ctx) { struct dce110_stream_encoder *enc110 = - dm_alloc(sizeof(struct dce110_stream_encoder)); + kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -439,7 +439,7 @@ static struct stream_encoder *dce112_stream_encoder_create( return &enc110->base; BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -461,7 +461,7 @@ static const struct dce_hwseq_mask hwseq_mask = { static struct dce_hwseq *dce112_hwseq_create( struct dc_context *ctx) { - struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); if (hws) { hws->ctx = ctx; @@ -501,7 +501,8 @@ static struct mem_input *dce112_mem_input_create( struct dc_context *ctx, uint32_t inst) { - struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); + struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), + GFP_KERNEL); if (!dce_mi) { BREAK_TO_DEBUGGER(); @@ -514,7 +515,7 @@ static struct mem_input *dce112_mem_input_create( static void dce112_transform_destroy(struct transform **xfm) { - dm_free(TO_DCE_TRANSFORM(*xfm)); + kfree(TO_DCE_TRANSFORM(*xfm)); *xfm = NULL; } @@ -523,7 +524,7 @@ static struct transform *dce112_transform_create( uint32_t inst) { struct dce_transform *transform = - dm_alloc(sizeof(struct dce_transform)); + kzalloc(sizeof(struct dce_transform), GFP_KERNEL); if (!transform) return NULL; @@ -535,7 +536,7 @@ static struct transform *dce112_transform_create( } BREAK_TO_DEBUGGER(); - dm_free(transform); + kfree(transform); return NULL; } @@ -554,7 +555,7 @@ struct link_encoder *dce112_link_encoder_create( const struct encoder_init_data *enc_init_data) { struct dce110_link_encoder *enc110 = - dm_alloc(sizeof(struct dce110_link_encoder)); + kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -571,14 +572,14 @@ struct link_encoder *dce112_link_encoder_create( } BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } static struct input_pixel_processor *dce112_ipp_create( struct dc_context *ctx, uint32_t inst) { - struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); + struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); if (!ipp) { BREAK_TO_DEBUGGER(); @@ -595,7 +596,7 @@ struct output_pixel_processor *dce112_opp_create( uint32_t inst) { struct dce110_opp *opp = - dm_alloc(sizeof(struct dce110_opp)); + kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); if (!opp) return NULL; @@ -605,7 +606,7 @@ struct output_pixel_processor *dce112_opp_create( return &opp->base; BREAK_TO_DEBUGGER(); - dm_free(opp); + kfree(opp); return NULL; } @@ -617,7 +618,7 @@ struct clock_source *dce112_clock_source_create( bool dp_clk_src) { struct dce110_clk_src *clk_src = - dm_alloc(sizeof(struct dce110_clk_src)); + kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); if (!clk_src) return NULL; @@ -634,7 +635,7 @@ struct clock_source *dce112_clock_source_create( void dce112_clock_source_destroy(struct clock_source **clk_src) { - dm_free(TO_DCE110_CLK_SRC(*clk_src)); + kfree(TO_DCE110_CLK_SRC(*clk_src)); *clk_src = NULL; } @@ -653,19 +654,19 @@ static void destruct(struct dce110_resource_pool *pool) dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); + kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } if (pool->base.timing_generators[i] != NULL) { - dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i])); + kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } for (i = 0; i < pool->base.stream_enc_count; i++) { if (pool->base.stream_enc[i] != NULL) - dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); + kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); } for (i = 0; i < pool->base.clk_src_count; i++) { @@ -940,7 +941,7 @@ static void dce112_destroy_resource_pool(struct resource_pool **pool) struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); destruct(dce110_pool); - dm_free(dce110_pool); + kfree(dce110_pool); *pool = NULL; } @@ -1298,7 +1299,7 @@ struct resource_pool *dce112_create_resource_pool( struct dc *dc) { struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); + kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); if (!pool) return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index e5d2d98982f7..6b5d5948ddb7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -351,7 +351,7 @@ struct output_pixel_processor *dce120_opp_create( uint32_t inst) { struct dce110_opp *opp = - dm_alloc(sizeof(struct dce110_opp)); + kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); if (!opp) return NULL; @@ -361,7 +361,7 @@ struct output_pixel_processor *dce120_opp_create( return &opp->base; BREAK_TO_DEBUGGER(); - dm_free(opp); + kfree(opp); return NULL; } @@ -388,7 +388,7 @@ struct clock_source *dce120_clock_source_create( bool dp_clk_src) { struct dce110_clk_src *clk_src = - dm_alloc(sizeof(*clk_src)); + kzalloc(sizeof(*clk_src), GFP_KERNEL); if (!clk_src) return NULL; @@ -405,7 +405,7 @@ struct clock_source *dce120_clock_source_create( void dce120_clock_source_destroy(struct clock_source **clk_src) { - dm_free(TO_DCE110_CLK_SRC(*clk_src)); + kfree(TO_DCE110_CLK_SRC(*clk_src)); *clk_src = NULL; } @@ -428,7 +428,7 @@ static struct timing_generator *dce120_timing_generator_create( const struct dce110_timing_generator_offsets *offsets) { struct dce110_timing_generator *tg110 = - dm_alloc(sizeof(struct dce110_timing_generator)); + kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); if (!tg110) return NULL; @@ -437,13 +437,13 @@ static struct timing_generator *dce120_timing_generator_create( return &tg110->base; BREAK_TO_DEBUGGER(); - dm_free(tg110); + kfree(tg110); return NULL; } static void dce120_transform_destroy(struct transform **xfm) { - dm_free(TO_DCE_TRANSFORM(*xfm)); + kfree(TO_DCE_TRANSFORM(*xfm)); *xfm = NULL; } @@ -462,7 +462,7 @@ static void destruct(struct dce110_resource_pool *pool) dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); + kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } @@ -471,7 +471,7 @@ static void destruct(struct dce110_resource_pool *pool) } if (pool->base.timing_generators[i] != NULL) { - dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i])); + kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } @@ -483,7 +483,7 @@ static void destruct(struct dce110_resource_pool *pool) for (i = 0; i < pool->base.stream_enc_count; i++) { if (pool->base.stream_enc[i] != NULL) - dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); + kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); } for (i = 0; i < pool->base.clk_src_count; i++) { @@ -539,7 +539,7 @@ static struct link_encoder *dce120_link_encoder_create( const struct encoder_init_data *enc_init_data) { struct dce110_link_encoder *enc110 = - dm_alloc(sizeof(struct dce110_link_encoder)); + kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -556,14 +556,14 @@ static struct link_encoder *dce120_link_encoder_create( } BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } static struct input_pixel_processor *dce120_ipp_create( struct dc_context *ctx, uint32_t inst) { - struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); + struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); if (!ipp) { BREAK_TO_DEBUGGER(); @@ -580,7 +580,7 @@ static struct stream_encoder *dce120_stream_encoder_create( struct dc_context *ctx) { struct dce110_stream_encoder *enc110 = - dm_alloc(sizeof(struct dce110_stream_encoder)); + kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -591,7 +591,7 @@ static struct stream_encoder *dce120_stream_encoder_create( return &enc110->base; BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -614,7 +614,7 @@ static const struct dce_hwseq_mask hwseq_mask = { static struct dce_hwseq *dce120_hwseq_create( struct dc_context *ctx) { - struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); if (hws) { hws->ctx = ctx; @@ -654,7 +654,8 @@ static struct mem_input *dce120_mem_input_create( struct dc_context *ctx, uint32_t inst) { - struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); + struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), + GFP_KERNEL); if (!dce_mi) { BREAK_TO_DEBUGGER(); @@ -670,7 +671,7 @@ static struct transform *dce120_transform_create( uint32_t inst) { struct dce_transform *transform = - dm_alloc(sizeof(struct dce_transform)); + kzalloc(sizeof(struct dce_transform), GFP_KERNEL); if (!transform) return NULL; @@ -682,7 +683,7 @@ static struct transform *dce120_transform_create( } BREAK_TO_DEBUGGER(); - dm_free(transform); + kfree(transform); return NULL; } @@ -691,7 +692,7 @@ static void dce120_destroy_resource_pool(struct resource_pool **pool) struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); destruct(dce110_pool); - dm_free(dce110_pool); + kfree(dce110_pool); *pool = NULL; } @@ -1006,7 +1007,7 @@ struct resource_pool *dce120_create_resource_pool( struct dc *dc) { struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); + kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); if (!pool) return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c index 77626d7624c6..cc1c0d390945 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c @@ -819,7 +819,7 @@ bool dce80_compressor_construct(struct dce80_compressor *compressor, struct compressor *dce80_compressor_create(struct dc_context *ctx) { struct dce80_compressor *cp80 = - dm_alloc(sizeof(struct dce80_compressor)); + kzalloc(sizeof(struct dce80_compressor), GFP_KERNEL); if (!cp80) return NULL; @@ -828,12 +828,12 @@ struct compressor *dce80_compressor_create(struct dc_context *ctx) return &cp80->base; BREAK_TO_DEBUGGER(); - dm_free(cp80); + kfree(cp80); return NULL; } void dce80_compressor_destroy(struct compressor **compressor) { - dm_free(TO_DCE80_COMPRESSOR(*compressor)); + kfree(TO_DCE80_COMPRESSOR(*compressor)); *compressor = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 5453f02ea8ca..170509a4a221 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -399,7 +399,7 @@ static struct timing_generator *dce80_timing_generator_create( const struct dce110_timing_generator_offsets *offsets) { struct dce110_timing_generator *tg110 = - dm_alloc(sizeof(struct dce110_timing_generator)); + kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); if (!tg110) return NULL; @@ -408,7 +408,7 @@ static struct timing_generator *dce80_timing_generator_create( return &tg110->base; BREAK_TO_DEBUGGER(); - dm_free(tg110); + kfree(tg110); return NULL; } @@ -417,7 +417,7 @@ static struct output_pixel_processor *dce80_opp_create( uint32_t inst) { struct dce110_opp *opp = - dm_alloc(sizeof(struct dce110_opp)); + kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); if (!opp) return NULL; @@ -427,7 +427,7 @@ static struct output_pixel_processor *dce80_opp_create( return &opp->base; BREAK_TO_DEBUGGER(); - dm_free(opp); + kfree(opp); return NULL; } @@ -436,7 +436,7 @@ static struct stream_encoder *dce80_stream_encoder_create( struct dc_context *ctx) { struct dce110_stream_encoder *enc110 = - dm_alloc(sizeof(struct dce110_stream_encoder)); + kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -447,7 +447,7 @@ static struct stream_encoder *dce80_stream_encoder_create( return &enc110->base; BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -469,7 +469,7 @@ static const struct dce_hwseq_mask hwseq_mask = { static struct dce_hwseq *dce80_hwseq_create( struct dc_context *ctx) { - struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); if (hws) { hws->ctx = ctx; @@ -514,7 +514,8 @@ static struct mem_input *dce80_mem_input_create( struct dc_context *ctx, uint32_t inst) { - struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); + struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), + GFP_KERNEL); if (!dce_mi) { BREAK_TO_DEBUGGER(); @@ -528,7 +529,7 @@ static struct mem_input *dce80_mem_input_create( static void dce80_transform_destroy(struct transform **xfm) { - dm_free(TO_DCE_TRANSFORM(*xfm)); + kfree(TO_DCE_TRANSFORM(*xfm)); *xfm = NULL; } @@ -537,7 +538,7 @@ static struct transform *dce80_transform_create( uint32_t inst) { struct dce_transform *transform = - dm_alloc(sizeof(struct dce_transform)); + kzalloc(sizeof(struct dce_transform), GFP_KERNEL); if (!transform) return NULL; @@ -549,7 +550,7 @@ static struct transform *dce80_transform_create( } BREAK_TO_DEBUGGER(); - dm_free(transform); + kfree(transform); return NULL; } @@ -565,7 +566,7 @@ struct link_encoder *dce80_link_encoder_create( const struct encoder_init_data *enc_init_data) { struct dce110_link_encoder *enc110 = - dm_alloc(sizeof(struct dce110_link_encoder)); + kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -582,7 +583,7 @@ struct link_encoder *dce80_link_encoder_create( } BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -594,7 +595,7 @@ struct clock_source *dce80_clock_source_create( bool dp_clk_src) { struct dce110_clk_src *clk_src = - dm_alloc(sizeof(struct dce110_clk_src)); + kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); if (!clk_src) return NULL; @@ -611,14 +612,14 @@ struct clock_source *dce80_clock_source_create( void dce80_clock_source_destroy(struct clock_source **clk_src) { - dm_free(TO_DCE110_CLK_SRC(*clk_src)); + kfree(TO_DCE110_CLK_SRC(*clk_src)); *clk_src = NULL; } static struct input_pixel_processor *dce80_ipp_create( struct dc_context *ctx, uint32_t inst) { - struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); + struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); if (!ipp) { BREAK_TO_DEBUGGER(); @@ -645,19 +646,19 @@ static void destruct(struct dce110_resource_pool *pool) dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); + kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } if (pool->base.timing_generators[i] != NULL) { - dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i])); + kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } for (i = 0; i < pool->base.stream_enc_count; i++) { if (pool->base.stream_enc[i] != NULL) - dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); + kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); } for (i = 0; i < pool->base.clk_src_count; i++) { @@ -781,7 +782,7 @@ static void dce80_destroy_resource_pool(struct resource_pool **pool) struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); destruct(dce110_pool); - dm_free(dce110_pool); + kfree(dce110_pool); *pool = NULL; } @@ -948,7 +949,7 @@ struct resource_pool *dce80_create_resource_pool( struct dc *dc) { struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); + kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); if (!pool) return NULL; @@ -1113,7 +1114,7 @@ struct resource_pool *dce81_create_resource_pool( struct dc *dc) { struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); + kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); if (!pool) return NULL; @@ -1274,7 +1275,7 @@ struct resource_pool *dce83_create_resource_pool( struct dc *dc) { struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); + kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); if (!pool) return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c index 5e0e2464eab3..67bd6a738fe9 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c @@ -225,7 +225,7 @@ static void ippn10_cursor_set_position( static void dcn10_ipp_destroy(struct input_pixel_processor **ipp) { - dm_free(TO_DCN10_IPP(*ipp)); + kfree(TO_DCN10_IPP(*ipp)); *ipp = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c index 8048782ac599..a136f70b7a3c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c @@ -314,7 +314,7 @@ static void oppn10_set_stereo_polarity( static void dcn10_opp_destroy(struct output_pixel_processor **opp) { - dm_free(TO_DCN10_OPP(*opp)); + kfree(TO_DCN10_OPP(*opp)); *opp = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 298eb44ad9bf..71adda0e5b59 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -468,7 +468,7 @@ static const struct dc_debug debug_defaults_diags = { static void dcn10_dpp_destroy(struct transform **xfm) { - dm_free(TO_DCN10_DPP(*xfm)); + kfree(TO_DCN10_DPP(*xfm)); *xfm = NULL; } @@ -477,7 +477,7 @@ static struct transform *dcn10_dpp_create( uint32_t inst) { struct dcn10_dpp *dpp = - dm_alloc(sizeof(struct dcn10_dpp)); + kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL); if (!dpp) return NULL; @@ -487,7 +487,7 @@ static struct transform *dcn10_dpp_create( return &dpp->base; BREAK_TO_DEBUGGER(); - dm_free(dpp); + kfree(dpp); return NULL; } @@ -495,7 +495,7 @@ static struct input_pixel_processor *dcn10_ipp_create( struct dc_context *ctx, uint32_t inst) { struct dcn10_ipp *ipp = - dm_alloc(sizeof(struct dcn10_ipp)); + kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); if (!ipp) { BREAK_TO_DEBUGGER(); @@ -512,7 +512,7 @@ static struct output_pixel_processor *dcn10_opp_create( struct dc_context *ctx, uint32_t inst) { struct dcn10_opp *opp = - dm_alloc(sizeof(struct dcn10_opp)); + kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL); if (!opp) { BREAK_TO_DEBUGGER(); @@ -526,7 +526,8 @@ static struct output_pixel_processor *dcn10_opp_create( static struct mpc *dcn10_mpc_create(struct dc_context *ctx) { - struct dcn10_mpc *mpc10 = dm_alloc(sizeof(struct dcn10_mpc)); + struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc), + GFP_KERNEL); if (!mpc10) return NULL; @@ -545,7 +546,7 @@ static struct timing_generator *dcn10_timing_generator_create( uint32_t instance) { struct dcn10_timing_generator *tgn10 = - dm_alloc(sizeof(struct dcn10_timing_generator)); + kzalloc(sizeof(struct dcn10_timing_generator), GFP_KERNEL); if (!tgn10) return NULL; @@ -577,7 +578,7 @@ struct link_encoder *dcn10_link_encoder_create( const struct encoder_init_data *enc_init_data) { struct dce110_link_encoder *enc110 = - dm_alloc(sizeof(struct dce110_link_encoder)); + kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -594,7 +595,7 @@ struct link_encoder *dcn10_link_encoder_create( } BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -606,7 +607,7 @@ struct clock_source *dcn10_clock_source_create( bool dp_clk_src) { struct dce110_clk_src *clk_src = - dm_alloc(sizeof(struct dce110_clk_src)); + kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); if (!clk_src) return NULL; @@ -641,7 +642,7 @@ static struct stream_encoder *dcn10_stream_encoder_create( struct dc_context *ctx) { struct dce110_stream_encoder *enc110 = - dm_alloc(sizeof(struct dce110_stream_encoder)); + kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -652,7 +653,7 @@ static struct stream_encoder *dcn10_stream_encoder_create( return &enc110->base; BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -671,7 +672,7 @@ static const struct dce_hwseq_mask hwseq_mask = { static struct dce_hwseq *dcn10_hwseq_create( struct dc_context *ctx) { - struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); if (hws) { hws->ctx = ctx; @@ -698,13 +699,13 @@ static const struct resource_create_funcs res_create_maximus_funcs = { void dcn10_clock_source_destroy(struct clock_source **clk_src) { - dm_free(TO_DCE110_CLK_SRC(*clk_src)); + kfree(TO_DCE110_CLK_SRC(*clk_src)); *clk_src = NULL; } static struct pp_smu_funcs_rv *dcn10_pp_smu_create(struct dc_context *ctx) { - struct pp_smu_funcs_rv *pp_smu = dm_alloc(sizeof(*pp_smu)); + struct pp_smu_funcs_rv *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); if (!pp_smu) return pp_smu; @@ -722,13 +723,13 @@ static void destruct(struct dcn10_resource_pool *pool) /* TODO: free dcn version of stream encoder once implemented * rather than using virtual stream encoder */ - dm_free(pool->base.stream_enc[i]); + kfree(pool->base.stream_enc[i]); pool->base.stream_enc[i] = NULL; } } if (pool->base.mpc != NULL) { - dm_free(TO_DCN10_MPC(pool->base.mpc)); + kfree(TO_DCN10_MPC(pool->base.mpc)); pool->base.mpc = NULL; } for (i = 0; i < pool->base.pipe_count; i++) { @@ -742,7 +743,7 @@ static void destruct(struct dcn10_resource_pool *pool) pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCN10_MEM_INPUT(pool->base.mis[i])); + kfree(TO_DCN10_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } @@ -751,14 +752,14 @@ static void destruct(struct dcn10_resource_pool *pool) } if (pool->base.timing_generators[i] != NULL) { - dm_free(DCN10TG_FROM_TG(pool->base.timing_generators[i])); + kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } for (i = 0; i < pool->base.stream_enc_count; i++) { if (pool->base.stream_enc[i] != NULL) - dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); + kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); } for (i = 0; i < pool->base.audio_count; i++) { @@ -767,7 +768,7 @@ static void destruct(struct dcn10_resource_pool *pool) } for (i = 0; i < pool->base.res_cap->num_dwb; i++) { - dm_free(pool->base.dwbc[i]); + kfree(pool->base.dwbc[i]); pool->base.dwbc[i] = NULL; } @@ -792,7 +793,7 @@ static void destruct(struct dcn10_resource_pool *pool) if (pool->base.display_clock != NULL) dce_disp_clk_destroy(&pool->base.display_clock); - dm_free(pool->base.pp_smu); + kfree(pool->base.pp_smu); } static struct mem_input *dcn10_mem_input_create( @@ -800,7 +801,7 @@ static struct mem_input *dcn10_mem_input_create( uint32_t inst) { struct dcn10_mem_input *mem_inputn10 = - dm_alloc(sizeof(struct dcn10_mem_input)); + kzalloc(sizeof(struct dcn10_mem_input), GFP_KERNEL); if (!mem_inputn10) return NULL; @@ -810,7 +811,7 @@ static struct mem_input *dcn10_mem_input_create( return &mem_inputn10->base; BREAK_TO_DEBUGGER(); - dm_free(mem_inputn10); + kfree(mem_inputn10); return NULL; } @@ -1207,7 +1208,7 @@ static void dcn10_destroy_resource_pool(struct resource_pool **pool) struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool); destruct(dcn10_pool); - dm_free(dcn10_pool); + kfree(dcn10_pool); *pool = NULL; } @@ -1239,7 +1240,8 @@ static bool dcn10_dwbc_create(struct dc_context *ctx, struct resource_pool *pool uint32_t dwb_count = pool->res_cap->num_dwb; for (i = 0; i < dwb_count; i++) { - struct dcn10_dwbc *dwbc10 = dm_alloc(sizeof(struct dcn10_dwbc)); + struct dcn10_dwbc *dwbc10 = kzalloc(sizeof(struct dcn10_dwbc), + GFP_KERNEL); if (!dwbc10) { dm_error("DC: failed to create dwbc10!\n"); @@ -1517,7 +1519,7 @@ struct resource_pool *dcn10_create_resource_pool( struct dc *dc) { struct dcn10_resource_pool *pool = - dm_alloc(sizeof(struct dcn10_resource_pool)); + kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL); if (!pool) return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c b/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c index d42eb3de2ea4..1d1efd72b291 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c @@ -239,7 +239,7 @@ struct gpio *dal_gpio_create( uint32_t en, enum gpio_pin_output_state output_state) { - struct gpio *gpio = dm_alloc(sizeof(struct gpio)); + struct gpio *gpio = kzalloc(sizeof(struct gpio), GFP_KERNEL); if (!gpio) { ASSERT_CRITICAL(false); @@ -266,7 +266,7 @@ void dal_gpio_destroy( dal_gpio_close(*gpio); - dm_free(*gpio); + kfree(*gpio); *gpio = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c index eeb1cd0f75a6..d4e5ef64e489 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c @@ -59,7 +59,7 @@ struct gpio_service *dal_gpio_service_create( uint32_t index_of_id; - service = dm_alloc(sizeof(struct gpio_service)); + service = kzalloc(sizeof(struct gpio_service), GFP_KERNEL); if (!service) { BREAK_TO_DEBUGGER(); @@ -98,7 +98,8 @@ struct gpio_service *dal_gpio_service_create( if (number_of_bits) { uint32_t index_of_uint = 0; - slot = dm_alloc(number_of_uints * sizeof(uint32_t)); + slot = kzalloc(number_of_uints * sizeof(uint32_t), + GFP_KERNEL); if (!slot) { BREAK_TO_DEBUGGER(); @@ -130,11 +131,11 @@ failure_2: slot = service->busyness[index_of_id]; if (slot) - dm_free(slot); + kfree(slot); }; failure_1: - dm_free(service); + kfree(service); return NULL; } @@ -171,13 +172,13 @@ void dal_gpio_service_destroy( uint32_t *slot = (*ptr)->busyness[index_of_id]; if (slot) - dm_free(slot); + kfree(slot); ++index_of_id; } while (index_of_id < GPIO_ID_COUNT); } - dm_free(*ptr); + kfree(*ptr); *ptr = NULL; } @@ -399,7 +400,7 @@ void dal_gpio_destroy_irq( dal_gpio_close(*irq); dal_gpio_destroy(irq); - dm_free(*irq); + kfree(*irq); *irq = NULL; } @@ -417,7 +418,7 @@ struct ddc *dal_gpio_create_ddc( if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en)) return NULL; - ddc = dm_alloc(sizeof(struct ddc)); + ddc = kzalloc(sizeof(struct ddc), GFP_KERNEL); if (!ddc) { BREAK_TO_DEBUGGER(); @@ -450,7 +451,7 @@ failure_2: dal_gpio_destroy(&ddc->pin_data); failure_1: - dm_free(ddc); + kfree(ddc); return NULL; } @@ -466,7 +467,7 @@ void dal_gpio_destroy_ddc( dal_ddc_close(*ddc); dal_gpio_destroy(&(*ddc)->pin_data); dal_gpio_destroy(&(*ddc)->pin_clock); - dm_free(*ddc); + kfree(*ddc); *ddc = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c index 47e0f8f24a86..7b6efa4f2efd 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c @@ -55,7 +55,7 @@ static void destroy( destruct(pin); - dm_free(pin); + kfree(pin); *ptr = NULL; } @@ -225,7 +225,7 @@ struct hw_gpio_pin *dal_hw_ddc_create( enum gpio_id id, uint32_t en) { - struct hw_ddc *pin = dm_alloc(sizeof(struct hw_ddc)); + struct hw_ddc *pin = kzalloc(sizeof(struct hw_ddc), GFP_KERNEL); if (!pin) { ASSERT_CRITICAL(false); @@ -237,7 +237,7 @@ struct hw_gpio_pin *dal_hw_ddc_create( ASSERT_CRITICAL(false); - dm_free(pin); + kfree(pin); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c index f7d049c0e62a..87b580fa4bc9 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c @@ -101,7 +101,7 @@ void dal_hw_factory_destroy( return; } - dm_free(*factory); + kfree(*factory); *factory = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c index 9634e8841d90..0c255c02045b 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c @@ -72,7 +72,7 @@ static void destroy( destruct(hpd); - dm_free(hpd); + kfree(hpd); *ptr = NULL; } @@ -157,7 +157,7 @@ struct hw_gpio_pin *dal_hw_hpd_create( enum gpio_id id, uint32_t en) { - struct hw_hpd *hpd = dm_alloc(sizeof(struct hw_hpd)); + struct hw_hpd *hpd = kzalloc(sizeof(struct hw_hpd), GFP_KERNEL); if (!hpd) { ASSERT_CRITICAL(false); @@ -169,7 +169,7 @@ struct hw_gpio_pin *dal_hw_hpd_create( ASSERT_CRITICAL(false); - dm_free(hpd); + kfree(hpd); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c index 0712cafb4c42..c45a2ee8c336 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c @@ -88,7 +88,7 @@ struct i2caux *dal_i2caux_dce100_create( struct dc_context *ctx) { struct i2caux_dce110 *i2caux_dce110 = - dm_alloc(sizeof(struct i2caux_dce110)); + kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL); if (!i2caux_dce110) { ASSERT_CRITICAL(false); @@ -106,7 +106,7 @@ struct i2caux *dal_i2caux_dce100_create( ASSERT_CRITICAL(false); - dm_free(i2caux_dce110); + kfree(i2caux_dce110); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c index d3eaf8977a60..4b673b48bf42 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c @@ -87,7 +87,7 @@ static void destroy( destruct(engine); - dm_free(engine); + kfree(engine); *aux_engine = NULL; } @@ -464,7 +464,7 @@ struct aux_engine *dal_aux_engine_dce110_create( return NULL; } - engine = dm_alloc(sizeof(*engine)); + engine = kzalloc(sizeof(*engine), GFP_KERNEL); if (!engine) { ASSERT_CRITICAL(false); @@ -476,7 +476,7 @@ struct aux_engine *dal_aux_engine_dce110_create( ASSERT_CRITICAL(false); - dm_free(engine); + kfree(engine); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c index 80d06ad78e07..aab77a81008a 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c @@ -469,7 +469,7 @@ static void destroy( dal_i2c_hw_engine_destruct(&engine_dce110->base); - dm_free(engine_dce110); + kfree(engine_dce110); *i2c_engine = NULL; } @@ -559,7 +559,8 @@ struct i2c_engine *dal_i2c_hw_engine_dce110_create( return NULL; } - engine_dce10 = dm_alloc(sizeof(struct i2c_hw_engine_dce110)); + engine_dce10 = kzalloc(sizeof(struct i2c_hw_engine_dce110), + GFP_KERNEL); if (!engine_dce10) { ASSERT_CRITICAL(false); @@ -571,7 +572,7 @@ struct i2c_engine *dal_i2c_hw_engine_dce110_create( ASSERT_CRITICAL(false); - dm_free(engine_dce10); + kfree(engine_dce10); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c index 996813d9165f..bf2c4b240b78 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c @@ -88,7 +88,7 @@ static void destroy( destruct(sw_engine); - dm_free(sw_engine); + kfree(sw_engine); *engine = NULL; } @@ -153,7 +153,8 @@ struct i2c_engine *dal_i2c_sw_engine_dce110_create( return NULL; } - engine_dce110 = dm_alloc(sizeof(struct i2c_sw_engine_dce110)); + engine_dce110 = kzalloc(sizeof(struct i2c_sw_engine_dce110), + GFP_KERNEL); if (!engine_dce110) { ASSERT_CRITICAL(false); @@ -165,7 +166,7 @@ struct i2c_engine *dal_i2c_sw_engine_dce110_create( ASSERT_CRITICAL(false); - dm_free(engine_dce110); + kfree(engine_dce110); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c index 1c00ed0010d9..ae9adb389319 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c @@ -68,7 +68,7 @@ static void destroy( destruct(i2caux_dce110); - dm_free(i2caux_dce110); + kfree(i2caux_dce110); *i2c_engine = NULL; } @@ -299,7 +299,7 @@ struct i2caux *dal_i2caux_dce110_create( struct dc_context *ctx) { struct i2caux_dce110 *i2caux_dce110 = - dm_alloc(sizeof(struct i2caux_dce110)); + kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL); if (!i2caux_dce110) { ASSERT_CRITICAL(false); @@ -317,7 +317,7 @@ struct i2caux *dal_i2caux_dce110_create( ASSERT_CRITICAL(false); - dm_free(i2caux_dce110); + kfree(i2caux_dce110); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.c index d74f3f15d600..715ba4390957 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.c @@ -122,7 +122,7 @@ struct i2caux *dal_i2caux_dce112_create( struct dc_context *ctx) { struct i2caux_dce110 *i2caux_dce110 = - dm_alloc(sizeof(struct i2caux_dce110)); + kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL); if (!i2caux_dce110) { ASSERT_CRITICAL(false); @@ -134,7 +134,7 @@ struct i2caux *dal_i2caux_dce112_create( ASSERT_CRITICAL(false); - dm_free(i2caux_dce110); + kfree(i2caux_dce110); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c index 91198295f1a4..d52827ae3f1a 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c @@ -101,7 +101,7 @@ struct i2caux *dal_i2caux_dce120_create( struct dc_context *ctx) { struct i2caux_dce110 *i2caux_dce110 = - dm_alloc(sizeof(struct i2caux_dce110)); + kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL); if (!i2caux_dce110) { ASSERT_CRITICAL(false); @@ -119,7 +119,7 @@ struct i2caux *dal_i2caux_dce120_create( ASSERT_CRITICAL(false); - dm_free(i2caux_dce110); + kfree(i2caux_dce110); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c index 423c38ac880c..d41e37c94214 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c @@ -190,7 +190,7 @@ static void destroy( destruct(engine); - dm_free(engine); + kfree(engine); *i2c_engine = NULL; } @@ -867,7 +867,7 @@ struct i2c_engine *dal_i2c_hw_engine_dce80_create( return NULL; } - engine = dm_alloc(sizeof(struct i2c_hw_engine_dce80)); + engine = kzalloc(sizeof(struct i2c_hw_engine_dce80), GFP_KERNEL); if (!engine) { BREAK_TO_DEBUGGER(); @@ -879,7 +879,7 @@ struct i2c_engine *dal_i2c_hw_engine_dce80_create( BREAK_TO_DEBUGGER(); - dm_free(engine); + kfree(engine); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c index 804a3266c578..6be77bc931c6 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c @@ -103,7 +103,7 @@ static void destroy( destruct(sw_engine); - dm_free(sw_engine); + kfree(sw_engine); *engine = NULL; } @@ -165,7 +165,7 @@ struct i2c_engine *dal_i2c_sw_engine_dce80_create( return NULL; } - engine = dm_alloc(sizeof(struct i2c_sw_engine_dce80)); + engine = kzalloc(sizeof(struct i2c_sw_engine_dce80), GFP_KERNEL); if (!engine) { BREAK_TO_DEBUGGER(); @@ -177,7 +177,7 @@ struct i2c_engine *dal_i2c_sw_engine_dce80_create( BREAK_TO_DEBUGGER(); - dm_free(engine); + kfree(engine); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c index 5e71450c44e0..d3c157e5eccd 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c @@ -101,7 +101,7 @@ static void destroy( destruct(i2caux_dce80); - dm_free(i2caux_dce80); + kfree(i2caux_dce80); *i2c_engine = NULL; } @@ -277,7 +277,7 @@ struct i2caux *dal_i2caux_dce80_create( struct dc_context *ctx) { struct i2caux_dce80 *i2caux_dce80 = - dm_alloc(sizeof(struct i2caux_dce80)); + kzalloc(sizeof(struct i2caux_dce80), GFP_KERNEL); if (!i2caux_dce80) { BREAK_TO_DEBUGGER(); @@ -289,7 +289,7 @@ struct i2caux *dal_i2caux_dce80_create( BREAK_TO_DEBUGGER(); - dm_free(i2caux_dce80); + kfree(i2caux_dce80); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c index 9f17d2e4376b..f8659f1c5f9d 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c @@ -101,7 +101,7 @@ struct i2caux *dal_i2caux_dcn10_create( struct dc_context *ctx) { struct i2caux_dce110 *i2caux_dce110 = - dm_alloc(sizeof(struct i2caux_dce110)); + kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL); if (!i2caux_dce110) { ASSERT_CRITICAL(false); @@ -119,7 +119,7 @@ struct i2caux *dal_i2caux_dcn10_create( ASSERT_CRITICAL(false); - dm_free(i2caux_dce110); + kfree(i2caux_dce110); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.c b/drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.c index 029bf735036c..1fdb3252920b 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.c @@ -59,7 +59,7 @@ static void destroy( { destruct(*i2c_engine); - dm_free(*i2c_engine); + kfree(*i2c_engine); *i2c_engine = NULL; } @@ -90,7 +90,8 @@ static bool construct( struct i2caux *dal_i2caux_diag_fpga_create( struct dc_context *ctx) { - struct i2caux *i2caux = dm_alloc(sizeof(struct i2caux)); + struct i2caux *i2caux = kzalloc(sizeof(struct i2caux), + GFP_KERNEL); if (!i2caux) { ASSERT_CRITICAL(false); @@ -102,7 +103,7 @@ struct i2caux *dal_i2caux_diag_fpga_create( ASSERT_CRITICAL(false); - dm_free(i2caux); + kfree(i2caux); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c index 95bc4457d44b..9d0077ade12c 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c @@ -541,7 +541,7 @@ static void destroy( { dal_i2c_sw_engine_destruct(FROM_I2C_ENGINE(*ptr)); - dm_free(*ptr); + kfree(*ptr); *ptr = NULL; } @@ -592,7 +592,7 @@ struct i2c_engine *dal_i2c_sw_engine_create( return NULL; } - engine = dm_alloc(sizeof(struct i2c_sw_engine)); + engine = kzalloc(sizeof(struct i2c_sw_engine), GFP_KERNEL); if (!engine) { BREAK_TO_DEBUGGER(); @@ -604,7 +604,7 @@ struct i2c_engine *dal_i2c_sw_engine_create( BREAK_TO_DEBUGGER(); - dm_free(engine); + kfree(engine); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c index 7cce28489dba..a6c3a7229def 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c @@ -422,7 +422,8 @@ bool construct( struct irq_service *dal_irq_service_dce110_create( struct irq_service_init_data *init_data) { - struct irq_service *irq_service = dm_alloc(sizeof(*irq_service)); + struct irq_service *irq_service = kzalloc(sizeof(*irq_service), + GFP_KERNEL); if (!irq_service) return NULL; @@ -430,6 +431,6 @@ struct irq_service *dal_irq_service_dce110_create( if (construct(irq_service, init_data)) return irq_service; - dm_free(irq_service); + kfree(irq_service); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c index 3871633ac635..61d7c286802a 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c @@ -281,7 +281,8 @@ static bool construct( struct irq_service *dal_irq_service_dce120_create( struct irq_service_init_data *init_data) { - struct irq_service *irq_service = dm_alloc(sizeof(*irq_service)); + struct irq_service *irq_service = kzalloc(sizeof(*irq_service), + GFP_KERNEL); if (!irq_service) return NULL; @@ -289,6 +290,6 @@ struct irq_service *dal_irq_service_dce120_create( if (construct(irq_service, init_data)) return irq_service; - dm_free(irq_service); + kfree(irq_service); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c index f458ef8e4c57..d6e1fb665d90 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c @@ -293,7 +293,8 @@ static bool construct( struct irq_service *dal_irq_service_dce80_create( struct irq_service_init_data *init_data) { - struct irq_service *irq_service = dm_alloc(sizeof(*irq_service)); + struct irq_service *irq_service = kzalloc(sizeof(*irq_service), + GFP_KERNEL); if (!irq_service) return NULL; @@ -301,7 +302,7 @@ struct irq_service *dal_irq_service_dce80_create( if (construct(irq_service, init_data)) return irq_service; - dm_free(irq_service); + kfree(irq_service); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c index be59f0a654e2..f6e861162a6e 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c @@ -348,7 +348,8 @@ static bool construct( struct irq_service *dal_irq_service_dcn10_create( struct irq_service_init_data *init_data) { - struct irq_service *irq_service = dm_alloc(sizeof(*irq_service)); + struct irq_service *irq_service = kzalloc(sizeof(*irq_service), + GFP_KERNEL); if (!irq_service) return NULL; @@ -356,6 +357,6 @@ struct irq_service *dal_irq_service_dcn10_create( if (construct(irq_service, init_data)) return irq_service; - dm_free(irq_service); + kfree(irq_service); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c index 0a1fae4ef83a..ce20622c7c89 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c +++ b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c @@ -66,7 +66,7 @@ void dal_irq_service_destroy(struct irq_service **irq_service) return; } - dm_free(*irq_service); + kfree(*irq_service); *irq_service = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c index 57b5a3babdf8..db513abd735a 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c @@ -87,7 +87,7 @@ static void virtual_link_encoder_connect_dig_be_to_fe( static void virtual_link_encoder_destroy(struct link_encoder **enc) { - dm_free(*enc); + kfree(*enc); *enc = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c index 7fe6085e6e37..3dc1733eea20 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c @@ -121,7 +121,7 @@ bool virtual_stream_encoder_construct( struct stream_encoder *virtual_stream_encoder_create( struct dc_context *ctx, struct dc_bios *bp) { - struct stream_encoder *enc = dm_alloc(sizeof(*enc)); + struct stream_encoder *enc = kzalloc(sizeof(*enc), GFP_KERNEL); if (!enc) return NULL; @@ -130,7 +130,7 @@ struct stream_encoder *virtual_stream_encoder_create( return enc; BREAK_TO_DEBUGGER(); - dm_free(enc); + kfree(enc); return NULL; } diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 52350d0e68d0..4d7db4aa28e0 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -143,7 +143,7 @@ static bool check_dc_support(const struct dc *dc) struct mod_freesync *mod_freesync_create(struct dc *dc) { struct core_freesync *core_freesync = - dm_alloc(sizeof(struct core_freesync)); + kzalloc(sizeof(struct core_freesync), GFP_KERNEL); struct persistent_data_flag flag; @@ -153,8 +153,8 @@ struct mod_freesync *mod_freesync_create(struct dc *dc) if (core_freesync == NULL) goto fail_alloc_context; - core_freesync->map = dm_alloc(sizeof(struct freesync_entity) * - MOD_FREESYNC_MAX_CONCURRENT_STREAMS); + core_freesync->map = kzalloc(sizeof(struct freesync_entity) * MOD_FREESYNC_MAX_CONCURRENT_STREAMS, + GFP_KERNEL); if (core_freesync->map == NULL) goto fail_alloc_map; @@ -197,10 +197,10 @@ struct mod_freesync *mod_freesync_create(struct dc *dc) return &core_freesync->public; fail_construct: - dm_free(core_freesync->map); + kfree(core_freesync->map); fail_alloc_map: - dm_free(core_freesync); + kfree(core_freesync); fail_alloc_context: return NULL; @@ -217,9 +217,9 @@ void mod_freesync_destroy(struct mod_freesync *mod_freesync) if (core_freesync->map[i].stream) dc_stream_release(core_freesync->map[i].stream); - dm_free(core_freesync->map); + kfree(core_freesync->map); - dm_free(core_freesync); + kfree(core_freesync); } } -- cgit v1.2.3