From 95574c6961476e26236f16b48bfd98d6a1ceff4c Mon Sep 17 00:00:00 2001 From: Wesley Chalmers Date: Sun, 21 Feb 2021 23:05:48 -0500 Subject: drm/amd/display: BIOS LTTPR Caps Interface [WHY] Some platforms will have LTTPR capabilities forced on by VBIOS flags; the functions added here will access those flags. Signed-off-by: Wesley Chalmers Reviewed-by: Jun Lei Acked-by: Anson Jacob Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/atomfirmware.h | 37 +++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/include/atomfirmware.h') diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h index 58364a8eb1f3..82b3cd89b383 100644 --- a/drivers/gpu/drm/amd/include/atomfirmware.h +++ b/drivers/gpu/drm/amd/include/atomfirmware.h @@ -981,6 +981,40 @@ struct atom_display_controller_info_v4_2 uint8_t reserved3[8]; }; +struct atom_display_controller_info_v4_3 +{ + struct atom_common_table_header table_header; + uint32_t display_caps; + uint32_t bootup_dispclk_10khz; + uint16_t dce_refclk_10khz; + uint16_t i2c_engine_refclk_10khz; + uint16_t dvi_ss_percentage; // in unit of 0.001% + uint16_t dvi_ss_rate_10hz; + uint16_t hdmi_ss_percentage; // in unit of 0.001% + uint16_t hdmi_ss_rate_10hz; + uint16_t dp_ss_percentage; // in unit of 0.001% + uint16_t dp_ss_rate_10hz; + uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode + uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode + uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode + uint8_t ss_reserved; + uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available + uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available + uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable + uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable + uint16_t dpphy_refclk_10khz; + uint16_t reserved2; + uint8_t dcnip_min_ver; + uint8_t dcnip_max_ver; + uint8_t max_disp_pipe_num; + uint8_t max_vbios_active_disp_pipe_num; + uint8_t max_ppll_num; + uint8_t max_disp_phy_num; + uint8_t max_aux_pairs; + uint8_t remotedisplayconfig; + uint8_t reserved3[8]; +}; + struct atom_display_controller_info_v4_4 { struct atom_common_table_header table_header; uint32_t display_caps; @@ -1043,7 +1077,8 @@ enum dce_info_caps_def DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 =0x04, // only for VBIOS DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08, - + // only for VBIOS + DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE =0x20, }; /* -- cgit v1.2.3 From dd8a86877ec0dece66b5633b57622767696fc31f Mon Sep 17 00:00:00 2001 From: Wesley Chalmers Date: Wed, 17 Mar 2021 16:36:47 -0400 Subject: drm/amd/display: Interface for LTTPR interop [WHY] The logic to toggle LTTPR transparent/non-transparent requires 2 flags provided by BIOS [HOW] Repurpose the interface to get dce caps so both LTTPR querying functions can use them. Signed-off-by: Wesley Chalmers Reviewed-by: Jun Lei Acked-by: Anson Jacob Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 75 ++++++++++++++++++---- drivers/gpu/drm/amd/display/dc/dc_bios_types.h | 3 + drivers/gpu/drm/amd/include/atomfirmware.h | 1 + 3 files changed, 67 insertions(+), 12 deletions(-) (limited to 'drivers/gpu/drm/amd/include/atomfirmware.h') diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c index 2ee0c6fc069a..d79f4fe06c47 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c @@ -916,7 +916,7 @@ static enum bp_result bios_parser_get_soc_bb_info( return result; } -static enum bp_result get_lttpr_caps_v4_1( +static enum bp_result get_disp_caps_v4_1( struct bios_parser *bp, uint8_t *dce_caps) { @@ -935,12 +935,12 @@ static enum bp_result get_lttpr_caps_v4_1( if (!disp_cntl_tbl) return BP_RESULT_BADBIOSTABLE; - *dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); + *dce_caps = disp_cntl_tbl->display_caps; return result; } -static enum bp_result get_lttpr_caps_v4_2( +static enum bp_result get_disp_caps_v4_2( struct bios_parser *bp, uint8_t *dce_caps) { @@ -959,12 +959,12 @@ static enum bp_result get_lttpr_caps_v4_2( if (!disp_cntl_tbl) return BP_RESULT_BADBIOSTABLE; - *dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); + *dce_caps = disp_cntl_tbl->display_caps; return result; } -static enum bp_result get_lttpr_caps_v4_3( +static enum bp_result get_disp_caps_v4_3( struct bios_parser *bp, uint8_t *dce_caps) { @@ -983,12 +983,12 @@ static enum bp_result get_lttpr_caps_v4_3( if (!disp_cntl_tbl) return BP_RESULT_BADBIOSTABLE; - *dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); + *dce_caps = disp_cntl_tbl->display_caps; return result; } -static enum bp_result get_lttpr_caps_v4_4( +static enum bp_result get_disp_caps_v4_4( struct bios_parser *bp, uint8_t *dce_caps) { @@ -1007,7 +1007,52 @@ static enum bp_result get_lttpr_caps_v4_4( if (!disp_cntl_tbl) return BP_RESULT_BADBIOSTABLE; - *dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); + *dce_caps = disp_cntl_tbl->display_caps; + + return result; +} + +static enum bp_result bios_parser_get_lttpr_interop( + struct dc_bios *dcb, + uint8_t *dce_caps) +{ + struct bios_parser *bp = BP_FROM_DCB(dcb); + enum bp_result result = BP_RESULT_UNSUPPORTED; + struct atom_common_table_header *header; + struct atom_data_revision tbl_revision; + + if (!DATA_TABLES(dce_info)) + return BP_RESULT_UNSUPPORTED; + + header = GET_IMAGE(struct atom_common_table_header, + DATA_TABLES(dce_info)); + get_atom_data_table_revision(header, &tbl_revision); + switch (tbl_revision.major) { + case 4: + switch (tbl_revision.minor) { + case 1: + result = get_disp_caps_v4_1(bp, dce_caps); + *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); + break; + case 2: + result = get_disp_caps_v4_2(bp, dce_caps); + *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); + break; + case 3: + result = get_disp_caps_v4_3(bp, dce_caps); + *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); + break; + case 4: + result = get_disp_caps_v4_4(bp, dce_caps); + *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); + break; + default: + break; + } + break; + default: + break; + } return result; } @@ -1031,16 +1076,20 @@ static enum bp_result bios_parser_get_lttpr_caps( case 4: switch (tbl_revision.minor) { case 1: - result = get_lttpr_caps_v4_1(bp, dce_caps); + result = get_disp_caps_v4_1(bp, dce_caps); + *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); break; case 2: - result = get_lttpr_caps_v4_2(bp, dce_caps); + result = get_disp_caps_v4_2(bp, dce_caps); + *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); break; case 3: - result = get_lttpr_caps_v4_3(bp, dce_caps); + result = get_disp_caps_v4_3(bp, dce_caps); + *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); break; case 4: - result = get_lttpr_caps_v4_4(bp, dce_caps); + result = get_disp_caps_v4_4(bp, dce_caps); + *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); break; default: break; @@ -2670,6 +2719,8 @@ static const struct dc_vbios_funcs vbios_funcs = { .get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info, .get_lttpr_caps = bios_parser_get_lttpr_caps, + + .get_lttpr_interop = bios_parser_get_lttpr_interop, }; static bool bios_parser2_construct( diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h index 1b957c60156b..67abda44eb1f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h @@ -153,6 +153,9 @@ struct dc_vbios_funcs { enum bp_result (*get_lttpr_caps)( struct dc_bios *dcb, uint8_t *dce_caps); + enum bp_result (*get_lttpr_interop)( + struct dc_bios *dcb, + uint8_t *dce_caps); }; struct bios_registers { diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h index 82b3cd89b383..c77ed38c20fb 100644 --- a/drivers/gpu/drm/amd/include/atomfirmware.h +++ b/drivers/gpu/drm/amd/include/atomfirmware.h @@ -1079,6 +1079,7 @@ enum dce_info_caps_def DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08, // only for VBIOS DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE =0x20, + DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE = 0x40, }; /* -- cgit v1.2.3 From af48a06daaf15e0ee7c354a1e5ce6e8b06d67a38 Mon Sep 17 00:00:00 2001 From: Xiaojian Du Date: Tue, 13 Apr 2021 15:03:42 +0800 Subject: drm/amd: update the atomfirmware header for smu12 This patch is to update the atomfirmware header for smu12. v2: remove some unnecessary members Signed-off-by: Xiaojian Du Acked-by: Alex Deucher Reviewed-by: Huang Rui Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/atomfirmware.h | 41 ++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'drivers/gpu/drm/amd/include/atomfirmware.h') diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h index c77ed38c20fb..f2564ba21c0b 100644 --- a/drivers/gpu/drm/amd/include/atomfirmware.h +++ b/drivers/gpu/drm/amd/include/atomfirmware.h @@ -3336,6 +3336,47 @@ enum atom_smu11_syspll3_1_clock_id { SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK }; +enum atom_smu12_syspll_id { + SMU12_SYSPLL0_ID = 0, + SMU12_SYSPLL1_ID = 1, + SMU12_SYSPLL2_ID = 2, + SMU12_SYSPLL3_0_ID = 3, + SMU12_SYSPLL3_1_ID = 4, +}; + +enum atom_smu12_syspll0_clock_id { + SMU12_SYSPLL0_SMNCLK_ID = 0, // SOCCLK + SMU12_SYSPLL0_SOCCLK_ID = 1, // SOCCLK + SMU12_SYSPLL0_MP0CLK_ID = 2, // MP0CLK + SMU12_SYSPLL0_MP1CLK_ID = 3, // MP1CLK + SMU12_SYSPLL0_MP2CLK_ID = 4, // MP2CLK + SMU12_SYSPLL0_VCLK_ID = 5, // VCLK + SMU12_SYSPLL0_LCLK_ID = 6, // LCLK + SMU12_SYSPLL0_DCLK_ID = 7, // DCLK + SMU12_SYSPLL0_ACLK_ID = 8, // ACLK + SMU12_SYSPLL0_ISPCLK_ID = 9, // ISPCLK + SMU12_SYSPLL0_SHUBCLK_ID = 10, // SHUBCLK +}; + +enum atom_smu12_syspll1_clock_id { + SMU12_SYSPLL1_DISPCLK_ID = 0, // DISPCLK + SMU12_SYSPLL1_DPPCLK_ID = 1, // DPPCLK + SMU12_SYSPLL1_DPREFCLK_ID = 2, // DPREFCLK + SMU12_SYSPLL1_DCFCLK_ID = 3, // DCFCLK +}; + +enum atom_smu12_syspll2_clock_id { + SMU12_SYSPLL2_Pre_GFXCLK_ID = 0, // Pre_GFXCLK +}; + +enum atom_smu12_syspll3_0_clock_id { + SMU12_SYSPLL3_0_FCLK_ID = 0, // FCLK +}; + +enum atom_smu12_syspll3_1_clock_id { + SMU12_SYSPLL3_1_UMCCLK_ID = 0, // UMCCLK +}; + struct atom_get_smu_clock_info_output_parameters_v3_1 { union { -- cgit v1.2.3