diff options
211 files changed, 8956 insertions, 5644 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 4fddc509e78e..99b75aa1c2ec 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -22,13 +22,13 @@ #if defined(CONFIG_DEBUG_ICEDCC) #ifdef CONFIG_CPU_V6 - .macro loadsp, rb + .macro loadsp, rb, tmp .endm .macro writeb, ch, rb mcr p14, 0, \ch, c0, c5, 0 .endm #elif defined(CONFIG_CPU_V7) - .macro loadsp, rb + .macro loadsp, rb, tmp .endm .macro writeb, ch, rb wait: mrc p14, 0, pc, c0, c1, 0 @@ -36,13 +36,13 @@ wait: mrc p14, 0, pc, c0, c1, 0 mcr p14, 0, \ch, c0, c5, 0 .endm #elif defined(CONFIG_CPU_XSCALE) - .macro loadsp, rb + .macro loadsp, rb, tmp .endm .macro writeb, ch, rb mcr p14, 0, \ch, c8, c0, 0 .endm #else - .macro loadsp, rb + .macro loadsp, rb, tmp .endm .macro writeb, ch, rb mcr p14, 0, \ch, c1, c0, 0 @@ -58,7 +58,7 @@ wait: mrc p14, 0, pc, c0, c1, 0 .endm #if defined(CONFIG_ARCH_SA1100) - .macro loadsp, rb + .macro loadsp, rb, tmp mov \rb, #0x80000000 @ physical base address #ifdef CONFIG_DEBUG_LL_SER3 add \rb, \rb, #0x00050000 @ Ser3 @@ -67,13 +67,13 @@ wait: mrc p14, 0, pc, c0, c1, 0 #endif .endm #elif defined(CONFIG_ARCH_S3C2410) - .macro loadsp, rb + .macro loadsp, rb, tmp mov \rb, #0x50000000 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT .endm #else - .macro loadsp, rb - addruart \rb + .macro loadsp, rb, tmp + addruart \rb, \tmp .endm #endif #endif @@ -1025,7 +1025,7 @@ phex: adr r3, phexbuf strb r2, [r3, r1] b 1b -puts: loadsp r3 +puts: loadsp r3, r1 1: ldrb r2, [r0], #1 teq r2, #0 moveq pc, lr @@ -1042,7 +1042,7 @@ puts: loadsp r3 putc: mov r2, r0 mov r0, #0 - loadsp r3 + loadsp r3, r1 b 2b memdump: mov r12, r0 diff --git a/arch/arm/configs/omap3_defconfig b/arch/arm/configs/omap3_defconfig index 367be98a6aef..714835e5ebec 100644 --- a/arch/arm/configs/omap3_defconfig +++ b/arch/arm/configs/omap3_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.32-rc8 -# Tue Dec 1 14:04:02 2009 +# Linux kernel version: 2.6.33-rc5 +# Tue Jan 26 11:05:31 2010 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -20,6 +20,8 @@ CONFIG_ARCH_HAS_CPUFREQ=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_OPROFILE_ARMV6=y +CONFIG_OPROFILE_ARM11_CORE=y CONFIG_OPROFILE_ARMV7=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -33,6 +35,12 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y @@ -48,6 +56,7 @@ CONFIG_BSD_PROCESS_ACCT=y # CONFIG_TREE_RCU=y # CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set # CONFIG_RCU_TRACE is not set CONFIG_RCU_FANOUT=32 # CONFIG_RCU_FANOUT_EXACT is not set @@ -69,6 +78,7 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_RD_GZIP=y # CONFIG_RD_BZIP2 is not set # CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y CONFIG_ANON_INODES=y @@ -133,14 +143,41 @@ CONFIG_LBDAF=y # IO Schedulers # CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set # CONFIG_DEFAULT_DEADLINE is not set CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set CONFIG_FREEZER=y # @@ -169,6 +206,7 @@ CONFIG_MMU=y # CONFIG_ARCH_IXP2000 is not set # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set # CONFIG_ARCH_KIRKWOOD is not set # CONFIG_ARCH_LOKI is not set # CONFIG_ARCH_MV78XX0 is not set @@ -191,21 +229,23 @@ CONFIG_MMU=y # CONFIG_ARCH_DAVINCI is not set CONFIG_ARCH_OMAP=y # CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set # # TI OMAP Implementations # CONFIG_ARCH_OMAP_OTG=y # CONFIG_ARCH_OMAP1 is not set -# CONFIG_ARCH_OMAP2 is not set +CONFIG_ARCH_OMAP2PLUS=y +CONFIG_ARCH_OMAP2=y CONFIG_ARCH_OMAP3=y -# CONFIG_ARCH_OMAP4 is not set +CONFIG_ARCH_OMAP4=y # # OMAP Feature Selections # -# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set -# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set +CONFIG_OMAP_DEBUG_DEVICES=y +CONFIG_OMAP_DEBUG_LEDS=y CONFIG_OMAP_RESET_CLOCKS=y CONFIG_OMAP_MUX=y CONFIG_OMAP_MUX_DEBUG=y @@ -216,43 +256,66 @@ CONFIG_OMAP_MCBSP=y CONFIG_OMAP_32K_TIMER=y CONFIG_OMAP_32K_TIMER_HZ=128 CONFIG_OMAP_DM_TIMER=y -# CONFIG_OMAP_LL_DEBUG_UART1 is not set -# CONFIG_OMAP_LL_DEBUG_UART2 is not set -# CONFIG_OMAP_LL_DEBUG_UART3 is not set -CONFIG_OMAP_LL_DEBUG_NONE=y # CONFIG_OMAP_PM_NONE is not set CONFIG_OMAP_PM_NOOP=y -CONFIG_ARCH_OMAP34XX=y +CONFIG_MACH_OMAP_GENERIC=y + +# +# OMAP Core Type +# +CONFIG_ARCH_OMAP2420=y +# CONFIG_ARCH_OMAP2430 is not set CONFIG_ARCH_OMAP3430=y +CONFIG_OMAP_PACKAGE_CBB=y +CONFIG_OMAP_PACKAGE_CUS=y +CONFIG_OMAP_PACKAGE_CBP=y # # OMAP Board Type # +CONFIG_MACH_OMAP2_TUSB6010=y +CONFIG_MACH_OMAP_H4=y +CONFIG_MACH_OMAP_APOLLON=y +# CONFIG_MACH_OMAP_2430SDP is not set CONFIG_MACH_OMAP3_BEAGLE=y CONFIG_MACH_OMAP_LDP=y CONFIG_MACH_OVERO=y CONFIG_MACH_OMAP3EVM=y CONFIG_MACH_OMAP3517EVM=y CONFIG_MACH_OMAP3_PANDORA=y +CONFIG_MACH_OMAP3_TOUCHBOOK=y CONFIG_MACH_OMAP_3430SDP=y +CONFIG_MACH_NOKIA_N800=y +CONFIG_MACH_NOKIA_N810=y +CONFIG_MACH_NOKIA_N810_WIMAX=y +CONFIG_MACH_NOKIA_N8X0=y CONFIG_MACH_NOKIA_RX51=y CONFIG_MACH_OMAP_ZOOM2=y CONFIG_MACH_OMAP_ZOOM3=y CONFIG_MACH_CM_T35=y CONFIG_MACH_IGEP0020=y CONFIG_MACH_OMAP_3630SDP=y +CONFIG_MACH_OMAP_4430SDP=y +# CONFIG_OMAP3_EMU is not set +# CONFIG_OMAP3_SDRC_AC_TIMING is not set # # Processor Type # -CONFIG_CPU_32v6K=y +CONFIG_CPU_V6=y +# CONFIG_CPU_32v6K is not set CONFIG_CPU_V7=y +CONFIG_CPU_32v6=y CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV6=y CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V6=y CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V6=y CONFIG_CPU_CACHE_V7=y CONFIG_CPU_CACHE_VIPT=y CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y CONFIG_CPU_TLB_V7=y CONFIG_CPU_HAS_ASID=y CONFIG_CPU_CP15=y @@ -268,9 +331,11 @@ CONFIG_ARM_THUMBEE=y # CONFIG_CPU_BPREDICT_DISABLE is not set CONFIG_HAS_TLS_REG=y CONFIG_ARM_L1_CACHE_SHIFT=6 +# CONFIG_ARM_ERRATA_411920 is not set # CONFIG_ARM_ERRATA_430973 is not set # CONFIG_ARM_ERRATA_458693 is not set # CONFIG_ARM_ERRATA_460075 is not set +CONFIG_ARM_GIC=y CONFIG_COMMON_CLKDEV=y # @@ -287,6 +352,7 @@ CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_SMP is not set CONFIG_VMSPLIT_3G=y # CONFIG_VMSPLIT_2G is not set # CONFIG_VMSPLIT_1G is not set @@ -298,6 +364,7 @@ CONFIG_HZ=128 # CONFIG_THUMB2_KERNEL is not set CONFIG_AEABI=y CONFIG_OABI_COMPAT=y +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set # CONFIG_HIGHMEM is not set @@ -308,12 +375,10 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_SPLIT_PTLOCK_CPUS=999999 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_LEDS=y @@ -509,15 +574,18 @@ CONFIG_BT_HCIBPA10X=y # CONFIG_BT_MRVL is not set # CONFIG_AF_RXRPC is not set CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y CONFIG_CFG80211=y # CONFIG_NL80211_TESTMODE is not set # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set # CONFIG_CFG80211_REG_DEBUG is not set CONFIG_CFG80211_DEFAULT_PS=y -CONFIG_CFG80211_DEFAULT_PS_VALUE=1 # CONFIG_CFG80211_DEBUGFS is not set CONFIG_WIRELESS_OLD_REGULATORY=y -CONFIG_WIRELESS_EXT=y +CONFIG_CFG80211_WEXT=y CONFIG_WIRELESS_EXT_SYSFS=y CONFIG_LIB80211=y # CONFIG_LIB80211_DEBUG is not set @@ -671,6 +739,7 @@ CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_UB is not set CONFIG_BLK_DEV_RAM=y @@ -681,9 +750,12 @@ CONFIG_BLK_DEV_RAM_SIZE=16384 # CONFIG_ATA_OVER_ETH is not set # CONFIG_MG_DISK is not set CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_ISL29003 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set # CONFIG_C2PORT is not set # @@ -694,6 +766,7 @@ CONFIG_MISC_DEVICES=y CONFIG_EEPROM_LEGACY=y # CONFIG_EEPROM_MAX6875 is not set # CONFIG_EEPROM_93CX6 is not set +# CONFIG_IWMC3200TOP is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -792,28 +865,26 @@ CONFIG_SMSC911X=y CONFIG_NETDEV_1000=y CONFIG_NETDEV_10000=y CONFIG_WLAN=y -# CONFIG_WLAN_PRE80211 is not set -CONFIG_WLAN_80211=y -CONFIG_LIBERTAS=y -CONFIG_LIBERTAS_USB=y -CONFIG_LIBERTAS_SDIO=y -# CONFIG_LIBERTAS_SPI is not set -CONFIG_LIBERTAS_DEBUG=y # CONFIG_LIBERTAS_THINFIRM is not set # CONFIG_AT76C50X_USB is not set # CONFIG_USB_ZD1201 is not set # CONFIG_USB_NET_RNDIS_WLAN is not set # CONFIG_RTL8187 is not set # CONFIG_MAC80211_HWSIM is not set -# CONFIG_P54_COMMON is not set # CONFIG_ATH_COMMON is not set -# CONFIG_HOSTAP is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set -# CONFIG_ZD1211RW is not set +# CONFIG_HOSTAP is not set +# CONFIG_IWM is not set +CONFIG_LIBERTAS=y +CONFIG_LIBERTAS_USB=y +CONFIG_LIBERTAS_SDIO=y +# CONFIG_LIBERTAS_SPI is not set +CONFIG_LIBERTAS_DEBUG=y +# CONFIG_P54_COMMON is not set # CONFIG_RT2X00 is not set # CONFIG_WL12XX is not set -# CONFIG_IWM is not set +# CONFIG_ZD1211RW is not set # # Enable WiMAX (Networking options) to see the WiMAX drivers @@ -861,6 +932,7 @@ CONFIG_USB_NET_ZAURUS=y CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set # CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set # # Userland interfaces @@ -889,6 +961,7 @@ CONFIG_KEYBOARD_GPIO=y # CONFIG_KEYBOARD_OPENCORES is not set # CONFIG_KEYBOARD_STOWAWAY is not set # CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_OMAP is not set CONFIG_KEYBOARD_TWL4030=y # CONFIG_KEYBOARD_XTKBD is not set CONFIG_INPUT_MOUSE=y @@ -914,6 +987,7 @@ CONFIG_TOUCHSCREEN_ADS7846=y # CONFIG_TOUCHSCREEN_AD7879_I2C is not set # CONFIG_TOUCHSCREEN_AD7879_SPI is not set # CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set # CONFIG_TOUCHSCREEN_EETI is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GUNZE is not set @@ -948,6 +1022,7 @@ CONFIG_SERIO=y CONFIG_SERIO_SERPORT=y CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set # CONFIG_GAMEPORT is not set # @@ -986,6 +1061,7 @@ CONFIG_UNIX98_PTYS=y # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_HW_RANDOM_TIMERIOMEM is not set +CONFIG_HW_RANDOM_OMAP=y # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set @@ -1024,7 +1100,6 @@ CONFIG_I2C_OMAP=y # # Miscellaneous I2C Chip support # -# CONFIG_DS1682 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set @@ -1040,6 +1115,8 @@ CONFIG_SPI_MASTER=y # CONFIG_SPI_BITBANG is not set # CONFIG_SPI_GPIO is not set CONFIG_SPI_OMAP24XX=y +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set # # SPI Protocol Masters @@ -1067,6 +1144,7 @@ CONFIG_GPIO_SYSFS=y # CONFIG_GPIO_PCA953X is not set # CONFIG_GPIO_PCF857X is not set CONFIG_GPIO_TWL4030=y +# CONFIG_GPIO_ADP5588 is not set # # PCI GPIO expanders: @@ -1141,6 +1219,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_LM63 is not set # CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set # CONFIG_SENSORS_LM75 is not set # CONFIG_SENSORS_LM77 is not set # CONFIG_SENSORS_LM78 is not set @@ -1166,6 +1245,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_TMP421 is not set @@ -1179,6 +1259,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set # CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set # CONFIG_THERMAL is not set CONFIG_WATCHDOG=y CONFIG_WATCHDOG_NOWAYOUT=y @@ -1204,20 +1285,22 @@ CONFIG_SSB_POSSIBLE=y # # Multifunction device drivers # -# CONFIG_MFD_CORE is not set +CONFIG_MFD_CORE=y # CONFIG_MFD_SM501 is not set # CONFIG_MFD_ASIC3 is not set # CONFIG_HTC_EGPIO is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_TPS65010 is not set +# CONFIG_MENELAUS is not set CONFIG_TWL4030_CORE=y # CONFIG_TWL4030_POWER is not set -# CONFIG_TWL4030_CODEC is not set +CONFIG_TWL4030_CODEC=y # CONFIG_MFD_TMIO is not set # CONFIG_MFD_T7L66XB is not set # CONFIG_MFD_TC6387XB is not set # CONFIG_MFD_TC6393XB is not set # CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM831X is not set # CONFIG_MFD_WM8350_I2C is not set @@ -1225,6 +1308,8 @@ CONFIG_TWL4030_CORE=y # CONFIG_MFD_MC13783 is not set # CONFIG_AB3100_CORE is not set # CONFIG_EZX_PCAP is not set +# CONFIG_MFD_88PM8607 is not set +# CONFIG_AB4500_CORE is not set CONFIG_REGULATOR=y # CONFIG_REGULATOR_DEBUG is not set CONFIG_REGULATOR_FIXED_VOLTAGE=y @@ -1232,6 +1317,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set # CONFIG_REGULATOR_BQ24022 is not set # CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8660 is not set CONFIG_REGULATOR_TWL4030=y # CONFIG_REGULATOR_LP3971 is not set # CONFIG_REGULATOR_TPS65023 is not set @@ -1267,6 +1353,7 @@ CONFIG_FB_TILEBLITTING=y # # CONFIG_FB_UVESA is not set # CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_TMIO is not set # CONFIG_FB_VIRTUAL is not set # CONFIG_FB_METRONOME is not set # CONFIG_FB_MB862XX is not set @@ -1281,6 +1368,7 @@ CONFIG_FB_OMAP_079M3R=y # CONFIG_FB_OMAP_LCD_MIPID is not set # CONFIG_FB_OMAP_BOOTLOADER_INIT is not set CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2 +# CONFIG_OMAP2_DSS is not set CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y # CONFIG_LCD_LMS283GF05 is not set @@ -1364,12 +1452,15 @@ CONFIG_SND_USB_AUDIO=y CONFIG_SND_SOC=y CONFIG_SND_OMAP_SOC=y CONFIG_SND_OMAP_SOC_MCBSP=y +# CONFIG_SND_OMAP_SOC_N810 is not set # CONFIG_SND_OMAP_SOC_OVERO is not set # CONFIG_SND_OMAP_SOC_OMAP3EVM is not set +# CONFIG_SND_OMAP_SOC_AM3517EVM is not set # CONFIG_SND_OMAP_SOC_SDP3430 is not set CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=y # CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE is not set # CONFIG_SND_OMAP_SOC_ZOOM2 is not set +# CONFIG_SND_OMAP_SOC_IGEP0020 is not set CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_ALL_CODECS is not set CONFIG_SND_SOC_TWL4030=y @@ -1418,7 +1509,7 @@ CONFIG_USB_HID=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y -# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y CONFIG_USB=y CONFIG_USB_DEBUG=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y @@ -1441,6 +1532,7 @@ CONFIG_USB_MON=y # USB Host Controller Drivers # # CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_EHCI_HCD is not set # CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set # CONFIG_USB_ISP1760_HCD is not set @@ -1556,16 +1648,18 @@ CONFIG_USB_GADGET_SELECTED=y # CONFIG_USB_GADGET_LANGWELL is not set # CONFIG_USB_GADGET_DUMMY_HCD is not set CONFIG_USB_GADGET_DUALSPEED=y -CONFIG_USB_ZERO=y +CONFIG_USB_ZERO=m # CONFIG_USB_ZERO_HNPTEST is not set # CONFIG_USB_AUDIO is not set # CONFIG_USB_ETH is not set # CONFIG_USB_GADGETFS is not set # CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_MASS_STORAGE is not set # CONFIG_USB_G_SERIAL is not set # CONFIG_USB_MIDI_GADGET is not set # CONFIG_USB_G_PRINTER is not set # CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_MULTI is not set # # OTG and related infrastructure @@ -1573,6 +1667,7 @@ CONFIG_USB_ZERO=y CONFIG_USB_OTG_UTILS=y # CONFIG_USB_GPIO_VBUS is not set # CONFIG_ISP1301_OMAP is not set +# CONFIG_USB_ULPI is not set CONFIG_TWL4030_USB=y CONFIG_NOP_USB_XCEIV=y CONFIG_MMC=y @@ -1609,7 +1704,9 @@ CONFIG_LEDS_GPIO_PLATFORM=y # CONFIG_LEDS_LP3944 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_REGULATOR is not set # CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set # # LED Triggers @@ -1653,6 +1750,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_PCF8563 is not set # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set CONFIG_RTC_DRV_TWL4030=y # CONFIG_RTC_DRV_S35390A is not set # CONFIG_RTC_DRV_FM3130 is not set @@ -1683,7 +1781,9 @@ CONFIG_RTC_DRV_TWL4030=y # CONFIG_RTC_DRV_M48T86 is not set # CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set # CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1951,6 +2051,7 @@ CONFIG_DEBUG_INFO=y # CONFIG_LKDTM is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set # CONFIG_PAGE_POISONING is not set CONFIG_NOP_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y @@ -1983,7 +2084,9 @@ CONFIG_ARM_UNWIND=y # CONFIG_DEBUG_ERRORS is not set # CONFIG_DEBUG_STACK_USAGE is not set CONFIG_DEBUG_LL=y +# CONFIG_EARLY_PRINTK is not set # CONFIG_DEBUG_ICEDCC is not set +# CONFIG_OC_ETM is not set # # Security options @@ -1993,9 +2096,12 @@ CONFIG_SECURITY=y # CONFIG_SECURITYFS is not set # CONFIG_SECURITY_NETWORK is not set # CONFIG_SECURITY_PATH is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -# CONFIG_SECURITY_ROOTPLUG is not set # CONFIG_SECURITY_TOMOYO is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" CONFIG_CRYPTO=y # diff --git a/arch/arm/configs/rx51_defconfig b/arch/arm/configs/rx51_defconfig index b6eeebb31761..426ae948aefe 100644 --- a/arch/arm/configs/rx51_defconfig +++ b/arch/arm/configs/rx51_defconfig @@ -1354,7 +1354,7 @@ CONFIG_USB_OTG_UTILS=y # CONFIG_USB_GPIO_VBUS is not set # CONFIG_ISP1301_OMAP is not set CONFIG_TWL4030_USB=y -CONFIG_MMC=y +CONFIG_MMC=m # CONFIG_MMC_DEBUG is not set # CONFIG_MMC_UNSAFE_RESUME is not set @@ -1362,7 +1362,7 @@ CONFIG_MMC=y # MMC/SD/SDIO Card Drivers # CONFIG_MMC_BLOCK=m -CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_MMC_BLOCK_BOUNCE is not set # CONFIG_SDIO_UART is not set # CONFIG_MMC_TEST is not set diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S index 5c91addcaebc..a38b4879441d 100644 --- a/arch/arm/kernel/debug.S +++ b/arch/arm/kernel/debug.S @@ -24,7 +24,7 @@ #if defined(CONFIG_CPU_V6) - .macro addruart, rx + .macro addruart, rx, tmp .endm .macro senduart, rd, rx @@ -51,7 +51,7 @@ #elif defined(CONFIG_CPU_V7) - .macro addruart, rx + .macro addruart, rx, tmp .endm .macro senduart, rd, rx @@ -71,7 +71,7 @@ wait: mrc p14, 0, pc, c0, c1, 0 #elif defined(CONFIG_CPU_XSCALE) - .macro addruart, rx + .macro addruart, rx, tmp .endm .macro senduart, rd, rx @@ -98,7 +98,7 @@ wait: mrc p14, 0, pc, c0, c1, 0 #else - .macro addruart, rx + .macro addruart, rx, tmp .endm .macro senduart, rd, rx @@ -164,7 +164,7 @@ ENDPROC(printhex2) .ltorg ENTRY(printascii) - addruart r3 + addruart r3, r1 b 2f 1: waituart r2, r3 senduart r1, r3 @@ -180,7 +180,7 @@ ENTRY(printascii) ENDPROC(printascii) ENTRY(printch) - addruart r3 + addruart r3, r1 mov r1, r0 mov r0, #0 b 1b diff --git a/arch/arm/mach-aaec2000/include/mach/debug-macro.S b/arch/arm/mach-aaec2000/include/mach/debug-macro.S index 0b6351d7c389..a9cac368bfe6 100644 --- a/arch/arm/mach-aaec2000/include/mach/debug-macro.S +++ b/arch/arm/mach-aaec2000/include/mach/debug-macro.S @@ -10,7 +10,7 @@ */ #include "hardware.h" - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? moveq \rx, #0x80000000 @ physical diff --git a/arch/arm/mach-at91/include/mach/debug-macro.S b/arch/arm/mach-at91/include/mach/debug-macro.S index 29052ba66ada..9e750a1c1b5a 100644 --- a/arch/arm/mach-at91/include/mach/debug-macro.S +++ b/arch/arm/mach-at91/include/mach/debug-macro.S @@ -14,7 +14,7 @@ #include <mach/hardware.h> #include <mach/at91_dbgu.h> - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? ldreq \rx, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address) diff --git a/arch/arm/mach-clps711x/include/mach/debug-macro.S b/arch/arm/mach-clps711x/include/mach/debug-macro.S index 64baf9f87408..fedd8076a689 100644 --- a/arch/arm/mach-clps711x/include/mach/debug-macro.S +++ b/arch/arm/mach-clps711x/include/mach/debug-macro.S @@ -13,7 +13,7 @@ #include <asm/hardware/clps7111.h> - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? moveq \rx, #CLPS7111_PHYS_BASE diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S index 17ab5236da66..3cd93a801d9b 100644 --- a/arch/arm/mach-davinci/include/mach/debug-macro.S +++ b/arch/arm/mach-davinci/include/mach/debug-macro.S @@ -19,7 +19,7 @@ #include <linux/serial_reg.h> #define UART_SHIFT 2 - .macro addruart, rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? moveq \rx, #0x01000000 @ physical base address diff --git a/arch/arm/mach-dove/include/mach/debug-macro.S b/arch/arm/mach-dove/include/mach/debug-macro.S index 9b89ec7d3040..1521d13f1d14 100644 --- a/arch/arm/mach-dove/include/mach/debug-macro.S +++ b/arch/arm/mach-dove/include/mach/debug-macro.S @@ -8,7 +8,7 @@ #include <mach/bridge-regs.h> - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? ldreq \rx, =DOVE_SB_REGS_PHYS_BASE diff --git a/arch/arm/mach-ebsa110/include/mach/debug-macro.S b/arch/arm/mach-ebsa110/include/mach/debug-macro.S index 1dde8227f3a2..ebbd89f0e6c0 100644 --- a/arch/arm/mach-ebsa110/include/mach/debug-macro.S +++ b/arch/arm/mach-ebsa110/include/mach/debug-macro.S @@ -11,7 +11,7 @@ * **/ - .macro addruart,rx + .macro addruart, rx, tmp mov \rx, #0xf0000000 orr \rx, \rx, #0x00000be0 .endm diff --git a/arch/arm/mach-ep93xx/include/mach/debug-macro.S b/arch/arm/mach-ep93xx/include/mach/debug-macro.S index 802858bc8095..5cd22444e223 100644 --- a/arch/arm/mach-ep93xx/include/mach/debug-macro.S +++ b/arch/arm/mach-ep93xx/include/mach/debug-macro.S @@ -11,7 +11,7 @@ */ #include <mach/ep93xx-regs.h> - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? ldreq \rx, =EP93XX_APB_PHYS_BASE @ Physical base diff --git a/arch/arm/mach-footbridge/include/mach/debug-macro.S b/arch/arm/mach-footbridge/include/mach/debug-macro.S index 4329b8123570..60dda1318f22 100644 --- a/arch/arm/mach-footbridge/include/mach/debug-macro.S +++ b/arch/arm/mach-footbridge/include/mach/debug-macro.S @@ -15,7 +15,7 @@ #ifndef CONFIG_DEBUG_DC21285_PORT /* For NetWinder debugging */ - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? moveq \rx, #0x7c000000 @ physical @@ -32,7 +32,7 @@ .equ dc21285_high, ARMCSR_BASE & 0xff000000 .equ dc21285_low, ARMCSR_BASE & 0x00ffffff - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? moveq \rx, #0x42000000 diff --git a/arch/arm/mach-gemini/include/mach/debug-macro.S b/arch/arm/mach-gemini/include/mach/debug-macro.S index d04a6eaeae14..ad477047069d 100644 --- a/arch/arm/mach-gemini/include/mach/debug-macro.S +++ b/arch/arm/mach-gemini/include/mach/debug-macro.S @@ -11,7 +11,7 @@ */ #include <mach/hardware.h> - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? ldreq \rx, =GEMINI_UART_BASE @ physical diff --git a/arch/arm/mach-h720x/include/mach/debug-macro.S b/arch/arm/mach-h720x/include/mach/debug-macro.S index 6294a1344dda..a9ee8f0d48b7 100644 --- a/arch/arm/mach-h720x/include/mach/debug-macro.S +++ b/arch/arm/mach-h720x/include/mach/debug-macro.S @@ -14,7 +14,7 @@ .equ io_virt, IO_BASE .equ io_phys, IO_START - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? moveq \rx, #io_phys @ physical base address diff --git a/arch/arm/mach-integrator/include/mach/debug-macro.S b/arch/arm/mach-integrator/include/mach/debug-macro.S index d347d659ea30..87a6888ae011 100644 --- a/arch/arm/mach-integrator/include/mach/debug-macro.S +++ b/arch/arm/mach-integrator/include/mach/debug-macro.S @@ -11,7 +11,7 @@ * */ - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? moveq \rx, #0x16000000 @ physical base address diff --git a/arch/arm/mach-iop13xx/include/mach/debug-macro.S b/arch/arm/mach-iop13xx/include/mach/debug-macro.S index 9037d2e8557c..c9d6ba46963d 100644 --- a/arch/arm/mach-iop13xx/include/mach/debug-macro.S +++ b/arch/arm/mach-iop13xx/include/mach/debug-macro.S @@ -11,7 +11,7 @@ * published by the Free Software Foundation. */ - .macro addruart, rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ mmu enabled? moveq \rx, #0xff000000 @ physical diff --git a/arch/arm/mach-iop32x/include/mach/debug-macro.S b/arch/arm/mach-iop32x/include/mach/debug-macro.S index 58b01664ffba..736afe1edd1f 100644 --- a/arch/arm/mach-iop32x/include/mach/debug-macro.S +++ b/arch/arm/mach-iop32x/include/mach/debug-macro.S @@ -11,7 +11,7 @@ * published by the Free Software Foundation. */ - .macro addruart, rx + .macro addruart, rx, tmp mov \rx, #0xfe000000 @ physical as well as virtual orr \rx, \rx, #0x00800000 @ location of the UART .endm diff --git a/arch/arm/mach-iop33x/include/mach/debug-macro.S b/arch/arm/mach-iop33x/include/mach/debug-macro.S index a60c9ef05cc3..addb2da78422 100644 --- a/arch/arm/mach-iop33x/include/mach/debug-macro.S +++ b/arch/arm/mach-iop33x/include/mach/debug-macro.S @@ -11,7 +11,7 @@ * published by the Free Software Foundation. */ - .macro addruart, rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ mmu enabled? moveq \rx, #0xff000000 @ physical diff --git a/arch/arm/mach-ixp2000/include/mach/debug-macro.S b/arch/arm/mach-ixp2000/include/mach/debug-macro.S index 904ff56d2246..6a827681680f 100644 --- a/arch/arm/mach-ixp2000/include/mach/debug-macro.S +++ b/arch/arm/mach-ixp2000/include/mach/debug-macro.S @@ -11,7 +11,7 @@ * */ - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? moveq \rx, #0xc0000000 @ Physical base diff --git a/arch/arm/mach-ixp23xx/include/mach/debug-macro.S b/arch/arm/mach-ixp23xx/include/mach/debug-macro.S index 905db3188724..a82e375465e2 100644 --- a/arch/arm/mach-ixp23xx/include/mach/debug-macro.S +++ b/arch/arm/mach-ixp23xx/include/mach/debug-macro.S @@ -12,7 +12,7 @@ */ #include <mach/ixp23xx.h> - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ mmu enabled? ldreq \rx, =IXP23XX_PERIPHERAL_PHYS @ physical diff --git a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S index 7c6a6912acde..893873eb2a0d 100644 --- a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S +++ b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S @@ -10,7 +10,7 @@ * published by the Free Software Foundation. */ - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? moveq \rx, #0xc8000000 diff --git a/arch/arm/mach-kirkwood/include/mach/debug-macro.S b/arch/arm/mach-kirkwood/include/mach/debug-macro.S index a4a55c199d77..d0606774dea7 100644 --- a/arch/arm/mach-kirkwood/include/mach/debug-macro.S +++ b/arch/arm/mach-kirkwood/include/mach/debug-macro.S @@ -8,7 +8,7 @@ #include <mach/bridge-regs.h> - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? ldreq \rx, =KIRKWOOD_REGS_PHYS_BASE diff --git a/arch/arm/mach-ks8695/include/mach/debug-macro.S b/arch/arm/mach-ks8695/include/mach/debug-macro.S index 3782c3559497..cf2095da2372 100644 --- a/arch/arm/mach-ks8695/include/mach/debug-macro.S +++ b/arch/arm/mach-ks8695/include/mach/debug-macro.S @@ -14,7 +14,7 @@ #include <mach/hardware.h> #include <mach/regs-uart.h> - .macro addruart, rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? ldreq \rx, =KS8695_UART_PA @ physical base address diff --git a/arch/arm/mach-l7200/include/mach/debug-macro.S b/arch/arm/mach-l7200/include/mach/debug-macro.S index 34eed2a63e69..b69ed344c7c9 100644 --- a/arch/arm/mach-l7200/include/mach/debug-macro.S +++ b/arch/arm/mach-l7200/include/mach/debug-macro.S @@ -14,7 +14,7 @@ .equ io_virt, IO_BASE .equ io_phys, IO_START - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? moveq \rx, #io_phys @ physical base address diff --git a/arch/arm/mach-lh7a40x/include/mach/debug-macro.S b/arch/arm/mach-lh7a40x/include/mach/debug-macro.S index 85141ed5383d..c0dcbbba22ba 100644 --- a/arch/arm/mach-lh7a40x/include/mach/debug-macro.S +++ b/arch/arm/mach-lh7a40x/include/mach/debug-macro.S @@ -14,7 +14,7 @@ @ It is not known if this will be appropriate for every 40x @ board. - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? mov \rx, #0x00000700 @ offset from base diff --git a/arch/arm/mach-loki/include/mach/debug-macro.S b/arch/arm/mach-loki/include/mach/debug-macro.S index a8c20bd2f951..3136c913a92c 100644 --- a/arch/arm/mach-loki/include/mach/debug-macro.S +++ b/arch/arm/mach-loki/include/mach/debug-macro.S @@ -8,7 +8,7 @@ #include <mach/loki.h> - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? ldreq \rx, =LOKI_REGS_PHYS_BASE diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S index a850f87de51d..76deff238e1c 100644 --- a/arch/arm/mach-mmp/include/mach/debug-macro.S +++ b/arch/arm/mach-mmp/include/mach/debug-macro.S @@ -11,7 +11,7 @@ #include <mach/addr-map.h> - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? ldreq \rx, =APB_PHYS_BASE @ physical diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S index d48747ebcd3d..528750f307e9 100644 --- a/arch/arm/mach-msm/include/mach/debug-macro.S +++ b/arch/arm/mach-msm/include/mach/debug-macro.S @@ -20,7 +20,7 @@ #include <mach/msm_iomap.h> #ifdef CONFIG_MSM_DEBUG_UART - .macro addruart,rx + .macro addruart, rx, tmp @ see if the MMU is enabled and select appropriate base address mrc p15, 0, \rx, c1, c0 tst \rx, #1 @@ -40,7 +40,7 @@ beq 1001b .endm #else - .macro addruart,rx + .macro addruart, rx, tmp .endm .macro senduart,rd,rx diff --git a/arch/arm/mach-mv78xx0/include/mach/debug-macro.S b/arch/arm/mach-mv78xx0/include/mach/debug-macro.S index a06442fbd341..cd81689c4621 100644 --- a/arch/arm/mach-mv78xx0/include/mach/debug-macro.S +++ b/arch/arm/mach-mv78xx0/include/mach/debug-macro.S @@ -8,7 +8,7 @@ #include <mach/mv78xx0.h> - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? ldreq \rx, =MV78XX0_REGS_PHYS_BASE diff --git a/arch/arm/mach-netx/include/mach/debug-macro.S b/arch/arm/mach-netx/include/mach/debug-macro.S index 11b9d5b46390..e96339e71d88 100644 --- a/arch/arm/mach-netx/include/mach/debug-macro.S +++ b/arch/arm/mach-netx/include/mach/debug-macro.S @@ -13,7 +13,7 @@ #include "hardware.h" - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? moveq \rx, #0x00100000 @ physical diff --git a/arch/arm/mach-nomadik/include/mach/debug-macro.S b/arch/arm/mach-nomadik/include/mach/debug-macro.S index e876990e1569..4f92acfba954 100644 --- a/arch/arm/mach-nomadik/include/mach/debug-macro.S +++ b/arch/arm/mach-nomadik/include/mach/debug-macro.S @@ -10,7 +10,7 @@ * */ - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? moveq \rx, #0x10000000 @ physical base address diff --git a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S b/arch/arm/mach-ns9xxx/include/mach/debug-macro.S index c9530fba00aa..0859336a8e6d 100644 --- a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S +++ b/arch/arm/mach-ns9xxx/include/mach/debug-macro.S @@ -11,7 +11,7 @@ #include <mach/regs-board-a9m9750dev.h> - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 ldreq \rx, =NS9XXX_CSxSTAT_PHYS(0) diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index 9ce17f13d3f1..b6a537c875b8 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -3,7 +3,7 @@ # # Common support -obj-y := io.o id.o sram.o irq.o mux.o serial.o devices.o +obj-y := io.o id.o sram.o irq.o mux.o flash.o serial.o devices.o obj-y += clock.o clock_data.o opp_data.o obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c index 7e70c3c08da6..096f2ed102cb 100644 --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c @@ -18,18 +18,19 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> #include <linux/input.h> #include <linux/smc91x.h> #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <asm/mach/flash.h> #include <asm/mach/map.h> #include <plat/tc.h> #include <mach/gpio.h> #include <plat/mux.h> +#include <plat/flash.h> #include <plat/fpga.h> #include <plat/keypad.h> #include <plat/common.h> @@ -150,9 +151,9 @@ static struct mtd_partition nor_partitions[] = { }, }; -static struct flash_platform_data nor_data = { - .map_name = "cfi_probe", +static struct physmap_flash_data nor_data = { .width = 2, + .set_vpp = omap1_set_vpp, .parts = nor_partitions, .nr_parts = ARRAY_SIZE(nor_partitions), }; @@ -164,7 +165,7 @@ static struct resource nor_resource = { }; static struct platform_device nor_device = { - .name = "omapflash", + .name = "physmap-flash", .id = 0, .dev = { .platform_data = &nor_data, diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index fa7cecea19f9..d1100e4f65ac 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -26,6 +26,7 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> #include <linux/input.h> #include <linux/i2c/tps65010.h> #include <linux/smc91x.h> @@ -35,7 +36,6 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <asm/mach/flash.h> #include <asm/mach/map.h> #include <plat/mux.h> @@ -45,6 +45,7 @@ #include <plat/usb.h> #include <plat/keypad.h> #include <plat/common.h> +#include <plat/flash.h> #include "board-h2.h" @@ -121,9 +122,9 @@ static struct mtd_partition h2_nor_partitions[] = { } }; -static struct flash_platform_data h2_nor_data = { - .map_name = "cfi_probe", +static struct physmap_flash_data h2_nor_data = { .width = 2, + .set_vpp = omap1_set_vpp, .parts = h2_nor_partitions, .nr_parts = ARRAY_SIZE(h2_nor_partitions), }; @@ -134,7 +135,7 @@ static struct resource h2_nor_resource = { }; static struct platform_device h2_nor_device = { - .name = "omapflash", + .name = "physmap-flash", .id = 0, .dev = { .platform_data = &h2_nor_data, diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 6a7f9c391cf1..a53ab8297d25 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -25,6 +25,7 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> #include <linux/input.h> #include <linux/spi/spi.h> #include <linux/i2c/tps65010.h> @@ -37,7 +38,6 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <asm/mach/flash.h> #include <asm/mach/map.h> #include <mach/irqs.h> @@ -47,6 +47,7 @@ #include <plat/keypad.h> #include <plat/dma.h> #include <plat/common.h> +#include <plat/flash.h> #include "board-h3.h" @@ -126,9 +127,9 @@ static struct mtd_partition nor_partitions[] = { } }; -static struct flash_platform_data nor_data = { - .map_name = "cfi_probe", +static struct physmap_flash_data nor_data = { .width = 2, + .set_vpp = omap1_set_vpp, .parts = nor_partitions, .nr_parts = ARRAY_SIZE(nor_partitions), }; @@ -139,7 +140,7 @@ static struct resource nor_resource = { }; static struct platform_device nor_device = { - .name = "omapflash", + .name = "physmap-flash", .id = 0, .dev = { .platform_data = &nor_data, diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index 2133b006f6a3..5d12fd35681b 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c @@ -22,16 +22,17 @@ #include <linux/delay.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> #include <linux/input.h> #include <linux/smc91x.h> #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <asm/mach/flash.h> #include <asm/mach/map.h> #include <plat/mux.h> +#include <plat/flash.h> #include <plat/fpga.h> #include <mach/gpio.h> #include <plat/tc.h> @@ -94,9 +95,9 @@ static struct mtd_partition innovator_partitions[] = { } }; -static struct flash_platform_data innovator_flash_data = { - .map_name = "cfi_probe", +static struct physmap_flash_data innovator_flash_data = { .width = 2, + .set_vpp = omap1_set_vpp, .parts = innovator_partitions, .nr_parts = ARRAY_SIZE(innovator_partitions), }; @@ -108,7 +109,7 @@ static struct resource innovator_flash_resource = { }; static struct platform_device innovator_flash_device = { - .name = "omapflash", + .name = "physmap-flash", .id = 0, .dev = { .platform_data = &innovator_flash_data, diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index ccea4f448e9a..80d862001def 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -37,6 +37,7 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> #include <linux/i2c/tps65010.h> @@ -46,8 +47,8 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <asm/mach/flash.h> +#include <plat/flash.h> #include <plat/usb.h> #include <plat/mux.h> #include <plat/tc.h> @@ -94,9 +95,9 @@ static struct mtd_partition osk_partitions[] = { } }; -static struct flash_platform_data osk_flash_data = { - .map_name = "cfi_probe", +static struct physmap_flash_data osk_flash_data = { .width = 2, + .set_vpp = omap1_set_vpp, .parts = osk_partitions, .nr_parts = ARRAY_SIZE(osk_partitions), }; @@ -107,7 +108,7 @@ static struct resource osk_flash_resource = { }; static struct platform_device osk5912_flash_device = { - .name = "omapflash", + .name = "physmap-flash", .id = 0, .dev = { .platform_data = &osk_flash_data, diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 9fe887262bdf..569b4c9085cd 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c @@ -23,6 +23,7 @@ #include <linux/platform_device.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> #include <linux/spi/spi.h> #include <linux/interrupt.h> #include <linux/apm-emulation.h> @@ -31,9 +32,9 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <asm/mach/flash.h> #include <mach/gpio.h> +#include <plat/flash.h> #include <plat/mux.h> #include <plat/usb.h> #include <plat/tc.h> @@ -126,9 +127,9 @@ static struct mtd_partition palmte_rom_partitions[] = { }, }; -static struct flash_platform_data palmte_rom_data = { - .map_name = "map_rom", +static struct physmap_flash_data palmte_rom_data = { .width = 2, + .set_vpp = omap1_set_vpp, .parts = palmte_rom_partitions, .nr_parts = ARRAY_SIZE(palmte_rom_partitions), }; @@ -140,7 +141,7 @@ static struct resource palmte_rom_resource = { }; static struct platform_device palmte_rom_device = { - .name = "omapflash", + .name = "physmap-flash", .id = -1, .dev = { .platform_data = &palmte_rom_data, diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index af068e3e0fe7..6ad49a2cc1a0 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c @@ -21,16 +21,17 @@ #include <linux/interrupt.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> #include <linux/leds.h> #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <asm/mach/flash.h> #include <plat/led.h> #include <mach/gpio.h> +#include <plat/flash.h> #include <plat/mux.h> #include <plat/usb.h> #include <plat/dma.h> @@ -104,9 +105,9 @@ static struct mtd_partition palmtt_partitions[] = { } }; -static struct flash_platform_data palmtt_flash_data = { - .map_name = "cfi_probe", +static struct physmap_flash_data palmtt_flash_data = { .width = 2, + .set_vpp = omap1_set_vpp, .parts = palmtt_partitions, .nr_parts = ARRAY_SIZE(palmtt_partitions), }; @@ -118,7 +119,7 @@ static struct resource palmtt_flash_resource = { }; static struct platform_device palmtt_flash_device = { - .name = "omapflash", + .name = "physmap-flash", .id = 0, .dev = { .platform_data = &palmtt_flash_data, diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index c7a3b6f36500..6641de9257ef 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c @@ -25,14 +25,15 @@ #include <linux/interrupt.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <asm/mach/flash.h> #include <mach/gpio.h> +#include <plat/flash.h> #include <plat/mux.h> #include <plat/usb.h> #include <plat/dma.h> @@ -126,10 +127,9 @@ static struct mtd_partition palmz71_rom_partitions[] = { }, }; -static struct flash_platform_data palmz71_rom_data = { - .map_name = "map_rom", - .name = "onboardrom", +static struct physmap_flash_data palmz71_rom_data = { .width = 2, + .set_vpp = omap1_set_vpp, .parts = palmz71_rom_partitions, .nr_parts = ARRAY_SIZE(palmz71_rom_partitions), }; @@ -141,7 +141,7 @@ static struct resource palmz71_rom_resource = { }; static struct platform_device palmz71_rom_device = { - .name = "omapflash", + .name = "physmap-flash", .id = -1, .dev = { .platform_data = &palmz71_rom_data, diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index 1387a4f15da9..e854d5741c88 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c @@ -18,19 +18,20 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> #include <linux/input.h> #include <linux/smc91x.h> #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <asm/mach/flash.h> #include <asm/mach/map.h> #include <plat/tc.h> #include <mach/gpio.h> #include <plat/mux.h> #include <plat/fpga.h> +#include <plat/flash.h> #include <plat/keypad.h> #include <plat/common.h> #include <plat/board.h> @@ -117,9 +118,9 @@ static struct mtd_partition nor_partitions[] = { }, }; -static struct flash_platform_data nor_data = { - .map_name = "cfi_probe", +static struct physmap_flash_data nor_data = { .width = 2, + .set_vpp = omap1_set_vpp, .parts = nor_partitions, .nr_parts = ARRAY_SIZE(nor_partitions), }; @@ -131,7 +132,7 @@ static struct resource nor_resource = { }; static struct platform_device nor_device = { - .name = "omapflash", + .name = "physmap-flash", .id = 0, .dev = { .platform_data = &nor_data, diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index 7a97fac83d8d..2fb1e5f8e2ec 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c @@ -22,6 +22,7 @@ #include <linux/notifier.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> #include <linux/types.h> #include <linux/i2c.h> #include <linux/errno.h> @@ -29,10 +30,10 @@ #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <asm/mach/flash.h> #include <asm/mach/map.h> #include <mach/gpio.h> +#include <plat/flash.h> #include <plat/mux.h> #include <plat/dma.h> #include <plat/irda.h> @@ -287,9 +288,9 @@ static struct mtd_partition sx1_partitions[] = { } }; -static struct flash_platform_data sx1_flash_data = { - .map_name = "cfi_probe", +static struct physmap_flash_data sx1_flash_data = { .width = 2, + .set_vpp = omap1_set_vpp, .parts = sx1_partitions, .nr_parts = ARRAY_SIZE(sx1_partitions), }; @@ -310,7 +311,7 @@ static struct resource sx1_old_flash_resource[] = { }; static struct platform_device sx1_flash_device = { - .name = "omapflash", + .name = "physmap-flash", .id = 0, .dev = { .platform_data = &sx1_flash_data, @@ -327,7 +328,7 @@ static struct resource sx1_new_flash_resource = { }; static struct platform_device sx1_flash_device = { - .name = "omapflash", + .name = "physmap-flash", .id = 0, .dev = { .platform_data = &sx1_flash_data, diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index 169183537997..87b9436fe7c0 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c @@ -18,6 +18,7 @@ #include <linux/irq.h> #include <linux/init.h> #include <linux/kernel.h> +#include <linux/mtd/physmap.h> #include <linux/notifier.h> #include <linux/reboot.h> #include <linux/serial_8250.h> @@ -27,11 +28,11 @@ #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <asm/mach/flash.h> #include <asm/mach/map.h> #include <plat/common.h> #include <mach/gpio.h> +#include <plat/flash.h> #include <plat/mux.h> #include <plat/tc.h> #include <plat/usb.h> @@ -86,9 +87,9 @@ static int __init ext_uart_init(void) } arch_initcall(ext_uart_init); -static struct flash_platform_data voiceblue_flash_data = { - .map_name = "cfi_probe", +static struct physmap_flash_data voiceblue_flash_data = { .width = 2, + .set_vpp = omap1_set_vpp, }; static struct resource voiceblue_flash_resource = { @@ -98,7 +99,7 @@ static struct resource voiceblue_flash_resource = { }; static struct platform_device voiceblue_flash_device = { - .name = "omapflash", + .name = "physmap-flash", .id = 0, .dev = { .platform_data = &voiceblue_flash_data, diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 04f1d29cba2c..3e052f6532b1 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -52,12 +52,6 @@ const struct clkops clkops_dummy = { .disable = clk_omap1_dummy_disable, }; -/* XXX can be replaced with a fixed_divisor_recalc */ -unsigned long omap1_watchdog_recalc(struct clk *clk) -{ - return clk->parent->rate / 14; -} - unsigned long omap1_uart_recalc(struct clk *clk) { unsigned int val = __raw_readl(clk->enable_reg); diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index 65e7b5b85d83..edefb3440d30 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -149,7 +149,8 @@ static struct arm_idlect1_clk armwdt_ck = { .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_WDTCK, - .recalc = &omap1_watchdog_recalc, + .fixed_div = 14, + .recalc = &omap_fixed_divisor_recalc, }, .idlect_shift = 0, }; diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index a2d07aa75c9e..379100c17639 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -73,7 +73,7 @@ static inline void omap_init_rtc(void) {} # define INT_DSP_MAILBOX1 INT_1610_DSP_MAILBOX1 #endif -#define OMAP1_MBOX_BASE OMAP1_IO_ADDRESS(OMAP16XX_MAILBOX_BASE) +#define OMAP1_MBOX_BASE OMAP16XX_MAILBOX_BASE static struct resource mbox_resources[] = { { diff --git a/arch/arm/mach-omap1/flash.c b/arch/arm/mach-omap1/flash.c new file mode 100644 index 000000000000..0b07a78eeaa7 --- /dev/null +++ b/arch/arm/mach-omap1/flash.c @@ -0,0 +1,33 @@ +/* + * Flash support for OMAP1 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/mtd/mtd.h> +#include <linux/mtd/map.h> + +#include <plat/io.h> +#include <plat/tc.h> + +void omap1_set_vpp(struct map_info *map, int enable) +{ + static int count; + u32 l; + + if (enable) { + if (count++ == 0) { + l = omap_readl(EMIFS_CONFIG); + l |= OMAP_EMIFS_CONFIG_WP; + omap_writel(l, EMIFS_CONFIG); + } + } else { + if (count && (--count == 0)) { + l = omap_readl(EMIFS_CONFIG); + l &= ~OMAP_EMIFS_CONFIG_WP; + omap_writel(l, EMIFS_CONFIG); + } + } +} diff --git a/arch/arm/mach-omap1/include/mach/debug-macro.S b/arch/arm/mach-omap1/include/mach/debug-macro.S index aedb746fc33c..b6d9584544b4 100644 --- a/arch/arm/mach-omap1/include/mach/debug-macro.S +++ b/arch/arm/mach-omap1/include/mach/debug-macro.S @@ -11,18 +11,80 @@ * */ - .macro addruart,rx +#include <linux/serial_reg.h> + +#include <plat/serial.h> + + .pushsection .data +omap_uart_phys: .word 0x0 +omap_uart_virt: .word 0x0 + .popsection + + /* + * Note that this code won't work if the bootloader passes + * a wrong machine ID number in r1. To debug, just hardcode + * the desired UART phys and virt addresses temporarily into + * the omap_uart_phys and omap_uart_virt above. + */ + .macro addruart, rx, tmp + + /* Use omap_uart_phys/virt if already configured */ +9: mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =omap_uart_phys @ physical base address + ldrne \rx, =omap_uart_virt @ virtual base + ldr \rx, [\rx, #0] + cmp \rx, #0 @ is port configured? + bne 99f @ already configured + + /* Check 7XX UART1 scratchpad register for uart to use */ + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + moveq \rx, #0xff000000 @ physical base address + movne \rx, #0xfe000000 @ virtual base + orr \rx, \rx, #0x00fb0000 @ OMAP1UART1 + ldrb \rx, [\rx, #(UART_SCR << OMAP7XX_PORT_SHIFT)] + cmp \rx, #0 @ anything in 7XX scratchpad? + bne 10f @ found 7XX uart + + /* Check 15xx/16xx UART1 scratchpad register for uart to use */ mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? moveq \rx, #0xff000000 @ physical base address movne \rx, #0xfe000000 @ virtual base - orr \rx, \rx, #0x00fb0000 -#ifdef CONFIG_OMAP_LL_DEBUG_UART3 - orr \rx, \rx, #0x00009000 @ UART 3 -#endif -#if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3) - orr \rx, \rx, #0x00000800 @ UART 2 & 3 -#endif + orr \rx, \rx, #0x00fb0000 @ OMAP1UART1 + ldrb \rx, [\rx, #(UART_SCR << OMAP_PORT_SHIFT)] + + /* Select the UART to use based on the UART1 scratchpad value */ +10: cmp \rx, #0 @ no port configured? + beq 11f @ if none, try to use UART1 + cmp \rx, #OMAP1UART1 + beq 11f @ configure OMAP1UART1 + cmp \rx, #OMAP1UART2 + beq 12f @ configure OMAP1UART2 + cmp \rx, #OMAP1UART3 + beq 13f @ configure OMAP2UART3 + + /* Configure the UART offset from the phys/virt base */ +11: mov \rx, #0x00fb0000 @ OMAP1UART1 + b 98f +12: mov \rx, #0x00fb0000 @ OMAP1UART1 + orr \rx, \rx, #0x00000800 @ OMAP1UART2 + b 98f +13: mov \rx, #0x00fb0000 @ OMAP1UART1 + orr \rx, \rx, #0x00000800 @ OMAP1UART2 + orr \rx, \rx, #0x00009000 @ OMAP1UART3 + + /* Store both phys and virt address for the uart */ +98: add \rx, \rx, #0xff000000 @ phys base + ldr \tmp, =omap_uart_phys + str \rx, [\tmp, #0] + sub \rx, \rx, #0xff000000 @ phys base + add \rx, \rx, #0xfe000000 @ virt base + ldr \tmp, =omap_uart_virt + str \rx, [\tmp, #0] + b 9b +99: .endm .macro senduart,rd,rx @@ -30,13 +92,13 @@ .endm .macro busyuart,rd,rx -1001: ldrb \rd, [\rx, #(0x5 << 2)] @ OMAP-1510 and friends - and \rd, \rd, #0x60 - teq \rd, #0x60 +1001: ldrb \rd, [\rx, #(UART_LSR << OMAP_PORT_SHIFT)] + and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE) + teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE) beq 1002f - ldrb \rd, [\rx, #(0x5 << 0)] @ OMAP-730 only - and \rd, \rd, #0x60 - teq \rd, #0x60 + ldrb \rd, [\rx, #(UART_LSR << OMAP7XX_PORT_SHIFT)] + and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE) + teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE) bne 1001b 1002: .endm diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c index caf889aaa248..4f5b3da3d559 100644 --- a/arch/arm/mach-omap1/mailbox.c +++ b/arch/arm/mach-omap1/mailbox.c @@ -146,7 +146,6 @@ EXPORT_SYMBOL(mbox_dsp_info); static int __devinit omap1_mbox_probe(struct platform_device *pdev) { struct resource *res; - int ret = 0; if (pdev->num_resources != 2) { dev_err(&pdev->dev, "invalid number of resources: %d\n", @@ -160,12 +159,18 @@ static int __devinit omap1_mbox_probe(struct platform_device *pdev) dev_err(&pdev->dev, "invalid mem resource\n"); return -ENODEV; } - mbox_base = res->start; + + mbox_base = ioremap(res->start, resource_size(res)); + if (!mbox_base) { + dev_err(&pdev->dev, "ioremap failed\n"); + return -ENODEV; + } /* DSP IRQ */ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); if (unlikely(!res)) { dev_err(&pdev->dev, "invalid irq resource\n"); + iounmap(mbox_base); return -ENODEV; } mbox_dsp_info.irq = res->start; diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c index 6bddce104ee9..f9a5cf750b59 100644 --- a/arch/arm/mach-omap1/mcbsp.c +++ b/arch/arm/mach-omap1/mcbsp.c @@ -99,9 +99,11 @@ static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = { }, }; #define OMAP7XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap7xx_mcbsp_pdata) +#define OMAP7XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) #else #define omap7xx_mcbsp_pdata NULL #define OMAP7XX_MCBSP_PDATA_SZ 0 +#define OMAP7XX_MCBSP_REG_NUM 0 #endif #ifdef CONFIG_ARCH_OMAP15XX @@ -132,9 +134,11 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = { }, }; #define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata) +#define OMAP15XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) #else #define omap15xx_mcbsp_pdata NULL #define OMAP15XX_MCBSP_PDATA_SZ 0 +#define OMAP15XX_MCBSP_REG_NUM 0 #endif #ifdef CONFIG_ARCH_OMAP16XX @@ -165,19 +169,25 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = { }, }; #define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata) +#define OMAP16XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) #else #define omap16xx_mcbsp_pdata NULL #define OMAP16XX_MCBSP_PDATA_SZ 0 +#define OMAP16XX_MCBSP_REG_NUM 0 #endif int __init omap1_mcbsp_init(void) { - if (cpu_is_omap7xx()) + if (cpu_is_omap7xx()) { omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ; - if (cpu_is_omap15xx()) + omap_mcbsp_cache_size = OMAP7XX_MCBSP_REG_NUM * sizeof(u16); + } else if (cpu_is_omap15xx()) { omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ; - if (cpu_is_omap16xx()) + omap_mcbsp_cache_size = OMAP15XX_MCBSP_REG_NUM * sizeof(u16); + } else if (cpu_is_omap16xx()) { omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ; + omap_mcbsp_cache_size = OMAP16XX_MCBSP_REG_NUM * sizeof(u16); + } mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), GFP_KERNEL); diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c index 6e5207c81cf4..349de90194e3 100644 --- a/arch/arm/mach-omap1/serial.c +++ b/arch/arm/mach-omap1/serial.c @@ -64,7 +64,7 @@ static void __init omap_serial_reset(struct plat_serial8250_port *p) static struct plat_serial8250_port serial_platform_data[] = { { - .mapbase = OMAP_UART1_BASE, + .mapbase = OMAP1_UART1_BASE, .irq = INT_UART1, .flags = UPF_BOOT_AUTOCONF, .iotype = UPIO_MEM, @@ -72,7 +72,7 @@ static struct plat_serial8250_port serial_platform_data[] = { .uartclk = OMAP16XX_BASE_BAUD * 16, }, { - .mapbase = OMAP_UART2_BASE, + .mapbase = OMAP1_UART2_BASE, .irq = INT_UART2, .flags = UPF_BOOT_AUTOCONF, .iotype = UPIO_MEM, @@ -80,7 +80,7 @@ static struct plat_serial8250_port serial_platform_data[] = { .uartclk = OMAP16XX_BASE_BAUD * 16, }, { - .mapbase = OMAP_UART3_BASE, + .mapbase = OMAP1_UART3_BASE, .irq = INT_UART3, .flags = UPF_BOOT_AUTOCONF, .iotype = UPIO_MEM, diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 606bf04f51b6..f90b225ef888 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -1,28 +1,19 @@ comment "OMAP Core Type" depends on ARCH_OMAP2 -config ARCH_OMAP24XX - bool "OMAP24xx Based System" - depends on ARCH_OMAP2 - config ARCH_OMAP2420 bool "OMAP2420 support" - depends on ARCH_OMAP24XX + depends on ARCH_OMAP2 select OMAP_DM_TIMER select ARCH_OMAP_OTG config ARCH_OMAP2430 bool "OMAP2430 support" - depends on ARCH_OMAP24XX - -config ARCH_OMAP34XX - bool "OMAP34xx Based System" - depends on ARCH_OMAP3 - select USB_ARCH_HAS_EHCI + depends on ARCH_OMAP2 config ARCH_OMAP3430 bool "OMAP3430 support" - depends on ARCH_OMAP3 && ARCH_OMAP34XX + depends on ARCH_OMAP3 select ARCH_OMAP_OTG config OMAP_PACKAGE_CBC @@ -38,11 +29,11 @@ config OMAP_PACKAGE_CBP bool comment "OMAP Board Type" - depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4 + depends on ARCH_OMAP2PLUS config MACH_OMAP_GENERIC bool "Generic OMAP board" - depends on ARCH_OMAP2 && ARCH_OMAP24XX + depends on ARCH_OMAP2 config MACH_OMAP2_TUSB6010 bool @@ -51,55 +42,55 @@ config MACH_OMAP2_TUSB6010 config MACH_OMAP_H4 bool "OMAP 2420 H4 board" - depends on ARCH_OMAP2 && ARCH_OMAP24XX + depends on ARCH_OMAP2 select OMAP_DEBUG_DEVICES config MACH_OMAP_APOLLON bool "OMAP 2420 Apollon board" - depends on ARCH_OMAP2 && ARCH_OMAP24XX + depends on ARCH_OMAP2 config MACH_OMAP_2430SDP bool "OMAP 2430 SDP board" - depends on ARCH_OMAP2 && ARCH_OMAP24XX + depends on ARCH_OMAP2 config MACH_OMAP3_BEAGLE bool "OMAP3 BEAGLE board" - depends on ARCH_OMAP3 && ARCH_OMAP34XX + depends on ARCH_OMAP3 select OMAP_PACKAGE_CBB config MACH_OMAP_LDP bool "OMAP3 LDP board" - depends on ARCH_OMAP3 && ARCH_OMAP34XX + depends on ARCH_OMAP3 select OMAP_PACKAGE_CBB config MACH_OVERO bool "Gumstix Overo board" - depends on ARCH_OMAP3 && ARCH_OMAP34XX + depends on ARCH_OMAP3 select OMAP_PACKAGE_CBB config MACH_OMAP3EVM bool "OMAP 3530 EVM board" - depends on ARCH_OMAP3 && ARCH_OMAP34XX + depends on ARCH_OMAP3 select OMAP_PACKAGE_CBB config MACH_OMAP3517EVM bool "OMAP3517/ AM3517 EVM board" - depends on ARCH_OMAP3 && ARCH_OMAP34XX + depends on ARCH_OMAP3 select OMAP_PACKAGE_CBB config MACH_OMAP3_PANDORA bool "OMAP3 Pandora" - depends on ARCH_OMAP3 && ARCH_OMAP34XX + depends on ARCH_OMAP3 select OMAP_PACKAGE_CBB config MACH_OMAP3_TOUCHBOOK bool "OMAP3 Touch Book" - depends on ARCH_OMAP3 && ARCH_OMAP34XX + depends on ARCH_OMAP3 select BACKLIGHT_CLASS_DEVICE config MACH_OMAP_3430SDP bool "OMAP 3430 SDP board" - depends on ARCH_OMAP3 && ARCH_OMAP34XX + depends on ARCH_OMAP3 select OMAP_PACKAGE_CBB config MACH_NOKIA_N800 @@ -120,33 +111,33 @@ config MACH_NOKIA_N8X0 config MACH_NOKIA_RX51 bool "Nokia RX-51 board" - depends on ARCH_OMAP3 && ARCH_OMAP34XX + depends on ARCH_OMAP3 select OMAP_PACKAGE_CBB config MACH_OMAP_ZOOM2 bool "OMAP3 Zoom2 board" - depends on ARCH_OMAP3 && ARCH_OMAP34XX + depends on ARCH_OMAP3 select OMAP_PACKAGE_CBB config MACH_OMAP_ZOOM3 bool "OMAP3630 Zoom3 board" - depends on ARCH_OMAP3 && ARCH_OMAP34XX + depends on ARCH_OMAP3 select OMAP_PACKAGE_CBP config MACH_CM_T35 bool "CompuLab CM-T35 module" - depends on ARCH_OMAP3 && ARCH_OMAP34XX + depends on ARCH_OMAP3 select OMAP_PACKAGE_CUS select OMAP_MUX config MACH_IGEP0020 bool "IGEP0020" - depends on ARCH_OMAP3 && ARCH_OMAP34XX + depends on ARCH_OMAP3 select OMAP_PACKAGE_CBB config MACH_OMAP_3630SDP bool "OMAP3630 SDP board" - depends on ARCH_OMAP3 && ARCH_OMAP34XX + depends on ARCH_OMAP3 select OMAP_PACKAGE_CBP config MACH_OMAP_4430SDP @@ -162,7 +153,7 @@ config OMAP3_EMU config OMAP3_SDRC_AC_TIMING bool "Enable SDRC AC timing register changes" - depends on ARCH_OMAP3 && ARCH_OMAP34XX + depends on ARCH_OMAP3 default n help If you know that none of your system initiators will attempt to diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index b32678b848bc..dfc49a0c6927 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -6,14 +6,22 @@ obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o omap-2-3-common = irq.o sdrc.o omap_hwmod.o -omap-3-4-common = dpll.o +omap-3-4-common = dpll3xxx.o prcm-common = prcm.o powerdomain.o -clock-common = clock.o clock_common_data.o clockdomain.o - -obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common) +clock-common = clock.o clock_common_data.o \ + clockdomain.o clkt_dpll.o \ + clkt_clksel.o +clock-omap2xxx = clkt2xxx_dpllcore.o \ + clkt2xxx_virt_prcm_set.o \ + clkt2xxx_apll.o clkt2xxx_osc.o \ + clkt2xxx_sys.o +clock-omap3xxx = clkt34xx_dpll3m2.o + +obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common) \ + $(clock-omap2xxx) obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) \ - $(omap-3-4-common) -obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) prcm.o clock.o + $(omap-3-4-common) $(clock-omap3xxx) +obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) $(prcm-common) $(clock-common) obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o @@ -26,6 +34,10 @@ obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o +AFLAGS_sram242x.o :=-Wa,-march=armv6 +AFLAGS_sram243x.o :=-Wa,-march=armv6 +AFLAGS_sram34xx.o :=-Wa,-march=armv7-a + # Pin multiplexing obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o @@ -36,9 +48,13 @@ obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o # Power Management ifeq ($(CONFIG_PM),y) obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o -obj-$(CONFIG_ARCH_OMAP24XX) += sleep24xx.o +obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o + +AFLAGS_sleep24xx.o :=-Wa,-march=armv6 +AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a + endif # PRCM @@ -71,42 +87,43 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y) obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o \ - mmc-twl4030.o + hsmmc.o obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o \ - mmc-twl4030.o + hsmmc.o obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o \ - mmc-twl4030.o + hsmmc.o obj-$(CONFIG_MACH_OVERO) += board-overo.o \ - mmc-twl4030.o + hsmmc.o obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o \ - mmc-twl4030.o + hsmmc.o obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o \ - mmc-twl4030.o + hsmmc.o obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o \ - mmc-twl4030.o + hsmmc.o \ + board-sdp-flash.o obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ board-rx51-sdram.o \ board-rx51-peripherals.o \ - mmc-twl4030.o + hsmmc.o obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom2.o \ board-zoom-peripherals.o \ - mmc-twl4030.o \ + hsmmc.o \ board-zoom-debugboard.o obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom3.o \ board-zoom-peripherals.o \ - mmc-twl4030.o \ + hsmmc.o \ board-zoom-debugboard.o obj-$(CONFIG_MACH_OMAP_3630SDP) += board-3630sdp.o \ board-zoom-peripherals.o \ - mmc-twl4030.o + hsmmc.o obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o \ - mmc-twl4030.o + hsmmc.o obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o \ - mmc-twl4030.o + hsmmc.o obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ - mmc-twl4030.o + hsmmc.o obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o @@ -119,5 +136,8 @@ obj-y += usb-ehci.o onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o obj-y += $(onenand-m) $(onenand-y) +nand-$(CONFIG_MTD_NAND_OMAP2) := gpmc-nand.o +obj-y += $(nand-m) $(nand-y) + smc91x-$(CONFIG_SMC91X) := gpmc-smc91x.o obj-y += $(smc91x-m) $(smc91x-y) diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index e508904fb67e..d6f55ef9059d 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -18,6 +18,7 @@ #include <linux/platform_device.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> #include <linux/delay.h> #include <linux/i2c/twl.h> #include <linux/err.h> @@ -28,7 +29,6 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <asm/mach/flash.h> #include <mach/gpio.h> #include <plat/mux.h> @@ -38,7 +38,7 @@ #include <plat/usb.h> #include <plat/gpmc-smc91x.h> -#include "mmc-twl4030.h" +#include "hsmmc.h" #define SDP2430_CS0_BASE 0x04000000 #define SECONDARY_LCD_GPIO 147 @@ -74,8 +74,7 @@ static struct mtd_partition sdp2430_partitions[] = { } }; -static struct flash_platform_data sdp2430_flash_data = { - .map_name = "cfi_probe", +static struct physmap_flash_data sdp2430_flash_data = { .width = 2, .parts = sdp2430_partitions, .nr_parts = ARRAY_SIZE(sdp2430_partitions), @@ -88,7 +87,7 @@ static struct resource sdp2430_flash_resource = { }; static struct platform_device sdp2430_flash_device = { - .name = "omapflash", + .name = "physmap-flash", .id = 0, .dev = { .platform_data = &sdp2430_flash_data, @@ -183,7 +182,7 @@ static int __init omap2430_i2c_init(void) return 0; } -static struct twl4030_hsmmc_info mmc[] __initdata = { +static struct omap2_hsmmc_info mmc[] __initdata = { { .mmc = 1, .wires = 4, @@ -202,7 +201,7 @@ static void __init omap_2430sdp_init(void) platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); omap_serial_init(); - twl4030_mmc_init(mmc); + omap2_hsmmc_init(mmc); usb_musb_init(); board_smc91x_init(); @@ -215,7 +214,7 @@ static void __init omap_2430sdp_init(void) static void __init omap_2430sdp_map_io(void) { omap2_set_globals_243x(); - omap2_map_common_io(); + omap243x_map_common_io(); } MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board") diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index c90b0d0b1927..5adef517a2b3 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -41,9 +41,11 @@ #include <plat/control.h> #include <plat/gpmc-smc91x.h> +#include <mach/board-sdp.h> + #include "mux.h" #include "sdram-qimonda-hyb18m512160af-6.h" -#include "mmc-twl4030.h" +#include "hsmmc.h" #define CONFIG_DISABLE_HFCLK 1 @@ -326,7 +328,7 @@ static struct twl4030_bci_platform_data sdp3430_bci_data = { .tblsize = ARRAY_SIZE(sdp3430_batt_table), }; -static struct twl4030_hsmmc_info mmc[] = { +static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, /* 8 bits (default) requires S6.3 == ON, @@ -363,7 +365,7 @@ static int sdp3430_twl_gpio_setup(struct device *dev, */ mmc[0].gpio_cd = gpio + 0; mmc[1].gpio_cd = gpio + 1; - twl4030_mmc_init(mmc); + omap2_hsmmc_init(mmc); /* link regulators to MMC adapters ... we "know" the * regulators will be set up only *after* we return. @@ -650,6 +652,114 @@ static struct omap_board_mux board_mux[] __initdata = { #define board_mux NULL #endif +static struct mtd_partition sdp_nor_partitions[] = { + /* bootloader (U-Boot, etc) in first sector */ + { + .name = "Bootloader-NOR", + .offset = 0, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + /* bootloader params in the next sector */ + { + .name = "Params-NOR", + .offset = MTDPART_OFS_APPEND, + .size = SZ_256K, + .mask_flags = 0, + }, + /* kernel */ + { + .name = "Kernel-NOR", + .offset = MTDPART_OFS_APPEND, + .size = SZ_2M, + .mask_flags = 0 + }, + /* file system */ + { + .name = "Filesystem-NOR", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0 + } +}; + +static struct mtd_partition sdp_onenand_partitions[] = { + { + .name = "X-Loader-OneNAND", + .offset = 0, + .size = 4 * (64 * 2048), + .mask_flags = MTD_WRITEABLE /* force read-only */ + }, + { + .name = "U-Boot-OneNAND", + .offset = MTDPART_OFS_APPEND, + .size = 2 * (64 * 2048), + .mask_flags = MTD_WRITEABLE /* force read-only */ + }, + { + .name = "U-Boot Environment-OneNAND", + .offset = MTDPART_OFS_APPEND, + .size = 1 * (64 * 2048), + }, + { + .name = "Kernel-OneNAND", + .offset = MTDPART_OFS_APPEND, + .size = 16 * (64 * 2048), + }, + { + .name = "File System-OneNAND", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct mtd_partition sdp_nand_partitions[] = { + /* All the partition sizes are listed in terms of NAND block size */ + { + .name = "X-Loader-NAND", + .offset = 0, + .size = 4 * (64 * 2048), + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "U-Boot-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ + .size = 10 * (64 * 2048), + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "Boot Env-NAND", + + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ + .size = 6 * (64 * 2048), + }, + { + .name = "Kernel-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ + .size = 40 * (64 * 2048), + }, + { + .name = "File System - NAND", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */ + }, +}; + +static struct flash_partitions sdp_flash_partitions[] = { + { + .parts = sdp_nor_partitions, + .nr_parts = ARRAY_SIZE(sdp_nor_partitions), + }, + { + .parts = sdp_onenand_partitions, + .nr_parts = ARRAY_SIZE(sdp_onenand_partitions), + }, + { + .parts = sdp_nand_partitions, + .nr_parts = ARRAY_SIZE(sdp_nand_partitions), + }, +}; + static void __init omap_3430sdp_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); @@ -666,6 +776,7 @@ static void __init omap_3430sdp_init(void) omap_serial_init(); usb_musb_init(); board_smc91x_init(); + sdp_flash_init(sdp_flash_partitions); sdp3430_display_init(); enable_board_wakeup_source(); usb_ehci_init(&ehci_pdata); @@ -674,7 +785,7 @@ static void __init omap_3430sdp_init(void) static void __init omap_3430sdp_map_io(void) { omap2_set_globals_343x(); - omap2_map_common_io(); + omap34xx_map_common_io(); } MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index 739059632811..4386d2b4a785 100755 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c @@ -68,8 +68,8 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { static void __init omap_sdp_map_io(void) { - omap2_set_globals_343x(); - omap2_map_common_io(); + omap2_set_globals_36xx(); + omap34xx_map_common_io(); } static struct omap_board_config_kernel sdp_config[] __initdata = { diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 0c6be6b4a7e2..793ce8f4e927 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -38,10 +38,6 @@ static struct platform_device *sdp4430_devices[] __initdata = { &sdp4430_lcd_device, }; -static struct omap_uart_config sdp4430_uart_config __initdata = { - .enabled_uarts = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3), -}; - static struct omap_lcd_config sdp4430_lcd_config __initdata = { .ctrl_name = "internal", }; @@ -87,7 +83,7 @@ static void __init omap_4430sdp_init(void) static void __init omap_4430sdp_map_io(void) { omap2_set_globals_443x(); - omap2_map_common_io(); + omap44xx_map_common_io(); } MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board") diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index b4e6eca0e8a9..ad323b46477d 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -22,6 +22,7 @@ #include <linux/gpio.h> #include <mach/hardware.h> +#include <mach/am35xx.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -29,9 +30,151 @@ #include <plat/board.h> #include <plat/common.h> #include <plat/usb.h> +#include <plat/display.h> #include "mux.h" +#define LCD_PANEL_PWR 176 +#define LCD_PANEL_BKLIGHT_PWR 182 +#define LCD_PANEL_PWM 181 + +static int lcd_enabled; +static int dvi_enabled; + +static void __init am3517_evm_display_init(void) +{ + int r; + + omap_mux_init_gpio(LCD_PANEL_PWR, OMAP_PIN_INPUT_PULLUP); + omap_mux_init_gpio(LCD_PANEL_BKLIGHT_PWR, OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_gpio(LCD_PANEL_PWM, OMAP_PIN_INPUT_PULLDOWN); + /* + * Enable GPIO 182 = LCD Backlight Power + */ + r = gpio_request(LCD_PANEL_BKLIGHT_PWR, "lcd_backlight_pwr"); + if (r) { + printk(KERN_ERR "failed to get lcd_backlight_pwr\n"); + return; + } + gpio_direction_output(LCD_PANEL_BKLIGHT_PWR, 1); + /* + * Enable GPIO 181 = LCD Panel PWM + */ + r = gpio_request(LCD_PANEL_PWM, "lcd_pwm"); + if (r) { + printk(KERN_ERR "failed to get lcd_pwm\n"); + goto err_1; + } + gpio_direction_output(LCD_PANEL_PWM, 1); + /* + * Enable GPIO 176 = LCD Panel Power enable pin + */ + r = gpio_request(LCD_PANEL_PWR, "lcd_panel_pwr"); + if (r) { + printk(KERN_ERR "failed to get lcd_panel_pwr\n"); + goto err_2; + } + gpio_direction_output(LCD_PANEL_PWR, 1); + + printk(KERN_INFO "Display initialized successfully\n"); + return; + +err_2: + gpio_free(LCD_PANEL_PWM); +err_1: + gpio_free(LCD_PANEL_BKLIGHT_PWR); +} + +static int am3517_evm_panel_enable_lcd(struct omap_dss_device *dssdev) +{ + if (dvi_enabled) { + printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); + return -EINVAL; + } + gpio_set_value(LCD_PANEL_PWR, 1); + lcd_enabled = 1; + + return 0; +} + +static void am3517_evm_panel_disable_lcd(struct omap_dss_device *dssdev) +{ + gpio_set_value(LCD_PANEL_PWR, 0); + lcd_enabled = 0; +} + +static struct omap_dss_device am3517_evm_lcd_device = { + .type = OMAP_DISPLAY_TYPE_DPI, + .name = "lcd", + .driver_name = "sharp_lq_panel", + .phy.dpi.data_lines = 16, + .platform_enable = am3517_evm_panel_enable_lcd, + .platform_disable = am3517_evm_panel_disable_lcd, +}; + +static int am3517_evm_panel_enable_tv(struct omap_dss_device *dssdev) +{ + return 0; +} + +static void am3517_evm_panel_disable_tv(struct omap_dss_device *dssdev) +{ +} + +static struct omap_dss_device am3517_evm_tv_device = { + .type = OMAP_DISPLAY_TYPE_VENC, + .name = "tv", + .driver_name = "venc", + .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, + .platform_enable = am3517_evm_panel_enable_tv, + .platform_disable = am3517_evm_panel_disable_tv, +}; + +static int am3517_evm_panel_enable_dvi(struct omap_dss_device *dssdev) +{ + if (lcd_enabled) { + printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); + return -EINVAL; + } + dvi_enabled = 1; + + return 0; +} + +static void am3517_evm_panel_disable_dvi(struct omap_dss_device *dssdev) +{ + dvi_enabled = 0; +} + +static struct omap_dss_device am3517_evm_dvi_device = { + .type = OMAP_DISPLAY_TYPE_DPI, + .name = "dvi", + .driver_name = "generic_panel", + .phy.dpi.data_lines = 24, + .platform_enable = am3517_evm_panel_enable_dvi, + .platform_disable = am3517_evm_panel_disable_dvi, +}; + +static struct omap_dss_device *am3517_evm_dss_devices[] = { + &am3517_evm_lcd_device, + &am3517_evm_tv_device, + &am3517_evm_dvi_device, +}; + +static struct omap_dss_board_info am3517_evm_dss_data = { + .num_devices = ARRAY_SIZE(am3517_evm_dss_devices), + .devices = am3517_evm_dss_devices, + .default_device = &am3517_evm_lcd_device, +}; + +struct platform_device am3517_evm_dss_device = { + .name = "omapdss", + .id = -1, + .dev = { + .platform_data = &am3517_evm_dss_data, + }, +}; + /* * Board initialization */ @@ -39,6 +182,7 @@ static struct omap_board_config_kernel am3517_evm_config[] __initdata = { }; static struct platform_device *am3517_evm_devices[] __initdata = { + &am3517_evm_dss_device, }; static void __init am3517_evm_init_irq(void) @@ -78,12 +222,14 @@ static void __init am3517_evm_init(void) omap_serial_init(); usb_ehci_init(&ehci_pdata); + /* DSS */ + am3517_evm_display_init(); } static void __init am3517_evm_map_io(void) { omap2_set_globals_343x(); - omap2_map_common_io(); + omap34xx_map_common_io(); } MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM") diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index fbbd68d69cc8..aa69fb999748 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -337,7 +337,7 @@ static void __init omap_apollon_init(void) static void __init omap_apollon_map_io(void) { omap2_set_globals_242x(); - omap2_map_common_io(); + omap242x_map_common_io(); } MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon") diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 2626a9f8a73a..8659c3e2ef6e 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -32,6 +32,9 @@ #include <linux/i2c/twl.h> #include <linux/regulator/machine.h> +#include <linux/spi/spi.h> +#include <linux/spi/tdo24m.h> + #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -41,12 +44,13 @@ #include <plat/nand.h> #include <plat/gpmc.h> #include <plat/usb.h> +#include <plat/display.h> #include <mach/hardware.h> #include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" -#include "mmc-twl4030.h" +#include "hsmmc.h" #define CM_T35_GPIO_PENDOWN 57 @@ -248,7 +252,6 @@ static inline void cm_t35_init_nand(void) {} #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) -#include <linux/spi/spi.h> #include <linux/spi/ads7846.h> #include <plat/mcspi.h> @@ -304,6 +307,193 @@ static void __init cm_t35_init_ads7846(void) static inline void cm_t35_init_ads7846(void) {} #endif +#define CM_T35_LCD_EN_GPIO 157 +#define CM_T35_LCD_BL_GPIO 58 +#define CM_T35_DVI_EN_GPIO 54 + +static int lcd_bl_gpio; +static int lcd_en_gpio; +static int dvi_en_gpio; + +static int lcd_enabled; +static int dvi_enabled; + +static int cm_t35_panel_enable_lcd(struct omap_dss_device *dssdev) +{ + if (dvi_enabled) { + printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); + return -EINVAL; + } + + gpio_set_value(lcd_en_gpio, 1); + gpio_set_value(lcd_bl_gpio, 1); + + lcd_enabled = 1; + + return 0; +} + +static void cm_t35_panel_disable_lcd(struct omap_dss_device *dssdev) +{ + lcd_enabled = 0; + + gpio_set_value(lcd_bl_gpio, 0); + gpio_set_value(lcd_en_gpio, 0); +} + +static int cm_t35_panel_enable_dvi(struct omap_dss_device *dssdev) +{ + if (lcd_enabled) { + printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); + return -EINVAL; + } + + gpio_set_value(dvi_en_gpio, 0); + dvi_enabled = 1; + + return 0; +} + +static void cm_t35_panel_disable_dvi(struct omap_dss_device *dssdev) +{ + gpio_set_value(dvi_en_gpio, 1); + dvi_enabled = 0; +} + +static int cm_t35_panel_enable_tv(struct omap_dss_device *dssdev) +{ + return 0; +} + +static void cm_t35_panel_disable_tv(struct omap_dss_device *dssdev) +{ +} + +static struct omap_dss_device cm_t35_lcd_device = { + .name = "lcd", + .driver_name = "toppoly_tdo35s_panel", + .type = OMAP_DISPLAY_TYPE_DPI, + .phy.dpi.data_lines = 18, + .platform_enable = cm_t35_panel_enable_lcd, + .platform_disable = cm_t35_panel_disable_lcd, +}; + +static struct omap_dss_device cm_t35_dvi_device = { + .name = "dvi", + .driver_name = "generic_panel", + .type = OMAP_DISPLAY_TYPE_DPI, + .phy.dpi.data_lines = 24, + .platform_enable = cm_t35_panel_enable_dvi, + .platform_disable = cm_t35_panel_disable_dvi, +}; + +static struct omap_dss_device cm_t35_tv_device = { + .name = "tv", + .driver_name = "venc", + .type = OMAP_DISPLAY_TYPE_VENC, + .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, + .platform_enable = cm_t35_panel_enable_tv, + .platform_disable = cm_t35_panel_disable_tv, +}; + +static struct omap_dss_device *cm_t35_dss_devices[] = { + &cm_t35_lcd_device, + &cm_t35_dvi_device, + &cm_t35_tv_device, +}; + +static struct omap_dss_board_info cm_t35_dss_data = { + .num_devices = ARRAY_SIZE(cm_t35_dss_devices), + .devices = cm_t35_dss_devices, + .default_device = &cm_t35_dvi_device, +}; + +static struct platform_device cm_t35_dss_device = { + .name = "omapdss", + .id = -1, + .dev = { + .platform_data = &cm_t35_dss_data, + }, +}; + +static struct omap2_mcspi_device_config tdo24m_mcspi_config = { + .turbo_mode = 0, + .single_channel = 1, /* 0: slave, 1: master */ +}; + +static struct tdo24m_platform_data tdo24m_config = { + .model = TDO35S, +}; + +static struct spi_board_info cm_t35_lcd_spi_board_info[] __initdata = { + { + .modalias = "tdo24m", + .bus_num = 4, + .chip_select = 0, + .max_speed_hz = 1000000, + .controller_data = &tdo24m_mcspi_config, + .platform_data = &tdo24m_config, + }, +}; + +static void __init cm_t35_init_display(void) +{ + int err; + + lcd_en_gpio = CM_T35_LCD_EN_GPIO; + lcd_bl_gpio = CM_T35_LCD_BL_GPIO; + dvi_en_gpio = CM_T35_DVI_EN_GPIO; + + spi_register_board_info(cm_t35_lcd_spi_board_info, + ARRAY_SIZE(cm_t35_lcd_spi_board_info)); + + err = gpio_request(lcd_en_gpio, "LCD RST"); + if (err) { + pr_err("CM-T35: failed to get LCD reset GPIO\n"); + goto out; + } + + err = gpio_request(lcd_bl_gpio, "LCD BL"); + if (err) { + pr_err("CM-T35: failed to get LCD backlight control GPIO\n"); + goto err_lcd_bl; + } + + err = gpio_request(dvi_en_gpio, "DVI EN"); + if (err) { + pr_err("CM-T35: failed to get DVI reset GPIO\n"); + goto err_dvi_en; + } + + gpio_export(lcd_en_gpio, 0); + gpio_export(lcd_bl_gpio, 0); + gpio_export(dvi_en_gpio, 0); + gpio_direction_output(lcd_en_gpio, 0); + gpio_direction_output(lcd_bl_gpio, 0); + gpio_direction_output(dvi_en_gpio, 1); + + msleep(50); + gpio_set_value(lcd_en_gpio, 1); + + err = platform_device_register(&cm_t35_dss_device); + if (err) { + pr_err("CM-T35: failed to register DSS device\n"); + goto err_dev_reg; + } + + return; + +err_dev_reg: + gpio_free(dvi_en_gpio); +err_dvi_en: + gpio_free(lcd_bl_gpio); +err_lcd_bl: + gpio_free(lcd_en_gpio); +out: + + return; +} + static struct regulator_consumer_supply cm_t35_vmmc1_supply = { .supply = "vmmc", }; @@ -312,6 +502,16 @@ static struct regulator_consumer_supply cm_t35_vsim_supply = { .supply = "vmmc_aux", }; +static struct regulator_consumer_supply cm_t35_vdac_supply = { + .supply = "vdda_dac", + .dev = &cm_t35_dss_device.dev, +}; + +static struct regulator_consumer_supply cm_t35_vdvi_supply = { + .supply = "vdvi", + .dev = &cm_t35_dss_device.dev, +}; + /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ static struct regulator_init_data cm_t35_vmmc1 = { .constraints = { @@ -342,6 +542,35 @@ static struct regulator_init_data cm_t35_vsim = { .consumer_supplies = &cm_t35_vsim_supply, }; +/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ +static struct regulator_init_data cm_t35_vdac = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &cm_t35_vdac_supply, +}; + +/* VPLL2 for digital video outputs */ +static struct regulator_init_data cm_t35_vpll2 = { + .constraints = { + .name = "VDVI", + .min_uV = 1800000, + .max_uV = 1800000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &cm_t35_vdvi_supply, +}; + static struct twl4030_usb_data cm_t35_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; @@ -364,7 +593,7 @@ static struct twl4030_keypad_data cm_t35_kp_data = { .rep = 1, }; -static struct twl4030_hsmmc_info mmc[] = { +static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, .wires = 4, @@ -413,7 +642,7 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio, /* gpio + 0 is "mmc0_cd" (input/IRQ) */ mmc[0].gpio_cd = gpio + 0; - twl4030_mmc_init(mmc); + omap2_hsmmc_init(mmc); /* link regulators to MMC adapters */ cm_t35_vmmc1_supply.dev = mmc[0].dev; @@ -445,6 +674,8 @@ static struct twl4030_platform_data cm_t35_twldata = { .gpio = &cm_t35_gpio_data, .vmmc1 = &cm_t35_vmmc1, .vsim = &cm_t35_vsim, + .vdac = &cm_t35_vdac, + .vpll2 = &cm_t35_vpll2, }; static struct i2c_board_info __initdata cm_t35_i2c_boardinfo[] = { @@ -479,7 +710,7 @@ static void __init cm_t35_init_irq(void) static void __init cm_t35_map_io(void) { omap2_set_globals_343x(); - omap2_map_common_io(); + omap34xx_map_common_io(); } static struct omap_board_mux board_mux[] __initdata = { @@ -568,6 +799,11 @@ static struct omap_board_mux board_mux[] __initdata = { OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + /* display controls */ + OMAP3_MUX(MCBSP1_FSR, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + OMAP3_MUX(GPMC_NCS7, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + OMAP3_MUX(GPMC_NCS3, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + /* TPS IRQ */ OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_WAKEUP_EN | \ OMAP_PIN_INPUT_PULLUP), @@ -584,6 +820,7 @@ static void __init cm_t35_init(void) cm_t35_init_ads7846(); cm_t35_init_ethernet(); cm_t35_init_led(); + cm_t35_init_display(); usb_musb_init(); } diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 7e6e6ca88be5..16cc06860670 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -50,7 +50,7 @@ static void __init omap_generic_init(void) static void __init omap_generic_map_io(void) { omap2_set_globals_242x(); /* should be 242x, 243x, or 343x */ - omap2_map_common_io(); + omap242x_map_common_io(); } MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx") diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index cfb7f1257d20..0665f2c8dc8e 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -16,6 +16,7 @@ #include <linux/platform_device.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> #include <linux/delay.h> #include <linux/workqueue.h> #include <linux/i2c.h> @@ -29,7 +30,6 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <asm/mach/flash.h> #include <plat/control.h> #include <mach/gpio.h> @@ -115,8 +115,7 @@ static struct mtd_partition h4_partitions[] = { } }; -static struct flash_platform_data h4_flash_data = { - .map_name = "cfi_probe", +static struct physmap_flash_data h4_flash_data = { .width = 2, .parts = h4_partitions, .nr_parts = ARRAY_SIZE(h4_partitions), @@ -127,7 +126,7 @@ static struct resource h4_flash_resource = { }; static struct platform_device h4_flash_device = { - .name = "omapflash", + .name = "physmap-flash", .id = 0, .dev = { .platform_data = &h4_flash_data, @@ -370,7 +369,7 @@ static void __init omap_h4_init(void) static void __init omap_h4_map_io(void) { omap2_set_globals_242x(); - omap2_map_common_io(); + omap242x_map_common_io(); } MACHINE_START(OMAP_H4, "OMAP2420 H4 board") diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 117b8fd7e3a6..adc1b46fa04e 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -30,7 +30,7 @@ #include <plat/usb.h> #include "mux.h" -#include "mmc-twl4030.h" +#include "hsmmc.h" #define IGEP2_SMSC911X_CS 5 #define IGEP2_SMSC911X_GPIO 176 @@ -121,7 +121,7 @@ static struct regulator_init_data igep2_vmmc1 = { .consumer_supplies = &igep2_vmmc1_supply, }; -static struct twl4030_hsmmc_info mmc[] = { +static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, .wires = 4, @@ -142,7 +142,7 @@ static int igep2_twl_gpio_setup(struct device *dev, { /* gpio + 0 is "mmc0_cd" (input/IRQ) */ mmc[0].gpio_cd = gpio + 0; - twl4030_mmc_init(mmc); + omap2_hsmmc_init(mmc); /* link regulators to MMC adapters ... we "know" the * regulators will be set up only *after* we return. @@ -246,7 +246,7 @@ static void __init igep2_init(void) static void __init igep2_map_io(void) { omap2_set_globals_343x(); - omap2_map_common_io(); + omap34xx_map_common_io(); } MACHINE_START(IGEP0020, "IGEP v2 board") diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index 995d4a2b2dfd..095adcb642b8 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -44,7 +44,7 @@ #include <plat/usb.h> #include "mux.h" -#include "mmc-twl4030.h" +#include "hsmmc.h" #define LDP_SMSC911X_CS 1 #define LDP_SMSC911X_GPIO 152 @@ -359,7 +359,7 @@ static int __init omap_i2c_init(void) return 0; } -static struct twl4030_hsmmc_info mmc[] __initdata = { +static struct omap2_hsmmc_info mmc[] __initdata = { { .mmc = 1, .wires = 4, @@ -396,7 +396,7 @@ static void __init omap_ldp_init(void) omap_serial_init(); usb_musb_init(); - twl4030_mmc_init(mmc); + omap2_hsmmc_init(mmc); /* link regulators to MMC adapters */ ldp_vmmc1_supply.dev = mmc[0].dev; } @@ -404,7 +404,7 @@ static void __init omap_ldp_init(void) static void __init omap_ldp_map_io(void) { omap2_set_globals_343x(); - omap2_map_common_io(); + omap34xx_map_common_io(); } MACHINE_START(OMAP_LDP, "OMAP LDP board") diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 764ab1ed576d..9de03f8e2e68 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -99,7 +99,7 @@ static void __init n8x0_onenand_init(void) {} static void __init n8x0_map_io(void) { omap2_set_globals_242x(); - omap2_map_common_io(); + omap242x_map_common_io(); } static void __init n8x0_init_irq(void) diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 231cb4ec1847..1bae69913376 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -45,7 +45,7 @@ #include <plat/timer-gp.h> #include "mux.h" -#include "mmc-twl4030.h" +#include "hsmmc.h" #define GPMC_CS0_BASE 0x60 #define GPMC_CS_SIZE 0x30 @@ -108,7 +108,7 @@ static struct platform_device omap3beagle_nand_device = { #include "sdram-micron-mt46h32m32lf-6.h" -static struct twl4030_hsmmc_info mmc[] = { +static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, .wires = 8, @@ -147,7 +147,7 @@ static int beagle_twl_gpio_setup(struct device *dev, } /* gpio + 0 is "mmc0_cd" (input/IRQ) */ mmc[0].gpio_cd = gpio + 0; - twl4030_mmc_init(mmc); + omap2_hsmmc_init(mmc); /* link regulators to MMC adapters */ beagle_vmmc1_supply.dev = mmc[0].dev; @@ -455,7 +455,7 @@ static void __init omap3_beagle_init(void) static void __init omap3_beagle_map_io(void) { omap2_set_globals_343x(); - omap2_map_common_io(); + omap34xx_map_common_io(); } MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 34de17851572..45227f394758 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -41,10 +41,11 @@ #include <plat/usb.h> #include <plat/common.h> #include <plat/mcspi.h> +#include <plat/display.h> #include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" -#include "mmc-twl4030.h" +#include "hsmmc.h" #define OMAP3_EVM_TS_GPIO 175 #define OMAP3_EVM_EHCI_VBUS 22 @@ -147,6 +148,187 @@ static inline void __init omap3evm_init_smsc911x(void) static inline void __init omap3evm_init_smsc911x(void) { return; } #endif +/* + * OMAP3EVM LCD Panel control signals + */ +#define OMAP3EVM_LCD_PANEL_LR 2 +#define OMAP3EVM_LCD_PANEL_UD 3 +#define OMAP3EVM_LCD_PANEL_INI 152 +#define OMAP3EVM_LCD_PANEL_ENVDD 153 +#define OMAP3EVM_LCD_PANEL_QVGA 154 +#define OMAP3EVM_LCD_PANEL_RESB 155 +#define OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO 210 +#define OMAP3EVM_DVI_PANEL_EN_GPIO 199 + +static int lcd_enabled; +static int dvi_enabled; + +static void __init omap3_evm_display_init(void) +{ + int r; + + r = gpio_request(OMAP3EVM_LCD_PANEL_RESB, "lcd_panel_resb"); + if (r) { + printk(KERN_ERR "failed to get lcd_panel_resb\n"); + return; + } + gpio_direction_output(OMAP3EVM_LCD_PANEL_RESB, 1); + + r = gpio_request(OMAP3EVM_LCD_PANEL_INI, "lcd_panel_ini"); + if (r) { + printk(KERN_ERR "failed to get lcd_panel_ini\n"); + goto err_1; + } + gpio_direction_output(OMAP3EVM_LCD_PANEL_INI, 1); + + r = gpio_request(OMAP3EVM_LCD_PANEL_QVGA, "lcd_panel_qvga"); + if (r) { + printk(KERN_ERR "failed to get lcd_panel_qvga\n"); + goto err_2; + } + gpio_direction_output(OMAP3EVM_LCD_PANEL_QVGA, 0); + + r = gpio_request(OMAP3EVM_LCD_PANEL_LR, "lcd_panel_lr"); + if (r) { + printk(KERN_ERR "failed to get lcd_panel_lr\n"); + goto err_3; + } + gpio_direction_output(OMAP3EVM_LCD_PANEL_LR, 1); + + r = gpio_request(OMAP3EVM_LCD_PANEL_UD, "lcd_panel_ud"); + if (r) { + printk(KERN_ERR "failed to get lcd_panel_ud\n"); + goto err_4; + } + gpio_direction_output(OMAP3EVM_LCD_PANEL_UD, 1); + + r = gpio_request(OMAP3EVM_LCD_PANEL_ENVDD, "lcd_panel_envdd"); + if (r) { + printk(KERN_ERR "failed to get lcd_panel_envdd\n"); + goto err_5; + } + gpio_direction_output(OMAP3EVM_LCD_PANEL_ENVDD, 0); + + return; + +err_5: + gpio_free(OMAP3EVM_LCD_PANEL_UD); +err_4: + gpio_free(OMAP3EVM_LCD_PANEL_LR); +err_3: + gpio_free(OMAP3EVM_LCD_PANEL_QVGA); +err_2: + gpio_free(OMAP3EVM_LCD_PANEL_INI); +err_1: + gpio_free(OMAP3EVM_LCD_PANEL_RESB); + +} + +static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev) +{ + if (dvi_enabled) { + printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); + return -EINVAL; + } + gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0); + + if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) + gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); + else + gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); + + lcd_enabled = 1; + return 0; +} + +static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev) +{ + gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1); + + if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) + gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); + else + gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); + + lcd_enabled = 0; +} + +static struct omap_dss_device omap3_evm_lcd_device = { + .name = "lcd", + .driver_name = "sharp_ls_panel", + .type = OMAP_DISPLAY_TYPE_DPI, + .phy.dpi.data_lines = 18, + .platform_enable = omap3_evm_enable_lcd, + .platform_disable = omap3_evm_disable_lcd, +}; + +static int omap3_evm_enable_tv(struct omap_dss_device *dssdev) +{ + return 0; +} + +static void omap3_evm_disable_tv(struct omap_dss_device *dssdev) +{ +} + +static struct omap_dss_device omap3_evm_tv_device = { + .name = "tv", + .driver_name = "venc", + .type = OMAP_DISPLAY_TYPE_VENC, + .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, + .platform_enable = omap3_evm_enable_tv, + .platform_disable = omap3_evm_disable_tv, +}; + +static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev) +{ + if (lcd_enabled) { + printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); + return -EINVAL; + } + + gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 1); + + dvi_enabled = 1; + return 0; +} + +static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev) +{ + gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 0); + + dvi_enabled = 0; +} + +static struct omap_dss_device omap3_evm_dvi_device = { + .name = "dvi", + .driver_name = "generic_panel", + .type = OMAP_DISPLAY_TYPE_DPI, + .phy.dpi.data_lines = 24, + .platform_enable = omap3_evm_enable_dvi, + .platform_disable = omap3_evm_disable_dvi, +}; + +static struct omap_dss_device *omap3_evm_dss_devices[] = { + &omap3_evm_lcd_device, + &omap3_evm_tv_device, + &omap3_evm_dvi_device, +}; + +static struct omap_dss_board_info omap3_evm_dss_data = { + .num_devices = ARRAY_SIZE(omap3_evm_dss_devices), + .devices = omap3_evm_dss_devices, + .default_device = &omap3_evm_lcd_device, +}; + +static struct platform_device omap3_evm_dss_device = { + .name = "omapdss", + .id = -1, + .dev = { + .platform_data = &omap3_evm_dss_data, + }, +}; + static struct regulator_consumer_supply omap3evm_vmmc1_supply = { .supply = "vmmc", }; @@ -185,7 +367,7 @@ static struct regulator_init_data omap3evm_vsim = { .consumer_supplies = &omap3evm_vsim_supply, }; -static struct twl4030_hsmmc_info mmc[] = { +static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, .wires = 4, @@ -225,7 +407,7 @@ static int omap3evm_twl_gpio_setup(struct device *dev, /* gpio + 0 is "mmc0_cd" (input/IRQ) */ omap_mux_init_gpio(63, OMAP_PIN_INPUT); mmc[0].gpio_cd = gpio + 0; - twl4030_mmc_init(mmc); + omap2_hsmmc_init(mmc); /* link regulators to MMC adapters */ omap3evm_vmmc1_supply.dev = mmc[0].dev; @@ -236,6 +418,14 @@ static int omap3evm_twl_gpio_setup(struct device *dev, * the P2 connector; notably LEDA for the LCD backlight. */ + /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */ + gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL"); + gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); + + /* gpio + 7 == DVI Enable */ + gpio_request(gpio + 7, "EN_DVI"); + gpio_direction_output(gpio + 7, 0); + /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */ gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; @@ -300,6 +490,47 @@ static struct twl4030_codec_data omap3evm_codec_data = { .audio = &omap3evm_audio_data, }; +static struct regulator_consumer_supply omap3_evm_vdda_dac_supply = { + .supply = "vdda_dac", + .dev = &omap3_evm_dss_device.dev, +}; + +/* VDAC for DSS driving S-Video */ +static struct regulator_init_data omap3_evm_vdac = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &omap3_evm_vdda_dac_supply, +}; + +/* VPLL2 for digital video outputs */ +static struct regulator_consumer_supply omap3_evm_vpll2_supply = { + .supply = "vdvi", + .dev = &omap3_evm_lcd_device.dev, +}; + +static struct regulator_init_data omap3_evm_vpll2 = { + .constraints = { + .name = "VDVI", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &omap3_evm_vpll2_supply, +}; + static struct twl4030_platform_data omap3evm_twldata = { .irq_base = TWL4030_IRQ_BASE, .irq_end = TWL4030_IRQ_END, @@ -310,6 +541,8 @@ static struct twl4030_platform_data omap3evm_twldata = { .usb = &omap3evm_usb_data, .gpio = &omap3evm_gpio_data, .codec = &omap3evm_codec_data, + .vdac = &omap3_evm_vdac, + .vpll2 = &omap3_evm_vpll2, }; static struct i2c_board_info __initdata omap3evm_i2c_boardinfo[] = { @@ -337,15 +570,6 @@ static int __init omap3_evm_i2c_init(void) return 0; } -static struct platform_device omap3_evm_lcd_device = { - .name = "omap3evm_lcd", - .id = -1, -}; - -static struct omap_lcd_config omap3_evm_lcd_config __initdata = { - .ctrl_name = "internal", -}; - static void ads7846_dev_init(void) { if (gpio_request(OMAP3_EVM_TS_GPIO, "ADS7846 pendown") < 0) @@ -393,7 +617,6 @@ struct spi_board_info omap3evm_spi_board_info[] = { }; static struct omap_board_config_kernel omap3_evm_config[] __initdata = { - { OMAP_TAG_LCD, &omap3_evm_lcd_config }, }; static void __init omap3_evm_init_irq(void) @@ -406,7 +629,7 @@ static void __init omap3_evm_init_irq(void) } static struct platform_device *omap3_evm_devices[] __initdata = { - &omap3_evm_lcd_device, + &omap3_evm_dss_device, }; static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { @@ -473,12 +696,13 @@ static void __init omap3_evm_init(void) usb_ehci_init(&ehci_pdata); ads7846_dev_init(); omap3evm_init_smsc911x(); + omap3_evm_display_init(); } static void __init omap3_evm_map_io(void) { omap2_set_globals_343x(); - omap2_map_common_io(); + omap34xx_map_common_io(); } MACHINE_START(OMAP3EVM, "OMAP3 EVM") diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index ef17cf1ab6d7..9967b5d24b50 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -43,7 +43,7 @@ #include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" -#include "mmc-twl4030.h" +#include "hsmmc.h" #define OMAP3_PANDORA_TS_GPIO 94 @@ -192,7 +192,7 @@ static struct twl4030_keypad_data pandora_kp_data = { .rep = 1, }; -static struct twl4030_hsmmc_info omap3pandora_mmc[] = { +static struct omap2_hsmmc_info omap3pandora_mmc[] = { { .mmc = 1, .wires = 4, @@ -231,7 +231,7 @@ static int omap3pandora_twl_gpio_setup(struct device *dev, /* gpio + {0,1} is "mmc{0,1}_cd" (input/IRQ) */ omap3pandora_mmc[0].gpio_cd = gpio + 0; omap3pandora_mmc[1].gpio_cd = gpio + 1; - twl4030_mmc_init(omap3pandora_mmc); + omap2_hsmmc_init(omap3pandora_mmc); /* link regulators to MMC adapters */ pandora_vmmc1_supply.dev = omap3pandora_mmc[0].dev; @@ -423,7 +423,7 @@ static void __init omap3pandora_init(void) static void __init omap3pandora_map_io(void) { omap2_set_globals_343x(); - omap2_map_common_io(); + omap34xx_map_common_io(); } MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index fe3d22cb2457..8252ba49a664 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -50,7 +50,7 @@ #include <plat/timer-gp.h> #include "mux.h" -#include "mmc-twl4030.h" +#include "hsmmc.h" #include <asm/setup.h> @@ -122,7 +122,7 @@ static struct platform_device omap3touchbook_nand_device = { #include "sdram-micron-mt46h32m32lf-6.h" -static struct twl4030_hsmmc_info mmc[] = { +static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, .wires = 8, @@ -161,7 +161,7 @@ static int touchbook_twl_gpio_setup(struct device *dev, } /* gpio + 0 is "mmc0_cd" (input/IRQ) */ mmc[0].gpio_cd = gpio + 0; - twl4030_mmc_init(mmc); + omap2_hsmmc_init(mmc); /* link regulators to MMC adapters */ touchbook_vmmc1_supply.dev = mmc[0].dev; @@ -557,7 +557,7 @@ static void __init omap3_touchbook_init(void) static void __init omap3_touchbook_map_io(void) { omap2_set_globals_343x(); - omap2_map_common_io(); + omap34xx_map_common_io(); } MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board") diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index d192dd98a591..7e6aa8292746 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -48,7 +48,7 @@ #include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" -#include "mmc-twl4030.h" +#include "hsmmc.h" #define OVERO_GPIO_BT_XGATE 15 #define OVERO_GPIO_W2W_NRESET 16 @@ -272,7 +272,7 @@ static void __init overo_flash_init(void) } } -static struct twl4030_hsmmc_info mmc[] = { +static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, .wires = 4, @@ -297,7 +297,7 @@ static struct regulator_consumer_supply overo_vmmc1_supply = { static int overo_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { - twl4030_mmc_init(mmc); + omap2_hsmmc_init(mmc); overo_vmmc1_supply.dev = mmc[0].dev; @@ -469,7 +469,7 @@ static void __init overo_init(void) static void __init overo_map_io(void) { omap2_set_globals_343x(); - omap2_map_common_io(); + omap34xx_map_common_io(); } MACHINE_START(OVERO, "Gumstix Overo") diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index acafdbc8aa16..4377a4cf36eb 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -34,7 +34,7 @@ #include <plat/gpmc-smc91x.h> #include "mux.h" -#include "mmc-twl4030.h" +#include "hsmmc.h" #define SYSTEM_REV_B_USES_VAUX3 0x1699 #define SYSTEM_REV_S_USES_VAUX3 0x8 @@ -209,7 +209,47 @@ static struct twl4030_madc_platform_data rx51_madc_data = { .irq_line = 1, }; -static struct twl4030_hsmmc_info mmc[] = { +/* Enable input logic and pull all lines up when eMMC is on. */ +static struct omap_board_mux rx51_mmc2_on_mux[] = { + OMAP3_MUX(SDMMC2_CMD, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), + OMAP3_MUX(SDMMC2_DAT0, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), + OMAP3_MUX(SDMMC2_DAT1, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), + OMAP3_MUX(SDMMC2_DAT2, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), + OMAP3_MUX(SDMMC2_DAT3, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), + OMAP3_MUX(SDMMC2_DAT4, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), + OMAP3_MUX(SDMMC2_DAT5, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), + OMAP3_MUX(SDMMC2_DAT6, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), + OMAP3_MUX(SDMMC2_DAT7, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; + +/* Disable input logic and pull all lines down when eMMC is off. */ +static struct omap_board_mux rx51_mmc2_off_mux[] = { + OMAP3_MUX(SDMMC2_CMD, OMAP_PULL_ENA | OMAP_MUX_MODE0), + OMAP3_MUX(SDMMC2_DAT0, OMAP_PULL_ENA | OMAP_MUX_MODE0), + OMAP3_MUX(SDMMC2_DAT1, OMAP_PULL_ENA | OMAP_MUX_MODE0), + OMAP3_MUX(SDMMC2_DAT2, OMAP_PULL_ENA | OMAP_MUX_MODE0), + OMAP3_MUX(SDMMC2_DAT3, OMAP_PULL_ENA | OMAP_MUX_MODE0), + OMAP3_MUX(SDMMC2_DAT4, OMAP_PULL_ENA | OMAP_MUX_MODE0), + OMAP3_MUX(SDMMC2_DAT5, OMAP_PULL_ENA | OMAP_MUX_MODE0), + OMAP3_MUX(SDMMC2_DAT6, OMAP_PULL_ENA | OMAP_MUX_MODE0), + OMAP3_MUX(SDMMC2_DAT7, OMAP_PULL_ENA | OMAP_MUX_MODE0), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; + +/* + * Current flows to eMMC when eMMC is off and the data lines are pulled up, + * so pull them down. N.B. we pull 8 lines because we are using 8 lines. + */ +static void rx51_mmc2_remux(struct device *dev, int slot, int power_on) +{ + if (power_on) + omap_mux_write_array(rx51_mmc2_on_mux); + else + omap_mux_write_array(rx51_mmc2_off_mux); +} + +static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "external", .mmc = 1, @@ -222,25 +262,29 @@ static struct twl4030_hsmmc_info mmc[] = { { .name = "internal", .mmc = 2, - .wires = 8, + .wires = 8, /* See also rx51_mmc2_remux */ .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .nonremovable = true, .power_saving = true, + .remux = rx51_mmc2_remux, }, {} /* Terminator */ }; static struct regulator_consumer_supply rx51_vmmc1_supply = { - .supply = "vmmc", + .supply = "vmmc", + .dev_name = "mmci-omap-hs.0", }; static struct regulator_consumer_supply rx51_vmmc2_supply = { - .supply = "vmmc", + .supply = "vmmc", + .dev_name = "mmci-omap-hs.1", }; static struct regulator_consumer_supply rx51_vsim_supply = { - .supply = "vmmc_aux", + .supply = "vmmc_aux", + .dev_name = "mmci-omap-hs.1", }; static struct regulator_init_data rx51_vaux1 = { @@ -375,12 +419,6 @@ static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n) gpio_request(gpio + 7, "speaker_en"); gpio_direction_output(gpio + 7, 1); - /* set up MMC adapters, linking their regulators to them */ - twl4030_mmc_init(mmc); - rx51_vmmc1_supply.dev = mmc[0].dev; - rx51_vmmc2_supply.dev = mmc[1].dev; - rx51_vsim_supply.dev = mmc[1].dev; - return 0; } @@ -751,5 +789,6 @@ void __init rx51_peripherals_init(void) rx51_init_wl1251(); spi_register_board_info(rx51_peripherals_spi_board_info, ARRAY_SIZE(rx51_peripherals_spi_board_info)); + omap2_hsmmc_init(mmc); } diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index 67bb3476b707..6a49f916103d 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -93,7 +93,7 @@ static void __init rx51_init(void) static void __init rx51_map_io(void) { omap2_set_globals_343x(); - omap2_map_common_io(); + omap34xx_map_common_io(); } MACHINE_START(NOKIA_RX51, "Nokia RX-51 board") diff --git a/arch/arm/mach-omap2/board-sdp-flash.c b/arch/arm/mach-omap2/board-sdp-flash.c new file mode 100644 index 000000000000..b1b88deec7f2 --- /dev/null +++ b/arch/arm/mach-omap2/board-sdp-flash.c @@ -0,0 +1,272 @@ +/* + * board-sdp-flash.c + * Modified from mach-omap2/board-3430sdp-flash.c + * + * Copyright (C) 2009 Nokia Corporation + * Copyright (C) 2009 Texas Instruments + * + * Vimal Singh <vimalsingh@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/mtd/physmap.h> +#include <linux/io.h> + +#include <plat/gpmc.h> +#include <plat/nand.h> +#include <plat/onenand.h> +#include <plat/tc.h> +#include <mach/board-sdp.h> + +#define REG_FPGA_REV 0x10 +#define REG_FPGA_DIP_SWITCH_INPUT2 0x60 +#define MAX_SUPPORTED_GPMC_CONFIG 3 + +#define DEBUG_BASE 0x08000000 /* debug board */ + +#define PDC_NOR 1 +#define PDC_NAND 2 +#define PDC_ONENAND 3 +#define DBG_MPDB 4 + +/* various memory sizes */ +#define FLASH_SIZE_SDPV1 SZ_64M /* NOR flash (64 Meg aligned) */ +#define FLASH_SIZE_SDPV2 SZ_128M /* NOR flash (256 Meg aligned) */ + +/* + * SDP3430 V2 Board CS organization + * Different from SDP3430 V1. Now 4 switches used to specify CS + * + * See also the Switch S8 settings in the comments. + * + * REVISIT: Add support for 2430 SDP + */ +static const unsigned char chip_sel_sdp[][GPMC_CS_NUM] = { + {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */ + {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */ + {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */ +}; + +static struct physmap_flash_data sdp_nor_data = { + .width = 2, +}; + +static struct resource sdp_nor_resource = { + .flags = IORESOURCE_MEM, +}; + +static struct platform_device sdp_nor_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &sdp_nor_data, + }, + .num_resources = 1, + .resource = &sdp_nor_resource, +}; + +static void +__init board_nor_init(struct flash_partitions sdp_nor_parts, u8 cs) +{ + int err; + + sdp_nor_data.parts = sdp_nor_parts.parts; + sdp_nor_data.nr_parts = sdp_nor_parts.nr_parts; + + /* Configure start address and size of NOR device */ + if (omap_rev() >= OMAP3430_REV_ES1_0) { + err = gpmc_cs_request(cs, FLASH_SIZE_SDPV2 - 1, + (unsigned long *)&sdp_nor_resource.start); + sdp_nor_resource.end = sdp_nor_resource.start + + FLASH_SIZE_SDPV2 - 1; + } else { + err = gpmc_cs_request(cs, FLASH_SIZE_SDPV1 - 1, + (unsigned long *)&sdp_nor_resource.start); + sdp_nor_resource.end = sdp_nor_resource.start + + FLASH_SIZE_SDPV1 - 1; + } + if (err < 0) { + printk(KERN_ERR "NOR: Can't request GPMC CS\n"); + return; + } + if (platform_device_register(&sdp_nor_device) < 0) + printk(KERN_ERR "Unable to register NOR device\n"); +} + +#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ + defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) +static struct omap_onenand_platform_data board_onenand_data = { + .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */ +}; + +static void +__init board_onenand_init(struct flash_partitions sdp_onenand_parts, u8 cs) +{ + board_onenand_data.cs = cs; + board_onenand_data.parts = sdp_onenand_parts.parts; + board_onenand_data.nr_parts = sdp_onenand_parts.nr_parts; + + gpmc_onenand_init(&board_onenand_data); +} +#else +static void +__init board_onenand_init(struct flash_partitions sdp_onenand_parts, u8 cs) +{ +} +#endif /* CONFIG_MTD_ONENAND_OMAP2 || CONFIG_MTD_ONENAND_OMAP2_MODULE */ + +#if defined(CONFIG_MTD_NAND_OMAP2) || \ + defined(CONFIG_MTD_NAND_OMAP2_MODULE) + +/* Note that all values in this struct are in nanoseconds */ +static struct gpmc_timings nand_timings = { + + .sync_clk = 0, + + .cs_on = 0, + .cs_rd_off = 36, + .cs_wr_off = 36, + + .adv_on = 6, + .adv_rd_off = 24, + .adv_wr_off = 36, + + .we_off = 30, + .oe_off = 48, + + .access = 54, + .rd_cycle = 72, + .wr_cycle = 72, + + .wr_access = 30, + .wr_data_mux_bus = 0, +}; + +static struct omap_nand_platform_data sdp_nand_data = { + .nand_setup = NULL, + .gpmc_t = &nand_timings, + .dma_channel = -1, /* disable DMA in OMAP NAND driver */ + .dev_ready = NULL, + .devsize = 0, /* '0' for 8-bit, '1' for 16-bit device */ +}; + +static void +__init board_nand_init(struct flash_partitions sdp_nand_parts, u8 cs) +{ + sdp_nand_data.cs = cs; + sdp_nand_data.parts = sdp_nand_parts.parts; + sdp_nand_data.nr_parts = sdp_nand_parts.nr_parts; + + sdp_nand_data.gpmc_cs_baseaddr = (void *)(OMAP34XX_GPMC_VIRT + + GPMC_CS0_BASE + + cs * GPMC_CS_SIZE); + sdp_nand_data.gpmc_baseaddr = (void *) (OMAP34XX_GPMC_VIRT); + + gpmc_nand_init(&sdp_nand_data); +} +#else +static void +__init board_nand_init(struct flash_partitions sdp_nand_parts, u8 cs) +{ +} +#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ + +/** + * get_gpmc0_type - Reads the FPGA DIP_SWITCH_INPUT_REGISTER2 to get + * the various cs values. + */ +static u8 get_gpmc0_type(void) +{ + u8 cs = 0; + void __iomem *fpga_map_addr; + + fpga_map_addr = ioremap(DEBUG_BASE, 4096); + if (!fpga_map_addr) + return -ENOMEM; + + if (!(__raw_readw(fpga_map_addr + REG_FPGA_REV))) + /* we dont have an DEBUG FPGA??? */ + /* Depend on #defines!! default to strata boot return param */ + goto unmap; + + /* S8-DIP-OFF = 1, S8-DIP-ON = 0 */ + cs = __raw_readw(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf; + + /* ES2.0 SDP's onwards 4 dip switches are provided for CS */ + if (omap_rev() >= OMAP3430_REV_ES1_0) + /* change (S8-1:4=DS-2:0) to (S8-4:1=DS-2:0) */ + cs = ((cs & 8) >> 3) | ((cs & 4) >> 1) | + ((cs & 2) << 1) | ((cs & 1) << 3); + else + /* change (S8-1:3=DS-2:0) to (S8-3:1=DS-2:0) */ + cs = ((cs & 4) >> 2) | (cs & 2) | ((cs & 1) << 2); +unmap: + iounmap(fpga_map_addr); + return cs; +} + +/** + * sdp3430_flash_init - Identify devices connected to GPMC and register. + * + * @return - void. + */ +void __init sdp_flash_init(struct flash_partitions sdp_partition_info[]) +{ + u8 cs = 0; + u8 norcs = GPMC_CS_NUM + 1; + u8 nandcs = GPMC_CS_NUM + 1; + u8 onenandcs = GPMC_CS_NUM + 1; + u8 idx; + unsigned char *config_sel = NULL; + + /* REVISIT: Is this return correct idx for 2430 SDP? + * for which cs configuration matches for 2430 SDP? + */ + idx = get_gpmc0_type(); + if (idx >= MAX_SUPPORTED_GPMC_CONFIG) { + printk(KERN_ERR "%s: Invalid chip select: %d\n", __func__, cs); + return; + } + config_sel = (unsigned char *)(chip_sel_sdp[idx]); + + while (cs < GPMC_CS_NUM) { + switch (config_sel[cs]) { + case PDC_NOR: + if (norcs > GPMC_CS_NUM) + norcs = cs; + break; + case PDC_NAND: + if (nandcs > GPMC_CS_NUM) + nandcs = cs; + break; + case PDC_ONENAND: + if (onenandcs > GPMC_CS_NUM) + onenandcs = cs; + break; + }; + cs++; + } + + if (norcs > GPMC_CS_NUM) + printk(KERN_INFO "OneNAND: Unable to find configuration " + " in GPMC\n "); + else + board_nor_init(sdp_partition_info[0], norcs); + + if (onenandcs > GPMC_CS_NUM) + printk(KERN_INFO "OneNAND: Unable to find configuration " + " in GPMC\n "); + else + board_onenand_init(sdp_partition_info[1], onenandcs); + + if (nandcs > GPMC_CS_NUM) + printk(KERN_INFO "NAND: Unable to find configuration " + " in GPMC\n "); + else + board_nand_init(sdp_partition_info[2], nandcs); +} diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index 1e3dfb652acc..9a0821fb7ea0 100755 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -24,7 +24,8 @@ #include <plat/common.h> #include <plat/usb.h> -#include "mmc-twl4030.h" +#include "mux.h" +#include "hsmmc.h" /* Zoom2 has Qwerty keyboard*/ static int board_keymap[] = { @@ -150,7 +151,7 @@ static struct regulator_init_data zoom_vsim = { .consumer_supplies = &zoom_vsim_supply, }; -static struct twl4030_hsmmc_info mmc[] __initdata = { +static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "external", .mmc = 1, @@ -175,7 +176,7 @@ static int zoom_twl_gpio_setup(struct device *dev, { /* gpio + 0 is "mmc0_cd" (input/IRQ) */ mmc[0].gpio_cd = gpio + 0; - twl4030_mmc_init(mmc); + omap2_hsmmc_init(mmc); /* link regulators to MMC adapters ... we "know" the * regulators will be set up only *after* we return. @@ -263,9 +264,17 @@ static int __init omap_i2c_init(void) return 0; } +static void enable_board_wakeup_source(void) +{ + /* T2 interrupt line (keypad) */ + omap_mux_init_signal("sys_nirq", + OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP); +} + void __init zoom_peripherals_init(void) { omap_i2c_init(); omap_serial_init(); usb_musb_init(); + enable_board_wakeup_source(); } diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c index bb87cf7878ff..9a26f84b1141 100644 --- a/arch/arm/mach-omap2/board-zoom2.c +++ b/arch/arm/mach-omap2/board-zoom2.c @@ -87,7 +87,7 @@ static void __init omap_zoom2_init(void) static void __init omap_zoom2_map_io(void) { omap2_set_globals_343x(); - omap2_map_common_io(); + omap34xx_map_common_io(); } MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c index a9fe9181b010..5e208942ca71 100644 --- a/arch/arm/mach-omap2/board-zoom3.c +++ b/arch/arm/mach-omap2/board-zoom3.c @@ -26,8 +26,8 @@ static void __init omap_zoom_map_io(void) { - omap2_set_globals_343x(); - omap2_map_common_io(); + omap2_set_globals_36xx(); + omap34xx_map_common_io(); } static struct omap_board_config_kernel zoom_config[] __initdata = { diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c new file mode 100644 index 000000000000..fc32ff8e790f --- /dev/null +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c @@ -0,0 +1,120 @@ +/* + * OMAP2xxx APLL clock control functions + * + * Copyright (C) 2005-2008 Texas Instruments, Inc. + * Copyright (C) 2004-2010 Nokia Corporation + * + * Contacts: + * Richard Woodruff <r-woodruff2@ti.com> + * Paul Walmsley + * + * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, + * Gordon McNutt and RidgeRun, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#undef DEBUG + +#include <linux/kernel.h> +#include <linux/clk.h> +#include <linux/io.h> + +#include <plat/clock.h> +#include <plat/prcm.h> + +#include "clock.h" +#include "clock2xxx.h" +#include "cm.h" +#include "cm-regbits-24xx.h" + +/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ +#define EN_APLL_STOPPED 0 +#define EN_APLL_LOCKED 3 + +/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */ +#define APLLS_CLKIN_19_2MHZ 0 +#define APLLS_CLKIN_13MHZ 2 +#define APLLS_CLKIN_12MHZ 3 + +/* Private functions */ + +/* Enable an APLL if off */ +static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) +{ + u32 cval, apll_mask; + + apll_mask = EN_APLL_LOCKED << clk->enable_bit; + + cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); + + if ((cval & apll_mask) == apll_mask) + return 0; /* apll already enabled */ + + cval &= ~apll_mask; + cval |= apll_mask; + cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); + + omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), status_mask, + clk->name); + + /* + * REVISIT: Should we return an error code if omap2_wait_clock_ready() + * fails? + */ + return 0; +} + +static int omap2_clk_apll96_enable(struct clk *clk) +{ + return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL); +} + +static int omap2_clk_apll54_enable(struct clk *clk) +{ + return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL); +} + +/* Stop APLL */ +static void omap2_clk_apll_disable(struct clk *clk) +{ + u32 cval; + + cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); + cval &= ~(EN_APLL_LOCKED << clk->enable_bit); + cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); +} + +/* Public data */ + +const struct clkops clkops_apll96 = { + .enable = omap2_clk_apll96_enable, + .disable = omap2_clk_apll_disable, +}; + +const struct clkops clkops_apll54 = { + .enable = omap2_clk_apll54_enable, + .disable = omap2_clk_apll_disable, +}; + +/* Public functions */ + +u32 omap2xxx_get_apll_clkin(void) +{ + u32 aplls, srate = 0; + + aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); + aplls &= OMAP24XX_APLLS_CLKIN_MASK; + aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; + + if (aplls == APLLS_CLKIN_19_2MHZ) + srate = 19200000; + else if (aplls == APLLS_CLKIN_13MHZ) + srate = 13000000; + else if (aplls == APLLS_CLKIN_12MHZ) + srate = 12000000; + + return srate; +} + diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c new file mode 100644 index 000000000000..019048434f13 --- /dev/null +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c @@ -0,0 +1,173 @@ +/* + * DPLL + CORE_CLK composite clock functions + * + * Copyright (C) 2005-2008 Texas Instruments, Inc. + * Copyright (C) 2004-2010 Nokia Corporation + * + * Contacts: + * Richard Woodruff <r-woodruff2@ti.com> + * Paul Walmsley + * + * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, + * Gordon McNutt and RidgeRun, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * XXX The DPLL and CORE clocks should be split into two separate clock + * types. + */ +#undef DEBUG + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/clk.h> +#include <linux/io.h> + +#include <plat/clock.h> +#include <plat/sram.h> +#include <plat/sdrc.h> + +#include "clock.h" +#include "clock2xxx.h" +#include "opp2xxx.h" +#include "cm.h" +#include "cm-regbits-24xx.h" + +/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ + +/** + * omap2xxx_clk_get_core_rate - return the CORE_CLK rate + * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck") + * + * Returns the CORE_CLK rate. CORE_CLK can have one of three rate + * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz + * (the latter is unusual). This currently should be called with + * struct clk *dpll_ck, which is a composite clock of dpll_ck and + * core_ck. + */ +unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) +{ + long long core_clk; + u32 v; + + core_clk = omap2_get_dpll_rate(clk); + + v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + v &= OMAP24XX_CORE_CLK_SRC_MASK; + + if (v == CORE_CLK_SRC_32K) + core_clk = 32768; + else + core_clk *= v; + + return core_clk; +} + +/* + * Uses the current prcm set to tell if a rate is valid. + * You can go slower, but not faster within a given rate set. + */ +static long omap2_dpllcore_round_rate(unsigned long target_rate) +{ + u32 high, low, core_clk_src; + + core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; + + if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ + high = curr_prcm_set->dpll_speed * 2; + low = curr_prcm_set->dpll_speed; + } else { /* DPLL clockout x 2 */ + high = curr_prcm_set->dpll_speed; + low = curr_prcm_set->dpll_speed / 2; + } + +#ifdef DOWN_VARIABLE_DPLL + if (target_rate > high) + return high; + else + return target_rate; +#else + if (target_rate > low) + return high; + else + return low; +#endif + +} + +unsigned long omap2_dpllcore_recalc(struct clk *clk) +{ + return omap2xxx_clk_get_core_rate(clk); +} + +int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) +{ + u32 cur_rate, low, mult, div, valid_rate, done_rate; + u32 bypass = 0; + struct prcm_config tmpset; + const struct dpll_data *dd; + + cur_rate = omap2xxx_clk_get_core_rate(dclk); + mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + mult &= OMAP24XX_CORE_CLK_SRC_MASK; + + if ((rate == (cur_rate / 2)) && (mult == 2)) { + omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); + } else if ((rate == (cur_rate * 2)) && (mult == 1)) { + omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); + } else if (rate != cur_rate) { + valid_rate = omap2_dpllcore_round_rate(rate); + if (valid_rate != rate) + return -EINVAL; + + if (mult == 1) + low = curr_prcm_set->dpll_speed; + else + low = curr_prcm_set->dpll_speed / 2; + + dd = clk->dpll_data; + if (!dd) + return -EINVAL; + + tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); + tmpset.cm_clksel1_pll &= ~(dd->mult_mask | + dd->div1_mask); + div = ((curr_prcm_set->xtal_speed / 1000000) - 1); + tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; + if (rate > low) { + tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; + mult = ((rate / 2) / 1000000); + done_rate = CORE_CLK_SRC_DPLL_X2; + } else { + tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL; + mult = (rate / 1000000); + done_rate = CORE_CLK_SRC_DPLL; + } + tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask)); + tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); + + /* Worst case */ + tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS; + + if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ + bypass = 1; + + /* For omap2xxx_sdrc_init_params() */ + omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); + + /* Force dll lock mode */ + omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, + bypass); + + /* Errata: ret dll entry state */ + omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); + omap2xxx_sdrc_reprogram(done_rate, 0); + } + + return 0; +} + diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c new file mode 100644 index 000000000000..2167be84a5bc --- /dev/null +++ b/arch/arm/mach-omap2/clkt2xxx_osc.c @@ -0,0 +1,62 @@ +/* + * OMAP2xxx osc_clk-specific clock code + * + * Copyright (C) 2005-2008 Texas Instruments, Inc. + * Copyright (C) 2004-2010 Nokia Corporation + * + * Contacts: + * Richard Woodruff <r-woodruff2@ti.com> + * Paul Walmsley + * + * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, + * Gordon McNutt and RidgeRun, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#undef DEBUG + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/clk.h> +#include <linux/io.h> + +#include <plat/clock.h> + +#include "clock.h" +#include "clock2xxx.h" +#include "prm.h" +#include "prm-regbits-24xx.h" + +static int omap2_enable_osc_ck(struct clk *clk) +{ + u32 pcc; + + pcc = __raw_readl(prcm_clksrc_ctrl); + + __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); + + return 0; +} + +static void omap2_disable_osc_ck(struct clk *clk) +{ + u32 pcc; + + pcc = __raw_readl(prcm_clksrc_ctrl); + + __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); +} + +const struct clkops clkops_oscck = { + .enable = omap2_enable_osc_ck, + .disable = omap2_disable_osc_ck, +}; + +unsigned long omap2_osc_clk_recalc(struct clk *clk) +{ + return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv(); +} + diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c new file mode 100644 index 000000000000..822b5a79f457 --- /dev/null +++ b/arch/arm/mach-omap2/clkt2xxx_sys.c @@ -0,0 +1,50 @@ +/* + * OMAP2xxx sys_clk-specific clock code + * + * Copyright (C) 2005-2008 Texas Instruments, Inc. + * Copyright (C) 2004-2010 Nokia Corporation + * + * Contacts: + * Richard Woodruff <r-woodruff2@ti.com> + * Paul Walmsley + * + * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, + * Gordon McNutt and RidgeRun, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#undef DEBUG + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/clk.h> +#include <linux/io.h> + +#include <plat/clock.h> + +#include "clock.h" +#include "clock2xxx.h" +#include "prm.h" +#include "prm-regbits-24xx.h" + +void __iomem *prcm_clksrc_ctrl; + +u32 omap2xxx_get_sysclkdiv(void) +{ + u32 div; + + div = __raw_readl(prcm_clksrc_ctrl); + div &= OMAP_SYSCLKDIV_MASK; + div >>= OMAP_SYSCLKDIV_SHIFT; + + return div; +} + +unsigned long omap2xxx_sys_clk_recalc(struct clk *clk) +{ + return clk->parent->rate / omap2xxx_get_sysclkdiv(); +} + + diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c new file mode 100644 index 000000000000..3b1eac4d5390 --- /dev/null +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -0,0 +1,254 @@ +/* + * OMAP2xxx DVFS virtual clock functions + * + * Copyright (C) 2005-2008 Texas Instruments, Inc. + * Copyright (C) 2004-2010 Nokia Corporation + * + * Contacts: + * Richard Woodruff <r-woodruff2@ti.com> + * Paul Walmsley + * + * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, + * Gordon McNutt and RidgeRun, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * XXX Some of this code should be replaceable by the upcoming OPP layer + * code. However, some notion of "rate set" is probably still necessary + * for OMAP2xxx at least. Rate sets should be generalized so they can be + * used for any OMAP chip, not just OMAP2xxx. In particular, Richard Woodruff + * has in the past expressed a preference to use rate sets for OPP changes, + * rather than dynamically recalculating the clock tree, so if someone wants + * this badly enough to write the code to handle it, we should support it + * as an option. + */ +#undef DEBUG + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/cpufreq.h> + +#include <plat/clock.h> +#include <plat/sram.h> +#include <plat/sdrc.h> + +#include "clock.h" +#include "clock2xxx.h" +#include "opp2xxx.h" +#include "cm.h" +#include "cm-regbits-24xx.h" + +const struct prcm_config *curr_prcm_set; +const struct prcm_config *rate_table; + +/** + * omap2_table_mpu_recalc - just return the MPU speed + * @clk: virt_prcm_set struct clk + * + * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. + */ +unsigned long omap2_table_mpu_recalc(struct clk *clk) +{ + return curr_prcm_set->mpu_speed; +} + +/* + * Look for a rate equal or less than the target rate given a configuration set. + * + * What's not entirely clear is "which" field represents the key field. + * Some might argue L3-DDR, others ARM, others IVA. This code is simple and + * just uses the ARM rates. + */ +long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) +{ + const struct prcm_config *ptr; + long highest_rate; + long sys_ck_rate; + + sys_ck_rate = clk_get_rate(sclk); + + highest_rate = -EINVAL; + + for (ptr = rate_table; ptr->mpu_speed; ptr++) { + if (!(ptr->flags & cpu_mask)) + continue; + if (ptr->xtal_speed != sys_ck_rate) + continue; + + highest_rate = ptr->mpu_speed; + + /* Can check only after xtal frequency check */ + if (ptr->mpu_speed <= rate) + break; + } + return highest_rate; +} + +/* Sets basic clocks based on the specified rate */ +int omap2_select_table_rate(struct clk *clk, unsigned long rate) +{ + u32 cur_rate, done_rate, bypass = 0, tmp; + const struct prcm_config *prcm; + unsigned long found_speed = 0; + unsigned long flags; + long sys_ck_rate; + + sys_ck_rate = clk_get_rate(sclk); + + for (prcm = rate_table; prcm->mpu_speed; prcm++) { + if (!(prcm->flags & cpu_mask)) + continue; + + if (prcm->xtal_speed != sys_ck_rate) + continue; + + if (prcm->mpu_speed <= rate) { + found_speed = prcm->mpu_speed; + break; + } + } + + if (!found_speed) { + printk(KERN_INFO "Could not set MPU rate to %luMHz\n", + rate / 1000000); + return -EINVAL; + } + + curr_prcm_set = prcm; + cur_rate = omap2xxx_clk_get_core_rate(dclk); + + if (prcm->dpll_speed == cur_rate / 2) { + omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); + } else if (prcm->dpll_speed == cur_rate * 2) { + omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); + } else if (prcm->dpll_speed != cur_rate) { + local_irq_save(flags); + + if (prcm->dpll_speed == prcm->xtal_speed) + bypass = 1; + + if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) == + CORE_CLK_SRC_DPLL_X2) + done_rate = CORE_CLK_SRC_DPLL_X2; + else + done_rate = CORE_CLK_SRC_DPLL; + + /* MPU divider */ + cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); + + /* dsp + iva1 div(2420), iva2.1(2430) */ + cm_write_mod_reg(prcm->cm_clksel_dsp, + OMAP24XX_DSP_MOD, CM_CLKSEL); + + cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); + + /* Major subsystem dividers */ + tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; + cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, + CM_CLKSEL1); + + if (cpu_is_omap2430()) + cm_write_mod_reg(prcm->cm_clksel_mdm, + OMAP2430_MDM_MOD, CM_CLKSEL); + + /* x2 to enter omap2xxx_sdrc_init_params() */ + omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); + + omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, + bypass); + + omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); + omap2xxx_sdrc_reprogram(done_rate, 0); + + local_irq_restore(flags); + } + + return 0; +} + +#ifdef CONFIG_CPU_FREQ +/* + * Walk PRCM rate table and fillout cpufreq freq_table + * XXX This should be replaced by an OPP layer in the near future + */ +static struct cpufreq_frequency_table *freq_table; + +void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table) +{ + const struct prcm_config *prcm; + long sys_ck_rate; + int i = 0; + int tbl_sz = 0; + + if (!cpu_is_omap24xx()) + return; + + sys_ck_rate = clk_get_rate(sclk); + + for (prcm = rate_table; prcm->mpu_speed; prcm++) { + if (!(prcm->flags & cpu_mask)) + continue; + if (prcm->xtal_speed != sys_ck_rate) + continue; + + /* don't put bypass rates in table */ + if (prcm->dpll_speed == prcm->xtal_speed) + continue; + + tbl_sz++; + } + + /* + * XXX Ensure that we're doing what CPUFreq expects for this error + * case and the following one + */ + if (tbl_sz == 0) { + pr_warning("%s: no matching entries in rate_table\n", + __func__); + return; + } + + /* Include the CPUFREQ_TABLE_END terminator entry */ + tbl_sz++; + + freq_table = kzalloc(sizeof(struct cpufreq_frequency_table) * tbl_sz, + GFP_ATOMIC); + if (!freq_table) { + pr_err("%s: could not kzalloc frequency table\n", __func__); + return; + } + + for (prcm = rate_table; prcm->mpu_speed; prcm++) { + if (!(prcm->flags & cpu_mask)) + continue; + if (prcm->xtal_speed != sys_ck_rate) + continue; + + /* don't put bypass rates in table */ + if (prcm->dpll_speed == prcm->xtal_speed) + continue; + + freq_table[i].index = i; + freq_table[i].frequency = prcm->mpu_speed / 1000; + i++; + } + + freq_table[i].index = i; + freq_table[i].frequency = CPUFREQ_TABLE_END; + + *table = &freq_table[0]; +} + +void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table) +{ + if (!cpu_is_omap24xx()) + return; + + kfree(freq_table); +} + +#endif diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c new file mode 100644 index 000000000000..8716a01d1f5b --- /dev/null +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -0,0 +1,120 @@ +/* + * OMAP34xx M2 divider clock code + * + * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2010 Nokia Corporation + * + * Paul Walmsley + * Jouni Högander + * + * Parts of this code are based on code written by + * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#undef DEBUG + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/clk.h> +#include <linux/io.h> + +#include <plat/clock.h> +#include <plat/sram.h> +#include <plat/sdrc.h> + +#include "clock.h" +#include "clock34xx.h" +#include "sdrc.h" + +#define CYCLES_PER_MHZ 1000000 + +/* + * CORE DPLL (DPLL3) M2 divider rate programming functions + * + * These call into SRAM code to do the actual CM writes, since the SDRAM + * is clocked from DPLL3. + */ + +/** + * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider + * @clk: struct clk * of DPLL to set + * @rate: rounded target rate + * + * Program the DPLL M2 divider with the rounded target rate. Returns + * -EINVAL upon error, or 0 upon success. + */ +int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) +{ + u32 new_div = 0; + u32 unlock_dll = 0; + u32 c; + unsigned long validrate, sdrcrate, _mpurate; + struct omap_sdrc_params *sdrc_cs0; + struct omap_sdrc_params *sdrc_cs1; + int ret; + + if (!clk || !rate) + return -EINVAL; + + validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); + if (validrate != rate) + return -EINVAL; + + sdrcrate = sdrc_ick_p->rate; + if (rate > clk->rate) + sdrcrate <<= ((rate / clk->rate) >> 1); + else + sdrcrate >>= ((clk->rate / rate) >> 1); + + ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1); + if (ret) + return -EINVAL; + + if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) { + pr_debug("clock: will unlock SDRC DLL\n"); + unlock_dll = 1; + } + + /* + * XXX This only needs to be done when the CPU frequency changes + */ + _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ; + c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; + c += 1; /* for safety */ + c *= SDRC_MPURATE_LOOPS; + c >>= SDRC_MPURATE_SCALE; + if (c == 0) + c = 1; + + pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, + validrate); + pr_debug("clock: SDRC CS0 timing params used:" + " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", + sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, + sdrc_cs0->actim_ctrlb, sdrc_cs0->mr); + if (sdrc_cs1) + pr_debug("clock: SDRC CS1 timing params used: " + " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", + sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, + sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); + + if (sdrc_cs1) + omap3_configure_core_dpll( + new_div, unlock_dll, c, rate > clk->rate, + sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, + sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, + sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, + sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); + else + omap3_configure_core_dpll( + new_div, unlock_dll, c, rate > clk->rate, + sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, + sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, + 0, 0, 0, 0); + + return 0; +} + diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c new file mode 100644 index 000000000000..25a2363106de --- /dev/null +++ b/arch/arm/mach-omap2/clkt_clksel.c @@ -0,0 +1,417 @@ +/* + * clkt_clksel.c - OMAP2/3/4 clksel clock functions + * + * Copyright (C) 2005-2008 Texas Instruments, Inc. + * Copyright (C) 2004-2010 Nokia Corporation + * + * Contacts: + * Richard Woodruff <r-woodruff2@ti.com> + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * XXX At some point these clksel clocks should be split into + * "divider" clocks and "mux" clocks to better match the hardware. + * + * XXX Currently these clocks are only used in the OMAP2/3/4 code, but + * many of the OMAP1 clocks should be convertible to use this + * mechanism. + */ +#undef DEBUG + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/clk.h> +#include <linux/io.h> + +#include <plat/clock.h> + +#include "clock.h" +#include "cm.h" +#include "cm-regbits-24xx.h" +#include "cm-regbits-34xx.h" + +/* Private functions */ + +/** + * _omap2_get_clksel_by_parent - return clksel struct for a given clk & parent + * @clk: OMAP struct clk ptr to inspect + * @src_clk: OMAP struct clk ptr of the parent clk to search for + * + * Scan the struct clksel array associated with the clock to find + * the element associated with the supplied parent clock address. + * Returns a pointer to the struct clksel on success or NULL on error. + */ +static const struct clksel *_omap2_get_clksel_by_parent(struct clk *clk, + struct clk *src_clk) +{ + const struct clksel *clks; + + if (!clk->clksel) + return NULL; + + for (clks = clk->clksel; clks->parent; clks++) { + if (clks->parent == src_clk) + break; /* Found the requested parent */ + } + + if (!clks->parent) { + printk(KERN_ERR "clock: Could not find parent clock %s in " + "clksel array of clock %s\n", src_clk->name, + clk->name); + return NULL; + } + + return clks; +} + +/* + * Converts encoded control register address into a full address + * On error, the return value (parent_div) will be 0. + */ +static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk, + u32 *field_val) +{ + const struct clksel *clks; + const struct clksel_rate *clkr; + + clks = _omap2_get_clksel_by_parent(clk, src_clk); + if (!clks) + return 0; + + for (clkr = clks->rates; clkr->div; clkr++) { + if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE) + break; /* Found the default rate for this platform */ + } + + if (!clkr->div) { + printk(KERN_ERR "clock: Could not find default rate for " + "clock %s parent %s\n", clk->name, + src_clk->parent->name); + return 0; + } + + /* Should never happen. Add a clksel mask to the struct clk. */ + WARN_ON(clk->clksel_mask == 0); + + *field_val = clkr->val; + + return clkr->div; +} + + +/* Public functions */ + +/** + * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware + * @clk: OMAP clock struct ptr to use + * + * Given a pointer to a source-selectable struct clk, read the hardware + * register and determine what its parent is currently set to. Update the + * clk->parent field with the appropriate clk ptr. + */ +void omap2_init_clksel_parent(struct clk *clk) +{ + const struct clksel *clks; + const struct clksel_rate *clkr; + u32 r, found = 0; + + if (!clk->clksel) + return; + + r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; + r >>= __ffs(clk->clksel_mask); + + for (clks = clk->clksel; clks->parent && !found; clks++) { + for (clkr = clks->rates; clkr->div && !found; clkr++) { + if ((clkr->flags & cpu_mask) && (clkr->val == r)) { + if (clk->parent != clks->parent) { + pr_debug("clock: inited %s parent " + "to %s (was %s)\n", + clk->name, clks->parent->name, + ((clk->parent) ? + clk->parent->name : "NULL")); + clk_reparent(clk, clks->parent); + }; + found = 1; + } + } + } + + if (!found) + printk(KERN_ERR "clock: init parent: could not find " + "regval %0x for clock %s\n", r, clk->name); + + return; +} + +/* + * Used for clocks that are part of CLKSEL_xyz governed clocks. + * REVISIT: Maybe change to use clk->enable() functions like on omap1? + */ +unsigned long omap2_clksel_recalc(struct clk *clk) +{ + unsigned long rate; + u32 div = 0; + + pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); + + div = omap2_clksel_get_divisor(clk); + if (div == 0) + return clk->rate; + + rate = clk->parent->rate / div; + + pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div); + + return rate; +} + +/** + * omap2_clksel_round_rate_div - find divisor for the given clock and rate + * @clk: OMAP struct clk to use + * @target_rate: desired clock rate + * @new_div: ptr to where we should store the divisor + * + * Finds 'best' divider value in an array based on the source and target + * rates. The divider array must be sorted with smallest divider first. + * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, + * they are only settable as part of virtual_prcm set. + * + * Returns the rounded clock rate or returns 0xffffffff on error. + */ +u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, + u32 *new_div) +{ + unsigned long test_rate; + const struct clksel *clks; + const struct clksel_rate *clkr; + u32 last_div = 0; + + pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", + clk->name, target_rate); + + *new_div = 1; + + clks = _omap2_get_clksel_by_parent(clk, clk->parent); + if (!clks) + return ~0; + + for (clkr = clks->rates; clkr->div; clkr++) { + if (!(clkr->flags & cpu_mask)) + continue; + + /* Sanity check */ + if (clkr->div <= last_div) + pr_err("clock: clksel_rate table not sorted " + "for clock %s", clk->name); + + last_div = clkr->div; + + test_rate = clk->parent->rate / clkr->div; + + if (test_rate <= target_rate) + break; /* found it */ + } + + if (!clkr->div) { + pr_err("clock: Could not find divisor for target " + "rate %ld for clock %s parent %s\n", target_rate, + clk->name, clk->parent->name); + return ~0; + } + + *new_div = clkr->div; + + pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, + (clk->parent->rate / clkr->div)); + + return clk->parent->rate / clkr->div; +} + +/** + * omap2_clksel_round_rate - find rounded rate for the given clock and rate + * @clk: OMAP struct clk to use + * @target_rate: desired clock rate + * + * Compatibility wrapper for OMAP clock framework + * Finds best target rate based on the source clock and possible dividers. + * rates. The divider array must be sorted with smallest divider first. + * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, + * they are only settable as part of virtual_prcm set. + * + * Returns the rounded clock rate or returns 0xffffffff on error. + */ +long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) +{ + u32 new_div; + + return omap2_clksel_round_rate_div(clk, target_rate, &new_div); +} + + +/* Given a clock and a rate apply a clock specific rounding function */ +long omap2_clk_round_rate(struct clk *clk, unsigned long rate) +{ + if (clk->round_rate) + return clk->round_rate(clk, rate); + + if (clk->flags & RATE_FIXED) + printk(KERN_ERR "clock: generic omap2_clk_round_rate called " + "on fixed-rate clock %s\n", clk->name); + + return clk->rate; +} + +/** + * omap2_clksel_to_divisor() - turn clksel field value into integer divider + * @clk: OMAP struct clk to use + * @field_val: register field value to find + * + * Given a struct clk of a rate-selectable clksel clock, and a register field + * value to search for, find the corresponding clock divisor. The register + * field value should be pre-masked and shifted down so the LSB is at bit 0 + * before calling. Returns 0 on error + */ +u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val) +{ + const struct clksel *clks; + const struct clksel_rate *clkr; + + clks = _omap2_get_clksel_by_parent(clk, clk->parent); + if (!clks) + return 0; + + for (clkr = clks->rates; clkr->div; clkr++) { + if ((clkr->flags & cpu_mask) && (clkr->val == field_val)) + break; + } + + if (!clkr->div) { + printk(KERN_ERR "clock: Could not find fieldval %d for " + "clock %s parent %s\n", field_val, clk->name, + clk->parent->name); + return 0; + } + + return clkr->div; +} + +/** + * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value + * @clk: OMAP struct clk to use + * @div: integer divisor to search for + * + * Given a struct clk of a rate-selectable clksel clock, and a clock divisor, + * find the corresponding register field value. The return register value is + * the value before left-shifting. Returns ~0 on error + */ +u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) +{ + const struct clksel *clks; + const struct clksel_rate *clkr; + + /* should never happen */ + WARN_ON(div == 0); + + clks = _omap2_get_clksel_by_parent(clk, clk->parent); + if (!clks) + return ~0; + + for (clkr = clks->rates; clkr->div; clkr++) { + if ((clkr->flags & cpu_mask) && (clkr->div == div)) + break; + } + + if (!clkr->div) { + printk(KERN_ERR "clock: Could not find divisor %d for " + "clock %s parent %s\n", div, clk->name, + clk->parent->name); + return ~0; + } + + return clkr->val; +} + +/** + * omap2_clksel_get_divisor - get current divider applied to parent clock. + * @clk: OMAP struct clk to use. + * + * Returns the integer divisor upon success or 0 on error. + */ +u32 omap2_clksel_get_divisor(struct clk *clk) +{ + u32 v; + + if (!clk->clksel_mask) + return 0; + + v = __raw_readl(clk->clksel_reg) & clk->clksel_mask; + v >>= __ffs(clk->clksel_mask); + + return omap2_clksel_to_divisor(clk, v); +} + +int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) +{ + u32 v, field_val, validrate, new_div = 0; + + if (!clk->clksel_mask) + return -EINVAL; + + validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); + if (validrate != rate) + return -EINVAL; + + field_val = omap2_divisor_to_clksel(clk, new_div); + if (field_val == ~0) + return -EINVAL; + + v = __raw_readl(clk->clksel_reg); + v &= ~clk->clksel_mask; + v |= field_val << __ffs(clk->clksel_mask); + __raw_writel(v, clk->clksel_reg); + v = __raw_readl(clk->clksel_reg); /* OCP barrier */ + + clk->rate = clk->parent->rate / new_div; + + omap2xxx_clk_commit(clk); + + return 0; +} + +int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) +{ + u32 field_val, v, parent_div; + + if (!clk->clksel) + return -EINVAL; + + parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val); + if (!parent_div) + return -EINVAL; + + /* Set new source value (previous dividers if any in effect) */ + v = __raw_readl(clk->clksel_reg); + v &= ~clk->clksel_mask; + v |= field_val << __ffs(clk->clksel_mask); + __raw_writel(v, clk->clksel_reg); + v = __raw_readl(clk->clksel_reg); /* OCP barrier */ + + omap2xxx_clk_commit(clk); + + clk_reparent(clk, new_parent); + + /* CLKSEL clocks follow their parents' rates, divided by a divisor */ + clk->rate = new_parent->rate; + + if (parent_div > 0) + clk->rate /= parent_div; + + pr_debug("clock: set parent of %s to %s (new rate %ld)\n", + clk->name, clk->parent->name, clk->rate); + + return 0; +} diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c new file mode 100644 index 000000000000..9eee0e67d5d6 --- /dev/null +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -0,0 +1,386 @@ +/* + * OMAP2/3/4 DPLL clock functions + * + * Copyright (C) 2005-2008 Texas Instruments, Inc. + * Copyright (C) 2004-2010 Nokia Corporation + * + * Contacts: + * Richard Woodruff <r-woodruff2@ti.com> + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#undef DEBUG + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/clk.h> +#include <linux/io.h> + +#include <asm/div64.h> + +#include <plat/clock.h> + +#include "clock.h" +#include "cm.h" +#include "cm-regbits-24xx.h" +#include "cm-regbits-34xx.h" + +/* DPLL rate rounding: minimum DPLL multiplier, divider values */ +#define DPLL_MIN_MULTIPLIER 1 +#define DPLL_MIN_DIVIDER 1 + +/* Possible error results from _dpll_test_mult */ +#define DPLL_MULT_UNDERFLOW -1 + +/* + * Scale factor to mitigate roundoff errors in DPLL rate rounding. + * The higher the scale factor, the greater the risk of arithmetic overflow, + * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR + * must be a power of DPLL_SCALE_BASE. + */ +#define DPLL_SCALE_FACTOR 64 +#define DPLL_SCALE_BASE 2 +#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ + (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) + +/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ +#define DPLL_FINT_BAND1_MIN 750000 +#define DPLL_FINT_BAND1_MAX 2100000 +#define DPLL_FINT_BAND2_MIN 7500000 +#define DPLL_FINT_BAND2_MAX 21000000 + +/* _dpll_test_fint() return codes */ +#define DPLL_FINT_UNDERFLOW -1 +#define DPLL_FINT_INVALID -2 + +/* Private functions */ + +/* + * _dpll_test_fint - test whether an Fint value is valid for the DPLL + * @clk: DPLL struct clk to test + * @n: divider value (N) to test + * + * Tests whether a particular divider @n will result in a valid DPLL + * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter + * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate + * (assuming that it is counting N upwards), or -2 if the enclosing loop + * should skip to the next iteration (again assuming N is increasing). + */ +static int _dpll_test_fint(struct clk *clk, u8 n) +{ + struct dpll_data *dd; + long fint; + int ret = 0; + + dd = clk->dpll_data; + + /* DPLL divider must result in a valid jitter correction val */ + fint = clk->parent->rate / (n + 1); + if (fint < DPLL_FINT_BAND1_MIN) { + + pr_debug("rejecting n=%d due to Fint failure, " + "lowering max_divider\n", n); + dd->max_divider = n; + ret = DPLL_FINT_UNDERFLOW; + + } else if (fint > DPLL_FINT_BAND1_MAX && + fint < DPLL_FINT_BAND2_MIN) { + + pr_debug("rejecting n=%d due to Fint failure\n", n); + ret = DPLL_FINT_INVALID; + + } else if (fint > DPLL_FINT_BAND2_MAX) { + + pr_debug("rejecting n=%d due to Fint failure, " + "boosting min_divider\n", n); + dd->min_divider = n; + ret = DPLL_FINT_INVALID; + + } + + return ret; +} + +static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, + unsigned int m, unsigned int n) +{ + unsigned long long num; + + num = (unsigned long long)parent_rate * m; + do_div(num, n); + return num; +} + +/* + * _dpll_test_mult - test a DPLL multiplier value + * @m: pointer to the DPLL m (multiplier) value under test + * @n: current DPLL n (divider) value under test + * @new_rate: pointer to storage for the resulting rounded rate + * @target_rate: the desired DPLL rate + * @parent_rate: the DPLL's parent clock rate + * + * This code tests a DPLL multiplier value, ensuring that the + * resulting rate will not be higher than the target_rate, and that + * the multiplier value itself is valid for the DPLL. Initially, the + * integer pointed to by the m argument should be prescaled by + * multiplying by DPLL_SCALE_FACTOR. The code will replace this with + * a non-scaled m upon return. This non-scaled m will result in a + * new_rate as close as possible to target_rate (but not greater than + * target_rate) given the current (parent_rate, n, prescaled m) + * triple. Returns DPLL_MULT_UNDERFLOW in the event that the + * non-scaled m attempted to underflow, which can allow the calling + * function to bail out early; or 0 upon success. + */ +static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, + unsigned long target_rate, + unsigned long parent_rate) +{ + int r = 0, carry = 0; + + /* Unscale m and round if necessary */ + if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) + carry = 1; + *m = (*m / DPLL_SCALE_FACTOR) + carry; + + /* + * The new rate must be <= the target rate to avoid programming + * a rate that is impossible for the hardware to handle + */ + *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); + if (*new_rate > target_rate) { + (*m)--; + *new_rate = 0; + } + + /* Guard against m underflow */ + if (*m < DPLL_MIN_MULTIPLIER) { + *m = DPLL_MIN_MULTIPLIER; + *new_rate = 0; + r = DPLL_MULT_UNDERFLOW; + } + + if (*new_rate == 0) + *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); + + return r; +} + +/* Public functions */ + +void omap2_init_dpll_parent(struct clk *clk) +{ + u32 v; + struct dpll_data *dd; + + dd = clk->dpll_data; + if (!dd) + return; + + /* Return bypass rate if DPLL is bypassed */ + v = __raw_readl(dd->control_reg); + v &= dd->enable_mask; + v >>= __ffs(dd->enable_mask); + + /* Reparent in case the dpll is in bypass */ + if (cpu_is_omap24xx()) { + if (v == OMAP2XXX_EN_DPLL_LPBYPASS || + v == OMAP2XXX_EN_DPLL_FRBYPASS) + clk_reparent(clk, dd->clk_bypass); + } else if (cpu_is_omap34xx()) { + if (v == OMAP3XXX_EN_DPLL_LPBYPASS || + v == OMAP3XXX_EN_DPLL_FRBYPASS) + clk_reparent(clk, dd->clk_bypass); + } else if (cpu_is_omap44xx()) { + if (v == OMAP4XXX_EN_DPLL_LPBYPASS || + v == OMAP4XXX_EN_DPLL_FRBYPASS || + v == OMAP4XXX_EN_DPLL_MNBYPASS) + clk_reparent(clk, dd->clk_bypass); + } + return; +} + +/** + * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate + * @clk: struct clk * of a DPLL + * + * DPLLs can be locked or bypassed - basically, enabled or disabled. + * When locked, the DPLL output depends on the M and N values. When + * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock + * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and + * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively + * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk. + * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is + * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 + * if the clock @clk is not a DPLL. + */ +u32 omap2_get_dpll_rate(struct clk *clk) +{ + long long dpll_clk; + u32 dpll_mult, dpll_div, v; + struct dpll_data *dd; + + dd = clk->dpll_data; + if (!dd) + return 0; + + /* Return bypass rate if DPLL is bypassed */ + v = __raw_readl(dd->control_reg); + v &= dd->enable_mask; + v >>= __ffs(dd->enable_mask); + + if (cpu_is_omap24xx()) { + if (v == OMAP2XXX_EN_DPLL_LPBYPASS || + v == OMAP2XXX_EN_DPLL_FRBYPASS) + return dd->clk_bypass->rate; + } else if (cpu_is_omap34xx()) { + if (v == OMAP3XXX_EN_DPLL_LPBYPASS || + v == OMAP3XXX_EN_DPLL_FRBYPASS) + return dd->clk_bypass->rate; + } else if (cpu_is_omap44xx()) { + if (v == OMAP4XXX_EN_DPLL_LPBYPASS || + v == OMAP4XXX_EN_DPLL_FRBYPASS || + v == OMAP4XXX_EN_DPLL_MNBYPASS) + return dd->clk_bypass->rate; + } + + v = __raw_readl(dd->mult_div1_reg); + dpll_mult = v & dd->mult_mask; + dpll_mult >>= __ffs(dd->mult_mask); + dpll_div = v & dd->div1_mask; + dpll_div >>= __ffs(dd->div1_mask); + + dpll_clk = (long long)dd->clk_ref->rate * dpll_mult; + do_div(dpll_clk, dpll_div + 1); + + return dpll_clk; +} + +/* DPLL rate rounding code */ + +/** + * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding + * @clk: struct clk * of the DPLL + * @tolerance: maximum rate error tolerance + * + * Set the maximum DPLL rate error tolerance for the rate rounding + * algorithm. The rate tolerance is an attempt to balance DPLL power + * saving (the least divider value "n") vs. rate fidelity (the least + * difference between the desired DPLL target rate and the rounded + * rate out of the algorithm). So, increasing the tolerance is likely + * to decrease DPLL power consumption and increase DPLL rate error. + * Returns -EINVAL if provided a null clock ptr or a clk that is not a + * DPLL; or 0 upon success. + */ +int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance) +{ + if (!clk || !clk->dpll_data) + return -EINVAL; + + clk->dpll_data->rate_tolerance = tolerance; + + return 0; +} + +/** + * omap2_dpll_round_rate - round a target rate for an OMAP DPLL + * @clk: struct clk * for a DPLL + * @target_rate: desired DPLL clock rate + * + * Given a DPLL, a desired target rate, and a rate tolerance, round + * the target rate to a possible, programmable rate for this DPLL. + * Rate tolerance is assumed to be set by the caller before this + * function is called. Attempts to select the minimum possible n + * within the tolerance to reduce power consumption. Stores the + * computed (m, n) in the DPLL's dpll_data structure so set_rate() + * will not need to call this (expensive) function again. Returns ~0 + * if the target rate cannot be rounded, either because the rate is + * too low or because the rate tolerance is set too tightly; or the + * rounded rate upon success. + */ +long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) +{ + int m, n, r, e, scaled_max_m; + unsigned long scaled_rt_rp, new_rate; + int min_e = -1, min_e_m = -1, min_e_n = -1; + struct dpll_data *dd; + + if (!clk || !clk->dpll_data) + return ~0; + + dd = clk->dpll_data; + + pr_debug("clock: starting DPLL round_rate for clock %s, target rate " + "%ld\n", clk->name, target_rate); + + scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR); + scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; + + dd->last_rounded_rate = 0; + + for (n = dd->min_divider; n <= dd->max_divider; n++) { + + /* Is the (input clk, divider) pair valid for the DPLL? */ + r = _dpll_test_fint(clk, n); + if (r == DPLL_FINT_UNDERFLOW) + break; + else if (r == DPLL_FINT_INVALID) + continue; + + /* Compute the scaled DPLL multiplier, based on the divider */ + m = scaled_rt_rp * n; + + /* + * Since we're counting n up, a m overflow means we + * can bail out completely (since as n increases in + * the next iteration, there's no way that m can + * increase beyond the current m) + */ + if (m > scaled_max_m) + break; + + r = _dpll_test_mult(&m, n, &new_rate, target_rate, + dd->clk_ref->rate); + + /* m can't be set low enough for this n - try with a larger n */ + if (r == DPLL_MULT_UNDERFLOW) + continue; + + e = target_rate - new_rate; + pr_debug("clock: n = %d: m = %d: rate error is %d " + "(new_rate = %ld)\n", n, m, e, new_rate); + + if (min_e == -1 || + min_e >= (int)(abs(e) - dd->rate_tolerance)) { + min_e = e; + min_e_m = m; + min_e_n = n; + + pr_debug("clock: found new least error %d\n", min_e); + + /* We found good settings -- bail out now */ + if (min_e <= dd->rate_tolerance) + break; + } + } + + if (min_e < 0) { + pr_debug("clock: error: target rate or tolerance too low\n"); + return ~0; + } + + dd->last_rounded_m = min_e_m; + dd->last_rounded_n = min_e_n; + dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate, + min_e_m, min_e_n); + + pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", + min_e, min_e_m, min_e_n); + pr_debug("clock: final rate: %ld (target rate: %ld)\n", + dd->last_rounded_rate, target_rate); + + return dd->last_rounded_rate; +} + diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 759c72a48f7f..999b91e023b1 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -28,10 +28,7 @@ #include <plat/clockdomain.h> #include <plat/cpu.h> #include <plat/prcm.h> -#include <asm/div64.h> -#include <plat/sdrc.h> -#include "sdrc.h" #include "clock.h" #include "prm.h" #include "prm-regbits-24xx.h" @@ -39,81 +36,66 @@ #include "cm-regbits-24xx.h" #include "cm-regbits-34xx.h" -/* DPLL rate rounding: minimum DPLL multiplier, divider values */ -#define DPLL_MIN_MULTIPLIER 1 -#define DPLL_MIN_DIVIDER 1 - -/* Possible error results from _dpll_test_mult */ -#define DPLL_MULT_UNDERFLOW -1 - -/* - * Scale factor to mitigate roundoff errors in DPLL rate rounding. - * The higher the scale factor, the greater the risk of arithmetic overflow, - * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR - * must be a power of DPLL_SCALE_BASE. - */ -#define DPLL_SCALE_FACTOR 64 -#define DPLL_SCALE_BASE 2 -#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ - (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) - -/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ -#define DPLL_FINT_BAND1_MIN 750000 -#define DPLL_FINT_BAND1_MAX 2100000 -#define DPLL_FINT_BAND2_MIN 7500000 -#define DPLL_FINT_BAND2_MAX 21000000 - -/* _dpll_test_fint() return codes */ -#define DPLL_FINT_UNDERFLOW -1 -#define DPLL_FINT_INVALID -2 - u8 cpu_mask; /*------------------------------------------------------------------------- * OMAP2/3/4 specific clock functions *-------------------------------------------------------------------------*/ -void omap2_init_dpll_parent(struct clk *clk) +/* Private functions */ + +/** + * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE + * @clk: struct clk * belonging to the module + * + * If the necessary clocks for the OMAP hardware IP block that + * corresponds to clock @clk are enabled, then wait for the module to + * indicate readiness (i.e., to leave IDLE). This code does not + * belong in the clock code and will be moved in the medium term to + * module-dependent code. No return value. + */ +static void _omap2_module_wait_ready(struct clk *clk) { - u32 v; - struct dpll_data *dd; + void __iomem *companion_reg, *idlest_reg; + u8 other_bit, idlest_bit; - dd = clk->dpll_data; - if (!dd) - return; + /* Not all modules have multiple clocks that their IDLEST depends on */ + if (clk->ops->find_companion) { + clk->ops->find_companion(clk, &companion_reg, &other_bit); + if (!(__raw_readl(companion_reg) & (1 << other_bit))) + return; + } - /* Return bypass rate if DPLL is bypassed */ - v = __raw_readl(dd->control_reg); - v &= dd->enable_mask; - v >>= __ffs(dd->enable_mask); + clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit); - /* Reparent in case the dpll is in bypass */ - if (cpu_is_omap24xx()) { - if (v == OMAP2XXX_EN_DPLL_LPBYPASS || - v == OMAP2XXX_EN_DPLL_FRBYPASS) - clk_reparent(clk, dd->clk_bypass); - } else if (cpu_is_omap34xx()) { - if (v == OMAP3XXX_EN_DPLL_LPBYPASS || - v == OMAP3XXX_EN_DPLL_FRBYPASS) - clk_reparent(clk, dd->clk_bypass); - } else if (cpu_is_omap44xx()) { - if (v == OMAP4XXX_EN_DPLL_LPBYPASS || - v == OMAP4XXX_EN_DPLL_FRBYPASS || - v == OMAP4XXX_EN_DPLL_MNBYPASS) - clk_reparent(clk, dd->clk_bypass); - } - return; + omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name); } +/* Enables clock without considering parent dependencies or use count + * REVISIT: Maybe change this to use clk->enable like on omap1? + */ +static int _omap2_clk_enable(struct clk *clk) +{ + return clk->ops->enable(clk); +} + +/* Disables clock without considering parent dependencies or use count */ +static void _omap2_clk_disable(struct clk *clk) +{ + clk->ops->disable(clk); +} + +/* Public functions */ + /** - * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware + * omap2xxx_clk_commit - commit clock parent/rate changes in hardware * @clk: struct clk * * * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes * don't take effect until the VALID_CONFIG bit is written, write the * VALID_CONFIG bit and wait for the write to complete. No return value. */ -static void _omap2xxx_clk_commit(struct clk *clk) +void omap2xxx_clk_commit(struct clk *clk) { if (!cpu_is_omap24xx()) return; @@ -127,52 +109,6 @@ static void _omap2xxx_clk_commit(struct clk *clk) prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP2_PRCM_CLKCFG_CTRL_OFFSET); } -/* - * _dpll_test_fint - test whether an Fint value is valid for the DPLL - * @clk: DPLL struct clk to test - * @n: divider value (N) to test - * - * Tests whether a particular divider @n will result in a valid DPLL - * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter - * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate - * (assuming that it is counting N upwards), or -2 if the enclosing loop - * should skip to the next iteration (again assuming N is increasing). - */ -static int _dpll_test_fint(struct clk *clk, u8 n) -{ - struct dpll_data *dd; - long fint; - int ret = 0; - - dd = clk->dpll_data; - - /* DPLL divider must result in a valid jitter correction val */ - fint = clk->parent->rate / (n + 1); - if (fint < DPLL_FINT_BAND1_MIN) { - - pr_debug("rejecting n=%d due to Fint failure, " - "lowering max_divider\n", n); - dd->max_divider = n; - ret = DPLL_FINT_UNDERFLOW; - - } else if (fint > DPLL_FINT_BAND1_MAX && - fint < DPLL_FINT_BAND2_MIN) { - - pr_debug("rejecting n=%d due to Fint failure\n", n); - ret = DPLL_FINT_INVALID; - - } else if (fint > DPLL_FINT_BAND2_MAX) { - - pr_debug("rejecting n=%d due to Fint failure, " - "boosting min_divider\n", n); - dd->min_divider = n; - ret = DPLL_FINT_INVALID; - - } - - return ret; -} - /** * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk * @clk: OMAP clock struct ptr to use @@ -181,7 +117,6 @@ static int _dpll_test_fint(struct clk *clk, u8 n) * clockdomain pointer, and save it into the struct clk. Intended to be * called during clk_register(). No return value. */ -#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ void omap2_init_clk_clkdm(struct clk *clk) { struct clockdomain *clkdm; @@ -199,117 +134,6 @@ void omap2_init_clk_clkdm(struct clk *clk) "clkdm %s\n", clk->name, clk->clkdm_name); } } -#endif - -/** - * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware - * @clk: OMAP clock struct ptr to use - * - * Given a pointer to a source-selectable struct clk, read the hardware - * register and determine what its parent is currently set to. Update the - * clk->parent field with the appropriate clk ptr. - */ -void omap2_init_clksel_parent(struct clk *clk) -{ - const struct clksel *clks; - const struct clksel_rate *clkr; - u32 r, found = 0; - - if (!clk->clksel) - return; - - r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; - r >>= __ffs(clk->clksel_mask); - - for (clks = clk->clksel; clks->parent && !found; clks++) { - for (clkr = clks->rates; clkr->div && !found; clkr++) { - if ((clkr->flags & cpu_mask) && (clkr->val == r)) { - if (clk->parent != clks->parent) { - pr_debug("clock: inited %s parent " - "to %s (was %s)\n", - clk->name, clks->parent->name, - ((clk->parent) ? - clk->parent->name : "NULL")); - clk_reparent(clk, clks->parent); - }; - found = 1; - } - } - } - - if (!found) - printk(KERN_ERR "clock: init parent: could not find " - "regval %0x for clock %s\n", r, clk->name); - - return; -} - -/** - * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate - * @clk: struct clk * of a DPLL - * - * DPLLs can be locked or bypassed - basically, enabled or disabled. - * When locked, the DPLL output depends on the M and N values. When - * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock - * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and - * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively - * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk. - * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is - * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 - * if the clock @clk is not a DPLL. - */ -u32 omap2_get_dpll_rate(struct clk *clk) -{ - long long dpll_clk; - u32 dpll_mult, dpll_div, v; - struct dpll_data *dd; - - dd = clk->dpll_data; - if (!dd) - return 0; - - /* Return bypass rate if DPLL is bypassed */ - v = __raw_readl(dd->control_reg); - v &= dd->enable_mask; - v >>= __ffs(dd->enable_mask); - - if (cpu_is_omap24xx()) { - if (v == OMAP2XXX_EN_DPLL_LPBYPASS || - v == OMAP2XXX_EN_DPLL_FRBYPASS) - return dd->clk_bypass->rate; - } else if (cpu_is_omap34xx()) { - if (v == OMAP3XXX_EN_DPLL_LPBYPASS || - v == OMAP3XXX_EN_DPLL_FRBYPASS) - return dd->clk_bypass->rate; - } else if (cpu_is_omap44xx()) { - if (v == OMAP4XXX_EN_DPLL_LPBYPASS || - v == OMAP4XXX_EN_DPLL_FRBYPASS || - v == OMAP4XXX_EN_DPLL_MNBYPASS) - return dd->clk_bypass->rate; - } - - v = __raw_readl(dd->mult_div1_reg); - dpll_mult = v & dd->mult_mask; - dpll_mult >>= __ffs(dd->mult_mask); - dpll_div = v & dd->div1_mask; - dpll_div >>= __ffs(dd->div1_mask); - - dpll_clk = (long long)dd->clk_ref->rate * dpll_mult; - do_div(dpll_clk, dpll_div + 1); - - return dpll_clk; -} - -/* - * Used for clocks that have the same value as the parent clock, - * divided by some factor - */ -unsigned long omap2_fixed_divisor_recalc(struct clk *clk) -{ - WARN_ON(!clk->fixed_div); - - return clk->parent->rate / clk->fixed_div; -} /** * omap2_clk_dflt_find_companion - find companion clock to @clk @@ -370,33 +194,6 @@ void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, *idlest_bit = clk->enable_bit; } -/** - * omap2_module_wait_ready - wait for an OMAP module to leave IDLE - * @clk: struct clk * belonging to the module - * - * If the necessary clocks for the OMAP hardware IP block that - * corresponds to clock @clk are enabled, then wait for the module to - * indicate readiness (i.e., to leave IDLE). This code does not - * belong in the clock code and will be moved in the medium term to - * module-dependent code. No return value. - */ -static void omap2_module_wait_ready(struct clk *clk) -{ - void __iomem *companion_reg, *idlest_reg; - u8 other_bit, idlest_bit; - - /* Not all modules have multiple clocks that their IDLEST depends on */ - if (clk->ops->find_companion) { - clk->ops->find_companion(clk, &companion_reg, &other_bit); - if (!(__raw_readl(companion_reg) & (1 << other_bit))) - return; - } - - clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit); - - omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name); -} - int omap2_dflt_clk_enable(struct clk *clk) { u32 v; @@ -416,7 +213,7 @@ int omap2_dflt_clk_enable(struct clk *clk) v = __raw_readl(clk->enable_reg); /* OCP barrier */ if (clk->ops->find_idlest) - omap2_module_wait_ready(clk); + _omap2_module_wait_ready(clk); return 0; } @@ -456,30 +253,14 @@ const struct clkops clkops_omap2_dflt = { .disable = omap2_dflt_clk_disable, }; -/* Enables clock without considering parent dependencies or use count - * REVISIT: Maybe change this to use clk->enable like on omap1? - */ -static int _omap2_clk_enable(struct clk *clk) -{ - return clk->ops->enable(clk); -} - -/* Disables clock without considering parent dependencies or use count */ -static void _omap2_clk_disable(struct clk *clk) -{ - clk->ops->disable(clk); -} - void omap2_clk_disable(struct clk *clk) { if (clk->usecount > 0 && !(--clk->usecount)) { _omap2_clk_disable(clk); if (clk->parent) omap2_clk_disable(clk->parent); -#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ if (clk->clkdm) omap2_clkdm_clk_disable(clk->clkdm, clk); -#endif } } @@ -489,10 +270,8 @@ int omap2_clk_enable(struct clk *clk) int ret = 0; if (clk->usecount++ == 0) { -#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ if (clk->clkdm) omap2_clkdm_clk_enable(clk->clkdm, clk); -#endif if (clk->parent) { ret = omap2_clk_enable(clk->parent); @@ -511,282 +290,12 @@ int omap2_clk_enable(struct clk *clk) return ret; err: -#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ if (clk->clkdm) omap2_clkdm_clk_disable(clk->clkdm, clk); -#endif clk->usecount--; return ret; } -/* - * Used for clocks that are part of CLKSEL_xyz governed clocks. - * REVISIT: Maybe change to use clk->enable() functions like on omap1? - */ -unsigned long omap2_clksel_recalc(struct clk *clk) -{ - unsigned long rate; - u32 div = 0; - - pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); - - div = omap2_clksel_get_divisor(clk); - if (div == 0) - return clk->rate; - - rate = clk->parent->rate / div; - - pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div); - - return rate; -} - -/** - * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent - * @clk: OMAP struct clk ptr to inspect - * @src_clk: OMAP struct clk ptr of the parent clk to search for - * - * Scan the struct clksel array associated with the clock to find - * the element associated with the supplied parent clock address. - * Returns a pointer to the struct clksel on success or NULL on error. - */ -static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk, - struct clk *src_clk) -{ - const struct clksel *clks; - - if (!clk->clksel) - return NULL; - - for (clks = clk->clksel; clks->parent; clks++) { - if (clks->parent == src_clk) - break; /* Found the requested parent */ - } - - if (!clks->parent) { - printk(KERN_ERR "clock: Could not find parent clock %s in " - "clksel array of clock %s\n", src_clk->name, - clk->name); - return NULL; - } - - return clks; -} - -/** - * omap2_clksel_round_rate_div - find divisor for the given clock and rate - * @clk: OMAP struct clk to use - * @target_rate: desired clock rate - * @new_div: ptr to where we should store the divisor - * - * Finds 'best' divider value in an array based on the source and target - * rates. The divider array must be sorted with smallest divider first. - * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, - * they are only settable as part of virtual_prcm set. - * - * Returns the rounded clock rate or returns 0xffffffff on error. - */ -u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, - u32 *new_div) -{ - unsigned long test_rate; - const struct clksel *clks; - const struct clksel_rate *clkr; - u32 last_div = 0; - - pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", - clk->name, target_rate); - - *new_div = 1; - - clks = omap2_get_clksel_by_parent(clk, clk->parent); - if (!clks) - return ~0; - - for (clkr = clks->rates; clkr->div; clkr++) { - if (!(clkr->flags & cpu_mask)) - continue; - - /* Sanity check */ - if (clkr->div <= last_div) - pr_err("clock: clksel_rate table not sorted " - "for clock %s", clk->name); - - last_div = clkr->div; - - test_rate = clk->parent->rate / clkr->div; - - if (test_rate <= target_rate) - break; /* found it */ - } - - if (!clkr->div) { - pr_err("clock: Could not find divisor for target " - "rate %ld for clock %s parent %s\n", target_rate, - clk->name, clk->parent->name); - return ~0; - } - - *new_div = clkr->div; - - pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, - (clk->parent->rate / clkr->div)); - - return (clk->parent->rate / clkr->div); -} - -/** - * omap2_clksel_round_rate - find rounded rate for the given clock and rate - * @clk: OMAP struct clk to use - * @target_rate: desired clock rate - * - * Compatibility wrapper for OMAP clock framework - * Finds best target rate based on the source clock and possible dividers. - * rates. The divider array must be sorted with smallest divider first. - * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, - * they are only settable as part of virtual_prcm set. - * - * Returns the rounded clock rate or returns 0xffffffff on error. - */ -long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) -{ - u32 new_div; - - return omap2_clksel_round_rate_div(clk, target_rate, &new_div); -} - - -/* Given a clock and a rate apply a clock specific rounding function */ -long omap2_clk_round_rate(struct clk *clk, unsigned long rate) -{ - if (clk->round_rate) - return clk->round_rate(clk, rate); - - if (clk->flags & RATE_FIXED) - printk(KERN_ERR "clock: generic omap2_clk_round_rate called " - "on fixed-rate clock %s\n", clk->name); - - return clk->rate; -} - -/** - * omap2_clksel_to_divisor() - turn clksel field value into integer divider - * @clk: OMAP struct clk to use - * @field_val: register field value to find - * - * Given a struct clk of a rate-selectable clksel clock, and a register field - * value to search for, find the corresponding clock divisor. The register - * field value should be pre-masked and shifted down so the LSB is at bit 0 - * before calling. Returns 0 on error - */ -u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val) -{ - const struct clksel *clks; - const struct clksel_rate *clkr; - - clks = omap2_get_clksel_by_parent(clk, clk->parent); - if (!clks) - return 0; - - for (clkr = clks->rates; clkr->div; clkr++) { - if ((clkr->flags & cpu_mask) && (clkr->val == field_val)) - break; - } - - if (!clkr->div) { - printk(KERN_ERR "clock: Could not find fieldval %d for " - "clock %s parent %s\n", field_val, clk->name, - clk->parent->name); - return 0; - } - - return clkr->div; -} - -/** - * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value - * @clk: OMAP struct clk to use - * @div: integer divisor to search for - * - * Given a struct clk of a rate-selectable clksel clock, and a clock divisor, - * find the corresponding register field value. The return register value is - * the value before left-shifting. Returns ~0 on error - */ -u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) -{ - const struct clksel *clks; - const struct clksel_rate *clkr; - - /* should never happen */ - WARN_ON(div == 0); - - clks = omap2_get_clksel_by_parent(clk, clk->parent); - if (!clks) - return ~0; - - for (clkr = clks->rates; clkr->div; clkr++) { - if ((clkr->flags & cpu_mask) && (clkr->div == div)) - break; - } - - if (!clkr->div) { - printk(KERN_ERR "clock: Could not find divisor %d for " - "clock %s parent %s\n", div, clk->name, - clk->parent->name); - return ~0; - } - - return clkr->val; -} - -/** - * omap2_clksel_get_divisor - get current divider applied to parent clock. - * @clk: OMAP struct clk to use. - * - * Returns the integer divisor upon success or 0 on error. - */ -u32 omap2_clksel_get_divisor(struct clk *clk) -{ - u32 v; - - if (!clk->clksel_mask) - return 0; - - v = __raw_readl(clk->clksel_reg) & clk->clksel_mask; - v >>= __ffs(clk->clksel_mask); - - return omap2_clksel_to_divisor(clk, v); -} - -int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) -{ - u32 v, field_val, validrate, new_div = 0; - - if (!clk->clksel_mask) - return -EINVAL; - - validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); - if (validrate != rate) - return -EINVAL; - - field_val = omap2_divisor_to_clksel(clk, new_div); - if (field_val == ~0) - return -EINVAL; - - v = __raw_readl(clk->clksel_reg); - v &= ~clk->clksel_mask; - v |= field_val << __ffs(clk->clksel_mask); - __raw_writel(v, clk->clksel_reg); - v = __raw_readl(clk->clksel_reg); /* OCP barrier */ - - clk->rate = clk->parent->rate / new_div; - - _omap2xxx_clk_commit(clk); - - return 0; -} - - /* Set the clock rate for a clock source */ int omap2_clk_set_rate(struct clk *clk, unsigned long rate) { @@ -806,265 +315,15 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate) return ret; } -/* - * Converts encoded control register address into a full address - * On error, the return value (parent_div) will be 0. - */ -static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk, - u32 *field_val) -{ - const struct clksel *clks; - const struct clksel_rate *clkr; - - clks = omap2_get_clksel_by_parent(clk, src_clk); - if (!clks) - return 0; - - for (clkr = clks->rates; clkr->div; clkr++) { - if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE) - break; /* Found the default rate for this platform */ - } - - if (!clkr->div) { - printk(KERN_ERR "clock: Could not find default rate for " - "clock %s parent %s\n", clk->name, - src_clk->parent->name); - return 0; - } - - /* Should never happen. Add a clksel mask to the struct clk. */ - WARN_ON(clk->clksel_mask == 0); - - *field_val = clkr->val; - - return clkr->div; -} - int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) { - u32 field_val, v, parent_div; - if (clk->flags & CONFIG_PARTICIPANT) return -EINVAL; if (!clk->clksel) return -EINVAL; - parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val); - if (!parent_div) - return -EINVAL; - - /* Set new source value (previous dividers if any in effect) */ - v = __raw_readl(clk->clksel_reg); - v &= ~clk->clksel_mask; - v |= field_val << __ffs(clk->clksel_mask); - __raw_writel(v, clk->clksel_reg); - v = __raw_readl(clk->clksel_reg); /* OCP barrier */ - - _omap2xxx_clk_commit(clk); - - clk_reparent(clk, new_parent); - - /* CLKSEL clocks follow their parents' rates, divided by a divisor */ - clk->rate = new_parent->rate; - - if (parent_div > 0) - clk->rate /= parent_div; - - pr_debug("clock: set parent of %s to %s (new rate %ld)\n", - clk->name, clk->parent->name, clk->rate); - - return 0; -} - -/* DPLL rate rounding code */ - -/** - * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding - * @clk: struct clk * of the DPLL - * @tolerance: maximum rate error tolerance - * - * Set the maximum DPLL rate error tolerance for the rate rounding - * algorithm. The rate tolerance is an attempt to balance DPLL power - * saving (the least divider value "n") vs. rate fidelity (the least - * difference between the desired DPLL target rate and the rounded - * rate out of the algorithm). So, increasing the tolerance is likely - * to decrease DPLL power consumption and increase DPLL rate error. - * Returns -EINVAL if provided a null clock ptr or a clk that is not a - * DPLL; or 0 upon success. - */ -int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance) -{ - if (!clk || !clk->dpll_data) - return -EINVAL; - - clk->dpll_data->rate_tolerance = tolerance; - - return 0; -} - -static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, - unsigned int m, unsigned int n) -{ - unsigned long long num; - - num = (unsigned long long)parent_rate * m; - do_div(num, n); - return num; -} - -/* - * _dpll_test_mult - test a DPLL multiplier value - * @m: pointer to the DPLL m (multiplier) value under test - * @n: current DPLL n (divider) value under test - * @new_rate: pointer to storage for the resulting rounded rate - * @target_rate: the desired DPLL rate - * @parent_rate: the DPLL's parent clock rate - * - * This code tests a DPLL multiplier value, ensuring that the - * resulting rate will not be higher than the target_rate, and that - * the multiplier value itself is valid for the DPLL. Initially, the - * integer pointed to by the m argument should be prescaled by - * multiplying by DPLL_SCALE_FACTOR. The code will replace this with - * a non-scaled m upon return. This non-scaled m will result in a - * new_rate as close as possible to target_rate (but not greater than - * target_rate) given the current (parent_rate, n, prescaled m) - * triple. Returns DPLL_MULT_UNDERFLOW in the event that the - * non-scaled m attempted to underflow, which can allow the calling - * function to bail out early; or 0 upon success. - */ -static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, - unsigned long target_rate, - unsigned long parent_rate) -{ - int r = 0, carry = 0; - - /* Unscale m and round if necessary */ - if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) - carry = 1; - *m = (*m / DPLL_SCALE_FACTOR) + carry; - - /* - * The new rate must be <= the target rate to avoid programming - * a rate that is impossible for the hardware to handle - */ - *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); - if (*new_rate > target_rate) { - (*m)--; - *new_rate = 0; - } - - /* Guard against m underflow */ - if (*m < DPLL_MIN_MULTIPLIER) { - *m = DPLL_MIN_MULTIPLIER; - *new_rate = 0; - r = DPLL_MULT_UNDERFLOW; - } - - if (*new_rate == 0) - *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); - - return r; -} - -/** - * omap2_dpll_round_rate - round a target rate for an OMAP DPLL - * @clk: struct clk * for a DPLL - * @target_rate: desired DPLL clock rate - * - * Given a DPLL, a desired target rate, and a rate tolerance, round - * the target rate to a possible, programmable rate for this DPLL. - * Rate tolerance is assumed to be set by the caller before this - * function is called. Attempts to select the minimum possible n - * within the tolerance to reduce power consumption. Stores the - * computed (m, n) in the DPLL's dpll_data structure so set_rate() - * will not need to call this (expensive) function again. Returns ~0 - * if the target rate cannot be rounded, either because the rate is - * too low or because the rate tolerance is set too tightly; or the - * rounded rate upon success. - */ -long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) -{ - int m, n, r, e, scaled_max_m; - unsigned long scaled_rt_rp, new_rate; - int min_e = -1, min_e_m = -1, min_e_n = -1; - struct dpll_data *dd; - - if (!clk || !clk->dpll_data) - return ~0; - - dd = clk->dpll_data; - - pr_debug("clock: starting DPLL round_rate for clock %s, target rate " - "%ld\n", clk->name, target_rate); - - scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR); - scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; - - dd->last_rounded_rate = 0; - - for (n = dd->min_divider; n <= dd->max_divider; n++) { - - /* Is the (input clk, divider) pair valid for the DPLL? */ - r = _dpll_test_fint(clk, n); - if (r == DPLL_FINT_UNDERFLOW) - break; - else if (r == DPLL_FINT_INVALID) - continue; - - /* Compute the scaled DPLL multiplier, based on the divider */ - m = scaled_rt_rp * n; - - /* - * Since we're counting n up, a m overflow means we - * can bail out completely (since as n increases in - * the next iteration, there's no way that m can - * increase beyond the current m) - */ - if (m > scaled_max_m) - break; - - r = _dpll_test_mult(&m, n, &new_rate, target_rate, - dd->clk_ref->rate); - - /* m can't be set low enough for this n - try with a larger n */ - if (r == DPLL_MULT_UNDERFLOW) - continue; - - e = target_rate - new_rate; - pr_debug("clock: n = %d: m = %d: rate error is %d " - "(new_rate = %ld)\n", n, m, e, new_rate); - - if (min_e == -1 || - min_e >= (int)(abs(e) - dd->rate_tolerance)) { - min_e = e; - min_e_m = m; - min_e_n = n; - - pr_debug("clock: found new least error %d\n", min_e); - - /* We found good settings -- bail out now */ - if (min_e <= dd->rate_tolerance) - break; - } - } - - if (min_e < 0) { - pr_debug("clock: error: target rate or tolerance too low\n"); - return ~0; - } - - dd->last_rounded_m = min_e_m; - dd->last_rounded_n = min_e_n; - dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate, - min_e_m, min_e_n); - - pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", - min_e, min_e_m, min_e_n); - pr_debug("clock: final rate: %ld (target rate: %ld)\n", - dd->last_rounded_rate, target_rate); - - return dd->last_rounded_rate; + return omap2_clksel_set_parent(clk, new_parent); } /*------------------------------------------------------------------------- @@ -1092,3 +351,20 @@ void omap2_clk_disable_unused(struct clk *clk) pwrdm_clkdm_state_switch(clk->clkdm); } #endif + +/* Common data */ + +struct clk_functions omap2_clk_functions = { + .clk_enable = omap2_clk_enable, + .clk_disable = omap2_clk_disable, + .clk_round_rate = omap2_clk_round_rate, + .clk_set_rate = omap2_clk_set_rate, + .clk_set_parent = omap2_clk_set_parent, + .clk_disable_unused = omap2_clk_disable_unused, +#ifdef CONFIG_CPU_FREQ + /* These will be removed when the OPP code is integrated */ + .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, + .clk_exit_cpufreq_table = omap2_clk_exit_cpufreq_table, +#endif +}; + diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 93c48df3b5b1..fcb99cce5fc8 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -47,7 +47,6 @@ #define DPLL_LOW_POWER_BYPASS 0x5 #define DPLL_LOCKED 0x7 -int omap2_clk_init(void); int omap2_clk_enable(struct clk *clk); void omap2_clk_disable(struct clk *clk); long omap2_clk_round_rate(struct clk *clk, unsigned long rate); @@ -78,19 +77,45 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, u32 *new_div); u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val); u32 omap2_divisor_to_clksel(struct clk *clk, u32 div); -unsigned long omap2_fixed_divisor_recalc(struct clk *clk); long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); +int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent); u32 omap2_get_dpll_rate(struct clk *clk); void omap2_init_dpll_parent(struct clk *clk); int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); -void omap2_clk_prepare_for_reboot(void); + + +#ifdef CONFIG_ARCH_OMAP2 +void omap2xxx_clk_prepare_for_reboot(void); +#else +static inline void omap2xxx_clk_prepare_for_reboot(void) +{ +} +#endif + +#ifdef CONFIG_ARCH_OMAP3 +void omap3_clk_prepare_for_reboot(void); +#else +static inline void omap3_clk_prepare_for_reboot(void) +{ +} +#endif + +#ifdef CONFIG_ARCH_OMAP4 +void omap4_clk_prepare_for_reboot(void); +#else +static inline void omap4_clk_prepare_for_reboot(void) +{ +} +#endif + int omap2_dflt_clk_enable(struct clk *clk); void omap2_dflt_clk_disable(struct clk *clk); void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, u8 *other_bit); void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, u8 *idlest_bit); +void omap2xxx_clk_commit(struct clk *clk); extern u8 cpu_mask; @@ -104,5 +129,12 @@ extern const struct clksel_rate gpt_32k_rates[]; extern const struct clksel_rate gpt_sys_rates[]; extern const struct clksel_rate gfx_l3_rates[]; +#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ) +extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table); +extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table); +#else +#define omap2_clk_init_cpufreq_table 0 +#define omap2_clk_exit_cpufreq_table 0 +#endif #endif diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c index 5420356eb407..a48b01ab0e35 100644 --- a/arch/arm/mach-omap2/clock2xxx.c +++ b/arch/arm/mach-omap2/clock2xxx.c @@ -1,15 +1,15 @@ /* - * linux/arch/arm/mach-omap2/clock.c + * clock2xxx.c - OMAP2xxx-specific clock integration code * - * Copyright (C) 2005-2008 Texas Instruments, Inc. - * Copyright (C) 2004-2008 Nokia Corporation + * Copyright (C) 2005-2008 Texas Instruments, Inc. + * Copyright (C) 2004-2010 Nokia Corporation * - * Contacts: - * Richard Woodruff <r-woodruff2@ti.com> - * Paul Walmsley + * Contacts: + * Richard Woodruff <r-woodruff2@ti.com> + * Paul Walmsley * - * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, - * Gordon McNutt and RidgeRun, Inc. + * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, + * Gordon McNutt and RidgeRun, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -17,55 +17,25 @@ */ #undef DEBUG -#include <linux/module.h> #include <linux/kernel.h> -#include <linux/device.h> -#include <linux/list.h> #include <linux/errno.h> -#include <linux/delay.h> #include <linux/clk.h> #include <linux/io.h> -#include <linux/cpufreq.h> -#include <linux/bitops.h> #include <plat/clock.h> -#include <plat/sram.h> -#include <plat/prcm.h> -#include <plat/clkdev_omap.h> -#include <asm/div64.h> -#include <asm/clkdev.h> -#include <plat/sdrc.h> #include "clock.h" #include "clock2xxx.h" -#include "opp2xxx.h" -#include "prm.h" -#include "prm-regbits-24xx.h" #include "cm.h" #include "cm-regbits-24xx.h" - -/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ -#define EN_APLL_STOPPED 0 -#define EN_APLL_LOCKED 3 - -/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */ -#define APLLS_CLKIN_19_2MHZ 0 -#define APLLS_CLKIN_13MHZ 2 -#define APLLS_CLKIN_12MHZ 3 - -/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ - -const struct prcm_config *curr_prcm_set; -const struct prcm_config *rate_table; - struct clk *vclk, *sclk, *dclk; -void __iomem *prcm_clksrc_ctrl; - -/*------------------------------------------------------------------------- +/* * Omap24xx specific clock functions - *-------------------------------------------------------------------------*/ + */ + +#ifdef CONFIG_ARCH_OMAP2430 /** * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS @@ -86,6 +56,10 @@ static void omap2430_clk_i2chs_find_idlest(struct clk *clk, *idlest_bit = clk->enable_bit; } +#else +#define omap2430_clk_i2chs_find_idlest NULL +#endif + /* 2430 I2CHS has non-standard IDLEST register */ const struct clkops clkops_omap2430_i2chs_wait = { .enable = omap2_dflt_clk_enable, @@ -94,491 +68,10 @@ const struct clkops clkops_omap2430_i2chs_wait = { .find_companion = omap2_clk_dflt_find_companion, }; -/** - * omap2xxx_clk_get_core_rate - return the CORE_CLK rate - * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck") - * - * Returns the CORE_CLK rate. CORE_CLK can have one of three rate - * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz - * (the latter is unusual). This currently should be called with - * struct clk *dpll_ck, which is a composite clock of dpll_ck and - * core_ck. - */ -unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) -{ - long long core_clk; - u32 v; - - core_clk = omap2_get_dpll_rate(clk); - - v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); - v &= OMAP24XX_CORE_CLK_SRC_MASK; - - if (v == CORE_CLK_SRC_32K) - core_clk = 32768; - else - core_clk *= v; - - return core_clk; -} - -static int omap2_enable_osc_ck(struct clk *clk) -{ - u32 pcc; - - pcc = __raw_readl(prcm_clksrc_ctrl); - - __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); - - return 0; -} - -static void omap2_disable_osc_ck(struct clk *clk) -{ - u32 pcc; - - pcc = __raw_readl(prcm_clksrc_ctrl); - - __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); -} - -const struct clkops clkops_oscck = { - .enable = omap2_enable_osc_ck, - .disable = omap2_disable_osc_ck, -}; - -#ifdef OLD_CK -/* Recalculate SYST_CLK */ -static void omap2_sys_clk_recalc(struct clk *clk) -{ - u32 div = PRCM_CLKSRC_CTRL; - div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */ - div >>= clk->rate_offset; - clk->rate = (clk->parent->rate / div); - propagate_rate(clk); -} -#endif /* OLD_CK */ - -/* Enable an APLL if off */ -static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) -{ - u32 cval, apll_mask; - - apll_mask = EN_APLL_LOCKED << clk->enable_bit; - - cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); - - if ((cval & apll_mask) == apll_mask) - return 0; /* apll already enabled */ - - cval &= ~apll_mask; - cval |= apll_mask; - cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); - - omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), status_mask, - clk->name); - - /* - * REVISIT: Should we return an error code if omap2_wait_clock_ready() - * fails? - */ - return 0; -} - -static int omap2_clk_apll96_enable(struct clk *clk) -{ - return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL); -} - -static int omap2_clk_apll54_enable(struct clk *clk) -{ - return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL); -} - -/* Stop APLL */ -static void omap2_clk_apll_disable(struct clk *clk) -{ - u32 cval; - - cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); - cval &= ~(EN_APLL_LOCKED << clk->enable_bit); - cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); -} - -const struct clkops clkops_apll96 = { - .enable = omap2_clk_apll96_enable, - .disable = omap2_clk_apll_disable, -}; - -const struct clkops clkops_apll54 = { - .enable = omap2_clk_apll54_enable, - .disable = omap2_clk_apll_disable, -}; - -/* - * Uses the current prcm set to tell if a rate is valid. - * You can go slower, but not faster within a given rate set. - */ -long omap2_dpllcore_round_rate(unsigned long target_rate) -{ - u32 high, low, core_clk_src; - - core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); - core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; - - if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ - high = curr_prcm_set->dpll_speed * 2; - low = curr_prcm_set->dpll_speed; - } else { /* DPLL clockout x 2 */ - high = curr_prcm_set->dpll_speed; - low = curr_prcm_set->dpll_speed / 2; - } - -#ifdef DOWN_VARIABLE_DPLL - if (target_rate > high) - return high; - else - return target_rate; -#else - if (target_rate > low) - return high; - else - return low; -#endif - -} - -unsigned long omap2_dpllcore_recalc(struct clk *clk) -{ - return omap2xxx_clk_get_core_rate(clk); -} - -int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) -{ - u32 cur_rate, low, mult, div, valid_rate, done_rate; - u32 bypass = 0; - struct prcm_config tmpset; - const struct dpll_data *dd; - - cur_rate = omap2xxx_clk_get_core_rate(dclk); - mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); - mult &= OMAP24XX_CORE_CLK_SRC_MASK; - - if ((rate == (cur_rate / 2)) && (mult == 2)) { - omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); - } else if ((rate == (cur_rate * 2)) && (mult == 1)) { - omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); - } else if (rate != cur_rate) { - valid_rate = omap2_dpllcore_round_rate(rate); - if (valid_rate != rate) - return -EINVAL; - - if (mult == 1) - low = curr_prcm_set->dpll_speed; - else - low = curr_prcm_set->dpll_speed / 2; - - dd = clk->dpll_data; - if (!dd) - return -EINVAL; - - tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); - tmpset.cm_clksel1_pll &= ~(dd->mult_mask | - dd->div1_mask); - div = ((curr_prcm_set->xtal_speed / 1000000) - 1); - tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); - tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; - if (rate > low) { - tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; - mult = ((rate / 2) / 1000000); - done_rate = CORE_CLK_SRC_DPLL_X2; - } else { - tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL; - mult = (rate / 1000000); - done_rate = CORE_CLK_SRC_DPLL; - } - tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask)); - tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); - - /* Worst case */ - tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS; - - if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ - bypass = 1; - - /* For omap2xxx_sdrc_init_params() */ - omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); - - /* Force dll lock mode */ - omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, - bypass); - - /* Errata: ret dll entry state */ - omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); - omap2xxx_sdrc_reprogram(done_rate, 0); - } - - return 0; -} - -/** - * omap2_table_mpu_recalc - just return the MPU speed - * @clk: virt_prcm_set struct clk - * - * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. - */ -unsigned long omap2_table_mpu_recalc(struct clk *clk) -{ - return curr_prcm_set->mpu_speed; -} - -/* - * Look for a rate equal or less than the target rate given a configuration set. - * - * What's not entirely clear is "which" field represents the key field. - * Some might argue L3-DDR, others ARM, others IVA. This code is simple and - * just uses the ARM rates. - */ -long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) -{ - const struct prcm_config *ptr; - long highest_rate; - long sys_ck_rate; - - sys_ck_rate = clk_get_rate(sclk); - - highest_rate = -EINVAL; - - for (ptr = rate_table; ptr->mpu_speed; ptr++) { - if (!(ptr->flags & cpu_mask)) - continue; - if (ptr->xtal_speed != sys_ck_rate) - continue; - - highest_rate = ptr->mpu_speed; - - /* Can check only after xtal frequency check */ - if (ptr->mpu_speed <= rate) - break; - } - return highest_rate; -} - -/* Sets basic clocks based on the specified rate */ -int omap2_select_table_rate(struct clk *clk, unsigned long rate) -{ - u32 cur_rate, done_rate, bypass = 0, tmp; - const struct prcm_config *prcm; - unsigned long found_speed = 0; - unsigned long flags; - long sys_ck_rate; - - sys_ck_rate = clk_get_rate(sclk); - - for (prcm = rate_table; prcm->mpu_speed; prcm++) { - if (!(prcm->flags & cpu_mask)) - continue; - - if (prcm->xtal_speed != sys_ck_rate) - continue; - - if (prcm->mpu_speed <= rate) { - found_speed = prcm->mpu_speed; - break; - } - } - - if (!found_speed) { - printk(KERN_INFO "Could not set MPU rate to %luMHz\n", - rate / 1000000); - return -EINVAL; - } - - curr_prcm_set = prcm; - cur_rate = omap2xxx_clk_get_core_rate(dclk); - - if (prcm->dpll_speed == cur_rate / 2) { - omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); - } else if (prcm->dpll_speed == cur_rate * 2) { - omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); - } else if (prcm->dpll_speed != cur_rate) { - local_irq_save(flags); - - if (prcm->dpll_speed == prcm->xtal_speed) - bypass = 1; - - if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) == - CORE_CLK_SRC_DPLL_X2) - done_rate = CORE_CLK_SRC_DPLL_X2; - else - done_rate = CORE_CLK_SRC_DPLL; - - /* MPU divider */ - cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); - - /* dsp + iva1 div(2420), iva2.1(2430) */ - cm_write_mod_reg(prcm->cm_clksel_dsp, - OMAP24XX_DSP_MOD, CM_CLKSEL); - - cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); - - /* Major subsystem dividers */ - tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; - cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, - CM_CLKSEL1); - - if (cpu_is_omap2430()) - cm_write_mod_reg(prcm->cm_clksel_mdm, - OMAP2430_MDM_MOD, CM_CLKSEL); - - /* x2 to enter omap2xxx_sdrc_init_params() */ - omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); - - omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, - bypass); - - omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); - omap2xxx_sdrc_reprogram(done_rate, 0); - - local_irq_restore(flags); - } - - return 0; -} - -#ifdef CONFIG_CPU_FREQ -/* - * Walk PRCM rate table and fillout cpufreq freq_table - * XXX This should be replaced by an OPP layer in the near future - */ -static struct cpufreq_frequency_table *freq_table; - -void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table) -{ - const struct prcm_config *prcm; - long sys_ck_rate; - int i = 0; - int tbl_sz = 0; - - sys_ck_rate = clk_get_rate(sclk); - - for (prcm = rate_table; prcm->mpu_speed; prcm++) { - if (!(prcm->flags & cpu_mask)) - continue; - if (prcm->xtal_speed != sys_ck_rate) - continue; - - /* don't put bypass rates in table */ - if (prcm->dpll_speed == prcm->xtal_speed) - continue; - - tbl_sz++; - } - - /* - * XXX Ensure that we're doing what CPUFreq expects for this error - * case and the following one - */ - if (tbl_sz == 0) { - pr_warning("%s: no matching entries in rate_table\n", - __func__); - return; - } - - /* Include the CPUFREQ_TABLE_END terminator entry */ - tbl_sz++; - - freq_table = kzalloc(sizeof(struct cpufreq_frequency_table) * tbl_sz, - GFP_ATOMIC); - if (!freq_table) { - pr_err("%s: could not kzalloc frequency table\n", __func__); - return; - } - - for (prcm = rate_table; prcm->mpu_speed; prcm++) { - if (!(prcm->flags & cpu_mask)) - continue; - if (prcm->xtal_speed != sys_ck_rate) - continue; - - /* don't put bypass rates in table */ - if (prcm->dpll_speed == prcm->xtal_speed) - continue; - - freq_table[i].index = i; - freq_table[i].frequency = prcm->mpu_speed / 1000; - i++; - } - - freq_table[i].index = i; - freq_table[i].frequency = CPUFREQ_TABLE_END; - - *table = &freq_table[0]; -} - -void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table) -{ - kfree(freq_table); -} - -#endif - -struct clk_functions omap2_clk_functions = { - .clk_enable = omap2_clk_enable, - .clk_disable = omap2_clk_disable, - .clk_round_rate = omap2_clk_round_rate, - .clk_set_rate = omap2_clk_set_rate, - .clk_set_parent = omap2_clk_set_parent, - .clk_disable_unused = omap2_clk_disable_unused, -#ifdef CONFIG_CPU_FREQ - .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, - .clk_exit_cpufreq_table = omap2_clk_exit_cpufreq_table, -#endif -}; - -static u32 omap2_get_apll_clkin(void) -{ - u32 aplls, srate = 0; - - aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); - aplls &= OMAP24XX_APLLS_CLKIN_MASK; - aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; - - if (aplls == APLLS_CLKIN_19_2MHZ) - srate = 19200000; - else if (aplls == APLLS_CLKIN_13MHZ) - srate = 13000000; - else if (aplls == APLLS_CLKIN_12MHZ) - srate = 12000000; - - return srate; -} - -static u32 omap2_get_sysclkdiv(void) -{ - u32 div; - - div = __raw_readl(prcm_clksrc_ctrl); - div &= OMAP_SYSCLKDIV_MASK; - div >>= OMAP_SYSCLKDIV_SHIFT; - - return div; -} - -unsigned long omap2_osc_clk_recalc(struct clk *clk) -{ - return omap2_get_apll_clkin() * omap2_get_sysclkdiv(); -} - -unsigned long omap2_sys_clk_recalc(struct clk *clk) -{ - return clk->parent->rate / omap2_get_sysclkdiv(); -} - /* * Set clocks for bypass mode for reboot to work. */ -void omap2_clk_prepare_for_reboot(void) +void omap2xxx_clk_prepare_for_reboot(void) { u32 rate; @@ -593,11 +86,14 @@ void omap2_clk_prepare_for_reboot(void) * Switch the MPU rate if specified on cmdline. * We cannot do this early until cmdline is parsed. */ -static int __init omap2_clk_arch_init(void) +static int __init omap2xxx_clk_arch_init(void) { struct clk *virt_prcm_set, *sys_ck, *dpll_ck, *mpu_ck; unsigned long sys_ck_rate; + if (!cpu_is_omap24xx()) + return 0; + if (!mpurate) return -EINVAL; @@ -621,6 +117,6 @@ static int __init omap2_clk_arch_init(void) return 0; } -arch_initcall(omap2_clk_arch_init); +arch_initcall(omap2xxx_clk_arch_init); diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h index e35efde4bd80..32f3d0aa8fc4 100644 --- a/arch/arm/mach-omap2/clock2xxx.h +++ b/arch/arm/mach-omap2/clock2xxx.h @@ -11,12 +11,15 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk); int omap2_select_table_rate(struct clk *clk, unsigned long rate); long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); -unsigned long omap2_sys_clk_recalc(struct clk *clk); +unsigned long omap2xxx_sys_clk_recalc(struct clk *clk); unsigned long omap2_osc_clk_recalc(struct clk *clk); -unsigned long omap2_sys_clk_recalc(struct clk *clk); unsigned long omap2_dpllcore_recalc(struct clk *clk); int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); unsigned long omap2xxx_clk_get_core_rate(struct clk *clk); +u32 omap2xxx_get_apll_clkin(void); +u32 omap2xxx_get_sysclkdiv(void); +void omap2xxx_clk_prepare_for_reboot(void); +int omap2xxx_clk_init(void); /* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */ #ifdef CONFIG_ARCH_OMAP2420 diff --git a/arch/arm/mach-omap2/clock2xxx_data.c b/arch/arm/mach-omap2/clock2xxx_data.c index 97dc7cf7751d..52c7a6c2d9e0 100644 --- a/arch/arm/mach-omap2/clock2xxx_data.c +++ b/arch/arm/mach-omap2/clock2xxx_data.c @@ -79,7 +79,7 @@ static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ .ops = &clkops_null, .parent = &osc_ck, .clkdm_name = "wkup_clkdm", - .recalc = &omap2_sys_clk_recalc, + .recalc = &omap2xxx_sys_clk_recalc, }; static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ @@ -261,7 +261,7 @@ static struct clk func_12m_ck = { .parent = &func_48m_ck, .fixed_div = 4, .clkdm_name = "wkup_clkdm", - .recalc = &omap2_fixed_divisor_recalc, + .recalc = &omap_fixed_divisor_recalc, }; /* Secure timer, only available in secure mode */ @@ -557,7 +557,7 @@ static struct clk iva1_mpu_int_ifck = { .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, .fixed_div = 2, - .recalc = &omap2_fixed_divisor_recalc, + .recalc = &omap_fixed_divisor_recalc, }; /* @@ -2238,7 +2238,7 @@ static struct omap_clk omap24xx_clks[] = { * init code */ -int __init omap2_clk_init(void) +int __init omap2xxx_clk_init(void) { const struct prcm_config *prcm; struct omap_clk *c; @@ -2264,7 +2264,7 @@ int __init omap2_clk_init(void) osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); propagate_rate(&osc_ck); - sys_ck.rate = omap2_sys_clk_recalc(&sys_ck); + sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck); propagate_rate(&sys_ck); for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index d4217b93e10b..ae9e2c82eb6a 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -2,10 +2,10 @@ * OMAP3-specific clock framework functions * * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2009 Nokia Corporation + * Copyright (C) 2007-2010 Nokia Corporation * - * Written by Paul Walmsley - * Testing and integration fixes by Jouni Högander + * Paul Walmsley + * Jouni Högander * * Parts of this code are based on code written by * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu @@ -16,34 +16,22 @@ */ #undef DEBUG -#include <linux/module.h> #include <linux/kernel.h> -#include <linux/device.h> -#include <linux/list.h> #include <linux/errno.h> #include <linux/delay.h> #include <linux/clk.h> #include <linux/io.h> -#include <linux/limits.h> -#include <linux/bitops.h> #include <plat/cpu.h> #include <plat/clock.h> -#include <plat/sram.h> -#include <plat/sdrc.h> -#include <asm/div64.h> -#include <asm/clkdev.h> #include "clock.h" #include "clock34xx.h" -#include "sdrc.h" #include "prm.h" #include "prm-regbits-34xx.h" #include "cm.h" #include "cm-regbits-34xx.h" -#define CYCLES_PER_MHZ 1000000 - /* * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks * that are sourced by DPLL5, and both of these require this clock @@ -142,7 +130,7 @@ const struct clkops clkops_omap3430es2_hsotgusb_wait = { .find_companion = omap2_clk_dflt_find_companion, }; -const struct clkops clkops_noncore_dpll_ops = { +const struct clkops omap3_clkops_noncore_dpll_ops = { .enable = omap3_noncore_dpll_enable, .disable = omap3_noncore_dpll_disable, }; @@ -162,129 +150,7 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) return omap3_noncore_dpll_set_rate(clk, rate); } - -/* - * CORE DPLL (DPLL3) rate programming functions - * - * These call into SRAM code to do the actual CM writes, since the SDRAM - * is clocked from DPLL3. - */ - -/** - * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider - * @clk: struct clk * of DPLL to set - * @rate: rounded target rate - * - * Program the DPLL M2 divider with the rounded target rate. Returns - * -EINVAL upon error, or 0 upon success. - */ -int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) -{ - u32 new_div = 0; - u32 unlock_dll = 0; - u32 c; - unsigned long validrate, sdrcrate, _mpurate; - struct omap_sdrc_params *sdrc_cs0; - struct omap_sdrc_params *sdrc_cs1; - int ret; - - if (!clk || !rate) - return -EINVAL; - - validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); - if (validrate != rate) - return -EINVAL; - - sdrcrate = sdrc_ick_p->rate; - if (rate > clk->rate) - sdrcrate <<= ((rate / clk->rate) >> 1); - else - sdrcrate >>= ((clk->rate / rate) >> 1); - - ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1); - if (ret) - return -EINVAL; - - if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) { - pr_debug("clock: will unlock SDRC DLL\n"); - unlock_dll = 1; - } - - /* - * XXX This only needs to be done when the CPU frequency changes - */ - _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ; - c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; - c += 1; /* for safety */ - c *= SDRC_MPURATE_LOOPS; - c >>= SDRC_MPURATE_SCALE; - if (c == 0) - c = 1; - - pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, - validrate); - pr_debug("clock: SDRC CS0 timing params used:" - " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", - sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, - sdrc_cs0->actim_ctrlb, sdrc_cs0->mr); - if (sdrc_cs1) - pr_debug("clock: SDRC CS1 timing params used: " - " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", - sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, - sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); - - if (sdrc_cs1) - omap3_configure_core_dpll( - new_div, unlock_dll, c, rate > clk->rate, - sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, - sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, - sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, - sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); - else - omap3_configure_core_dpll( - new_div, unlock_dll, c, rate > clk->rate, - sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, - sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, - 0, 0, 0, 0); - - return 0; -} - -/* Common clock code */ - -/* - * As it is structured now, this will prevent an OMAP2/3 multiboot - * kernel from compiling. This will need further attention. - */ -#if defined(CONFIG_ARCH_OMAP3) - -struct clk_functions omap2_clk_functions = { - .clk_enable = omap2_clk_enable, - .clk_disable = omap2_clk_disable, - .clk_round_rate = omap2_clk_round_rate, - .clk_set_rate = omap2_clk_set_rate, - .clk_set_parent = omap2_clk_set_parent, - .clk_disable_unused = omap2_clk_disable_unused, -}; - -/* - * Set clocks for bypass mode for reboot to work. - */ -void omap2_clk_prepare_for_reboot(void) -{ - /* REVISIT: Not ready for 343x */ -#if 0 - u32 rate; - - if (vclk == NULL || sclk == NULL) - return; - - rate = clk_get_rate(sclk); - clk_set_rate(vclk, rate); -#endif -} - -void omap3_clk_lock_dpll5(void) +void __init omap3_clk_lock_dpll5(void) { struct clk *dpll5_clk; struct clk *dpll5_m2_clk; @@ -306,17 +172,22 @@ void omap3_clk_lock_dpll5(void) return; } +/* Common clock code */ + /* REVISIT: Move this init stuff out into clock.c */ /* * Switch the MPU rate if specified on cmdline. * We cannot do this early until cmdline is parsed. */ -static int __init omap2_clk_arch_init(void) +static int __init omap3xxx_clk_arch_init(void) { struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck; unsigned long osc_sys_rate; + if (!cpu_is_omap34xx()) + return 0; + if (!mpurate) return -EINVAL; @@ -345,9 +216,6 @@ static int __init omap2_clk_arch_init(void) return 0; } -arch_initcall(omap2_clk_arch_init); - - -#endif +arch_initcall(omap3xxx_clk_arch_init); diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 9a2c07eac9ad..313efc0e5a0f 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -8,6 +8,7 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H #define __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H +int omap3xxx_clk_init(void); int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); void omap3_clk_lock_dpll5(void); @@ -19,6 +20,6 @@ extern struct clk *arm_fck_p; extern const struct clkops clkops_omap3430es2_ssi_wait; extern const struct clkops clkops_omap3430es2_hsotgusb_wait; extern const struct clkops clkops_omap3430es2_dss_usbhost_wait; -extern const struct clkops clkops_noncore_dpll_ops; +extern const struct clkops omap3_clkops_noncore_dpll_ops; #endif diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c index 74930e3158e3..8728f1fbc5b1 100644 --- a/arch/arm/mach-omap2/clock34xx_data.c +++ b/arch/arm/mach-omap2/clock34xx_data.c @@ -337,7 +337,7 @@ static struct dpll_data dpll2_dd = { static struct clk dpll2_ck = { .name = "dpll2_ck", - .ops = &clkops_noncore_dpll_ops, + .ops = &omap3_clkops_noncore_dpll_ops, .parent = &sys_ck, .dpll_data = &dpll2_dd, .round_rate = &omap2_dpll_round_rate, @@ -554,7 +554,7 @@ static struct dpll_data dpll4_dd = { static struct clk dpll4_ck = { .name = "dpll4_ck", - .ops = &clkops_noncore_dpll_ops, + .ops = &omap3_clkops_noncore_dpll_ops, .parent = &sys_ck, .dpll_data = &dpll4_dd, .round_rate = &omap2_dpll_round_rate, @@ -735,7 +735,7 @@ static struct clk omap_12m_fck = { .ops = &clkops_null, .parent = &omap_48m_fck, .fixed_div = 4, - .recalc = &omap2_fixed_divisor_recalc, + .recalc = &omap_fixed_divisor_recalc, }; /* This virstual clock is the source for dpll4_m4x2_ck */ @@ -854,7 +854,7 @@ static struct dpll_data dpll5_dd = { static struct clk dpll5_ck = { .name = "dpll5_ck", - .ops = &clkops_noncore_dpll_ops, + .ops = &omap3_clkops_noncore_dpll_ops, .parent = &sys_ck, .dpll_data = &dpll5_dd, .round_rate = &omap2_dpll_round_rate, @@ -1588,7 +1588,7 @@ static struct clk ssi_sst_fck_3430es1 = { .ops = &clkops_null, .parent = &ssi_ssr_fck_3430es1, .fixed_div = 2, - .recalc = &omap2_fixed_divisor_recalc, + .recalc = &omap_fixed_divisor_recalc, }; static struct clk ssi_sst_fck_3430es2 = { @@ -1596,7 +1596,7 @@ static struct clk ssi_sst_fck_3430es2 = { .ops = &clkops_null, .parent = &ssi_ssr_fck_3430es2, .fixed_div = 2, - .recalc = &omap2_fixed_divisor_recalc, + .recalc = &omap_fixed_divisor_recalc, }; @@ -2988,139 +2988,140 @@ static struct clk wdt1_fck = { * clkdev */ -static struct omap_clk omap34xx_clks[] = { - CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X), - CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X), - CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X), - CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2), - CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X), - CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X), - CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X), - CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X), - CLK(NULL, "sys_ck", &sys_ck, CK_343X), - CLK(NULL, "sys_altclk", &sys_altclk, CK_343X), - CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X), - CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X), - CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X), - CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X), - CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X), +/* XXX At some point we should rename this file to clock3xxx_data.c */ +static struct omap_clk omap3xxx_clks[] = { + CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX), + CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX), + CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX), + CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_AM35XX), + CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX), + CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX), + CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX), + CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), + CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), + CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), + CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), + CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX), + CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), + CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX), + CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX), CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X), CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X), - CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X), - CLK(NULL, "core_ck", &core_ck, CK_343X), - CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X), - CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X), - CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X), - CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X), - CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X), - CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X), - CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X), - CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X), - CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X), - CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X), - CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X), - CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X), - CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X), - CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X), - CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X), - CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X), - CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X), - CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X), - CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X), - CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X), - CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X), - CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X), - CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X), - CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X), - CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X), - CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2), - CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2), - CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X), - CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X), - CLK(NULL, "corex2_fck", &corex2_fck, CK_343X), - CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X), - CLK(NULL, "mpu_ck", &mpu_ck, CK_343X), - CLK(NULL, "arm_fck", &arm_fck, CK_343X), - CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X), + CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX), + CLK(NULL, "core_ck", &core_ck, CK_3XXX), + CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX), + CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX), + CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX), + CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX), + CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX), + CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX), + CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX), + CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX), + CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX), + CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX), + CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX), + CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX), + CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX), + CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX), + CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX), + CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX), + CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX), + CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX), + CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX), + CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX), + CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX), + CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX), + CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX), + CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX), + CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX), + CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2 | CK_AM35XX), + CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2 | CK_AM35XX), + CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX), + CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX), + CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX), + CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX), + CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX), + CLK(NULL, "arm_fck", &arm_fck, CK_3XXX), + CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X), CLK(NULL, "iva2_ck", &iva2_ck, CK_343X), - CLK(NULL, "l3_ick", &l3_ick, CK_343X), - CLK(NULL, "l4_ick", &l4_ick, CK_343X), - CLK(NULL, "rm_ick", &rm_ick, CK_343X), + CLK(NULL, "l3_ick", &l3_ick, CK_3XXX), + CLK(NULL, "l4_ick", &l4_ick, CK_3XXX), + CLK(NULL, "rm_ick", &rm_ick, CK_3XXX), CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1), CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1), CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), - CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2), - CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2), + CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2 | CK_3517), + CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2 | CK_3517), CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), CLK(NULL, "modem_fck", &modem_fck, CK_343X), CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X), CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X), - CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X), - CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X), - CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2), - CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2), - CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2), - CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X), - CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2), - CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X), + CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX), + CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX), + CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_AM35XX), + CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_AM35XX), + CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX), + CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), + CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2 | CK_AM35XX), + CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX), CLK(NULL, "mspro_fck", &mspro_fck, CK_343X), - CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X), - CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X), - CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X), - CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X), - CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X), - CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X), - CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X), - CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X), - CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X), - CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X), - CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X), - CLK(NULL, "uart2_fck", &uart2_fck, CK_343X), - CLK(NULL, "uart1_fck", &uart1_fck, CK_343X), + CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX), + CLK("i2c_omap.3", "fck", &i2c3_fck, CK_3XXX), + CLK("i2c_omap.2", "fck", &i2c2_fck, CK_3XXX), + CLK("i2c_omap.1", "fck", &i2c1_fck, CK_3XXX), + CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_3XXX), + CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_3XXX), + CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX), + CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_3XXX), + CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_3XXX), + CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_3XXX), + CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_3XXX), + CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX), + CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX), CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), - CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X), - CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X), + CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX), + CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX), CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2), CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2), - CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X), + CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX), CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2), - CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X), - CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X), + CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX), + CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX), CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), CLK(NULL, "pka_ick", &pka_ick, CK_343X), - CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X), - CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2), - CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2), + CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), + CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_AM35XX), + CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX), CLK(NULL, "icr_ick", &icr_ick, CK_343X), CLK(NULL, "aes2_ick", &aes2_ick, CK_343X), CLK(NULL, "sha12_ick", &sha12_ick, CK_343X), CLK(NULL, "des2_ick", &des2_ick, CK_343X), - CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X), - CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X), + CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX), + CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX), CLK(NULL, "mspro_ick", &mspro_ick, CK_343X), - CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X), - CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X), - CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X), - CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X), - CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X), - CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X), - CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X), - CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X), - CLK(NULL, "uart2_ick", &uart2_ick, CK_343X), - CLK(NULL, "uart1_ick", &uart1_ick, CK_343X), - CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X), - CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X), - CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X), - CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X), + CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), + CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), + CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX), + CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX), + CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX), + CLK("i2c_omap.3", "ick", &i2c3_ick, CK_3XXX), + CLK("i2c_omap.2", "ick", &i2c2_ick, CK_3XXX), + CLK("i2c_omap.1", "ick", &i2c1_ick, CK_3XXX), + CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX), + CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX), + CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX), + CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX), + CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX), + CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX), CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X), - CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X), + CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX), CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X), CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2), @@ -3131,96 +3132,100 @@ static struct omap_clk omap34xx_clks[] = { CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), CLK(NULL, "des1_ick", &des1_ick, CK_343X), CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), - CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2), - CLK("omapdss", "tv_fck", &dss_tv_fck, CK_343X), - CLK("omapdss", "video_fck", &dss_96m_fck, CK_343X), - CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_343X), + CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2 | CK_AM35XX), + CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX), + CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX), + CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX), CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1), - CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2), + CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2 | CK_AM35XX), CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), CLK(NULL, "cam_ick", &cam_ick, CK_343X), CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), - CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2), - CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2), - CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2), + CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2 | CK_AM35XX), + CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX), + CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2 | CK_AM35XX), CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2), - CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X), - CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X), - CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X), - CLK("omap_wdt", "fck", &wdt2_fck, CK_343X), + CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX), + CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX), + CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX), + CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX), CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X), CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2), - CLK("omap_wdt", "ick", &wdt2_ick, CK_343X), - CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X), - CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X), - CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X), - CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X), - CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X), - CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X), - CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X), - CLK(NULL, "uart3_fck", &uart3_fck, CK_343X), - CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X), - CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X), - CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X), - CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X), - CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X), - CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X), - CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X), - CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X), - CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X), - CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X), - CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X), - CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X), - CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X), - CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X), - CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X), - CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X), - CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X), - CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X), - CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X), - CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X), - CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X), - CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X), - CLK(NULL, "uart3_ick", &uart3_ick, CK_343X), - CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X), - CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X), - CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X), - CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X), - CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X), - CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X), - CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X), - CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X), - CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X), - CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X), - CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X), - CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X), - CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X), - CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X), - CLK("etb", "emu_src_ck", &emu_src_ck, CK_343X), - CLK(NULL, "pclk_fck", &pclk_fck, CK_343X), - CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X), - CLK(NULL, "atclk_fck", &atclk_fck, CK_343X), - CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X), - CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X), + CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX), + CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX), + CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX), + CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX), + CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX), + CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX), + CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX), + CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), + CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), + CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX), + CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX), + CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX), + CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX), + CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX), + CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX), + CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX), + CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX), + CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX), + CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX), + CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX), + CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX), + CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX), + CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX), + CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX), + CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX), + CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX), + CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX), + CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX), + CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX), + CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX), + CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX), + CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX), + CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX), + CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX), + CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX), + CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX), + CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX), + CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX), + CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX), + CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX), + CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX), + CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX), + CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX), + CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_3XXX), + CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_3XXX), + CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_3XXX), + CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX), + CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX), + CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX), + CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX), + CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX), + CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX), CLK(NULL, "sr1_fck", &sr1_fck, CK_343X), CLK(NULL, "sr2_fck", &sr2_fck, CK_343X), CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X), - CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X), - CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X), - CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X), + CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX), + CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX), + CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX), }; -int __init omap2_clk_init(void) +int __init omap3xxx_clk_init(void) { - /* struct prcm_config *prcm; */ struct omap_clk *c; - /* u32 clkrate; */ - u32 cpu_clkflg; - - if (cpu_is_omap34xx()) { + u32 cpu_clkflg = CK_3XXX; + + if (cpu_is_omap3517()) { + cpu_mask = RATE_IN_343X | RATE_IN_3430ES2; + cpu_clkflg |= CK_3517; + } else if (cpu_is_omap3505()) { + cpu_mask = RATE_IN_343X | RATE_IN_3430ES2; + cpu_clkflg |= CK_3505; + } else if (cpu_is_omap34xx()) { cpu_mask = RATE_IN_343X; - cpu_clkflg = CK_343X; + cpu_clkflg |= CK_343X; /* * Update this if there are further clock changes between ES2 @@ -3237,31 +3242,16 @@ int __init omap2_clk_init(void) clk_init(&omap2_clk_functions); - for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) + for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); c++) clk_preinit(c->lk.clk); - for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) + for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); c++) if (c->cpu & cpu_clkflg) { clkdev_add(&c->lk); clk_register(c->lk.clk); omap2_init_clk_clkdm(c->lk.clk); } - /* REVISIT: Not yet ready for OMAP3 */ -#if 0 - /* Check the MPU rate set by bootloader */ - clkrate = omap2_get_dpll_rate_24xx(&dpll_ck); - for (prcm = rate_table; prcm->mpu_speed; prcm++) { - if (!(prcm->flags & cpu_mask)) - continue; - if (prcm->xtal_speed != sys_ck.rate) - continue; - if (prcm->dpll_speed <= clkrate) - break; - } - curr_prcm_set = prcm; -#endif - recalculate_root_clocks(); printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): " diff --git a/arch/arm/mach-omap2/clock44xx.c b/arch/arm/mach-omap2/clock44xx.c index e370868a79a8..84ee6b0c7995 100644 --- a/arch/arm/mach-omap2/clock44xx.c +++ b/arch/arm/mach-omap2/clock44xx.c @@ -13,21 +13,7 @@ #include <linux/errno.h> #include "clock.h" -struct clk_functions omap2_clk_functions = { - .clk_enable = omap2_clk_enable, - .clk_disable = omap2_clk_disable, - .clk_round_rate = omap2_clk_round_rate, - .clk_set_rate = omap2_clk_set_rate, - .clk_set_parent = omap2_clk_set_parent, - .clk_disable_unused = omap2_clk_disable_unused, -}; - -const struct clkops clkops_noncore_dpll_ops = { +const struct clkops omap4_clkops_noncore_dpll_ops = { .enable = &omap3_noncore_dpll_enable, .disable = &omap3_noncore_dpll_disable, }; - -void omap2_clk_prepare_for_reboot(void) -{ - return; -} diff --git a/arch/arm/mach-omap2/clock44xx.h b/arch/arm/mach-omap2/clock44xx.h index 59b9ced4daa1..efe849416aac 100644 --- a/arch/arm/mach-omap2/clock44xx.h +++ b/arch/arm/mach-omap2/clock44xx.h @@ -10,6 +10,8 @@ #define OMAP4430_MAX_DPLL_MULT 2048 #define OMAP4430_MAX_DPLL_DIV 128 -extern const struct clkops clkops_noncore_dpll_ops; +int omap4xxx_clk_init(void); + +extern const struct clkops omap4_clkops_noncore_dpll_ops; #endif diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 9d882bcb56e3..86af31d80a34 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -279,7 +279,7 @@ static struct clk dpll_abe_ck = { .parent = &abe_dpll_refclk_mux_ck, .dpll_data = &dpll_abe_dd, .init = &omap2_init_dpll_parent, - .ops = &clkops_noncore_dpll_ops, + .ops = &omap4_clkops_noncore_dpll_ops, .recalc = &omap3_dpll_recalc, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, @@ -668,7 +668,7 @@ static struct clk dpll_iva_ck = { .parent = &dpll_sys_ref_clk, .dpll_data = &dpll_iva_dd, .init = &omap2_init_dpll_parent, - .ops = &clkops_noncore_dpll_ops, + .ops = &omap4_clkops_noncore_dpll_ops, .recalc = &omap3_dpll_recalc, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, @@ -731,7 +731,7 @@ static struct clk dpll_mpu_ck = { .parent = &dpll_sys_ref_clk, .dpll_data = &dpll_mpu_dd, .init = &omap2_init_dpll_parent, - .ops = &clkops_noncore_dpll_ops, + .ops = &omap4_clkops_noncore_dpll_ops, .recalc = &omap3_dpll_recalc, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, @@ -807,7 +807,7 @@ static struct clk dpll_per_ck = { .parent = &dpll_sys_ref_clk, .dpll_data = &dpll_per_dd, .init = &omap2_init_dpll_parent, - .ops = &clkops_noncore_dpll_ops, + .ops = &omap4_clkops_noncore_dpll_ops, .recalc = &omap3_dpll_recalc, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, @@ -930,7 +930,7 @@ static struct clk dpll_unipro_ck = { .parent = &dpll_sys_ref_clk, .dpll_data = &dpll_unipro_dd, .init = &omap2_init_dpll_parent, - .ops = &clkops_noncore_dpll_ops, + .ops = &omap4_clkops_noncore_dpll_ops, .recalc = &omap3_dpll_recalc, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, @@ -988,7 +988,7 @@ static struct clk dpll_usb_ck = { .parent = &dpll_sys_ref_clk, .dpll_data = &dpll_usb_dd, .init = &omap2_init_dpll_parent, - .ops = &clkops_noncore_dpll_ops, + .ops = &omap4_clkops_noncore_dpll_ops, .recalc = &omap3_dpll_recalc, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, @@ -2726,11 +2726,9 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X), }; -int __init omap2_clk_init(void) +int __init omap4xxx_clk_init(void) { - /* struct prcm_config *prcm; */ struct omap_clk *c; - /* u32 clkrate; */ u32 cpu_clkflg; if (cpu_is_omap44xx()) { @@ -2749,9 +2747,7 @@ int __init omap2_clk_init(void) if (c->cpu & cpu_clkflg) { clkdev_add(&c->lk); clk_register(c->lk.clk); - /* TODO omap2_init_clk_clkdm(c->lk.clk); - */ } recalculate_root_clocks(); diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index dd285f001467..a38a615b422f 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -1,10 +1,11 @@ /* - * OMAP2/3 clockdomain framework functions + * OMAP2/3/4 clockdomain framework functions * - * Copyright (C) 2008 Texas Instruments, Inc. + * Copyright (C) 2008-2009 Texas Instruments, Inc. * Copyright (C) 2008-2009 Nokia Corporation * * Written by Paul Walmsley and Jouni Högander + * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -26,43 +27,124 @@ #include <linux/bitops.h> -#include <plat/clock.h> - #include "prm.h" #include "prm-regbits-24xx.h" #include "cm.h" +#include <plat/clock.h> #include <plat/powerdomain.h> #include <plat/clockdomain.h> +#include <plat/prcm.h> /* clkdm_list contains all registered struct clockdomains */ static LIST_HEAD(clkdm_list); -/* clkdm_mutex protects clkdm_list add and del ops */ -static DEFINE_MUTEX(clkdm_mutex); - -/* array of powerdomain deps to be added/removed when clkdm in hwsup mode */ -static struct clkdm_pwrdm_autodep *autodeps; +/* array of clockdomain deps to be added/removed when clkdm in hwsup mode */ +static struct clkdm_autodep *autodeps; /* Private functions */ +static struct clockdomain *_clkdm_lookup(const char *name) +{ + struct clockdomain *clkdm, *temp_clkdm; + + if (!name) + return NULL; + + clkdm = NULL; + + list_for_each_entry(temp_clkdm, &clkdm_list, node) { + if (!strcmp(name, temp_clkdm->name)) { + clkdm = temp_clkdm; + break; + } + } + + return clkdm; +} + +/** + * _clkdm_register - register a clockdomain + * @clkdm: struct clockdomain * to register + * + * Adds a clockdomain to the internal clockdomain list. + * Returns -EINVAL if given a null pointer, -EEXIST if a clockdomain is + * already registered by the provided name, or 0 upon success. + */ +static int _clkdm_register(struct clockdomain *clkdm) +{ + struct powerdomain *pwrdm; + + if (!clkdm || !clkdm->name) + return -EINVAL; + + if (!omap_chip_is(clkdm->omap_chip)) + return -EINVAL; + + pwrdm = pwrdm_lookup(clkdm->pwrdm.name); + if (!pwrdm) { + pr_err("clockdomain: %s: powerdomain %s does not exist\n", + clkdm->name, clkdm->pwrdm.name); + return -EINVAL; + } + clkdm->pwrdm.ptr = pwrdm; + + /* Verify that the clockdomain is not already registered */ + if (_clkdm_lookup(clkdm->name)) + return -EEXIST; + + list_add(&clkdm->node, &clkdm_list); + + pwrdm_add_clkdm(pwrdm, clkdm); + + pr_debug("clockdomain: registered %s\n", clkdm->name); + + return 0; +} + +/* _clkdm_deps_lookup - look up the specified clockdomain in a clkdm list */ +static struct clkdm_dep *_clkdm_deps_lookup(struct clockdomain *clkdm, + struct clkdm_dep *deps) +{ + struct clkdm_dep *cd; + + if (!clkdm || !deps || !omap_chip_is(clkdm->omap_chip)) + return ERR_PTR(-EINVAL); + + for (cd = deps; cd->clkdm_name; cd++) { + if (!omap_chip_is(cd->omap_chip)) + continue; + + if (!cd->clkdm && cd->clkdm_name) + cd->clkdm = _clkdm_lookup(cd->clkdm_name); + + if (cd->clkdm == clkdm) + break; + } + + if (!cd->clkdm_name) + return ERR_PTR(-ENOENT); + + return cd; +} + /* - * _autodep_lookup - resolve autodep pwrdm names to pwrdm pointers; store - * @autodep: struct clkdm_pwrdm_autodep * to resolve + * _autodep_lookup - resolve autodep clkdm names to clkdm pointers; store + * @autodep: struct clkdm_autodep * to resolve * - * Resolve autodep powerdomain names to powerdomain pointers via - * pwrdm_lookup() and store the pointers in the autodep structure. An - * "autodep" is a powerdomain sleep/wakeup dependency that is + * Resolve autodep clockdomain names to clockdomain pointers via + * clkdm_lookup() and store the pointers in the autodep structure. An + * "autodep" is a clockdomain sleep/wakeup dependency that is * automatically added and removed whenever clocks in the associated * clockdomain are enabled or disabled (respectively) when the * clockdomain is in hardware-supervised mode. Meant to be called * once at clockdomain layer initialization, since these should remain * fixed for a particular architecture. No return value. */ -static void _autodep_lookup(struct clkdm_pwrdm_autodep *autodep) +static void _autodep_lookup(struct clkdm_autodep *autodep) { - struct powerdomain *pwrdm; + struct clockdomain *clkdm; if (!autodep) return; @@ -70,13 +152,13 @@ static void _autodep_lookup(struct clkdm_pwrdm_autodep *autodep) if (!omap_chip_is(autodep->omap_chip)) return; - pwrdm = pwrdm_lookup(autodep->pwrdm.name); - if (!pwrdm) { - pr_err("clockdomain: autodeps: powerdomain %s does not exist\n", - autodep->pwrdm.name); - pwrdm = ERR_PTR(-ENOENT); + clkdm = clkdm_lookup(autodep->clkdm.name); + if (!clkdm) { + pr_err("clockdomain: autodeps: clockdomain %s does not exist\n", + autodep->clkdm.name); + clkdm = ERR_PTR(-ENOENT); } - autodep->pwrdm.ptr = pwrdm; + autodep->clkdm.ptr = clkdm; } /* @@ -89,21 +171,21 @@ static void _autodep_lookup(struct clkdm_pwrdm_autodep *autodep) */ static void _clkdm_add_autodeps(struct clockdomain *clkdm) { - struct clkdm_pwrdm_autodep *autodep; + struct clkdm_autodep *autodep; - for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) { - if (IS_ERR(autodep->pwrdm.ptr)) + for (autodep = autodeps; autodep->clkdm.ptr; autodep++) { + if (IS_ERR(autodep->clkdm.ptr)) continue; if (!omap_chip_is(autodep->omap_chip)) continue; pr_debug("clockdomain: adding %s sleepdep/wkdep for " - "pwrdm %s\n", autodep->pwrdm.ptr->name, - clkdm->pwrdm.ptr->name); + "clkdm %s\n", autodep->clkdm.ptr->name, + clkdm->name); - pwrdm_add_sleepdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr); - pwrdm_add_wkdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr); + clkdm_add_sleepdep(clkdm, autodep->clkdm.ptr); + clkdm_add_wkdep(clkdm, autodep->clkdm.ptr); } } @@ -117,21 +199,21 @@ static void _clkdm_add_autodeps(struct clockdomain *clkdm) */ static void _clkdm_del_autodeps(struct clockdomain *clkdm) { - struct clkdm_pwrdm_autodep *autodep; + struct clkdm_autodep *autodep; - for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) { - if (IS_ERR(autodep->pwrdm.ptr)) + for (autodep = autodeps; autodep->clkdm.ptr; autodep++) { + if (IS_ERR(autodep->clkdm.ptr)) continue; if (!omap_chip_is(autodep->omap_chip)) continue; pr_debug("clockdomain: removing %s sleepdep/wkdep for " - "pwrdm %s\n", autodep->pwrdm.ptr->name, - clkdm->pwrdm.ptr->name); + "clkdm %s\n", autodep->clkdm.ptr->name, + clkdm->name); - pwrdm_del_sleepdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr); - pwrdm_del_wkdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr); + clkdm_del_sleepdep(clkdm, autodep->clkdm.ptr); + clkdm_del_wkdep(clkdm, autodep->clkdm.ptr); } } @@ -145,152 +227,167 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm) */ static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable) { - u32 v; + u32 bits, v; if (cpu_is_omap24xx()) { if (enable) - v = OMAP24XX_CLKSTCTRL_ENABLE_AUTO; + bits = OMAP24XX_CLKSTCTRL_ENABLE_AUTO; else - v = OMAP24XX_CLKSTCTRL_DISABLE_AUTO; - } else if (cpu_is_omap34xx()) { + bits = OMAP24XX_CLKSTCTRL_DISABLE_AUTO; + } else if (cpu_is_omap34xx() | cpu_is_omap44xx()) { if (enable) - v = OMAP34XX_CLKSTCTRL_ENABLE_AUTO; + bits = OMAP34XX_CLKSTCTRL_ENABLE_AUTO; else - v = OMAP34XX_CLKSTCTRL_DISABLE_AUTO; + bits = OMAP34XX_CLKSTCTRL_DISABLE_AUTO; } else { BUG(); } - cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, - v << __ffs(clkdm->clktrctrl_mask), - clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL); -} - -static struct clockdomain *_clkdm_lookup(const char *name) -{ - struct clockdomain *clkdm, *temp_clkdm; - - if (!name) - return NULL; + bits = bits << __ffs(clkdm->clktrctrl_mask); - clkdm = NULL; + v = __raw_readl(clkdm->clkstctrl_reg); + v &= ~(clkdm->clktrctrl_mask); + v |= bits; + __raw_writel(v, clkdm->clkstctrl_reg); - list_for_each_entry(temp_clkdm, &clkdm_list, node) { - if (!strcmp(name, temp_clkdm->name)) { - clkdm = temp_clkdm; - break; - } - } - - return clkdm; } - -/* Public functions */ - /** - * clkdm_init - set up the clockdomain layer - * @clkdms: optional pointer to an array of clockdomains to register - * @init_autodeps: optional pointer to an array of autodeps to register + * _init_wkdep_usecount - initialize wkdep usecounts to match hardware + * @clkdm: clockdomain to initialize wkdep usecounts * - * Set up internal state. If a pointer to an array of clockdomains - * was supplied, loop through the list of clockdomains, register all - * that are available on the current platform. Similarly, if a - * pointer to an array of clockdomain-powerdomain autodependencies was - * provided, register those. No return value. + * Initialize the wakeup dependency usecount variables for clockdomain @clkdm. + * If a wakeup dependency is present in the hardware, the usecount will be + * set to 1; otherwise, it will be set to 0. Software should clear all + * software wakeup dependencies prior to calling this function if it wishes + * to ensure that all usecounts start at 0. No return value. */ -void clkdm_init(struct clockdomain **clkdms, - struct clkdm_pwrdm_autodep *init_autodeps) +static void _init_wkdep_usecount(struct clockdomain *clkdm) { - struct clockdomain **c = NULL; - struct clkdm_pwrdm_autodep *autodep = NULL; + u32 v; + struct clkdm_dep *cd; - if (clkdms) - for (c = clkdms; *c; c++) - clkdm_register(*c); + if (!clkdm->wkdep_srcs) + return; - autodeps = init_autodeps; - if (autodeps) - for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) - _autodep_lookup(autodep); + for (cd = clkdm->wkdep_srcs; cd->clkdm_name; cd++) { + if (!omap_chip_is(cd->omap_chip)) + continue; + + if (!cd->clkdm && cd->clkdm_name) + cd->clkdm = _clkdm_lookup(cd->clkdm_name); + + if (!cd->clkdm) { + WARN(!cd->clkdm, "clockdomain: %s: wkdep clkdm %s not " + "found\n", clkdm->name, cd->clkdm_name); + continue; + } + + v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs, + PM_WKDEP, + (1 << cd->clkdm->dep_bit)); + + if (v) + pr_debug("clockdomain: %s: wakeup dependency already " + "set to wake up when %s wakes\n", + clkdm->name, cd->clkdm->name); + + atomic_set(&cd->wkdep_usecount, (v) ? 1 : 0); + } } /** - * clkdm_register - register a clockdomain - * @clkdm: struct clockdomain * to register + * _init_sleepdep_usecount - initialize sleepdep usecounts to match hardware + * @clkdm: clockdomain to initialize sleepdep usecounts * - * Adds a clockdomain to the internal clockdomain list. - * Returns -EINVAL if given a null pointer, -EEXIST if a clockdomain is - * already registered by the provided name, or 0 upon success. + * Initialize the sleep dependency usecount variables for clockdomain @clkdm. + * If a sleep dependency is present in the hardware, the usecount will be + * set to 1; otherwise, it will be set to 0. Software should clear all + * software sleep dependencies prior to calling this function if it wishes + * to ensure that all usecounts start at 0. No return value. */ -int clkdm_register(struct clockdomain *clkdm) +static void _init_sleepdep_usecount(struct clockdomain *clkdm) { - int ret = -EINVAL; - struct powerdomain *pwrdm; + u32 v; + struct clkdm_dep *cd; - if (!clkdm || !clkdm->name) - return -EINVAL; + if (!cpu_is_omap34xx()) + return; - if (!omap_chip_is(clkdm->omap_chip)) - return -EINVAL; + if (!clkdm->sleepdep_srcs) + return; - pwrdm = pwrdm_lookup(clkdm->pwrdm.name); - if (!pwrdm) { - pr_err("clockdomain: %s: powerdomain %s does not exist\n", - clkdm->name, clkdm->pwrdm.name); - return -EINVAL; - } - clkdm->pwrdm.ptr = pwrdm; + for (cd = clkdm->sleepdep_srcs; cd->clkdm_name; cd++) { + if (!omap_chip_is(cd->omap_chip)) + continue; - mutex_lock(&clkdm_mutex); - /* Verify that the clockdomain is not already registered */ - if (_clkdm_lookup(clkdm->name)) { - ret = -EEXIST; - goto cr_unlock; - } + if (!cd->clkdm && cd->clkdm_name) + cd->clkdm = _clkdm_lookup(cd->clkdm_name); - list_add(&clkdm->node, &clkdm_list); + if (!cd->clkdm) { + WARN(!cd->clkdm, "clockdomain: %s: sleepdep clkdm %s " + "not found\n", clkdm->name, cd->clkdm_name); + continue; + } - pwrdm_add_clkdm(pwrdm, clkdm); + v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs, + OMAP3430_CM_SLEEPDEP, + (1 << cd->clkdm->dep_bit)); - pr_debug("clockdomain: registered %s\n", clkdm->name); - ret = 0; + if (v) + pr_debug("clockdomain: %s: sleep dependency already " + "set to prevent from idling until %s " + "idles\n", clkdm->name, cd->clkdm->name); -cr_unlock: - mutex_unlock(&clkdm_mutex); + atomic_set(&cd->sleepdep_usecount, (v) ? 1 : 0); + } +}; - return ret; -} +/* Public functions */ /** - * clkdm_unregister - unregister a clockdomain - * @clkdm: struct clockdomain * to unregister + * clkdm_init - set up the clockdomain layer + * @clkdms: optional pointer to an array of clockdomains to register + * @init_autodeps: optional pointer to an array of autodeps to register * - * Removes a clockdomain from the internal clockdomain list. Returns - * -EINVAL if clkdm argument is NULL. + * Set up internal state. If a pointer to an array of clockdomains + * @clkdms was supplied, loop through the list of clockdomains, + * register all that are available on the current platform. Similarly, + * if a pointer to an array of clockdomain autodependencies + * @init_autodeps was provided, register those. No return value. */ -int clkdm_unregister(struct clockdomain *clkdm) +void clkdm_init(struct clockdomain **clkdms, + struct clkdm_autodep *init_autodeps) { - if (!clkdm) - return -EINVAL; - - pwrdm_del_clkdm(clkdm->pwrdm.ptr, clkdm); + struct clockdomain **c = NULL; + struct clockdomain *clkdm; + struct clkdm_autodep *autodep = NULL; - mutex_lock(&clkdm_mutex); - list_del(&clkdm->node); - mutex_unlock(&clkdm_mutex); + if (clkdms) + for (c = clkdms; *c; c++) + _clkdm_register(*c); - pr_debug("clockdomain: unregistered %s\n", clkdm->name); + autodeps = init_autodeps; + if (autodeps) + for (autodep = autodeps; autodep->clkdm.ptr; autodep++) + _autodep_lookup(autodep); - return 0; + /* + * Ensure that the *dep_usecount registers reflect the current + * state of the PRCM. + */ + list_for_each_entry(clkdm, &clkdm_list, node) { + _init_wkdep_usecount(clkdm); + _init_sleepdep_usecount(clkdm); + } } /** * clkdm_lookup - look up a clockdomain by name, return a pointer * @name: name of clockdomain * - * Find a registered clockdomain by its name. Returns a pointer to the - * struct clockdomain if found, or NULL otherwise. + * Find a registered clockdomain by its name @name. Returns a pointer + * to the struct clockdomain if found, or NULL otherwise. */ struct clockdomain *clkdm_lookup(const char *name) { @@ -301,14 +398,12 @@ struct clockdomain *clkdm_lookup(const char *name) clkdm = NULL; - mutex_lock(&clkdm_mutex); list_for_each_entry(temp_clkdm, &clkdm_list, node) { if (!strcmp(name, temp_clkdm->name)) { clkdm = temp_clkdm; break; } } - mutex_unlock(&clkdm_mutex); return clkdm; } @@ -317,8 +412,8 @@ struct clockdomain *clkdm_lookup(const char *name) * clkdm_for_each - call function on each registered clockdomain * @fn: callback function * * - * Call the supplied function for each registered clockdomain. - * The callback function can return anything but 0 to bail + * Call the supplied function @fn for each registered clockdomain. + * The callback function @fn can return anything but 0 to bail * out early from the iterator. The callback function is called with * the clkdm_mutex held, so no clockdomain structure manipulation * functions should be called from the callback, although hardware @@ -336,13 +431,11 @@ int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user), if (!fn) return -EINVAL; - mutex_lock(&clkdm_mutex); list_for_each_entry(clkdm, &clkdm_list, node) { ret = (*fn)(clkdm, user); if (ret) break; } - mutex_unlock(&clkdm_mutex); return ret; } @@ -353,7 +446,7 @@ int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user), * @clkdm: struct clockdomain * * * Return a pointer to the struct powerdomain that the specified clockdomain - * 'clkdm' exists in, or returns NULL if clkdm argument is NULL. + * @clkdm exists in, or returns NULL if @clkdm is NULL. */ struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm) { @@ -367,11 +460,309 @@ struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm) /* Hardware clockdomain control */ /** + * clkdm_add_wkdep - add a wakeup dependency from clkdm2 to clkdm1 + * @clkdm1: wake this struct clockdomain * up (dependent) + * @clkdm2: when this struct clockdomain * wakes up (source) + * + * When the clockdomain represented by @clkdm2 wakes up, wake up + * @clkdm1. Implemented in hardware on the OMAP, this feature is + * designed to reduce wakeup latency of the dependent clockdomain @clkdm1. + * Returns -EINVAL if presented with invalid clockdomain pointers, + * -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or 0 upon + * success. + */ +int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) +{ + struct clkdm_dep *cd; + + if (!clkdm1 || !clkdm2) + return -EINVAL; + + cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs); + if (IS_ERR(cd)) { + pr_debug("clockdomain: hardware cannot set/clear wake up of " + "%s when %s wakes up\n", clkdm1->name, clkdm2->name); + return PTR_ERR(cd); + } + + if (atomic_inc_return(&cd->wkdep_usecount) == 1) { + pr_debug("clockdomain: hardware will wake up %s when %s wakes " + "up\n", clkdm1->name, clkdm2->name); + + prm_set_mod_reg_bits((1 << clkdm2->dep_bit), + clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); + } + + return 0; +} + +/** + * clkdm_del_wkdep - remove a wakeup dependency from clkdm2 to clkdm1 + * @clkdm1: wake this struct clockdomain * up (dependent) + * @clkdm2: when this struct clockdomain * wakes up (source) + * + * Remove a wakeup dependency causing @clkdm1 to wake up when @clkdm2 + * wakes up. Returns -EINVAL if presented with invalid clockdomain + * pointers, -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or + * 0 upon success. + */ +int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) +{ + struct clkdm_dep *cd; + + if (!clkdm1 || !clkdm2) + return -EINVAL; + + cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs); + if (IS_ERR(cd)) { + pr_debug("clockdomain: hardware cannot set/clear wake up of " + "%s when %s wakes up\n", clkdm1->name, clkdm2->name); + return PTR_ERR(cd); + } + + if (atomic_dec_return(&cd->wkdep_usecount) == 0) { + pr_debug("clockdomain: hardware will no longer wake up %s " + "after %s wakes up\n", clkdm1->name, clkdm2->name); + + prm_clear_mod_reg_bits((1 << clkdm2->dep_bit), + clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); + } + + return 0; +} + +/** + * clkdm_read_wkdep - read wakeup dependency state from clkdm2 to clkdm1 + * @clkdm1: wake this struct clockdomain * up (dependent) + * @clkdm2: when this struct clockdomain * wakes up (source) + * + * Return 1 if a hardware wakeup dependency exists wherein @clkdm1 will be + * awoken when @clkdm2 wakes up; 0 if dependency is not set; -EINVAL + * if either clockdomain pointer is invalid; or -ENOENT if the hardware + * is incapable. + * + * REVISIT: Currently this function only represents software-controllable + * wakeup dependencies. Wakeup dependencies fixed in hardware are not + * yet handled here. + */ +int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) +{ + struct clkdm_dep *cd; + + if (!clkdm1 || !clkdm2) + return -EINVAL; + + cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs); + if (IS_ERR(cd)) { + pr_debug("clockdomain: hardware cannot set/clear wake up of " + "%s when %s wakes up\n", clkdm1->name, clkdm2->name); + return PTR_ERR(cd); + } + + /* XXX It's faster to return the atomic wkdep_usecount */ + return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP, + (1 << clkdm2->dep_bit)); +} + +/** + * clkdm_clear_all_wkdeps - remove all wakeup dependencies from target clkdm + * @clkdm: struct clockdomain * to remove all wakeup dependencies from + * + * Remove all inter-clockdomain wakeup dependencies that could cause + * @clkdm to wake. Intended to be used during boot to initialize the + * PRCM to a known state, after all clockdomains are put into swsup idle + * and woken up. Returns -EINVAL if @clkdm pointer is invalid, or + * 0 upon success. + */ +int clkdm_clear_all_wkdeps(struct clockdomain *clkdm) +{ + struct clkdm_dep *cd; + u32 mask = 0; + + if (!clkdm) + return -EINVAL; + + for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { + if (!omap_chip_is(cd->omap_chip)) + continue; + + /* PRM accesses are slow, so minimize them */ + mask |= 1 << cd->clkdm->dep_bit; + atomic_set(&cd->wkdep_usecount, 0); + } + + prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP); + + return 0; +} + +/** + * clkdm_add_sleepdep - add a sleep dependency from clkdm2 to clkdm1 + * @clkdm1: prevent this struct clockdomain * from sleeping (dependent) + * @clkdm2: when this struct clockdomain * is active (source) + * + * Prevent @clkdm1 from automatically going inactive (and then to + * retention or off) if @clkdm2 is active. Returns -EINVAL if + * presented with invalid clockdomain pointers or called on a machine + * that does not support software-configurable hardware sleep + * dependencies, -ENOENT if the specified dependency cannot be set in + * hardware, or 0 upon success. + */ +int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) +{ + struct clkdm_dep *cd; + + if (!cpu_is_omap34xx()) + return -EINVAL; + + if (!clkdm1 || !clkdm2) + return -EINVAL; + + cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs); + if (IS_ERR(cd)) { + pr_debug("clockdomain: hardware cannot set/clear sleep " + "dependency affecting %s from %s\n", clkdm1->name, + clkdm2->name); + return PTR_ERR(cd); + } + + if (atomic_inc_return(&cd->sleepdep_usecount) == 1) { + pr_debug("clockdomain: will prevent %s from sleeping if %s " + "is active\n", clkdm1->name, clkdm2->name); + + cm_set_mod_reg_bits((1 << clkdm2->dep_bit), + clkdm1->pwrdm.ptr->prcm_offs, + OMAP3430_CM_SLEEPDEP); + } + + return 0; +} + +/** + * clkdm_del_sleepdep - remove a sleep dependency from clkdm2 to clkdm1 + * @clkdm1: prevent this struct clockdomain * from sleeping (dependent) + * @clkdm2: when this struct clockdomain * is active (source) + * + * Allow @clkdm1 to automatically go inactive (and then to retention or + * off), independent of the activity state of @clkdm2. Returns -EINVAL + * if presented with invalid clockdomain pointers or called on a machine + * that does not support software-configurable hardware sleep dependencies, + * -ENOENT if the specified dependency cannot be cleared in hardware, or + * 0 upon success. + */ +int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) +{ + struct clkdm_dep *cd; + + if (!cpu_is_omap34xx()) + return -EINVAL; + + if (!clkdm1 || !clkdm2) + return -EINVAL; + + cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs); + if (IS_ERR(cd)) { + pr_debug("clockdomain: hardware cannot set/clear sleep " + "dependency affecting %s from %s\n", clkdm1->name, + clkdm2->name); + return PTR_ERR(cd); + } + + if (atomic_dec_return(&cd->sleepdep_usecount) == 0) { + pr_debug("clockdomain: will no longer prevent %s from " + "sleeping if %s is active\n", clkdm1->name, + clkdm2->name); + + cm_clear_mod_reg_bits((1 << clkdm2->dep_bit), + clkdm1->pwrdm.ptr->prcm_offs, + OMAP3430_CM_SLEEPDEP); + } + + return 0; +} + +/** + * clkdm_read_sleepdep - read sleep dependency state from clkdm2 to clkdm1 + * @clkdm1: prevent this struct clockdomain * from sleeping (dependent) + * @clkdm2: when this struct clockdomain * is active (source) + * + * Return 1 if a hardware sleep dependency exists wherein @clkdm1 will + * not be allowed to automatically go inactive if @clkdm2 is active; + * 0 if @clkdm1's automatic power state inactivity transition is independent + * of @clkdm2's; -EINVAL if either clockdomain pointer is invalid or called + * on a machine that does not support software-configurable hardware sleep + * dependencies; or -ENOENT if the hardware is incapable. + * + * REVISIT: Currently this function only represents software-controllable + * sleep dependencies. Sleep dependencies fixed in hardware are not + * yet handled here. + */ +int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) +{ + struct clkdm_dep *cd; + + if (!cpu_is_omap34xx()) + return -EINVAL; + + if (!clkdm1 || !clkdm2) + return -EINVAL; + + cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs); + if (IS_ERR(cd)) { + pr_debug("clockdomain: hardware cannot set/clear sleep " + "dependency affecting %s from %s\n", clkdm1->name, + clkdm2->name); + return PTR_ERR(cd); + } + + /* XXX It's faster to return the atomic sleepdep_usecount */ + return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, + OMAP3430_CM_SLEEPDEP, + (1 << clkdm2->dep_bit)); +} + +/** + * clkdm_clear_all_sleepdeps - remove all sleep dependencies from target clkdm + * @clkdm: struct clockdomain * to remove all sleep dependencies from + * + * Remove all inter-clockdomain sleep dependencies that could prevent + * @clkdm from idling. Intended to be used during boot to initialize the + * PRCM to a known state, after all clockdomains are put into swsup idle + * and woken up. Returns -EINVAL if @clkdm pointer is invalid, or + * 0 upon success. + */ +int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm) +{ + struct clkdm_dep *cd; + u32 mask = 0; + + if (!cpu_is_omap34xx()) + return -EINVAL; + + if (!clkdm) + return -EINVAL; + + for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) { + if (!omap_chip_is(cd->omap_chip)) + continue; + + /* PRM accesses are slow, so minimize them */ + mask |= 1 << cd->clkdm->dep_bit; + atomic_set(&cd->sleepdep_usecount, 0); + } + + prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, + OMAP3430_CM_SLEEPDEP); + + return 0; +} + +/** * omap2_clkdm_clktrctrl_read - read the clkdm's current state transition mode - * @clk: struct clk * of a clockdomain + * @clkdm: struct clkdm * of a clockdomain * - * Return the clockdomain's current state transition mode from the - * corresponding domain CM_CLKSTCTRL register. Returns -EINVAL if clk + * Return the clockdomain @clkdm current state transition mode from the + * corresponding domain CM_CLKSTCTRL register. Returns -EINVAL if @clkdm * is NULL or the current mode upon success. */ static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm) @@ -381,7 +772,7 @@ static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm) if (!clkdm) return -EINVAL; - v = cm_read_mod_reg(clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL); + v = __raw_readl(clkdm->clkstctrl_reg); v &= clkdm->clktrctrl_mask; v >>= __ffs(clkdm->clktrctrl_mask); @@ -393,7 +784,7 @@ static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm) * @clkdm: struct clockdomain * * * Instruct the CM to force a sleep transition on the specified - * clockdomain 'clkdm'. Returns -EINVAL if clk is NULL or if + * clockdomain @clkdm. Returns -EINVAL if @clkdm is NULL or if * clockdomain does not support software-initiated sleep; 0 upon * success. */ @@ -413,15 +804,17 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm) if (cpu_is_omap24xx()) { cm_set_mod_reg_bits(OMAP24XX_FORCESTATE, - clkdm->pwrdm.ptr->prcm_offs, PM_PWSTCTRL); + clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); - } else if (cpu_is_omap34xx()) { + } else if (cpu_is_omap34xx() | cpu_is_omap44xx()) { - u32 v = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP << + u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP << __ffs(clkdm->clktrctrl_mask)); - cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v, - clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL); + u32 v = __raw_readl(clkdm->clkstctrl_reg); + v &= ~(clkdm->clktrctrl_mask); + v |= bits; + __raw_writel(v, clkdm->clkstctrl_reg); } else { BUG(); @@ -435,7 +828,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm) * @clkdm: struct clockdomain * * * Instruct the CM to force a wakeup transition on the specified - * clockdomain 'clkdm'. Returns -EINVAL if clkdm is NULL or if the + * clockdomain @clkdm. Returns -EINVAL if @clkdm is NULL or if the * clockdomain does not support software-controlled wakeup; 0 upon * success. */ @@ -455,15 +848,17 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm) if (cpu_is_omap24xx()) { cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE, - clkdm->pwrdm.ptr->prcm_offs, PM_PWSTCTRL); + clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); - } else if (cpu_is_omap34xx()) { + } else if (cpu_is_omap34xx() | cpu_is_omap44xx()) { - u32 v = (OMAP34XX_CLKSTCTRL_FORCE_WAKEUP << + u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_WAKEUP << __ffs(clkdm->clktrctrl_mask)); - cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v, - clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL); + u32 v = __raw_readl(clkdm->clkstctrl_reg); + v &= ~(clkdm->clktrctrl_mask); + v |= bits; + __raw_writel(v, clkdm->clkstctrl_reg); } else { BUG(); @@ -476,7 +871,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm) * omap2_clkdm_allow_idle - enable hwsup idle transitions for clkdm * @clkdm: struct clockdomain * * - * Allow the hardware to automatically switch the clockdomain into + * Allow the hardware to automatically switch the clockdomain @clkdm into * active or idle states, as needed by downstream clocks. If the * clockdomain has any downstream clocks enabled in the clock * framework, wkdep/sleepdep autodependencies are added; this is so @@ -509,8 +904,8 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm) * @clkdm: struct clockdomain * * * Prevent the hardware from automatically switching the clockdomain - * into inactive or idle states. If the clockdomain has downstream - * clocks enabled in the clock framework, wkdep/sleepdep + * @clkdm into inactive or idle states. If the clockdomain has + * downstream clocks enabled in the clock framework, wkdep/sleepdep * autodependencies are removed. No return value. */ void omap2_clkdm_deny_idle(struct clockdomain *clkdm) @@ -541,14 +936,14 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm) * @clkdm: struct clockdomain * * @clk: struct clk * of the enabled downstream clock * - * Increment the usecount of this clockdomain 'clkdm' and ensure that - * it is awake. Intended to be called by clk_enable() code. If the - * clockdomain is in software-supervised idle mode, force the - * clockdomain to wake. If the clockdomain is in hardware-supervised - * idle mode, add clkdm-pwrdm autodependencies, to ensure that devices - * in the clockdomain can be read from/written to by on-chip processors. - * Returns -EINVAL if passed null pointers; returns 0 upon success or - * if the clockdomain is in hwsup idle mode. + * Increment the usecount of the clockdomain @clkdm and ensure that it + * is awake before @clk is enabled. Intended to be called by + * clk_enable() code. If the clockdomain is in software-supervised + * idle mode, force the clockdomain to wake. If the clockdomain is in + * hardware-supervised idle mode, add clkdm-pwrdm autodependencies, to + * ensure that devices in the clockdomain can be read from/written to + * by on-chip processors. Returns -EINVAL if passed null pointers; + * returns 0 upon success or if the clockdomain is in hwsup idle mode. */ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) { @@ -559,7 +954,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) * downstream clocks for debugging purposes? */ - if (!clkdm || !clk || !clkdm->clktrctrl_mask) + if (!clkdm || !clk || !clkdm->clkstctrl_reg) return -EINVAL; if (atomic_inc_return(&clkdm->usecount) > 1) @@ -593,13 +988,14 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) * @clkdm: struct clockdomain * * @clk: struct clk * of the disabled downstream clock * - * Decrement the usecount of this clockdomain 'clkdm'. Intended to be - * called by clk_disable() code. If the usecount goes to 0, put the - * clockdomain to sleep (software-supervised mode) or remove the - * clkdm-pwrdm autodependencies (hardware-supervised mode). Returns - * -EINVAL if passed null pointers; -ERANGE if the clkdm usecount - * underflows and debugging is enabled; or returns 0 upon success or - * if the clockdomain is in hwsup idle mode. + * Decrement the usecount of this clockdomain @clkdm when @clk is + * disabled. Intended to be called by clk_disable() code. If the + * clockdomain usecount goes to 0, put the clockdomain to sleep + * (software-supervised mode) or remove the clkdm autodependencies + * (hardware-supervised mode). Returns -EINVAL if passed null + * pointers; -ERANGE if the @clkdm usecount underflows and debugging + * is enabled; or returns 0 upon success or if the clockdomain is in + * hwsup idle mode. */ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) { @@ -610,7 +1006,7 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) * downstream clocks for debugging purposes? */ - if (!clkdm || !clk || !clkdm->clktrctrl_mask) + if (!clkdm || !clk || !clkdm->clkstctrl_reg) return -EINVAL; #ifdef DEBUG diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h index c4ee0761d908..8fc19ff2cd89 100644 --- a/arch/arm/mach-omap2/clockdomains.h +++ b/arch/arm/mach-omap2/clockdomains.h @@ -1,16 +1,420 @@ /* * OMAP2/3 clockdomains * - * Copyright (C) 2008 Texas Instruments, Inc. - * Copyright (C) 2008 Nokia Corporation + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * Copyright (C) 2008-2010 Nokia Corporation * - * Written by Paul Walmsley + * Written by Paul Walmsley and Jouni Högander + * + * This file contains clockdomains and clockdomain wakeup/sleep + * dependencies for the OMAP2/3 chips. Some notes: + * + * A useful validation rule for struct clockdomain: Any clockdomain + * referenced by a wkdep_srcs or sleepdep_srcs array must have a + * dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really just + * software-controllable dependencies. Non-software-controllable + * dependencies do exist, but they are not encoded below (yet). + * + * 24xx does not support programmable sleep dependencies (SLEEPDEP) + * + * The overly-specific dep_bit names are due to a bit name collision + * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift + * value are the same for all powerdomains: 2 + * + * XXX should dep_bit be a mask, so we can test to see if it is 0 as a + * sanity check? + * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE + */ + +/* + * To-Do List + * -> Port the Sleep/Wakeup dependencies for the domains + * from the Power domain framework */ #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H #include <plat/clockdomain.h> +#include "cm.h" +#include "prm.h" + +/* + * Clockdomain dependencies for wkdeps/sleepdeps + * + * XXX Hardware dependencies (e.g., dependencies that cannot be + * changed in software) are not included here yet, but should be. + */ + +/* OMAP2/3-common wakeup dependencies */ + +/* + * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP + * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE + * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE + * These can share data since they will never be present simultaneously + * on the same device. + */ +static struct clkdm_dep gfx_sgx_wkdeps[] = { + { + .clkdm_name = "core_l3_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) + }, + { + .clkdm_name = "core_l4_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) + }, + { + .clkdm_name = "iva2_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "mpu_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | + CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "wkup_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | + CHIP_IS_OMAP3430) + }, + { NULL }, +}; + + +/* 24XX-specific possible dependencies */ + +#ifdef CONFIG_ARCH_OMAP2 + +/* Wakeup dependency source arrays */ + +/* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */ +static struct clkdm_dep dsp_24xx_wkdeps[] = { + { + .clkdm_name = "core_l3_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) + }, + { + .clkdm_name = "core_l4_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) + }, + { + .clkdm_name = "mpu_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) + }, + { + .clkdm_name = "wkup_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) + }, + { NULL }, +}; + +/* + * 2420 PM_WKDEP_MPU: CORE, DSP, WKUP + * 2430 adds MDM + */ +static struct clkdm_dep mpu_24xx_wkdeps[] = { + { + .clkdm_name = "core_l3_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) + }, + { + .clkdm_name = "core_l4_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) + }, + { + .clkdm_name = "dsp_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) + }, + { + .clkdm_name = "wkup_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) + }, + { + .clkdm_name = "mdm_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) + }, + { NULL }, +}; + +/* + * 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP + * 2430 adds MDM + */ +static struct clkdm_dep core_24xx_wkdeps[] = { + { + .clkdm_name = "dsp_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) + }, + { + .clkdm_name = "gfx_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) + }, + { + .clkdm_name = "mpu_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) + }, + { + .clkdm_name = "wkup_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) + }, + { + .clkdm_name = "mdm_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) + }, + { NULL }, +}; + +#endif + + +/* 2430-specific possible wakeup dependencies */ + +#ifdef CONFIG_ARCH_OMAP2430 + +/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */ +static struct clkdm_dep mdm_2430_wkdeps[] = { + { + .clkdm_name = "core_l3_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) + }, + { + .clkdm_name = "core_l4_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) + }, + { + .clkdm_name = "mpu_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) + }, + { + .clkdm_name = "wkup_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) + }, + { NULL }, +}; + +#endif /* CONFIG_ARCH_OMAP2430 */ + + +/* OMAP3-specific possible dependencies */ + +#ifdef CONFIG_ARCH_OMAP3 + +/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */ +static struct clkdm_dep per_wkdeps[] = { + { + .clkdm_name = "core_l3_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "core_l4_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "iva2_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "mpu_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "wkup_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { NULL }, +}; + +/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */ +static struct clkdm_dep usbhost_wkdeps[] = { + { + .clkdm_name = "core_l3_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "core_l4_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "iva2_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "mpu_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "wkup_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { NULL }, +}; + +/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */ +static struct clkdm_dep mpu_3xxx_wkdeps[] = { + { + .clkdm_name = "core_l3_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "core_l4_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "iva2_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "dss_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "per_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { NULL }, +}; + +/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */ +static struct clkdm_dep iva2_wkdeps[] = { + { + .clkdm_name = "core_l3_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "core_l4_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "mpu_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "wkup_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "dss_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "per_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { NULL }, +}; + + +/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */ +static struct clkdm_dep cam_wkdeps[] = { + { + .clkdm_name = "iva2_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "mpu_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "wkup_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { NULL }, +}; + +/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */ +static struct clkdm_dep dss_wkdeps[] = { + { + .clkdm_name = "iva2_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "mpu_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "wkup_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { NULL }, +}; + +/* 3430: PM_WKDEP_NEON: MPU */ +static struct clkdm_dep neon_wkdeps[] = { + { + .clkdm_name = "mpu_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { NULL }, +}; + + +/* Sleep dependency source arrays for OMAP3-specific clkdms */ + +/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */ +static struct clkdm_dep dss_sleepdeps[] = { + { + .clkdm_name = "mpu_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "iva2_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { NULL }, +}; + +/* 3430: CM_SLEEPDEP_PER: MPU, IVA */ +static struct clkdm_dep per_sleepdeps[] = { + { + .clkdm_name = "mpu_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "iva2_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { NULL }, +}; + +/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */ +static struct clkdm_dep usbhost_sleepdeps[] = { + { + .clkdm_name = "mpu_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { + .clkdm_name = "iva2_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { NULL }, +}; + +/* 3430: CM_SLEEPDEP_CAM: MPU */ +static struct clkdm_dep cam_sleepdeps[] = { + { + .clkdm_name = "mpu_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { NULL }, +}; + +/* + * 3430ES1: CM_SLEEPDEP_GFX: MPU + * 3430ES2: CM_SLEEPDEP_SGX: MPU + * These can share data since they will never be present simultaneously + * on the same device. + */ +static struct clkdm_dep gfx_sgx_sleepdeps[] = { + { + .clkdm_name = "mpu_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + }, + { NULL }, +}; + +#endif /* CONFIG_ARCH_OMAP3 */ + /* * OMAP2/3-common clockdomains @@ -21,10 +425,13 @@ * sys_clkout/sys_clkout2. */ +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) + /* This is an implicit clockdomain - it is never defined as such in TRM */ static struct clockdomain wkup_clkdm = { .name = "wkup_clkdm", .pwrdm = { .name = "wkup_pwrdm" }, + .dep_bit = OMAP_EN_WKUP_SHIFT, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), }; @@ -40,6 +447,8 @@ static struct clockdomain cm_clkdm = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), }; +#endif + /* * 2420-only clockdomains */ @@ -50,6 +459,8 @@ static struct clockdomain mpu_2420_clkdm = { .name = "mpu_clkdm", .pwrdm = { .name = "mpu_pwrdm" }, .flags = CLKDM_CAN_HWSUP, + .clkstctrl_reg = OMAP2420_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL), + .wkdep_srcs = mpu_24xx_wkdeps, .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; @@ -58,11 +469,64 @@ static struct clockdomain iva1_2420_clkdm = { .name = "iva1_clkdm", .pwrdm = { .name = "dsp_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD, + OMAP2_CM_CLKSTCTRL), + .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT, + .wkdep_srcs = dsp_24xx_wkdeps, .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; -#endif /* CONFIG_ARCH_OMAP2420 */ +static struct clockdomain dsp_2420_clkdm = { + .name = "dsp_clkdm", + .pwrdm = { .name = "dsp_pwrdm" }, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD, + OMAP2_CM_CLKSTCTRL), + .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +static struct clockdomain gfx_2420_clkdm = { + .name = "gfx_clkdm", + .pwrdm = { .name = "gfx_pwrdm" }, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP2420_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL), + .wkdep_srcs = gfx_sgx_wkdeps, + .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +static struct clockdomain core_l3_2420_clkdm = { + .name = "core_l3_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .flags = CLKDM_CAN_HWSUP, + .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), + .wkdep_srcs = core_24xx_wkdeps, + .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +static struct clockdomain core_l4_2420_clkdm = { + .name = "core_l4_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .flags = CLKDM_CAN_HWSUP, + .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), + .wkdep_srcs = core_24xx_wkdeps, + .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +static struct clockdomain dss_2420_clkdm = { + .name = "dss_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .flags = CLKDM_CAN_HWSUP, + .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), + .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +#endif /* CONFIG_ARCH_OMAP2420 */ /* @@ -75,80 +539,105 @@ static struct clockdomain mpu_2430_clkdm = { .name = "mpu_clkdm", .pwrdm = { .name = "mpu_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP2430_CM_REGADDR(MPU_MOD, + OMAP2_CM_CLKSTCTRL), + .wkdep_srcs = mpu_24xx_wkdeps, .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; +/* Another case of bit name collisions between several registers: EN_MDM */ static struct clockdomain mdm_clkdm = { .name = "mdm_clkdm", .pwrdm = { .name = "mdm_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP2430_CM_REGADDR(OMAP2430_MDM_MOD, + OMAP2_CM_CLKSTCTRL), + .dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT, + .wkdep_srcs = mdm_2430_wkdeps, .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; -#endif /* CONFIG_ARCH_OMAP2430 */ - - -/* - * 24XX-only clockdomains - */ - -#if defined(CONFIG_ARCH_OMAP24XX) - -static struct clockdomain dsp_clkdm = { +static struct clockdomain dsp_2430_clkdm = { .name = "dsp_clkdm", .pwrdm = { .name = "dsp_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP2430_CM_REGADDR(OMAP24XX_DSP_MOD, + OMAP2_CM_CLKSTCTRL), + .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT, + .wkdep_srcs = dsp_24xx_wkdeps, .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; -static struct clockdomain gfx_24xx_clkdm = { +static struct clockdomain gfx_2430_clkdm = { .name = "gfx_clkdm", .pwrdm = { .name = "gfx_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP2430_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL), + .wkdep_srcs = gfx_sgx_wkdeps, .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; -static struct clockdomain core_l3_24xx_clkdm = { +/* + * XXX add usecounting for clkdm dependencies, otherwise the presence + * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm + * could cause trouble + */ +static struct clockdomain core_l3_2430_clkdm = { .name = "core_l3_clkdm", .pwrdm = { .name = "core_pwrdm" }, .flags = CLKDM_CAN_HWSUP, + .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), + .dep_bit = OMAP24XX_EN_CORE_SHIFT, + .wkdep_srcs = core_24xx_wkdeps, .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; -static struct clockdomain core_l4_24xx_clkdm = { +/* + * XXX add usecounting for clkdm dependencies, otherwise the presence + * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm + * could cause trouble + */ +static struct clockdomain core_l4_2430_clkdm = { .name = "core_l4_clkdm", .pwrdm = { .name = "core_pwrdm" }, .flags = CLKDM_CAN_HWSUP, + .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), + .dep_bit = OMAP24XX_EN_CORE_SHIFT, + .wkdep_srcs = core_24xx_wkdeps, .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; -static struct clockdomain dss_24xx_clkdm = { +static struct clockdomain dss_2430_clkdm = { .name = "dss_clkdm", .pwrdm = { .name = "core_pwrdm" }, .flags = CLKDM_CAN_HWSUP, + .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; -#endif /* CONFIG_ARCH_OMAP24XX */ +#endif /* CONFIG_ARCH_OMAP2430 */ /* - * 34xx clockdomains + * OMAP3 clockdomains */ -#if defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP3) -static struct clockdomain mpu_34xx_clkdm = { +static struct clockdomain mpu_3xxx_clkdm = { .name = "mpu_clkdm", .pwrdm = { .name = "mpu_pwrdm" }, .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL), + .dep_bit = OMAP3430_EN_MPU_SHIFT, + .wkdep_srcs = mpu_3xxx_wkdeps, .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; @@ -157,6 +646,9 @@ static struct clockdomain neon_clkdm = { .name = "neon_clkdm", .pwrdm = { .name = "neon_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_NEON_MOD, + OMAP2_CM_CLKSTCTRL), + .wkdep_srcs = neon_wkdeps, .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; @@ -165,6 +657,10 @@ static struct clockdomain iva2_clkdm = { .name = "iva2_clkdm", .pwrdm = { .name = "iva2_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, + OMAP2_CM_CLKSTCTRL), + .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT, + .wkdep_srcs = iva2_wkdeps, .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; @@ -173,6 +669,9 @@ static struct clockdomain gfx_3430es1_clkdm = { .name = "gfx_clkdm", .pwrdm = { .name = "gfx_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL), + .wkdep_srcs = gfx_sgx_wkdeps, + .sleepdep_srcs = gfx_sgx_sleepdeps, .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), }; @@ -181,6 +680,10 @@ static struct clockdomain sgx_clkdm = { .name = "sgx_clkdm", .pwrdm = { .name = "sgx_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, + OMAP2_CM_CLKSTCTRL), + .wkdep_srcs = gfx_sgx_wkdeps, + .sleepdep_srcs = gfx_sgx_sleepdeps, .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), }; @@ -196,30 +699,51 @@ static struct clockdomain d2d_clkdm = { .name = "d2d_clkdm", .pwrdm = { .name = "core_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; -static struct clockdomain core_l3_34xx_clkdm = { +/* + * XXX add usecounting for clkdm dependencies, otherwise the presence + * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm + * could cause trouble + */ +static struct clockdomain core_l3_3xxx_clkdm = { .name = "core_l3_clkdm", .pwrdm = { .name = "core_pwrdm" }, .flags = CLKDM_CAN_HWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), + .dep_bit = OMAP3430_EN_CORE_SHIFT, .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; -static struct clockdomain core_l4_34xx_clkdm = { +/* + * XXX add usecounting for clkdm dependencies, otherwise the presence + * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm + * could cause trouble + */ +static struct clockdomain core_l4_3xxx_clkdm = { .name = "core_l4_clkdm", .pwrdm = { .name = "core_pwrdm" }, .flags = CLKDM_CAN_HWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), + .dep_bit = OMAP3430_EN_CORE_SHIFT, .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; -static struct clockdomain dss_34xx_clkdm = { +/* Another case of bit name collisions between several registers: EN_DSS */ +static struct clockdomain dss_3xxx_clkdm = { .name = "dss_clkdm", .pwrdm = { .name = "dss_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, + OMAP2_CM_CLKSTCTRL), + .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT, + .wkdep_srcs = dss_wkdeps, + .sleepdep_srcs = dss_sleepdeps, .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; @@ -228,6 +752,10 @@ static struct clockdomain cam_clkdm = { .name = "cam_clkdm", .pwrdm = { .name = "cam_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, + OMAP2_CM_CLKSTCTRL), + .wkdep_srcs = cam_wkdeps, + .sleepdep_srcs = cam_sleepdeps, .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; @@ -236,6 +764,10 @@ static struct clockdomain usbhost_clkdm = { .name = "usbhost_clkdm", .pwrdm = { .name = "usbhost_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, + OMAP2_CM_CLKSTCTRL), + .wkdep_srcs = usbhost_wkdeps, + .sleepdep_srcs = usbhost_sleepdeps, .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), }; @@ -244,6 +776,11 @@ static struct clockdomain per_clkdm = { .name = "per_clkdm", .pwrdm = { .name = "per_pwrdm" }, .flags = CLKDM_CAN_HWSUP_SWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, + OMAP2_CM_CLKSTCTRL), + .dep_bit = OMAP3430_EN_PER_SHIFT, + .wkdep_srcs = per_wkdeps, + .sleepdep_srcs = per_sleepdeps, .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; @@ -256,6 +793,8 @@ static struct clockdomain emu_clkdm = { .name = "emu_clkdm", .pwrdm = { .name = "emu_pwrdm" }, .flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP, + .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, + OMAP2_CM_CLKSTCTRL), .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; @@ -290,64 +829,70 @@ static struct clockdomain dpll5_clkdm = { .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), }; -#endif /* CONFIG_ARCH_OMAP34XX */ +#endif /* CONFIG_ARCH_OMAP3 */ + +#include "clockdomains44xx.h" /* - * Clockdomain-powerdomain hwsup dependencies (34XX only) + * Clockdomain hwsup dependencies (OMAP3 only) */ -static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = { +static struct clkdm_autodep clkdm_autodeps[] = { { - .pwrdm = { .name = "mpu_pwrdm" }, + .clkdm = { .name = "mpu_clkdm" }, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }, { - .pwrdm = { .name = "iva2_pwrdm" }, + .clkdm = { .name = "iva2_clkdm" }, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }, { - .pwrdm = { .name = NULL }, + .clkdm = { .name = NULL }, } }; /* - * + * List of clockdomain pointers per platform */ static struct clockdomain *clockdomains_omap[] = { +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) &wkup_clkdm, &cm_clkdm, &prm_clkdm, +#endif #ifdef CONFIG_ARCH_OMAP2420 &mpu_2420_clkdm, &iva1_2420_clkdm, + &dsp_2420_clkdm, + &gfx_2420_clkdm, + &core_l3_2420_clkdm, + &core_l4_2420_clkdm, + &dss_2420_clkdm, #endif #ifdef CONFIG_ARCH_OMAP2430 &mpu_2430_clkdm, &mdm_clkdm, + &dsp_2430_clkdm, + &gfx_2430_clkdm, + &core_l3_2430_clkdm, + &core_l4_2430_clkdm, + &dss_2430_clkdm, #endif -#ifdef CONFIG_ARCH_OMAP24XX - &dsp_clkdm, - &gfx_24xx_clkdm, - &core_l3_24xx_clkdm, - &core_l4_24xx_clkdm, - &dss_24xx_clkdm, -#endif - -#ifdef CONFIG_ARCH_OMAP34XX - &mpu_34xx_clkdm, +#ifdef CONFIG_ARCH_OMAP3 + &mpu_3xxx_clkdm, &neon_clkdm, &iva2_clkdm, &gfx_3430es1_clkdm, &sgx_clkdm, &d2d_clkdm, - &core_l3_34xx_clkdm, - &core_l4_34xx_clkdm, - &dss_34xx_clkdm, + &core_l3_3xxx_clkdm, + &core_l4_3xxx_clkdm, + &dss_3xxx_clkdm, &cam_clkdm, &usbhost_clkdm, &per_clkdm, @@ -359,6 +904,33 @@ static struct clockdomain *clockdomains_omap[] = { &dpll5_clkdm, #endif +#ifdef CONFIG_ARCH_OMAP4 + &l4_cefuse_44xx_clkdm, + &l4_cfg_44xx_clkdm, + &tesla_44xx_clkdm, + &l3_gfx_44xx_clkdm, + &ivahd_44xx_clkdm, + &l4_secure_44xx_clkdm, + &l4_per_44xx_clkdm, + &abe_44xx_clkdm, + &l3_instr_44xx_clkdm, + &l3_init_44xx_clkdm, + &mpuss_44xx_clkdm, + &mpu0_44xx_clkdm, + &mpu1_44xx_clkdm, + &l3_emif_44xx_clkdm, + &l4_ao_44xx_clkdm, + &ducati_44xx_clkdm, + &l3_2_44xx_clkdm, + &l3_1_44xx_clkdm, + &l3_d2d_44xx_clkdm, + &iss_44xx_clkdm, + &l3_dss_44xx_clkdm, + &l4_wkup_44xx_clkdm, + &emu_sys_44xx_clkdm, + &l3_dma_44xx_clkdm, +#endif + NULL, }; diff --git a/arch/arm/mach-omap2/clockdomains44xx.h b/arch/arm/mach-omap2/clockdomains44xx.h new file mode 100644 index 000000000000..438aaee2e392 --- /dev/null +++ b/arch/arm/mach-omap2/clockdomains44xx.h @@ -0,0 +1,250 @@ +/* + * OMAP4 Clock domains framework + * + * Copyright (C) 2009 Texas Instruments, Inc. + * Copyright (C) 2009 Nokia Corporation + * + * Abhijit Pagare (abhijitpagare@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * To-Do List + * -> Populate the Sleep/Wakeup dependencies for the domains + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H +#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H + +#include <plat/clockdomain.h> + +#if defined(CONFIG_ARCH_OMAP4) + +static struct clockdomain l4_cefuse_44xx_clkdm = { + .name = "l4_cefuse_clkdm", + .pwrdm = { .name = "cefuse_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM_CEFUSE_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct clockdomain l4_cfg_44xx_clkdm = { + .name = "l4_cfg_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM_L4CFG_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .flags = CLKDM_CAN_HWSUP, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct clockdomain tesla_44xx_clkdm = { + .name = "tesla_clkdm", + .pwrdm = { .name = "tesla_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM_TESLA_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct clockdomain l3_gfx_44xx_clkdm = { + .name = "l3_gfx_clkdm", + .pwrdm = { .name = "gfx_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM_GFX_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct clockdomain ivahd_44xx_clkdm = { + .name = "ivahd_clkdm", + .pwrdm = { .name = "ivahd_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM_IVAHD_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct clockdomain l4_secure_44xx_clkdm = { + .name = "l4_secure_clkdm", + .pwrdm = { .name = "l4per_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM_L4SEC_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct clockdomain l4_per_44xx_clkdm = { + .name = "l4_per_clkdm", + .pwrdm = { .name = "l4per_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM_L4PER_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct clockdomain abe_44xx_clkdm = { + .name = "abe_clkdm", + .pwrdm = { .name = "abe_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM1_ABE_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct clockdomain l3_instr_44xx_clkdm = { + .name = "l3_instr_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM_L3INSTR_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct clockdomain l3_init_44xx_clkdm = { + .name = "l3_init_clkdm", + .pwrdm = { .name = "l3init_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM_L3INIT_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct clockdomain mpuss_44xx_clkdm = { + .name = "mpuss_clkdm", + .pwrdm = { .name = "mpu_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM_MPU_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct clockdomain mpu0_44xx_clkdm = { + .name = "mpu0_clkdm", + .pwrdm = { .name = "cpu0_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM_PDA_CPU0_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct clockdomain mpu1_44xx_clkdm = { + .name = "mpu1_clkdm", + .pwrdm = { .name = "cpu1_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM_PDA_CPU1_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct clockdomain l3_emif_44xx_clkdm = { + .name = "l3_emif_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM_MEMIF_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct clockdomain l4_ao_44xx_clkdm = { + .name = "l4_ao_clkdm", + .pwrdm = { .name = "always_on_core_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM_ALWON_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct clockdomain ducati_44xx_clkdm = { + .name = "ducati_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM_DUCATI_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct clockdomain l3_2_44xx_clkdm = { + .name = "l3_2_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM_L3_2_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .flags = CLKDM_CAN_HWSUP, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct clockdomain l3_1_44xx_clkdm = { + .name = "l3_1_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM_L3_1_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .flags = CLKDM_CAN_HWSUP, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct clockdomain l3_d2d_44xx_clkdm = { + .name = "l3_d2d_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM_D2D_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct clockdomain iss_44xx_clkdm = { + .name = "iss_clkdm", + .pwrdm = { .name = "cam_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM_CAM_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct clockdomain l3_dss_44xx_clkdm = { + .name = "l3_dss_clkdm", + .pwrdm = { .name = "dss_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM_DSS_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .flags = CLKDM_CAN_HWSUP_SWSUP, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct clockdomain l4_wkup_44xx_clkdm = { + .name = "l4_wkup_clkdm", + .pwrdm = { .name = "wkup_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM_WKUP_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .flags = CLKDM_CAN_HWSUP, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct clockdomain emu_sys_44xx_clkdm = { + .name = "emu_sys_clkdm", + .pwrdm = { .name = "emu_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM_EMU_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .flags = CLKDM_CAN_HWSUP, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct clockdomain l3_dma_44xx_clkdm = { + .name = "l3_dma_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .clkstctrl_reg = OMAP4430_CM_SDMA_CLKSTCTRL, + .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +#endif + +#endif diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h index 0e67f75aa35c..ac8458e43252 100644 --- a/arch/arm/mach-omap2/cm-regbits-44xx.h +++ b/arch/arm/mach-omap2/cm-regbits-44xx.h @@ -26,7 +26,7 @@ /* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ -#define OMAP4430_ABE_DYNDEP_SHIFT (1 << 3) +#define OMAP4430_ABE_DYNDEP_SHIFT 3 #define OMAP4430_ABE_DYNDEP_MASK BITFIELD(3, 3) /* @@ -34,15 +34,15 @@ * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, * CM_TESLA_STATICDEP */ -#define OMAP4430_ABE_STATDEP_SHIFT (1 << 3) +#define OMAP4430_ABE_STATDEP_SHIFT 3 #define OMAP4430_ABE_STATDEP_MASK BITFIELD(3, 3) /* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_ALWONCORE_DYNDEP_SHIFT (1 << 16) +#define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 #define OMAP4430_ALWONCORE_DYNDEP_MASK BITFIELD(16, 16) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ -#define OMAP4430_ALWONCORE_STATDEP_SHIFT (1 << 16) +#define OMAP4430_ALWONCORE_STATDEP_SHIFT 16 #define OMAP4430_ALWONCORE_STATDEP_MASK BITFIELD(16, 16) /* @@ -50,371 +50,371 @@ * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU */ -#define OMAP4430_AUTO_DPLL_MODE_SHIFT (1 << 0) +#define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 #define OMAP4430_AUTO_DPLL_MODE_MASK BITFIELD(0, 2) /* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_CEFUSE_DYNDEP_SHIFT (1 << 17) +#define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 #define OMAP4430_CEFUSE_DYNDEP_MASK BITFIELD(17, 17) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ -#define OMAP4430_CEFUSE_STATDEP_SHIFT (1 << 17) +#define OMAP4430_CEFUSE_STATDEP_SHIFT 17 #define OMAP4430_CEFUSE_STATDEP_MASK BITFIELD(17, 17) /* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT (1 << 13) +#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK BITFIELD(13, 13) /* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT (1 << 12) +#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12 #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK BITFIELD(12, 12) /* Used by CM_WKUP_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT (1 << 9) +#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK BITFIELD(9, 9) /* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT (1 << 11) +#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11 #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK BITFIELD(11, 11) /* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT (1 << 8) +#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK BITFIELD(8, 8) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT (1 << 11) +#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK BITFIELD(11, 11) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT (1 << 12) +#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK BITFIELD(12, 12) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT (1 << 13) +#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK BITFIELD(13, 13) /* Used by CM_CAM_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT (1 << 9) +#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9 #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK BITFIELD(9, 9) /* Used by CM_EMU_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT (1 << 9) +#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK BITFIELD(9, 9) /* Used by CM_CEFUSE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT (1 << 9) +#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK BITFIELD(9, 9) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT (1 << 9) +#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK BITFIELD(9, 9) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT (1 << 9) +#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK BITFIELD(9, 9) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT (1 << 10) +#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK BITFIELD(10, 10) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT (1 << 11) +#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK BITFIELD(11, 11) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT (1 << 12) +#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK BITFIELD(12, 12) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT (1 << 13) +#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK BITFIELD(13, 13) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT (1 << 14) +#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK BITFIELD(14, 14) /* Used by CM_DSS_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT (1 << 10) +#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10 #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK BITFIELD(10, 10) /* Used by CM_DSS_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT (1 << 9) +#define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9 #define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK BITFIELD(9, 9) /* Used by CM_DUCATI_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT (1 << 8) +#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK BITFIELD(8, 8) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_SHIFT (1 << 10) +#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_SHIFT 10 #define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_MASK BITFIELD(10, 10) /* Used by CM_EMU_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT (1 << 8) +#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK BITFIELD(8, 8) /* Used by CM_CAM_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT (1 << 10) +#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK BITFIELD(10, 10) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT (1 << 15) +#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK BITFIELD(15, 15) /* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT (1 << 10) +#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK BITFIELD(10, 10) /* Used by CM_DSS_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT (1 << 11) +#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK BITFIELD(11, 11) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT (1 << 20) +#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK BITFIELD(20, 20) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT (1 << 26) +#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK BITFIELD(26, 26) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT (1 << 21) +#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK BITFIELD(21, 21) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT (1 << 27) +#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK BITFIELD(27, 27) /* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_SHIFT (1 << 31) +#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_SHIFT 31 #define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_MASK BITFIELD(31, 31) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT (1 << 13) +#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK BITFIELD(13, 13) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT (1 << 12) +#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK BITFIELD(12, 12) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT (1 << 28) +#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK BITFIELD(28, 28) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT (1 << 29) +#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK BITFIELD(29, 29) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT (1 << 11) +#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK BITFIELD(11, 11) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT (1 << 16) +#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK BITFIELD(16, 16) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT (1 << 17) +#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK BITFIELD(17, 17) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT (1 << 18) +#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK BITFIELD(18, 18) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT (1 << 19) +#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK BITFIELD(19, 19) /* Used by CM_CAM_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT (1 << 8) +#define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK BITFIELD(8, 8) /* Used by CM_IVAHD_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT (1 << 8) +#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK BITFIELD(8, 8) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_SHIFT (1 << 14) +#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_SHIFT 14 #define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_MASK BITFIELD(14, 14) /* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK BITFIELD(8, 8) /* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK BITFIELD(8, 8) /* Used by CM_D2D_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK BITFIELD(8, 8) /* Used by CM_SDMA_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK BITFIELD(8, 8) /* Used by CM_DSS_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK BITFIELD(8, 8) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK BITFIELD(8, 8) /* Used by CM_GFX_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK BITFIELD(8, 8) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK BITFIELD(8, 8) /* Used by CM_L3INSTR_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK BITFIELD(8, 8) /* Used by CM_L4SEC_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT (1 << 8) +#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK BITFIELD(8, 8) /* Used by CM_ALWON_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT (1 << 8) +#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK BITFIELD(8, 8) /* Used by CM_CEFUSE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT (1 << 8) +#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK BITFIELD(8, 8) /* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT (1 << 8) +#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK BITFIELD(8, 8) /* Used by CM_D2D_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT (1 << 9) +#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK BITFIELD(9, 9) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT (1 << 9) +#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK BITFIELD(9, 9) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT (1 << 8) +#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK BITFIELD(8, 8) /* Used by CM_L4SEC_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT (1 << 9) +#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9 #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK BITFIELD(9, 9) /* Used by CM_WKUP_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT (1 << 12) +#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK BITFIELD(12, 12) /* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT (1 << 8) +#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK BITFIELD(8, 8) /* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT (1 << 9) +#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK BITFIELD(9, 9) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT (1 << 16) +#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK BITFIELD(16, 16) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT (1 << 17) +#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK BITFIELD(17, 17) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT (1 << 18) +#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK BITFIELD(18, 18) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT (1 << 19) +#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK BITFIELD(19, 19) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT (1 << 25) +#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK BITFIELD(25, 25) /* Used by CM_EMU_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_SHIFT (1 << 10) +#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_SHIFT 10 #define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_MASK BITFIELD(10, 10) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT (1 << 20) +#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK BITFIELD(20, 20) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT (1 << 21) +#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21 #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK BITFIELD(21, 21) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT (1 << 22) +#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK BITFIELD(22, 22) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT (1 << 24) +#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK BITFIELD(24, 24) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT (1 << 10) +#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK BITFIELD(10, 10) /* Used by CM_GFX_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT (1 << 9) +#define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9 #define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK BITFIELD(9, 9) /* Used by CM_ALWON_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT (1 << 11) +#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11 #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK BITFIELD(11, 11) /* Used by CM_ALWON_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT (1 << 10) +#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10 #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK BITFIELD(10, 10) /* Used by CM_ALWON_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT (1 << 9) +#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9 #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK BITFIELD(9, 9) /* Used by CM_WKUP_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT (1 << 8) +#define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_SYS_CLK_MASK BITFIELD(8, 8) /* Used by CM_TESLA_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT (1 << 8) +#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK BITFIELD(8, 8) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT (1 << 22) +#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK BITFIELD(22, 22) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT (1 << 23) +#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK BITFIELD(23, 23) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT (1 << 24) +#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK BITFIELD(24, 24) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT (1 << 15) +#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK BITFIELD(15, 15) /* Used by CM_WKUP_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT (1 << 10) +#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK BITFIELD(10, 10) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT (1 << 30) +#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK BITFIELD(30, 30) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT (1 << 25) +#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK BITFIELD(25, 25) /* Used by CM_WKUP_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT (1 << 11) +#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK BITFIELD(11, 11) /* @@ -426,7 +426,7 @@ * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, * CM1_ABE_TIMER8_CLKCTRL */ -#define OMAP4430_CLKSEL_SHIFT (1 << 24) +#define OMAP4430_CLKSEL_SHIFT 24 #define OMAP4430_CLKSEL_MASK BITFIELD(24, 24) /* @@ -434,43 +434,43 @@ * CM_DPLL_SYS_REF_CLKSEL, CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, * CM_CLKSEL_USB_60MHZ */ -#define OMAP4430_CLKSEL_0_0_SHIFT (1 << 0) +#define OMAP4430_CLKSEL_0_0_SHIFT 0 #define OMAP4430_CLKSEL_0_0_MASK BITFIELD(0, 0) /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ -#define OMAP4430_CLKSEL_0_1_SHIFT (1 << 0) +#define OMAP4430_CLKSEL_0_1_SHIFT 0 #define OMAP4430_CLKSEL_0_1_MASK BITFIELD(0, 1) /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */ -#define OMAP4430_CLKSEL_24_25_SHIFT (1 << 24) +#define OMAP4430_CLKSEL_24_25_SHIFT 24 #define OMAP4430_CLKSEL_24_25_MASK BITFIELD(24, 25) /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ -#define OMAP4430_CLKSEL_60M_SHIFT (1 << 24) +#define OMAP4430_CLKSEL_60M_SHIFT 24 #define OMAP4430_CLKSEL_60M_MASK BITFIELD(24, 24) /* Used by CM1_ABE_AESS_CLKCTRL */ -#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT (1 << 24) +#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 #define OMAP4430_CLKSEL_AESS_FCLK_MASK BITFIELD(24, 24) /* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ -#define OMAP4430_CLKSEL_CORE_SHIFT (1 << 0) +#define OMAP4430_CLKSEL_CORE_SHIFT 0 #define OMAP4430_CLKSEL_CORE_MASK BITFIELD(0, 0) /* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */ -#define OMAP4430_CLKSEL_CORE_1_1_SHIFT (1 << 1) +#define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 #define OMAP4430_CLKSEL_CORE_1_1_MASK BITFIELD(1, 1) /* Used by CM_WKUP_USIM_CLKCTRL */ -#define OMAP4430_CLKSEL_DIV_SHIFT (1 << 24) +#define OMAP4430_CLKSEL_DIV_SHIFT 24 #define OMAP4430_CLKSEL_DIV_MASK BITFIELD(24, 24) /* Used by CM_CAM_FDIF_CLKCTRL */ -#define OMAP4430_CLKSEL_FCLK_SHIFT (1 << 24) +#define OMAP4430_CLKSEL_FCLK_SHIFT 24 #define OMAP4430_CLKSEL_FCLK_MASK BITFIELD(24, 25) /* Used by CM_L4PER_MCBSP4_CLKCTRL */ -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT (1 << 25) +#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK BITFIELD(25, 25) /* @@ -478,58 +478,58 @@ * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, * CM1_ABE_MCBSP3_CLKCTRL */ -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT (1 << 26) +#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK BITFIELD(26, 27) /* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ -#define OMAP4430_CLKSEL_L3_SHIFT (1 << 4) +#define OMAP4430_CLKSEL_L3_SHIFT 4 #define OMAP4430_CLKSEL_L3_MASK BITFIELD(4, 4) /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ -#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT (1 << 2) +#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 #define OMAP4430_CLKSEL_L3_SHADOW_MASK BITFIELD(2, 2) /* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ -#define OMAP4430_CLKSEL_L4_SHIFT (1 << 8) +#define OMAP4430_CLKSEL_L4_SHIFT 8 #define OMAP4430_CLKSEL_L4_MASK BITFIELD(8, 8) /* Used by CM_CLKSEL_ABE */ -#define OMAP4430_CLKSEL_OPP_SHIFT (1 << 0) +#define OMAP4430_CLKSEL_OPP_SHIFT 0 #define OMAP4430_CLKSEL_OPP_MASK BITFIELD(0, 1) /* Used by CM_GFX_GFX_CLKCTRL */ -#define OMAP4430_CLKSEL_PER_192M_SHIFT (1 << 25) +#define OMAP4430_CLKSEL_PER_192M_SHIFT 25 #define OMAP4430_CLKSEL_PER_192M_MASK BITFIELD(25, 26) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ -#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT (1 << 27) +#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 #define OMAP4430_CLKSEL_PMD_STM_CLK_MASK BITFIELD(27, 29) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ -#define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT (1 << 24) +#define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK BITFIELD(24, 26) /* Used by CM_GFX_GFX_CLKCTRL */ -#define OMAP4430_CLKSEL_SGX_FCLK_SHIFT (1 << 24) +#define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24 #define OMAP4430_CLKSEL_SGX_FCLK_MASK BITFIELD(24, 24) /* * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL */ -#define OMAP4430_CLKSEL_SOURCE_SHIFT (1 << 24) +#define OMAP4430_CLKSEL_SOURCE_SHIFT 24 #define OMAP4430_CLKSEL_SOURCE_MASK BITFIELD(24, 25) /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */ -#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT (1 << 24) +#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 #define OMAP4430_CLKSEL_SOURCE_24_24_MASK BITFIELD(24, 24) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ -#define OMAP4430_CLKSEL_UTMI_P1_SHIFT (1 << 24) +#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 #define OMAP4430_CLKSEL_UTMI_P1_MASK BITFIELD(24, 24) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ -#define OMAP4430_CLKSEL_UTMI_P2_SHIFT (1 << 25) +#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 #define OMAP4430_CLKSEL_UTMI_P2_MASK BITFIELD(25, 25) /* @@ -544,23 +544,23 @@ * CM_IVAHD_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_TESLA_CLKSTCTRL, * CM1_ABE_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKTRCTRL_SHIFT (1 << 0) +#define OMAP4430_CLKTRCTRL_SHIFT 0 #define OMAP4430_CLKTRCTRL_MASK BITFIELD(0, 1) /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ -#define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT (1 << 0) +#define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0 #define OMAP4430_CORE_DPLL_EMU_DIV_MASK BITFIELD(0, 6) /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ -#define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT (1 << 8) +#define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8 #define OMAP4430_CORE_DPLL_EMU_MULT_MASK BITFIELD(8, 18) /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_D2D_DYNDEP_SHIFT (1 << 18) +#define OMAP4430_D2D_DYNDEP_SHIFT 18 #define OMAP4430_D2D_DYNDEP_MASK BITFIELD(18, 18) /* Used by CM_MPU_STATICDEP */ -#define OMAP4430_D2D_STATDEP_SHIFT (1 << 18) +#define OMAP4430_D2D_STATDEP_SHIFT 18 #define OMAP4430_D2D_STATDEP_MASK BITFIELD(18, 18) /* @@ -570,19 +570,19 @@ * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA, * CM_SSC_DELTAMSTEP_DPLL_MPU */ -#define OMAP4430_DELTAMSTEP_SHIFT (1 << 0) +#define OMAP4430_DELTAMSTEP_SHIFT 0 #define OMAP4430_DELTAMSTEP_MASK BITFIELD(0, 19) /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_DLL_OVERRIDE_SHIFT (1 << 2) +#define OMAP4430_DLL_OVERRIDE_SHIFT 2 #define OMAP4430_DLL_OVERRIDE_MASK BITFIELD(2, 2) /* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */ -#define OMAP4430_DLL_OVERRIDE_0_0_SHIFT (1 << 0) +#define OMAP4430_DLL_OVERRIDE_0_0_SHIFT 0 #define OMAP4430_DLL_OVERRIDE_0_0_MASK BITFIELD(0, 0) /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_DLL_RESET_SHIFT (1 << 3) +#define OMAP4430_DLL_RESET_SHIFT 3 #define OMAP4430_DLL_RESET_MASK BITFIELD(3, 3) /* @@ -590,40 +590,40 @@ * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU */ -#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT (1 << 23) +#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 #define OMAP4430_DPLL_BYP_CLKSEL_MASK BITFIELD(23, 23) /* Used by CM_CLKDCOLDO_DPLL_USB */ -#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT (1 << 8) +#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK BITFIELD(8, 8) /* Used by CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_CORE */ -#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT (1 << 20) +#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK BITFIELD(20, 20) /* * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, * CM_DIV_M3_DPLL_CORE */ -#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT (1 << 0) +#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK BITFIELD(0, 4) /* * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, * CM_DIV_M3_DPLL_CORE */ -#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT (1 << 5) +#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK BITFIELD(5, 5) /* * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, * CM_DIV_M3_DPLL_CORE */ -#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT (1 << 8) +#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK BITFIELD(8, 8) /* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */ -#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT (1 << 10) +#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK BITFIELD(10, 10) /* @@ -631,11 +631,11 @@ * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU */ -#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT (1 << 0) +#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 #define OMAP4430_DPLL_CLKOUT_DIV_MASK BITFIELD(0, 4) /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */ -#define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT (1 << 0) +#define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK BITFIELD(0, 6) /* @@ -643,11 +643,11 @@ * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU */ -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT (1 << 5) +#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK BITFIELD(5, 5) /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */ -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT (1 << 7) +#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK BITFIELD(7, 7) /* @@ -655,23 +655,23 @@ * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, * CM_DIV_M2_DPLL_MPU */ -#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT (1 << 8) +#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK BITFIELD(8, 8) /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT (1 << 8) +#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 #define OMAP4430_DPLL_CORE_DPLL_EN_MASK BITFIELD(8, 10) /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT (1 << 11) +#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 #define OMAP4430_DPLL_CORE_M2_DIV_MASK BITFIELD(11, 15) /* Used by CM_SHADOW_FREQ_CONFIG2 */ -#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT (1 << 3) +#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 #define OMAP4430_DPLL_CORE_M5_DIV_MASK BITFIELD(3, 7) /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_SHIFT (1 << 1) +#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_SHIFT 1 #define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_MASK BITFIELD(1, 1) /* @@ -679,11 +679,11 @@ * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU */ -#define OMAP4430_DPLL_DIV_SHIFT (1 << 0) +#define OMAP4430_DPLL_DIV_SHIFT 0 #define OMAP4430_DPLL_DIV_MASK BITFIELD(0, 6) /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */ -#define OMAP4430_DPLL_DIV_0_7_SHIFT (1 << 0) +#define OMAP4430_DPLL_DIV_0_7_SHIFT 0 #define OMAP4430_DPLL_DIV_0_7_MASK BITFIELD(0, 7) /* @@ -691,11 +691,11 @@ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU */ -#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT (1 << 8) +#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK BITFIELD(8, 8) /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */ -#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT (1 << 3) +#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK BITFIELD(3, 3) /* @@ -703,7 +703,7 @@ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU */ -#define OMAP4430_DPLL_EN_SHIFT (1 << 0) +#define OMAP4430_DPLL_EN_SHIFT 0 #define OMAP4430_DPLL_EN_MASK BITFIELD(0, 2) /* @@ -711,7 +711,7 @@ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU */ -#define OMAP4430_DPLL_LPMODE_EN_SHIFT (1 << 10) +#define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 #define OMAP4430_DPLL_LPMODE_EN_MASK BITFIELD(10, 10) /* @@ -719,11 +719,11 @@ * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU */ -#define OMAP4430_DPLL_MULT_SHIFT (1 << 8) +#define OMAP4430_DPLL_MULT_SHIFT 8 #define OMAP4430_DPLL_MULT_MASK BITFIELD(8, 18) /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */ -#define OMAP4430_DPLL_MULT_USB_SHIFT (1 << 8) +#define OMAP4430_DPLL_MULT_USB_SHIFT 8 #define OMAP4430_DPLL_MULT_USB_MASK BITFIELD(8, 19) /* @@ -731,11 +731,11 @@ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU */ -#define OMAP4430_DPLL_REGM4XEN_SHIFT (1 << 11) +#define OMAP4430_DPLL_REGM4XEN_SHIFT 11 #define OMAP4430_DPLL_REGM4XEN_MASK BITFIELD(11, 11) /* Used by CM_CLKSEL_DPLL_USB */ -#define OMAP4430_DPLL_SD_DIV_SHIFT (1 << 24) +#define OMAP4430_DPLL_SD_DIV_SHIFT 24 #define OMAP4430_DPLL_SD_DIV_MASK BITFIELD(24, 31) /* @@ -743,7 +743,7 @@ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU */ -#define OMAP4430_DPLL_SSC_ACK_SHIFT (1 << 13) +#define OMAP4430_DPLL_SSC_ACK_SHIFT 13 #define OMAP4430_DPLL_SSC_ACK_MASK BITFIELD(13, 13) /* @@ -751,7 +751,7 @@ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU */ -#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT (1 << 14) +#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK BITFIELD(14, 14) /* @@ -759,154 +759,154 @@ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU */ -#define OMAP4430_DPLL_SSC_EN_SHIFT (1 << 12) +#define OMAP4430_DPLL_SSC_EN_SHIFT 12 #define OMAP4430_DPLL_SSC_EN_MASK BITFIELD(12, 12) /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ -#define OMAP4430_DSS_DYNDEP_SHIFT (1 << 8) +#define OMAP4430_DSS_DYNDEP_SHIFT 8 #define OMAP4430_DSS_DYNDEP_MASK BITFIELD(8, 8) /* * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, * CM_MPU_STATICDEP */ -#define OMAP4430_DSS_STATDEP_SHIFT (1 << 8) +#define OMAP4430_DSS_STATDEP_SHIFT 8 #define OMAP4430_DSS_STATDEP_MASK BITFIELD(8, 8) /* Used by CM_L3_2_DYNAMICDEP */ -#define OMAP4430_DUCATI_DYNDEP_SHIFT (1 << 0) +#define OMAP4430_DUCATI_DYNDEP_SHIFT 0 #define OMAP4430_DUCATI_DYNDEP_MASK BITFIELD(0, 0) /* Used by CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP */ -#define OMAP4430_DUCATI_STATDEP_SHIFT (1 << 0) +#define OMAP4430_DUCATI_STATDEP_SHIFT 0 #define OMAP4430_DUCATI_STATDEP_MASK BITFIELD(0, 0) /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_FREQ_UPDATE_SHIFT (1 << 0) +#define OMAP4430_FREQ_UPDATE_SHIFT 0 #define OMAP4430_FREQ_UPDATE_MASK BITFIELD(0, 0) /* Used by CM_L3_2_DYNAMICDEP */ -#define OMAP4430_GFX_DYNDEP_SHIFT (1 << 10) +#define OMAP4430_GFX_DYNDEP_SHIFT 10 #define OMAP4430_GFX_DYNDEP_MASK BITFIELD(10, 10) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ -#define OMAP4430_GFX_STATDEP_SHIFT (1 << 10) +#define OMAP4430_GFX_STATDEP_SHIFT 10 #define OMAP4430_GFX_STATDEP_MASK BITFIELD(10, 10) /* Used by CM_SHADOW_FREQ_CONFIG2 */ -#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT (1 << 0) +#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 #define OMAP4430_GPMC_FREQ_UPDATE_MASK BITFIELD(0, 0) /* * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA */ -#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT (1 << 0) +#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK BITFIELD(0, 4) /* * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA */ -#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT (1 << 5) +#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK BITFIELD(5, 5) /* * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA */ -#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT (1 << 8) +#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK BITFIELD(8, 8) /* * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA */ -#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT (1 << 12) +#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK BITFIELD(12, 12) /* * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA */ -#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT (1 << 0) +#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK BITFIELD(0, 4) /* * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA */ -#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT (1 << 5) +#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK BITFIELD(5, 5) /* * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA */ -#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT (1 << 8) +#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK BITFIELD(8, 8) /* * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA */ -#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT (1 << 12) +#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK BITFIELD(12, 12) /* * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY */ -#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT (1 << 0) +#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK BITFIELD(0, 4) /* * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY */ -#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT (1 << 5) +#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK BITFIELD(5, 5) /* * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY */ -#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT (1 << 8) +#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK BITFIELD(8, 8) /* * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY */ -#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT (1 << 12) +#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK BITFIELD(12, 12) /* * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, * CM_DIV_M7_DPLL_CORE */ -#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT (1 << 0) +#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK BITFIELD(0, 4) /* * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, * CM_DIV_M7_DPLL_CORE */ -#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT (1 << 5) +#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK BITFIELD(5, 5) /* * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, * CM_DIV_M7_DPLL_CORE */ -#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT (1 << 8) +#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK BITFIELD(8, 8) /* * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, * CM_DIV_M7_DPLL_CORE */ -#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT (1 << 12) +#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK BITFIELD(12, 12) /* @@ -962,22 +962,22 @@ * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL */ -#define OMAP4430_IDLEST_SHIFT (1 << 16) +#define OMAP4430_IDLEST_SHIFT 16 #define OMAP4430_IDLEST_MASK BITFIELD(16, 17) /* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_ISS_DYNDEP_SHIFT (1 << 9) +#define OMAP4430_ISS_DYNDEP_SHIFT 9 #define OMAP4430_ISS_DYNDEP_MASK BITFIELD(9, 9) /* * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, * CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ -#define OMAP4430_ISS_STATDEP_SHIFT (1 << 9) +#define OMAP4430_ISS_STATDEP_SHIFT 9 #define OMAP4430_ISS_STATDEP_MASK BITFIELD(9, 9) /* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ -#define OMAP4430_IVAHD_DYNDEP_SHIFT (1 << 2) +#define OMAP4430_IVAHD_DYNDEP_SHIFT 2 #define OMAP4430_IVAHD_DYNDEP_MASK BITFIELD(2, 2) /* @@ -986,25 +986,25 @@ * CM_SDMA_STATICDEP_RESTORE, CM_DSS_STATICDEP, CM_MPU_STATICDEP, * CM_TESLA_STATICDEP */ -#define OMAP4430_IVAHD_STATDEP_SHIFT (1 << 2) +#define OMAP4430_IVAHD_STATDEP_SHIFT 2 #define OMAP4430_IVAHD_STATDEP_MASK BITFIELD(2, 2) /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ -#define OMAP4430_L3INIT_DYNDEP_SHIFT (1 << 7) +#define OMAP4430_L3INIT_DYNDEP_SHIFT 7 #define OMAP4430_L3INIT_DYNDEP_MASK BITFIELD(7, 7) /* * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ -#define OMAP4430_L3INIT_STATDEP_SHIFT (1 << 7) +#define OMAP4430_L3INIT_STATDEP_SHIFT 7 #define OMAP4430_L3INIT_STATDEP_MASK BITFIELD(7, 7) /* * Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, * CM_DSS_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ -#define OMAP4430_L3_1_DYNDEP_SHIFT (1 << 5) +#define OMAP4430_L3_1_DYNDEP_SHIFT 5 #define OMAP4430_L3_1_DYNDEP_MASK BITFIELD(5, 5) /* @@ -1013,7 +1013,7 @@ * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, * CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ -#define OMAP4430_L3_1_STATDEP_SHIFT (1 << 5) +#define OMAP4430_L3_1_STATDEP_SHIFT 5 #define OMAP4430_L3_1_STATDEP_MASK BITFIELD(5, 5) /* @@ -1022,7 +1022,7 @@ * CM_GFX_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, * CM_CAM_DYNAMICDEP, CM_IVAHD_DYNAMICDEP */ -#define OMAP4430_L3_2_DYNDEP_SHIFT (1 << 6) +#define OMAP4430_L3_2_DYNDEP_SHIFT 6 #define OMAP4430_L3_2_DYNDEP_MASK BITFIELD(6, 6) /* @@ -1031,11 +1031,11 @@ * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, * CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ -#define OMAP4430_L3_2_STATDEP_SHIFT (1 << 6) +#define OMAP4430_L3_2_STATDEP_SHIFT 6 #define OMAP4430_L3_2_STATDEP_MASK BITFIELD(6, 6) /* Used by CM_L3_1_DYNAMICDEP */ -#define OMAP4430_L4CFG_DYNDEP_SHIFT (1 << 12) +#define OMAP4430_L4CFG_DYNDEP_SHIFT 12 #define OMAP4430_L4CFG_DYNDEP_MASK BITFIELD(12, 12) /* @@ -1043,11 +1043,11 @@ * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, * CM_TESLA_STATICDEP */ -#define OMAP4430_L4CFG_STATDEP_SHIFT (1 << 12) +#define OMAP4430_L4CFG_STATDEP_SHIFT 12 #define OMAP4430_L4CFG_STATDEP_MASK BITFIELD(12, 12) /* Used by CM_L3_2_DYNAMICDEP */ -#define OMAP4430_L4PER_DYNDEP_SHIFT (1 << 13) +#define OMAP4430_L4PER_DYNDEP_SHIFT 13 #define OMAP4430_L4PER_DYNDEP_MASK BITFIELD(13, 13) /* @@ -1055,36 +1055,36 @@ * CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, * CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ -#define OMAP4430_L4PER_STATDEP_SHIFT (1 << 13) +#define OMAP4430_L4PER_STATDEP_SHIFT 13 #define OMAP4430_L4PER_STATDEP_MASK BITFIELD(13, 13) /* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ -#define OMAP4430_L4SEC_DYNDEP_SHIFT (1 << 14) +#define OMAP4430_L4SEC_DYNDEP_SHIFT 14 #define OMAP4430_L4SEC_DYNDEP_MASK BITFIELD(14, 14) /* * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP, * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP */ -#define OMAP4430_L4SEC_STATDEP_SHIFT (1 << 14) +#define OMAP4430_L4SEC_STATDEP_SHIFT 14 #define OMAP4430_L4SEC_STATDEP_MASK BITFIELD(14, 14) /* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_L4WKUP_DYNDEP_SHIFT (1 << 15) +#define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 #define OMAP4430_L4WKUP_DYNDEP_MASK BITFIELD(15, 15) /* * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP, * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ -#define OMAP4430_L4WKUP_STATDEP_SHIFT (1 << 15) +#define OMAP4430_L4WKUP_STATDEP_SHIFT 15 #define OMAP4430_L4WKUP_STATDEP_MASK BITFIELD(15, 15) /* * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, * CM_MPU_DYNAMICDEP */ -#define OMAP4430_MEMIF_DYNDEP_SHIFT (1 << 4) +#define OMAP4430_MEMIF_DYNDEP_SHIFT 4 #define OMAP4430_MEMIF_DYNDEP_MASK BITFIELD(4, 4) /* @@ -1093,7 +1093,7 @@ * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, * CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ -#define OMAP4430_MEMIF_STATDEP_SHIFT (1 << 4) +#define OMAP4430_MEMIF_STATDEP_SHIFT 4 #define OMAP4430_MEMIF_STATDEP_MASK BITFIELD(4, 4) /* @@ -1103,7 +1103,7 @@ * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, * CM_SSC_MODFREQDIV_DPLL_MPU */ -#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT (1 << 8) +#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 #define OMAP4430_MODFREQDIV_EXPONENT_MASK BITFIELD(8, 10) /* @@ -1113,7 +1113,7 @@ * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, * CM_SSC_MODFREQDIV_DPLL_MPU */ -#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT (1 << 0) +#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 #define OMAP4430_MODFREQDIV_MANTISSA_MASK BITFIELD(0, 6) /* @@ -1169,23 +1169,23 @@ * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL */ -#define OMAP4430_MODULEMODE_SHIFT (1 << 0) +#define OMAP4430_MODULEMODE_SHIFT 0 #define OMAP4430_MODULEMODE_MASK BITFIELD(0, 1) /* Used by CM_DSS_DSS_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT (1 << 9) +#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK BITFIELD(9, 9) /* Used by CM_WKUP_BANDGAP_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT (1 << 8) +#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 #define OMAP4430_OPTFCLKEN_BGAP_32K_MASK BITFIELD(8, 8) /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT (1 << 9) +#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 9 #define OMAP4430_OPTFCLKEN_CLK32K_MASK BITFIELD(9, 9) /* Used by CM_CAM_ISS_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT (1 << 8) +#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK BITFIELD(8, 8) /* @@ -1195,119 +1195,119 @@ * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE */ -#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT (1 << 8) +#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 #define OMAP4430_OPTFCLKEN_DBCLK_MASK BITFIELD(8, 8) /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT (1 << 8) +#define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8 #define OMAP4430_OPTFCLKEN_DLL_CLK_MASK BITFIELD(8, 8) /* Used by CM_DSS_DSS_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT (1 << 8) +#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 #define OMAP4430_OPTFCLKEN_DSSCLK_MASK BITFIELD(8, 8) /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT (1 << 8) +#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 #define OMAP4430_OPTFCLKEN_FCLK0_MASK BITFIELD(8, 8) /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT (1 << 9) +#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 #define OMAP4430_OPTFCLKEN_FCLK1_MASK BITFIELD(9, 9) /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT (1 << 10) +#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 #define OMAP4430_OPTFCLKEN_FCLK2_MASK BITFIELD(10, 10) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ -#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT (1 << 15) +#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK BITFIELD(15, 15) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ -#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT (1 << 13) +#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK BITFIELD(13, 13) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ -#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT (1 << 14) +#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK BITFIELD(14, 14) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ -#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT (1 << 11) +#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK BITFIELD(11, 11) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ -#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT (1 << 12) +#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK BITFIELD(12, 12) /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT (1 << 8) +#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK BITFIELD(8, 8) /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT (1 << 9) +#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK BITFIELD(9, 9) /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT (1 << 8) +#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 #define OMAP4430_OPTFCLKEN_PHY_48M_MASK BITFIELD(8, 8) /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT (1 << 10) +#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK BITFIELD(10, 10) /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT (1 << 11) +#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK BITFIELD(11, 11) /* Used by CM_DSS_DSS_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT (1 << 10) +#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK BITFIELD(10, 10) /* Used by CM_DSS_DSS_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT (1 << 11) +#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 #define OMAP4430_OPTFCLKEN_TV_CLK_MASK BITFIELD(11, 11) /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT (1 << 8) +#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK BITFIELD(8, 8) /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ -#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT (1 << 8) +#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK BITFIELD(8, 8) /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ -#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT (1 << 9) +#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK BITFIELD(9, 9) /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ -#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT (1 << 10) +#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK BITFIELD(10, 10) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ -#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT (1 << 8) +#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK BITFIELD(8, 8) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ -#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT (1 << 9) +#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK BITFIELD(9, 9) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ -#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT (1 << 10) +#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK BITFIELD(10, 10) /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_XCLK_SHIFT (1 << 8) +#define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 #define OMAP4430_OPTFCLKEN_XCLK_MASK BITFIELD(8, 8) /* Used by CM_EMU_OVERRIDE_DPLL_PER, CM_EMU_OVERRIDE_DPLL_CORE */ -#define OMAP4430_OVERRIDE_ENABLE_SHIFT (1 << 19) +#define OMAP4430_OVERRIDE_ENABLE_SHIFT 19 #define OMAP4430_OVERRIDE_ENABLE_MASK BITFIELD(19, 19) /* Used by CM_CLKSEL_ABE */ -#define OMAP4430_PAD_CLKS_GATE_SHIFT (1 << 8) +#define OMAP4430_PAD_CLKS_GATE_SHIFT 8 #define OMAP4430_PAD_CLKS_GATE_MASK BITFIELD(8, 8) /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */ -#define OMAP4430_PERF_CURRENT_SHIFT (1 << 0) +#define OMAP4430_PERF_CURRENT_SHIFT 0 #define OMAP4430_PERF_CURRENT_MASK BITFIELD(0, 7) /* @@ -1315,66 +1315,66 @@ * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD, * CM_IVA_DVFS_PERF_TESLA */ -#define OMAP4430_PERF_REQ_SHIFT (1 << 0) +#define OMAP4430_PERF_REQ_SHIFT 0 #define OMAP4430_PERF_REQ_MASK BITFIELD(0, 7) /* Used by CM_EMU_OVERRIDE_DPLL_PER */ -#define OMAP4430_PER_DPLL_EMU_DIV_SHIFT (1 << 0) +#define OMAP4430_PER_DPLL_EMU_DIV_SHIFT 0 #define OMAP4430_PER_DPLL_EMU_DIV_MASK BITFIELD(0, 6) /* Used by CM_EMU_OVERRIDE_DPLL_PER */ -#define OMAP4430_PER_DPLL_EMU_MULT_SHIFT (1 << 8) +#define OMAP4430_PER_DPLL_EMU_MULT_SHIFT 8 #define OMAP4430_PER_DPLL_EMU_MULT_MASK BITFIELD(8, 18) /* Used by CM_RESTORE_ST */ -#define OMAP4430_PHASE1_COMPLETED_SHIFT (1 << 0) +#define OMAP4430_PHASE1_COMPLETED_SHIFT 0 #define OMAP4430_PHASE1_COMPLETED_MASK BITFIELD(0, 0) /* Used by CM_RESTORE_ST */ -#define OMAP4430_PHASE2A_COMPLETED_SHIFT (1 << 1) +#define OMAP4430_PHASE2A_COMPLETED_SHIFT 1 #define OMAP4430_PHASE2A_COMPLETED_MASK BITFIELD(1, 1) /* Used by CM_RESTORE_ST */ -#define OMAP4430_PHASE2B_COMPLETED_SHIFT (1 << 2) +#define OMAP4430_PHASE2B_COMPLETED_SHIFT 2 #define OMAP4430_PHASE2B_COMPLETED_MASK BITFIELD(2, 2) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ -#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT (1 << 20) +#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 #define OMAP4430_PMD_STM_MUX_CTRL_MASK BITFIELD(20, 21) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ -#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT (1 << 22) +#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK BITFIELD(22, 23) /* Used by CM_DYN_DEP_PRESCAL */ -#define OMAP4430_PRESCAL_SHIFT (1 << 0) +#define OMAP4430_PRESCAL_SHIFT 0 #define OMAP4430_PRESCAL_MASK BITFIELD(0, 5) /* Used by REVISION_CM2, REVISION_CM1 */ -#define OMAP4430_REV_SHIFT (1 << 0) +#define OMAP4430_REV_SHIFT 0 #define OMAP4430_REV_MASK BITFIELD(0, 7) /* * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ -#define OMAP4430_SAR_MODE_SHIFT (1 << 4) +#define OMAP4430_SAR_MODE_SHIFT 4 #define OMAP4430_SAR_MODE_MASK BITFIELD(4, 4) /* Used by CM_SCALE_FCLK */ -#define OMAP4430_SCALE_FCLK_SHIFT (1 << 0) +#define OMAP4430_SCALE_FCLK_SHIFT 0 #define OMAP4430_SCALE_FCLK_MASK BITFIELD(0, 0) /* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_SDMA_DYNDEP_SHIFT (1 << 11) +#define OMAP4430_SDMA_DYNDEP_SHIFT 11 #define OMAP4430_SDMA_DYNDEP_MASK BITFIELD(11, 11) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ -#define OMAP4430_SDMA_STATDEP_SHIFT (1 << 11) +#define OMAP4430_SDMA_STATDEP_SHIFT 11 #define OMAP4430_SDMA_STATDEP_MASK BITFIELD(11, 11) /* Used by CM_CLKSEL_ABE */ -#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT (1 << 10) +#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 #define OMAP4430_SLIMBUS_CLK_GATE_MASK BITFIELD(10, 10) /* @@ -1390,7 +1390,7 @@ * CM_IVAHD_IVAHD_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL */ -#define OMAP4430_STBYST_SHIFT (1 << 18) +#define OMAP4430_STBYST_SHIFT 18 #define OMAP4430_STBYST_MASK BITFIELD(18, 18) /* @@ -1398,11 +1398,11 @@ * CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU */ -#define OMAP4430_ST_DPLL_CLK_SHIFT (1 << 0) +#define OMAP4430_ST_DPLL_CLK_SHIFT 0 #define OMAP4430_ST_DPLL_CLK_MASK BITFIELD(0, 0) /* Used by CM_CLKDCOLDO_DPLL_USB */ -#define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT (1 << 9) +#define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9 #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK BITFIELD(9, 9) /* @@ -1410,58 +1410,58 @@ * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, * CM_DIV_M2_DPLL_MPU */ -#define OMAP4430_ST_DPLL_CLKOUT_SHIFT (1 << 9) +#define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 #define OMAP4430_ST_DPLL_CLKOUT_MASK BITFIELD(9, 9) /* * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, * CM_DIV_M3_DPLL_CORE */ -#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT (1 << 9) +#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK BITFIELD(9, 9) /* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */ -#define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT (1 << 11) +#define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11 #define OMAP4430_ST_DPLL_CLKOUTX2_MASK BITFIELD(11, 11) /* * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA */ -#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT (1 << 9) +#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK BITFIELD(9, 9) /* * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA */ -#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT (1 << 9) +#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK BITFIELD(9, 9) /* * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY */ -#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT (1 << 9) +#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK BITFIELD(9, 9) /* * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, * CM_DIV_M7_DPLL_CORE */ -#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT (1 << 9) +#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK BITFIELD(9, 9) /* Used by CM_SYS_CLKSEL */ -#define OMAP4430_SYS_CLKSEL_SHIFT (1 << 0) +#define OMAP4430_SYS_CLKSEL_SHIFT 0 #define OMAP4430_SYS_CLKSEL_MASK BITFIELD(0, 2) /* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_TESLA_DYNDEP_SHIFT (1 << 1) +#define OMAP4430_TESLA_DYNDEP_SHIFT 1 #define OMAP4430_TESLA_DYNDEP_MASK BITFIELD(1, 1) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ -#define OMAP4430_TESLA_STATDEP_SHIFT (1 << 1) +#define OMAP4430_TESLA_STATDEP_SHIFT 1 #define OMAP4430_TESLA_STATDEP_MASK BITFIELD(1, 1) /* @@ -1469,6 +1469,6 @@ * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ -#define OMAP4430_WINDOWSIZE_SHIFT (1 << 24) +#define OMAP4430_WINDOWSIZE_SHIFT 24 #define OMAP4430_WINDOWSIZE_MASK BITFIELD(24, 27) #endif diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index 90a4086fbdf4..4e4ac8ccd7f5 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h @@ -67,7 +67,8 @@ #define CM_CLKSEL 0x0040 #define CM_CLKSEL1 CM_CLKSEL #define CM_CLKSEL2 0x0044 -#define CM_CLKSTCTRL 0x0048 +#define OMAP2_CM_CLKSTCTRL 0x0048 +#define OMAP4_CM_CLKSTCTRL 0x0000 /* Architecture-specific registers */ @@ -88,7 +89,7 @@ #define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL #define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2 #define OMAP3430_CM_SLEEPDEP CM_CLKSEL2 -#define OMAP3430_CM_CLKSEL3 CM_CLKSTCTRL +#define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL #define OMAP3430_CM_CLKSTST 0x004c #define OMAP3430ES2_CM_CLKSEL4 0x004c #define OMAP3430ES2_CM_CLKSEL5 0x0050 diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 18ad93160abb..c104d5ca65b2 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -141,7 +141,7 @@ static inline void omap_init_camera(void) #define MBOX_REG_SIZE 0x120 #ifdef CONFIG_ARCH_OMAP2 -static struct resource omap_mbox_resources[] = { +static struct resource omap2_mbox_resources[] = { { .start = OMAP24XX_MAILBOX_BASE, .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, @@ -156,10 +156,14 @@ static struct resource omap_mbox_resources[] = { .flags = IORESOURCE_IRQ, }, }; +static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources); +#else +#define omap2_mbox_resources NULL +#define omap2_mbox_resources_sz 0 #endif #ifdef CONFIG_ARCH_OMAP3 -static struct resource omap_mbox_resources[] = { +static struct resource omap3_mbox_resources[] = { { .start = OMAP34XX_MAILBOX_BASE, .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, @@ -170,12 +174,16 @@ static struct resource omap_mbox_resources[] = { .flags = IORESOURCE_IRQ, }, }; +static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources); +#else +#define omap3_mbox_resources NULL +#define omap3_mbox_resources_sz 0 #endif #ifdef CONFIG_ARCH_OMAP4 #define OMAP4_MBOX_REG_SIZE 0x130 -static struct resource omap_mbox_resources[] = { +static struct resource omap4_mbox_resources[] = { { .start = OMAP44XX_MAILBOX_BASE, .end = OMAP44XX_MAILBOX_BASE + @@ -187,6 +195,10 @@ static struct resource omap_mbox_resources[] = { .flags = IORESOURCE_IRQ, }, }; +static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources); +#else +#define omap4_mbox_resources NULL +#define omap4_mbox_resources_sz 0 #endif static struct platform_device mbox_device = { @@ -196,9 +208,15 @@ static struct platform_device mbox_device = { static inline void omap_init_mbox(void) { - if (cpu_is_omap2420() || cpu_is_omap3430() || cpu_is_omap44xx()) { - mbox_device.num_resources = ARRAY_SIZE(omap_mbox_resources); - mbox_device.resource = omap_mbox_resources; + if (cpu_is_omap24xx()) { + mbox_device.resource = omap2_mbox_resources; + mbox_device.num_resources = omap2_mbox_resources_sz; + } else if (cpu_is_omap34xx()) { + mbox_device.resource = omap3_mbox_resources; + mbox_device.num_resources = omap3_mbox_resources_sz; + } else if (cpu_is_omap44xx()) { + mbox_device.resource = omap4_mbox_resources; + mbox_device.num_resources = omap4_mbox_resources_sz; } else { pr_err("%s: platform not supported\n", __func__); return; @@ -492,7 +510,12 @@ static struct platform_device dummy_pdev = { **/ static void __init omap_hsmmc_reset(void) { - u32 i, nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC : + u32 i, nr_controllers; + + if (cpu_is_omap242x()) + return; + + nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC : (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC); for (i = 0; i < nr_controllers; i++) { diff --git a/arch/arm/mach-omap2/dpll.c b/arch/arm/mach-omap2/dpll3xxx.c index f6055b493294..2b559fc64855 100644 --- a/arch/arm/mach-omap2/dpll.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -44,17 +44,7 @@ #define MAX_DPLL_WAIT_TRIES 1000000 - -/** - * omap3_dpll_recalc - recalculate DPLL rate - * @clk: DPLL struct clk - * - * Recalculate and propagate the DPLL rate. - */ -unsigned long omap3_dpll_recalc(struct clk *clk) -{ - return omap2_get_dpll_rate(clk); -} +/* Private functions */ /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) @@ -136,8 +126,6 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) return f; } -/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ - /* * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness * @clk: pointer to a DPLL struct clk @@ -237,6 +225,63 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) return 0; } +/* + * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly + * @clk: struct clk * of DPLL to set + * @m: DPLL multiplier to set + * @n: DPLL divider to set + * @freqsel: FREQSEL value to set + * + * Program the DPLL with the supplied M, N values, and wait for the DPLL to + * lock.. Returns -EINVAL upon error, or 0 upon success. + */ +static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) +{ + struct dpll_data *dd = clk->dpll_data; + u32 v; + + /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ + _omap3_noncore_dpll_bypass(clk); + + /* Set jitter correction */ + if (!cpu_is_omap44xx()) { + v = __raw_readl(dd->control_reg); + v &= ~dd->freqsel_mask; + v |= freqsel << __ffs(dd->freqsel_mask); + __raw_writel(v, dd->control_reg); + } + + /* Set DPLL multiplier, divider */ + v = __raw_readl(dd->mult_div1_reg); + v &= ~(dd->mult_mask | dd->div1_mask); + v |= m << __ffs(dd->mult_mask); + v |= (n - 1) << __ffs(dd->div1_mask); + __raw_writel(v, dd->mult_div1_reg); + + /* We let the clock framework set the other output dividers later */ + + /* REVISIT: Set ramp-up delay? */ + + _omap3_noncore_dpll_lock(clk); + + return 0; +} + +/* Public functions */ + +/** + * omap3_dpll_recalc - recalculate DPLL rate + * @clk: DPLL struct clk + * + * Recalculate and propagate the DPLL rate. + */ +unsigned long omap3_dpll_recalc(struct clk *clk) +{ + return omap2_get_dpll_rate(clk); +} + +/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ + /** * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode * @clk: pointer to a DPLL struct clk @@ -292,48 +337,6 @@ void omap3_noncore_dpll_disable(struct clk *clk) /* Non-CORE DPLL rate set code */ -/* - * omap3_noncore_dpll_program - set non-core DPLL M,N values directly - * @clk: struct clk * of DPLL to set - * @m: DPLL multiplier to set - * @n: DPLL divider to set - * @freqsel: FREQSEL value to set - * - * Program the DPLL with the supplied M, N values, and wait for the DPLL to - * lock.. Returns -EINVAL upon error, or 0 upon success. - */ -int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) -{ - struct dpll_data *dd = clk->dpll_data; - u32 v; - - /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ - _omap3_noncore_dpll_bypass(clk); - - /* Set jitter correction */ - if (!cpu_is_omap44xx()) { - v = __raw_readl(dd->control_reg); - v &= ~dd->freqsel_mask; - v |= freqsel << __ffs(dd->freqsel_mask); - __raw_writel(v, dd->control_reg); - } - - /* Set DPLL multiplier, divider */ - v = __raw_readl(dd->mult_div1_reg); - v &= ~(dd->mult_mask | dd->div1_mask); - v |= m << __ffs(dd->mult_mask); - v |= (n - 1) << __ffs(dd->div1_mask); - __raw_writel(v, dd->mult_div1_reg); - - /* We let the clock framework set the other output dividers later */ - - /* REVISIT: Set ramp-up delay? */ - - _omap3_noncore_dpll_lock(clk); - - return 0; -} - /** * omap3_noncore_dpll_set_rate - set non-core DPLL rate * @clk: struct clk * of DPLL to set diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c index ec0d984a26fc..9c442e290ccb 100644 --- a/arch/arm/mach-omap2/emu.c +++ b/arch/arm/mach-omap2/emu.c @@ -56,6 +56,9 @@ static struct amba_device omap3_etm_device = { static int __init emu_init(void) { + if (!cpu_is_omap34xx()) + return -ENODEV; + amba_device_register(&omap3_etb_device, &iomem_resource); amba_device_register(&omap3_etm_device, &iomem_resource); diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c new file mode 100644 index 000000000000..64d74f05abbe --- /dev/null +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -0,0 +1,139 @@ +/* + * gpmc-nand.c + * + * Copyright (C) 2009 Texas Instruments + * Vimal Singh <vimalsingh@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/io.h> + +#include <asm/mach/flash.h> + +#include <plat/nand.h> +#include <plat/board.h> +#include <plat/gpmc.h> + +#define WR_RD_PIN_MONITORING 0x00600000 + +static struct omap_nand_platform_data *gpmc_nand_data; + +static struct resource gpmc_nand_resource = { + .flags = IORESOURCE_MEM, +}; + +static struct platform_device gpmc_nand_device = { + .name = "omap2-nand", + .id = 0, + .num_resources = 1, + .resource = &gpmc_nand_resource, +}; + +static int omap2_nand_gpmc_retime(void) +{ + struct gpmc_timings t; + int err; + + memset(&t, 0, sizeof(t)); + t.sync_clk = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->sync_clk); + t.cs_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_on); + t.adv_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->adv_on); + + /* Read */ + t.adv_rd_off = gpmc_round_ns_to_ticks( + gpmc_nand_data->gpmc_t->adv_rd_off); + t.oe_on = t.adv_on; + t.access = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->access); + t.oe_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->oe_off); + t.cs_rd_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_rd_off); + t.rd_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->rd_cycle); + + /* Write */ + t.adv_wr_off = gpmc_round_ns_to_ticks( + gpmc_nand_data->gpmc_t->adv_wr_off); + t.we_on = t.oe_on; + if (cpu_is_omap34xx()) { + t.wr_data_mux_bus = gpmc_round_ns_to_ticks( + gpmc_nand_data->gpmc_t->wr_data_mux_bus); + t.wr_access = gpmc_round_ns_to_ticks( + gpmc_nand_data->gpmc_t->wr_access); + } + t.we_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->we_off); + t.cs_wr_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_wr_off); + t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle); + + /* Configure GPMC */ + gpmc_cs_write_reg(gpmc_nand_data->cs, GPMC_CS_CONFIG1, + GPMC_CONFIG1_DEVICESIZE(gpmc_nand_data->devsize) | + GPMC_CONFIG1_DEVICETYPE_NAND); + + err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); + if (err) + return err; + + return 0; +} + +static int gpmc_nand_setup(void) +{ + struct device *dev = &gpmc_nand_device.dev; + + /* Set timings in GPMC */ + if (omap2_nand_gpmc_retime() < 0) { + dev_err(dev, "Unable to set gpmc timings\n"); + return -EINVAL; + } + + return 0; +} + +int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data) +{ + unsigned int val; + int err = 0; + struct device *dev = &gpmc_nand_device.dev; + + gpmc_nand_data = _nand_data; + gpmc_nand_data->nand_setup = gpmc_nand_setup; + gpmc_nand_device.dev.platform_data = gpmc_nand_data; + + err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, + &gpmc_nand_data->phys_base); + if (err < 0) { + dev_err(dev, "Cannot request GPMC CS\n"); + return err; + } + + err = gpmc_nand_setup(); + if (err < 0) { + dev_err(dev, "NAND platform setup failed: %d\n", err); + return err; + } + + /* Enable RD PIN Monitoring Reg */ + if (gpmc_nand_data->dev_ready) { + val = gpmc_cs_read_reg(gpmc_nand_data->cs, + GPMC_CS_CONFIG1); + val |= WR_RD_PIN_MONITORING; + gpmc_cs_write_reg(gpmc_nand_data->cs, + GPMC_CS_CONFIG1, val); + } + + err = platform_device_register(&gpmc_nand_device); + if (err < 0) { + dev_err(dev, "Unable to register NAND device\n"); + goto out_free_cs; + } + + return 0; + +out_free_cs: + gpmc_cs_free(gpmc_nand_data->cs); + + return err; +} diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 7027cdc1ba49..5bc3ca03551c 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -552,9 +552,10 @@ void __init gpmc_init(void) #ifdef CONFIG_ARCH_OMAP3 static struct omap3_gpmc_regs gpmc_context; -void omap3_gpmc_save_context() +void omap3_gpmc_save_context(void) { int i; + gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG); gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE); gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL); @@ -583,9 +584,10 @@ void omap3_gpmc_save_context() } } -void omap3_gpmc_restore_context() +void omap3_gpmc_restore_context(void) { int i; + gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig); gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable); gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl); diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c new file mode 100644 index 000000000000..9ad229594b46 --- /dev/null +++ b/arch/arm/mach-omap2/hsmmc.c @@ -0,0 +1,266 @@ +/* + * linux/arch/arm/mach-omap2/hsmmc.c + * + * Copyright (C) 2007-2008 Texas Instruments + * Copyright (C) 2008 Nokia Corporation + * Author: Texas Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/slab.h> +#include <linux/string.h> +#include <linux/delay.h> +#include <mach/hardware.h> +#include <plat/control.h> +#include <plat/mmc.h> +#include <plat/omap-pm.h> + +#include "hsmmc.h" + +#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) + +static u16 control_pbias_offset; +static u16 control_devconf1_offset; + +#define HSMMC_NAME_LEN 9 + +static struct hsmmc_controller { + char name[HSMMC_NAME_LEN + 1]; +} hsmmc[OMAP34XX_NR_MMC]; + +#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) + +static int hsmmc_get_context_loss(struct device *dev) +{ + return omap_pm_get_dev_context_loss_count(dev); +} + +#else +#define hsmmc_get_context_loss NULL +#endif + +static void hsmmc1_before_set_reg(struct device *dev, int slot, + int power_on, int vdd) +{ + u32 reg, prog_io; + struct omap_mmc_platform_data *mmc = dev->platform_data; + + if (mmc->slots[0].remux) + mmc->slots[0].remux(dev, slot, power_on); + + /* + * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the + * card with Vcc regulator (from twl4030 or whatever). OMAP has both + * 1.8V and 3.0V modes, controlled by the PBIAS register. + * + * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which + * is most naturally TWL VSIM; those pins also use PBIAS. + * + * FIXME handle VMMC1A as needed ... + */ + if (power_on) { + if (cpu_is_omap2430()) { + reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1); + if ((1 << vdd) >= MMC_VDD_30_31) + reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE; + else + reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE; + omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1); + } + + if (mmc->slots[0].internal_clock) { + reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + reg |= OMAP2_MMCSDIO1ADPCLKISEL; + omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0); + } + + reg = omap_ctrl_readl(control_pbias_offset); + if (cpu_is_omap3630()) { + /* Set MMC I/O to 52Mhz */ + prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); + prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL; + omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1); + } else { + reg |= OMAP2_PBIASSPEEDCTRL0; + } + reg &= ~OMAP2_PBIASLITEPWRDNZ0; + omap_ctrl_writel(reg, control_pbias_offset); + } else { + reg = omap_ctrl_readl(control_pbias_offset); + reg &= ~OMAP2_PBIASLITEPWRDNZ0; + omap_ctrl_writel(reg, control_pbias_offset); + } +} + +static void hsmmc1_after_set_reg(struct device *dev, int slot, + int power_on, int vdd) +{ + u32 reg; + + /* 100ms delay required for PBIAS configuration */ + msleep(100); + + if (power_on) { + reg = omap_ctrl_readl(control_pbias_offset); + reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0); + if ((1 << vdd) <= MMC_VDD_165_195) + reg &= ~OMAP2_PBIASLITEVMODE0; + else + reg |= OMAP2_PBIASLITEVMODE0; + omap_ctrl_writel(reg, control_pbias_offset); + } else { + reg = omap_ctrl_readl(control_pbias_offset); + reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 | + OMAP2_PBIASLITEVMODE0); + omap_ctrl_writel(reg, control_pbias_offset); + } +} + +static void hsmmc23_before_set_reg(struct device *dev, int slot, + int power_on, int vdd) +{ + struct omap_mmc_platform_data *mmc = dev->platform_data; + + if (mmc->slots[0].remux) + mmc->slots[0].remux(dev, slot, power_on); + + if (power_on) { + /* Only MMC2 supports a CLKIN */ + if (mmc->slots[0].internal_clock) { + u32 reg; + + reg = omap_ctrl_readl(control_devconf1_offset); + reg |= OMAP2_MMCSDIO2ADPCLKISEL; + omap_ctrl_writel(reg, control_devconf1_offset); + } + } +} + +static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; + +void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) +{ + struct omap2_hsmmc_info *c; + int nr_hsmmc = ARRAY_SIZE(hsmmc_data); + int i; + + if (cpu_is_omap2430()) { + control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; + control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; + } else { + control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; + control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; + } + + for (c = controllers; c->mmc; c++) { + struct hsmmc_controller *hc = hsmmc + c->mmc - 1; + struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; + + if (!c->mmc || c->mmc > nr_hsmmc) { + pr_debug("MMC%d: no such controller\n", c->mmc); + continue; + } + if (mmc) { + pr_debug("MMC%d: already configured\n", c->mmc); + continue; + } + + mmc = kzalloc(sizeof(struct omap_mmc_platform_data), + GFP_KERNEL); + if (!mmc) { + pr_err("Cannot allocate memory for mmc device!\n"); + goto done; + } + + if (c->name) + strncpy(hc->name, c->name, HSMMC_NAME_LEN); + else + snprintf(hc->name, ARRAY_SIZE(hc->name), + "mmc%islot%i", c->mmc, 1); + mmc->slots[0].name = hc->name; + mmc->nr_slots = 1; + mmc->slots[0].wires = c->wires; + mmc->slots[0].internal_clock = !c->ext_clock; + mmc->dma_mask = 0xffffffff; + + mmc->get_context_loss_count = hsmmc_get_context_loss; + + mmc->slots[0].switch_pin = c->gpio_cd; + mmc->slots[0].gpio_wp = c->gpio_wp; + + mmc->slots[0].remux = c->remux; + + if (c->cover_only) + mmc->slots[0].cover = 1; + + if (c->nonremovable) + mmc->slots[0].nonremovable = 1; + + if (c->power_saving) + mmc->slots[0].power_saving = 1; + + if (c->no_off) + mmc->slots[0].no_off = 1; + + if (c->vcc_aux_disable_is_sleep) + mmc->slots[0].vcc_aux_disable_is_sleep = 1; + + /* NOTE: MMC slots should have a Vcc regulator set up. + * This may be from a TWL4030-family chip, another + * controllable regulator, or a fixed supply. + * + * temporary HACK: ocr_mask instead of fixed supply + */ + mmc->slots[0].ocr_mask = c->ocr_mask; + + switch (c->mmc) { + case 1: + /* on-chip level shifting via PBIAS0/PBIAS1 */ + mmc->slots[0].before_set_reg = hsmmc1_before_set_reg; + mmc->slots[0].after_set_reg = hsmmc1_after_set_reg; + + /* Omap3630 HSMMC1 supports only 4-bit */ + if (cpu_is_omap3630() && c->wires > 4) { + c->wires = 4; + mmc->slots[0].wires = c->wires; + } + break; + case 2: + if (c->ext_clock) + c->transceiver = 1; + if (c->transceiver && c->wires > 4) + c->wires = 4; + /* FALLTHROUGH */ + case 3: + /* off-chip level shifting, or none */ + mmc->slots[0].before_set_reg = hsmmc23_before_set_reg; + mmc->slots[0].after_set_reg = NULL; + break; + default: + pr_err("MMC%d configuration not supported!\n", c->mmc); + kfree(mmc); + continue; + } + hsmmc_data[c->mmc - 1] = mmc; + } + + omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC); + + /* pass the device nodes back to board setup code */ + for (c = controllers; c->mmc; c++) { + struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; + + if (!c->mmc || c->mmc > nr_hsmmc) + continue; + c->dev = mmc->dev; + } + +done: + for (i = 0; i < nr_hsmmc; i++) + kfree(hsmmc_data[i]); +} + +#endif diff --git a/arch/arm/mach-omap2/mmc-twl4030.h b/arch/arm/mach-omap2/hsmmc.h index a47e68563fb6..36f0ba8d89e2 100644 --- a/arch/arm/mach-omap2/mmc-twl4030.h +++ b/arch/arm/mach-omap2/hsmmc.h @@ -6,7 +6,7 @@ * published by the Free Software Foundation. */ -struct twl4030_hsmmc_info { +struct omap2_hsmmc_info { u8 mmc; /* controller 1/2/3 */ u8 wires; /* 1/4/8 wires */ bool transceiver; /* MMC-2 option */ @@ -14,22 +14,24 @@ struct twl4030_hsmmc_info { bool cover_only; /* No card detect - just cover switch */ bool nonremovable; /* Nonremovable e.g. eMMC */ bool power_saving; /* Try to sleep or power off when possible */ + bool no_off; /* power_saving and power is not to go off */ + bool vcc_aux_disable_is_sleep; /* Regulator off remapped to sleep */ int gpio_cd; /* or -EINVAL */ int gpio_wp; /* or -EINVAL */ char *name; /* or NULL for default */ struct device *dev; /* returned: pointer to mmc adapter */ int ocr_mask; /* temporary HACK */ + /* Remux (pad configuation) when powering on/off */ + void (*remux)(struct device *dev, int slot, int power_on); }; -#if defined(CONFIG_REGULATOR) && \ - (defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ - defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)) +#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) -void twl4030_mmc_init(struct twl4030_hsmmc_info *); +void omap2_hsmmc_init(struct omap2_hsmmc_info *); #else -static inline void twl4030_mmc_init(struct twl4030_hsmmc_info *info) +static inline void omap2_hsmmc_init(struct omap2_hsmmc_info *info) { } diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 3d65c50bd017..9e7c4aeeae02 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -281,6 +281,7 @@ void __init omap4_check_revision(void) if ((hawkeye == 0xb852) && (rev == 0x0)) { omap_revision = OMAP4430_REV_ES1_0; + omap_chip.oc |= CHIP_IS_OMAP4430ES1; pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name); return; } diff --git a/arch/arm/mach-omap2/include/mach/am35xx.h b/arch/arm/mach-omap2/include/mach/am35xx.h new file mode 100644 index 000000000000..a705f946fc46 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/am35xx.h @@ -0,0 +1,26 @@ +/*: + * Address mappings and base address for AM35XX specific interconnects + * and peripherals. + * + * Copyright (C) 2009 Texas Instruments + * + * Author: Sriramakrishnan <srk@ti.com> + * Vaibhav Hiremath <hvaibhav@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_ARCH_AM35XX_H +#define __ASM_ARCH_AM35XX_H + +/* + * Base addresses + * Note: OMAP3430 IVA2 memory space is being used for AM35xx IPSS modules + */ +#define AM35XX_IPSS_EMAC_BASE 0x5C000000 +#define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000 +#define AM35XX_IPSS_HECC_BASE 0x5C050000 +#define AM35XX_IPSS_VPFE_BASE 0x5C060000 + +#endif /* __ASM_ARCH_AM35XX_H */ diff --git a/arch/arm/mach-omap2/include/mach/board-sdp.h b/arch/arm/mach-omap2/include/mach/board-sdp.h new file mode 100644 index 000000000000..465169c0908a --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/board-sdp.h @@ -0,0 +1,21 @@ +/* + * board-sdp.h + * + * Information structures for SDP-specific board config data + * + * Copyright (C) 2009 Nokia Corporation + * Copyright (C) 2009 Texas Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> + +struct flash_partitions { + struct mtd_partition *parts; + int nr_parts; +}; + +extern void sdp_flash_init(struct flash_partitions []); diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S index e9f255df9163..4a63a2ea484d 100644 --- a/arch/arm/mach-omap2/include/mach/debug-macro.S +++ b/arch/arm/mach-omap2/include/mach/debug-macro.S @@ -11,32 +11,107 @@ * */ - .macro addruart,rx +#include <linux/serial_reg.h> + +#include <plat/serial.h> + +#define UART_OFFSET(addr) ((addr) & 0x00ffffff) + + .pushsection .data +omap_uart_phys: .word 0 +omap_uart_virt: .word 0 +omap_uart_lsr: .word 0 + .popsection + + /* + * Note that this code won't work if the bootloader passes + * a wrong machine ID number in r1. To debug, just hardcode + * the desired UART phys and virt addresses temporarily into + * the omap_uart_phys and omap_uart_virt above. + */ + .macro addruart, rx, tmp + + /* Use omap_uart_phys/virt if already configured */ +10: mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =omap_uart_phys @ physical base address + ldrne \rx, =omap_uart_virt @ virtual base address + ldr \rx, [\rx, #0] + cmp \rx, #0 @ is port configured? + bne 99f @ already configured + + /* Check UART1 scratchpad register for uart to use */ mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? -#ifdef CONFIG_ARCH_OMAP2 moveq \rx, #0x48000000 @ physical base address movne \rx, #0xfa000000 @ virtual base - orr \rx, \rx, #0x0006a000 -#ifdef CONFIG_OMAP_LL_DEBUG_UART2 - add \rx, \rx, #0x00002000 @ UART 2 -#endif -#ifdef CONFIG_OMAP_LL_DEBUG_UART3 - add \rx, \rx, #0x00004000 @ UART 3 -#endif - -#elif defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) - moveq \rx, #0x48000000 @ physical base address - movne \rx, #0xfa000000 @ virtual base - orr \rx, \rx, #0x0006a000 -#ifdef CONFIG_OMAP_LL_DEBUG_UART2 - add \rx, \rx, #0x00002000 @ UART 2 -#endif -#ifdef CONFIG_OMAP_LL_DEBUG_UART3 - add \rx, \rx, #0x00fb0000 @ UART 3 - add \rx, \rx, #0x00006000 -#endif -#endif + orr \rx, \rx, #0x0006a000 @ uart1 on omap2/3/4 + ldrb \rx, [\rx, #(UART_SCR << OMAP_PORT_SHIFT)] @ scratchpad + + /* Select the UART to use based on the UART1 scratchpad value */ + cmp \rx, #0 @ no port configured? + beq 21f @ if none, try to use UART1 + cmp \rx, #OMAP2UART1 @ OMAP2/3/4UART1 + beq 21f @ configure OMAP2/3/4UART1 + cmp \rx, #OMAP2UART2 @ OMAP2/3/4UART2 + beq 22f @ configure OMAP2/3/4UART2 + cmp \rx, #OMAP2UART3 @ only on 24xx + beq 23f @ configure OMAP2UART3 + cmp \rx, #OMAP3UART3 @ only on 34xx + beq 33f @ configure OMAP3UART3 + cmp \rx, #OMAP4UART3 @ only on 44xx + beq 43f @ configure OMAP4UART3 + cmp \rx, #OMAP3UART4 @ only on 36xx + beq 34f @ configure OMAP3UART4 + cmp \rx, #OMAP4UART4 @ only on 44xx + beq 44f @ configure OMAP4UART4 + cmp \rx, #ZOOM_UART @ only on zoom2/3 + beq 95f @ configure ZOOM_UART + + /* Configure the UART offset from the phys/virt base */ +21: mov \rx, #UART_OFFSET(OMAP2_UART1_BASE) @ omap2/3/4 + b 98f +22: mov \rx, #UART_OFFSET(OMAP2_UART2_BASE) @ omap2/3/4 + b 98f +23: mov \rx, #UART_OFFSET(OMAP2_UART3_BASE) + b 98f +33: mov \rx, #UART_OFFSET(OMAP3_UART1_BASE) + add \rx, \rx, #0x00fb0000 + add \rx, \rx, #0x00006000 @ OMAP3_UART3_BASE + b 98f +34: mov \rx, #UART_OFFSET(OMAP3_UART1_BASE) + add \rx, \rx, #0x00fb0000 + add \rx, \rx, #0x00028000 @ OMAP3_UART4_BASE + b 98f +43: mov \rx, #UART_OFFSET(OMAP4_UART3_BASE) + b 98f +44: mov \rx, #UART_OFFSET(OMAP4_UART4_BASE) + b 98f +95: mov \rx, #ZOOM_UART_BASE + ldr \tmp, =omap_uart_phys + str \rx, [\tmp, #0] + mov \rx, #ZOOM_UART_VIRT + ldr \tmp, =omap_uart_virt + str \rx, [\tmp, #0] + mov \rx, #(UART_LSR << ZOOM_PORT_SHIFT) + ldr \tmp, =omap_uart_lsr + str \rx, [\tmp, #0] + b 10b + + /* Store both phys and virt address for the uart */ +98: add \rx, \rx, #0x48000000 @ phys base + ldr \tmp, =omap_uart_phys + str \rx, [\tmp, #0] + sub \rx, \rx, #0x48000000 @ phys base + add \rx, \rx, #0xfa000000 @ virt base + ldr \tmp, =omap_uart_virt + str \rx, [\tmp, #0] + mov \rx, #(UART_LSR << OMAP_PORT_SHIFT) + ldr \tmp, =omap_uart_lsr + str \rx, [\tmp, #0] + + b 10b +99: .endm .macro senduart,rd,rx @@ -44,15 +119,12 @@ .endm .macro busyuart,rd,rx -1001: ldrb \rd, [\rx, #(0x5 << 2)] @ OMAP-1510 and friends - and \rd, \rd, #0x60 - teq \rd, #0x60 - beq 1002f - ldrb \rd, [\rx, #(0x5 << 0)] @ OMAP-730 only - and \rd, \rd, #0x60 - teq \rd, #0x60 +1001: ldr \rd, =omap_uart_lsr + ldr \rd, [\rd, #0] + ldrb \rd, [\rx, \rd] + and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE) + teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE) bne 1001b -1002: .endm .macro waituart,rd,rx diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S index c7f1720bf282..ff25c7e4e606 100644 --- a/arch/arm/mach-omap2/include/mach/entry-macro.S +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S @@ -17,46 +17,134 @@ #include <plat/omap24xx.h> #include <plat/omap34xx.h> - -/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */ -#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430) -#define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE) -#elif defined(CONFIG_ARCH_OMAP34XX) -#define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) -#endif -#if defined(CONFIG_ARCH_OMAP4) #include <plat/omap44xx.h> -#endif -#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */ -#define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */ + +#include <plat/multi.h> + +#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE) +#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) +#define OMAP4_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE) +#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */ +#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */ .macro disable_fiq .endm - .macro get_irqnr_preamble, base, tmp + .macro arch_ret_to_user, tmp1, tmp2 .endm - .macro arch_ret_to_user, tmp1, tmp2 +/* + * Unoptimized irq functions for multi-omap2, 3 and 4 + */ + +#ifdef MULTI_OMAP2 + .pushsection .data +omap_irq_base: .word 0 + .popsection + + /* Configure the interrupt base on the first interrupt */ + .macro get_irqnr_preamble, base, tmp +9: + ldr \base, =omap_irq_base @ irq base address + ldr \base, [\base, #0] @ irq base value + cmp \base, #0 @ already configured? + bne 9997f @ nothing to do + + mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision + and \tmp, \tmp, #0x000f0000 @ only check architecture + cmp \tmp, #0x00060000 @ is v6? + beq 2400f @ found v6 so it's omap24xx + mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision + and \tmp, \tmp, #0x000000f0 @ check cortex 8 or 9 + cmp \tmp, #0x00000080 @ cortex A-8? + beq 3400f @ found A-8 so it's omap34xx + cmp \tmp, #0x00000090 @ cortex A-9? + beq 4400f @ found A-9 so it's omap44xx +2400: ldr \base, =OMAP2_IRQ_BASE + ldr \tmp, =omap_irq_base + str \base, [\tmp, #0] + b 9b +3400: ldr \base, =OMAP3_IRQ_BASE + ldr \tmp, =omap_irq_base + str \base, [\tmp, #0] + b 9b +4400: ldr \base, =OMAP4_IRQ_BASE + ldr \tmp, =omap_irq_base + str \base, [\tmp, #0] + b 9b +9997: .endm -#ifndef CONFIG_ARCH_OMAP4 + /* Check the pending interrupts. Note that base already set */ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \base, =OMAP2_VA_IC_BASE + tst \base, #0x100 @ gic address? + bne 4401f @ found gic + + /* Handle omap2 and omap3 */ ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */ cmp \irqnr, #0x0 - bne 2222f + bne 9998f ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */ cmp \irqnr, #0x0 - bne 2222f + bne 9998f ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ cmp \irqnr, #0x0 -2222: +9998: ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET] and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ + b 9999f + /* Handle omap4 */ +4401: ldr \irqstat, [\base, #GIC_CPU_INTACK] + ldr \tmp, =1021 + bic \irqnr, \irqstat, #0x1c00 + cmp \irqnr, #29 + cmpcc \irqnr, \irqnr + cmpne \irqnr, \tmp + cmpcs \irqnr, \irqnr +9999: .endm + + +#else /* MULTI_OMAP2 */ + + +/* + * Optimized irq functions for omap2, 3 and 4 + */ + +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) + .macro get_irqnr_preamble, base, tmp +#ifdef CONFIG_ARCH_OMAP2 + ldr \base, =OMAP2_IRQ_BASE #else -#define OMAP44XX_VA_GIC_CPU_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE) + ldr \base, =OMAP3_IRQ_BASE +#endif + .endm + + /* Check the pending interrupts. Note that base already set */ + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */ + cmp \irqnr, #0x0 + bne 9999f + ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */ + cmp \irqnr, #0x0 + bne 9999f + ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ + cmp \irqnr, #0x0 +9999: + ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET] + and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ + + .endm +#endif + + +#ifdef CONFIG_ARCH_OMAP4 + + .macro get_irqnr_preamble, base, tmp + ldr \base, =OMAP4_IRQ_BASE + .endm /* * The interrupt numbering scheme is defined in the @@ -78,7 +166,6 @@ * valid range for an IRQ (30-1020 inclusive). */ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \base, =OMAP44XX_VA_GIC_CPU_BASE ldr \irqstat, [\base, #GIC_CPU_INTACK] ldr \tmp, =1021 @@ -119,6 +206,7 @@ cmp \tmp, #0 .endm #endif +#endif /* MULTI_OMAP2 */ .macro irq_prio_table .endm diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 5a7996402c53..5a3d6f9107e4 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -35,7 +35,9 @@ #include <plat/serial.h> #include <plat/vram.h> -#include "clock.h" +#include "clock2xxx.h" +#include "clock34xx.h" +#include "clock44xx.h" #include <plat/omap-pm.h> #include <plat/powerdomain.h> @@ -53,7 +55,7 @@ * default mapping provided here. */ -#ifdef CONFIG_ARCH_OMAP24XX +#ifdef CONFIG_ARCH_OMAP2 static struct map_desc omap24xx_io_desc[] __initdata = { { .virtual = L3_24XX_VIRT, @@ -123,7 +125,7 @@ static struct map_desc omap243x_io_desc[] __initdata = { #endif #endif -#ifdef CONFIG_ARCH_OMAP34XX +#ifdef CONFIG_ARCH_OMAP3 static struct map_desc omap34xx_io_desc[] __initdata = { { .virtual = L3_34XX_VIRT, @@ -234,37 +236,54 @@ static struct map_desc omap44xx_io_desc[] __initdata = { }; #endif -void __init omap2_map_common_io(void) +static void __init _omap2_map_common_io(void) +{ + /* Normally devicemaps_init() would flush caches and tlb after + * mdesc->map_io(), but we must also do it here because of the CPU + * revision check below. + */ + local_flush_tlb_all(); + flush_cache_all(); + + omap2_check_revision(); + omap_sram_init(); + omapfb_reserve_sdram(); + omap_vram_reserve_sdram(); +} + +#ifdef CONFIG_ARCH_OMAP2420 +void __init omap242x_map_common_io() { -#if defined(CONFIG_ARCH_OMAP2420) iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); + _omap2_map_common_io(); +} #endif -#if defined(CONFIG_ARCH_OMAP2430) +#ifdef CONFIG_ARCH_OMAP2430 +void __init omap243x_map_common_io() +{ iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); + _omap2_map_common_io(); +} #endif -#if defined(CONFIG_ARCH_OMAP34XX) +#ifdef CONFIG_ARCH_OMAP3 +void __init omap34xx_map_common_io() +{ iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); + _omap2_map_common_io(); +} #endif -#if defined(CONFIG_ARCH_OMAP4) +#ifdef CONFIG_ARCH_OMAP4 +void __init omap44xx_map_common_io() +{ iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); -#endif - /* Normally devicemaps_init() would flush caches and tlb after - * mdesc->map_io(), but we must also do it here because of the CPU - * revision check below. - */ - local_flush_tlb_all(); - flush_cache_all(); - - omap2_check_revision(); - omap_sram_init(); - omapfb_reserve_sdram(); - omap_vram_reserve_sdram(); + _omap2_map_common_io(); } +#endif /* * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters @@ -312,15 +331,24 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, else if (cpu_is_omap34xx()) hwmods = omap34xx_hwmods; + pwrdm_init(powerdomains_omap); + clkdm_init(clockdomains_omap, clkdm_autodeps); #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */ /* The OPP tables have to be registered before a clk init */ omap_hwmod_init(hwmods); omap2_mux_init(); omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); - pwrdm_init(powerdomains_omap); - clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); #endif - omap2_clk_init(); + + if (cpu_is_omap24xx()) + omap2xxx_clk_init(); + else if (cpu_is_omap34xx()) + omap3xxx_clk_init(); + else if (cpu_is_omap44xx()) + omap4xxx_clk_init(); + else + pr_err("Could not init clock framework - unknown CPU\n"); + omap_serial_early_init(); #ifndef CONFIG_ARCH_OMAP4 omap_hwmod_late_init(); diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index 281ab6342448..2c9fd1c2a7c7 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c @@ -93,7 +93,7 @@ static int omap2_mbox_startup(struct omap_mbox *mbox) mbox_ick_handle = clk_get(NULL, "mailboxes_ick"); if (IS_ERR(mbox_ick_handle)) { - printk(KERN_ERR "Could not get mailboxes_ick: %d\n", + printk(KERN_ERR "Could not get mailboxes_ick: %ld\n", PTR_ERR(mbox_ick_handle)); return PTR_ERR(mbox_ick_handle); } diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index baa451733850..d601f9405d11 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -65,9 +65,11 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { }, }; #define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) +#define OMAP2420_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) #else #define omap2420_mcbsp_pdata NULL #define OMAP2420_MCBSP_PDATA_SZ 0 +#define OMAP2420_MCBSP_REG_NUM 0 #endif #ifdef CONFIG_ARCH_OMAP2430 @@ -114,12 +116,14 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { }, }; #define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) +#define OMAP2430_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) #else #define omap2430_mcbsp_pdata NULL #define OMAP2430_MCBSP_PDATA_SZ 0 +#define OMAP2430_MCBSP_REG_NUM 0 #endif -#ifdef CONFIG_ARCH_OMAP34XX +#ifdef CONFIG_ARCH_OMAP3 static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { { .phys_base = OMAP34XX_MCBSP1_BASE, @@ -168,9 +172,11 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { }, }; #define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) +#define OMAP34XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) #else #define omap34xx_mcbsp_pdata NULL #define OMAP34XX_MCBSP_PDATA_SZ 0 +#define OMAP34XX_MCBSP_REG_NUM 0 #endif static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { @@ -208,17 +214,23 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { }, }; #define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata) +#define OMAP44XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) static int __init omap2_mcbsp_init(void) { - if (cpu_is_omap2420()) + if (cpu_is_omap2420()) { omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ; - if (cpu_is_omap2430()) + omap_mcbsp_cache_size = OMAP2420_MCBSP_REG_NUM * sizeof(u16); + } else if (cpu_is_omap2430()) { omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ; - if (cpu_is_omap34xx()) + omap_mcbsp_cache_size = OMAP2430_MCBSP_REG_NUM * sizeof(u32); + } else if (cpu_is_omap34xx()) { omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ; - if (cpu_is_omap44xx()) + omap_mcbsp_cache_size = OMAP34XX_MCBSP_REG_NUM * sizeof(u32); + } else if (cpu_is_omap44xx()) { omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ; + omap_mcbsp_cache_size = OMAP44XX_MCBSP_REG_NUM * sizeof(u32); + } mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), GFP_KERNEL); diff --git a/arch/arm/mach-omap2/mmc-twl4030.c b/arch/arm/mach-omap2/mmc-twl4030.c deleted file mode 100644 index 8afe9dd3f150..000000000000 --- a/arch/arm/mach-omap2/mmc-twl4030.c +++ /dev/null @@ -1,542 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/mmc-twl4030.c - * - * Copyright (C) 2007-2008 Texas Instruments - * Copyright (C) 2008 Nokia Corporation - * Author: Texas Instruments - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/err.h> -#include <linux/io.h> -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/mmc/host.h> -#include <linux/regulator/consumer.h> - -#include <mach/hardware.h> -#include <plat/control.h> -#include <plat/mmc.h> -#include <plat/board.h> - -#include "mmc-twl4030.h" - - -#if defined(CONFIG_REGULATOR) && \ - (defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)) - -static u16 control_pbias_offset; -static u16 control_devconf1_offset; - -#define HSMMC_NAME_LEN 9 - -static struct twl_mmc_controller { - struct omap_mmc_platform_data *mmc; - /* Vcc == configured supply - * Vcc_alt == optional - * - MMC1, supply for DAT4..DAT7 - * - MMC2/MMC2, external level shifter voltage supply, for - * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) - */ - struct regulator *vcc; - struct regulator *vcc_aux; - char name[HSMMC_NAME_LEN + 1]; -} hsmmc[OMAP34XX_NR_MMC]; - -static int twl_mmc_card_detect(int irq) -{ - unsigned i; - - for (i = 0; i < ARRAY_SIZE(hsmmc); i++) { - struct omap_mmc_platform_data *mmc; - - mmc = hsmmc[i].mmc; - if (!mmc) - continue; - if (irq != mmc->slots[0].card_detect_irq) - continue; - - /* NOTE: assumes card detect signal is active-low */ - return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); - } - return -ENOSYS; -} - -static int twl_mmc_get_ro(struct device *dev, int slot) -{ - struct omap_mmc_platform_data *mmc = dev->platform_data; - - /* NOTE: assumes write protect signal is active-high */ - return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); -} - -static int twl_mmc_get_cover_state(struct device *dev, int slot) -{ - struct omap_mmc_platform_data *mmc = dev->platform_data; - - /* NOTE: assumes card detect signal is active-low */ - return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); -} - -/* - * MMC Slot Initialization. - */ -static int twl_mmc_late_init(struct device *dev) -{ - struct omap_mmc_platform_data *mmc = dev->platform_data; - int ret = 0; - int i; - - /* MMC/SD/SDIO doesn't require a card detect switch */ - if (gpio_is_valid(mmc->slots[0].switch_pin)) { - ret = gpio_request(mmc->slots[0].switch_pin, "mmc_cd"); - if (ret) - goto done; - ret = gpio_direction_input(mmc->slots[0].switch_pin); - if (ret) - goto err; - } - - /* require at least main regulator */ - for (i = 0; i < ARRAY_SIZE(hsmmc); i++) { - if (hsmmc[i].name == mmc->slots[0].name) { - struct regulator *reg; - - hsmmc[i].mmc = mmc; - - reg = regulator_get(dev, "vmmc"); - if (IS_ERR(reg)) { - dev_dbg(dev, "vmmc regulator missing\n"); - /* HACK: until fixed.c regulator is usable, - * we don't require a main regulator - * for MMC2 or MMC3 - */ - if (i != 0) - break; - ret = PTR_ERR(reg); - hsmmc[i].vcc = NULL; - goto err; - } - hsmmc[i].vcc = reg; - mmc->slots[0].ocr_mask = mmc_regulator_get_ocrmask(reg); - - /* allow an aux regulator */ - reg = regulator_get(dev, "vmmc_aux"); - hsmmc[i].vcc_aux = IS_ERR(reg) ? NULL : reg; - - /* UGLY HACK: workaround regulator framework bugs. - * When the bootloader leaves a supply active, it's - * initialized with zero usecount ... and we can't - * disable it without first enabling it. Until the - * framework is fixed, we need a workaround like this - * (which is safe for MMC, but not in general). - */ - if (regulator_is_enabled(hsmmc[i].vcc) > 0) { - regulator_enable(hsmmc[i].vcc); - regulator_disable(hsmmc[i].vcc); - } - if (hsmmc[i].vcc_aux) { - if (regulator_is_enabled(reg) > 0) { - regulator_enable(reg); - regulator_disable(reg); - } - } - - break; - } - } - - return 0; - -err: - gpio_free(mmc->slots[0].switch_pin); -done: - mmc->slots[0].card_detect_irq = 0; - mmc->slots[0].card_detect = NULL; - - dev_err(dev, "err %d configuring card detect\n", ret); - return ret; -} - -static void twl_mmc_cleanup(struct device *dev) -{ - struct omap_mmc_platform_data *mmc = dev->platform_data; - int i; - - gpio_free(mmc->slots[0].switch_pin); - for(i = 0; i < ARRAY_SIZE(hsmmc); i++) { - regulator_put(hsmmc[i].vcc); - regulator_put(hsmmc[i].vcc_aux); - } -} - -#ifdef CONFIG_PM - -static int twl_mmc_suspend(struct device *dev, int slot) -{ - struct omap_mmc_platform_data *mmc = dev->platform_data; - - disable_irq(mmc->slots[0].card_detect_irq); - return 0; -} - -static int twl_mmc_resume(struct device *dev, int slot) -{ - struct omap_mmc_platform_data *mmc = dev->platform_data; - - enable_irq(mmc->slots[0].card_detect_irq); - return 0; -} - -#else -#define twl_mmc_suspend NULL -#define twl_mmc_resume NULL -#endif - -#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) - -static int twl4030_mmc_get_context_loss(struct device *dev) -{ - /* FIXME: PM DPS not implemented yet */ - return 0; -} - -#else -#define twl4030_mmc_get_context_loss NULL -#endif - -static int twl_mmc1_set_power(struct device *dev, int slot, int power_on, - int vdd) -{ - u32 reg, prog_io; - int ret = 0; - struct twl_mmc_controller *c = &hsmmc[0]; - struct omap_mmc_platform_data *mmc = dev->platform_data; - - /* - * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the - * card with Vcc regulator (from twl4030 or whatever). OMAP has both - * 1.8V and 3.0V modes, controlled by the PBIAS register. - * - * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which - * is most naturally TWL VSIM; those pins also use PBIAS. - * - * FIXME handle VMMC1A as needed ... - */ - if (power_on) { - if (cpu_is_omap2430()) { - reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1); - if ((1 << vdd) >= MMC_VDD_30_31) - reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE; - else - reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE; - omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1); - } - - if (mmc->slots[0].internal_clock) { - reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); - reg |= OMAP2_MMCSDIO1ADPCLKISEL; - omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0); - } - - reg = omap_ctrl_readl(control_pbias_offset); - if (cpu_is_omap3630()) { - /* Set MMC I/O to 52Mhz */ - prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); - prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL; - omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1); - } else { - reg |= OMAP2_PBIASSPEEDCTRL0; - } - reg &= ~OMAP2_PBIASLITEPWRDNZ0; - omap_ctrl_writel(reg, control_pbias_offset); - - ret = mmc_regulator_set_ocr(c->vcc, vdd); - - /* 100ms delay required for PBIAS configuration */ - msleep(100); - reg = omap_ctrl_readl(control_pbias_offset); - reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0); - if ((1 << vdd) <= MMC_VDD_165_195) - reg &= ~OMAP2_PBIASLITEVMODE0; - else - reg |= OMAP2_PBIASLITEVMODE0; - omap_ctrl_writel(reg, control_pbias_offset); - } else { - reg = omap_ctrl_readl(control_pbias_offset); - reg &= ~OMAP2_PBIASLITEPWRDNZ0; - omap_ctrl_writel(reg, control_pbias_offset); - - ret = mmc_regulator_set_ocr(c->vcc, 0); - - /* 100ms delay required for PBIAS configuration */ - msleep(100); - reg = omap_ctrl_readl(control_pbias_offset); - reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 | - OMAP2_PBIASLITEVMODE0); - omap_ctrl_writel(reg, control_pbias_offset); - } - - return ret; -} - -static int twl_mmc23_set_power(struct device *dev, int slot, int power_on, int vdd) -{ - int ret = 0; - struct twl_mmc_controller *c = NULL; - struct omap_mmc_platform_data *mmc = dev->platform_data; - int i; - - for (i = 1; i < ARRAY_SIZE(hsmmc); i++) { - if (mmc == hsmmc[i].mmc) { - c = &hsmmc[i]; - break; - } - } - - if (c == NULL) - return -ENODEV; - - /* If we don't see a Vcc regulator, assume it's a fixed - * voltage always-on regulator. - */ - if (!c->vcc) - return 0; - - /* - * Assume Vcc regulator is used only to power the card ... OMAP - * VDDS is used to power the pins, optionally with a transceiver to - * support cards using voltages other than VDDS (1.8V nominal). When a - * transceiver is used, DAT3..7 are muxed as transceiver control pins. - * - * In some cases this regulator won't support enable/disable; - * e.g. it's a fixed rail for a WLAN chip. - * - * In other cases vcc_aux switches interface power. Example, for - * eMMC cards it represents VccQ. Sometimes transceivers or SDIO - * chips/cards need an interface voltage rail too. - */ - if (power_on) { - /* only MMC2 supports a CLKIN */ - if (mmc->slots[0].internal_clock) { - u32 reg; - - reg = omap_ctrl_readl(control_devconf1_offset); - reg |= OMAP2_MMCSDIO2ADPCLKISEL; - omap_ctrl_writel(reg, control_devconf1_offset); - } - ret = mmc_regulator_set_ocr(c->vcc, vdd); - /* enable interface voltage rail, if needed */ - if (ret == 0 && c->vcc_aux) { - ret = regulator_enable(c->vcc_aux); - if (ret < 0) - ret = mmc_regulator_set_ocr(c->vcc, 0); - } - } else { - if (c->vcc_aux && (ret = regulator_is_enabled(c->vcc_aux)) > 0) - ret = regulator_disable(c->vcc_aux); - if (ret == 0) - ret = mmc_regulator_set_ocr(c->vcc, 0); - } - - return ret; -} - -static int twl_mmc1_set_sleep(struct device *dev, int slot, int sleep, int vdd, - int cardsleep) -{ - struct twl_mmc_controller *c = &hsmmc[0]; - int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; - - return regulator_set_mode(c->vcc, mode); -} - -static int twl_mmc23_set_sleep(struct device *dev, int slot, int sleep, int vdd, - int cardsleep) -{ - struct twl_mmc_controller *c = NULL; - struct omap_mmc_platform_data *mmc = dev->platform_data; - int i, err, mode; - - for (i = 1; i < ARRAY_SIZE(hsmmc); i++) { - if (mmc == hsmmc[i].mmc) { - c = &hsmmc[i]; - break; - } - } - - if (c == NULL) - return -ENODEV; - - /* - * If we don't see a Vcc regulator, assume it's a fixed - * voltage always-on regulator. - */ - if (!c->vcc) - return 0; - - mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; - - if (!c->vcc_aux) - return regulator_set_mode(c->vcc, mode); - - if (cardsleep) { - /* VCC can be turned off if card is asleep */ - struct regulator *vcc_aux = c->vcc_aux; - - c->vcc_aux = NULL; - if (sleep) - err = twl_mmc23_set_power(dev, slot, 0, 0); - else - err = twl_mmc23_set_power(dev, slot, 1, vdd); - c->vcc_aux = vcc_aux; - } else - err = regulator_set_mode(c->vcc, mode); - if (err) - return err; - return regulator_set_mode(c->vcc_aux, mode); -} - -static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; - -void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers) -{ - struct twl4030_hsmmc_info *c; - int nr_hsmmc = ARRAY_SIZE(hsmmc_data); - int i; - - if (cpu_is_omap2430()) { - control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; - control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; - nr_hsmmc = 2; - } else { - control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; - control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; - } - - for (c = controllers; c->mmc; c++) { - struct twl_mmc_controller *twl = hsmmc + c->mmc - 1; - struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; - - if (!c->mmc || c->mmc > nr_hsmmc) { - pr_debug("MMC%d: no such controller\n", c->mmc); - continue; - } - if (mmc) { - pr_debug("MMC%d: already configured\n", c->mmc); - continue; - } - - mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL); - if (!mmc) { - pr_err("Cannot allocate memory for mmc device!\n"); - goto done; - } - - if (c->name) - strncpy(twl->name, c->name, HSMMC_NAME_LEN); - else - snprintf(twl->name, ARRAY_SIZE(twl->name), - "mmc%islot%i", c->mmc, 1); - mmc->slots[0].name = twl->name; - mmc->nr_slots = 1; - mmc->slots[0].wires = c->wires; - mmc->slots[0].internal_clock = !c->ext_clock; - mmc->dma_mask = 0xffffffff; - mmc->init = twl_mmc_late_init; - - /* note: twl4030 card detect GPIOs can disable VMMCx ... */ - if (gpio_is_valid(c->gpio_cd)) { - mmc->cleanup = twl_mmc_cleanup; - mmc->suspend = twl_mmc_suspend; - mmc->resume = twl_mmc_resume; - - mmc->slots[0].switch_pin = c->gpio_cd; - mmc->slots[0].card_detect_irq = gpio_to_irq(c->gpio_cd); - if (c->cover_only) - mmc->slots[0].get_cover_state = twl_mmc_get_cover_state; - else - mmc->slots[0].card_detect = twl_mmc_card_detect; - } else - mmc->slots[0].switch_pin = -EINVAL; - - mmc->get_context_loss_count = - twl4030_mmc_get_context_loss; - - /* write protect normally uses an OMAP gpio */ - if (gpio_is_valid(c->gpio_wp)) { - gpio_request(c->gpio_wp, "mmc_wp"); - gpio_direction_input(c->gpio_wp); - - mmc->slots[0].gpio_wp = c->gpio_wp; - mmc->slots[0].get_ro = twl_mmc_get_ro; - } else - mmc->slots[0].gpio_wp = -EINVAL; - - if (c->nonremovable) - mmc->slots[0].nonremovable = 1; - - if (c->power_saving) - mmc->slots[0].power_saving = 1; - - /* NOTE: MMC slots should have a Vcc regulator set up. - * This may be from a TWL4030-family chip, another - * controllable regulator, or a fixed supply. - * - * temporary HACK: ocr_mask instead of fixed supply - */ - mmc->slots[0].ocr_mask = c->ocr_mask; - - switch (c->mmc) { - case 1: - /* on-chip level shifting via PBIAS0/PBIAS1 */ - mmc->slots[0].set_power = twl_mmc1_set_power; - mmc->slots[0].set_sleep = twl_mmc1_set_sleep; - - /* Omap3630 HSMMC1 supports only 4-bit */ - if (cpu_is_omap3630() && c->wires > 4) { - c->wires = 4; - mmc->slots[0].wires = c->wires; - } - break; - case 2: - if (c->ext_clock) - c->transceiver = 1; - if (c->transceiver && c->wires > 4) - c->wires = 4; - /* FALLTHROUGH */ - case 3: - /* off-chip level shifting, or none */ - mmc->slots[0].set_power = twl_mmc23_set_power; - mmc->slots[0].set_sleep = twl_mmc23_set_sleep; - break; - default: - pr_err("MMC%d configuration not supported!\n", c->mmc); - kfree(mmc); - continue; - } - hsmmc_data[c->mmc - 1] = mmc; - } - - omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC); - - /* pass the device nodes back to board setup code */ - for (c = controllers; c->mmc; c++) { - struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; - - if (!c->mmc || c->mmc > nr_hsmmc) - continue; - c->dev = mmc->dev; - } - -done: - for (i = 0; i < nr_hsmmc; i++) - kfree(hsmmc_data[i]); -} - -#endif diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 5fef73f4743d..b4ca84ee0a95 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -75,7 +75,7 @@ void omap_mux_write_array(struct omap_board_mux *board_mux) } } -#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_OMAP_MUX) +#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_OMAP_MUX) static struct omap_mux_cfg arch_mux_cfg; @@ -369,7 +369,7 @@ int __init omap2_mux_init(void) /*----------------------------------------------------------------------------*/ -#ifdef CONFIG_ARCH_OMAP34XX +#ifdef CONFIG_ARCH_OMAP3 static LIST_HEAD(muxmodes); static DEFINE_MUTEX(muxmode_mutex); @@ -983,6 +983,38 @@ static void __init omap_mux_init_list(struct omap_mux *superset) } } +#ifdef CONFIG_OMAP_MUX + +static void omap_mux_init_package(struct omap_mux *superset, + struct omap_mux *package_subset, + struct omap_ball *package_balls) +{ + if (package_subset) + omap_mux_package_fixup(package_subset, superset); + if (package_balls) + omap_mux_package_init_balls(package_balls, superset); +} + +static void omap_mux_init_signals(struct omap_board_mux *board_mux) +{ + omap_mux_set_cmdline_signals(); + omap_mux_write_array(board_mux); +} + +#else + +static void omap_mux_init_package(struct omap_mux *superset, + struct omap_mux *package_subset, + struct omap_ball *package_balls) +{ +} + +static void omap_mux_init_signals(struct omap_board_mux *board_mux) +{ +} + +#endif + int __init omap_mux_init(u32 mux_pbase, u32 mux_size, struct omap_mux *superset, struct omap_mux *package_subset, @@ -999,22 +1031,12 @@ int __init omap_mux_init(u32 mux_pbase, u32 mux_size, return -ENODEV; } -#ifdef CONFIG_OMAP_MUX - if (package_subset) - omap_mux_package_fixup(package_subset, superset); - if (package_balls) - omap_mux_package_init_balls(package_balls, superset); -#endif - + omap_mux_init_package(superset, package_subset, package_balls); omap_mux_init_list(superset); - -#ifdef CONFIG_OMAP_MUX - omap_mux_set_cmdline_signals(); - omap_mux_write_array(board_mux); -#endif + omap_mux_init_signals(board_mux); return 0; } -#endif /* CONFIG_ARCH_OMAP34XX */ +#endif /* CONFIG_ARCH_OMAP3 */ diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h index f8c2e7a8f063..480abc56e605 100644 --- a/arch/arm/mach-omap2/mux.h +++ b/arch/arm/mach-omap2/mux.h @@ -102,7 +102,7 @@ struct omap_board_mux { u16 value; }; -#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_ARCH_OMAP3) /** * omap_mux_init_gpio - initialize a signal based on the GPIO number diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 478ae585ca39..70912d1c71e0 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -299,15 +299,14 @@ static int _disable_wakeup(struct omap_hwmod *oh) * be accessed by the IVA, there should be a sleepdep between the IVA * initiator and the module). Only applies to modules in smart-idle * mode. Returns -EINVAL upon error or passes along - * pwrdm_add_sleepdep() value upon success. + * clkdm_add_sleepdep() value upon success. */ static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) { if (!oh->_clk) return -EINVAL; - return pwrdm_add_sleepdep(oh->_clk->clkdm->pwrdm.ptr, - init_oh->_clk->clkdm->pwrdm.ptr); + return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); } /** @@ -320,15 +319,14 @@ static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) * be accessed by the IVA, there should be no sleepdep between the IVA * initiator and the module). Only applies to modules in smart-idle * mode. Returns -EINVAL upon error or passes along - * pwrdm_add_sleepdep() value upon success. + * clkdm_del_sleepdep() value upon success. */ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) { if (!oh->_clk) return -EINVAL; - return pwrdm_del_sleepdep(oh->_clk->clkdm->pwrdm.ptr, - init_oh->_clk->clkdm->pwrdm.ptr); + return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); } /** @@ -994,6 +992,23 @@ void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs) __raw_writel(v, oh->_rt_va + reg_offs); } +int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode) +{ + u32 v; + int retval = 0; + + if (!oh) + return -EINVAL; + + v = oh->_sysc_cache; + + retval = _set_slave_idlemode(oh, idlemode, &v); + if (!retval) + _write_sysconfig(v, oh); + + return retval; +} + /** * omap_hwmod_register - register a struct omap_hwmod * @oh: struct omap_hwmod * diff --git a/arch/arm/mach-omap2/omap_hwmod_34xx.h b/arch/arm/mach-omap2/omap_hwmod_34xx.h index b6076b9c364e..2e629dcb2fb1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_34xx.h +++ b/arch/arm/mach-omap2/omap_hwmod_34xx.h @@ -12,7 +12,7 @@ #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD34XX_H #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD34XX_H -#ifdef CONFIG_ARCH_OMAP34XX +#ifdef CONFIG_ARCH_OMAP3 #include <plat/omap_hwmod.h> #include <mach/irqs.h> diff --git a/arch/arm/mach-omap2/opp2xxx.h b/arch/arm/mach-omap2/opp2xxx.h index ed6df04e2f29..38b730550506 100644 --- a/arch/arm/mach-omap2/opp2xxx.h +++ b/arch/arm/mach-omap2/opp2xxx.h @@ -417,7 +417,12 @@ struct prcm_config { extern const struct prcm_config omap2420_rate_table[]; + +#ifdef CONFIG_ARCH_OMAP2430 extern const struct prcm_config omap2430_rate_table[]; +#else +#define omap2430_rate_table NULL +#endif extern const struct prcm_config *rate_table; extern const struct prcm_config *curr_prcm_set; diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index a0866268aa41..0ce356f351a3 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -67,9 +67,9 @@ void omap2_pm_dump(int mode, int resume, unsigned int us) #if 0 /* MPU */ DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET); - DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL); - DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL); - DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST); + DUMP_CM_MOD_REG(MPU_MOD, OMAP2_CM_CLKSTCTRL); + DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTCTRL); + DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTST); DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP); #endif #if 0 @@ -93,7 +93,7 @@ void omap2_pm_dump(int mode, int resume, unsigned int us) DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN); DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN); DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE); - DUMP_PRM_MOD_REG(CORE_MOD, PM_PWSTST); + DUMP_PRM_MOD_REG(CORE_MOD, OMAP2_PM_PWSTST); #endif #if 0 /* DSP */ @@ -103,11 +103,11 @@ void omap2_pm_dump(int mode, int resume, unsigned int us) DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST); DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE); DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL); - DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL); - DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL); - DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST); - DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL); - DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST); + DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_CM_CLKSTCTRL); + DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTCTRL); + DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTST); + DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTCTRL); + DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTST); } #endif } else { @@ -577,7 +577,7 @@ static int __init pm_dbg_init(void) (void) debugfs_create_file("time", S_IRUGO, d, (void *)DEBUG_FILE_TIMERS, &debug_fops); - pwrdm_for_each_nolock(pwrdms_setup, (void *)d); + pwrdm_for_each(pwrdms_setup, (void *)d); pm_dbg_dir = debugfs_create_dir("registers", d); if (IS_ERR(pm_dbg_dir)) diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index cba05b9f041f..374299ea7ade 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -57,11 +57,8 @@ static void (*omap2_sram_idle)(void); static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl, void __iomem *sdrc_power); -static struct powerdomain *mpu_pwrdm; -static struct powerdomain *core_pwrdm; - -static struct clockdomain *dsp_clkdm; -static struct clockdomain *gfx_clkdm; +static struct powerdomain *mpu_pwrdm, *core_pwrdm; +static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm; static struct clk *osc_ck, *emul_ck; @@ -219,11 +216,12 @@ static void omap2_enter_mpu_retention(void) /* Try to enter MPU retention */ prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | OMAP_LOGICRETSTATE, - MPU_MOD, PM_PWSTCTRL); + MPU_MOD, OMAP2_PM_PWSTCTRL); } else { /* Block MPU retention */ - prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL); + prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, + OMAP2_PM_PWSTCTRL); only_idle = 1; } @@ -333,9 +331,17 @@ static struct platform_suspend_ops omap_pm_ops = { .valid = suspend_valid_only_mem, }; -static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm, void *unused) +/* XXX This function should be shareable between OMAP2xxx and OMAP3 */ +static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) { - omap2_clkdm_allow_idle(clkdm); + clkdm_clear_all_wkdeps(clkdm); + clkdm_clear_all_sleepdeps(clkdm); + + if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) + omap2_clkdm_allow_idle(clkdm); + else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && + atomic_read(&clkdm->usecount) == 0) + omap2_clkdm_sleep(clkdm); return 0; } @@ -348,14 +354,6 @@ static void __init prcm_setup_regs(void) prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD, OMAP2_PRCM_SYSCONFIG_OFFSET); - /* Set all domain wakeup dependencies */ - prm_write_mod_reg(OMAP_EN_WKUP_MASK, MPU_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP); - prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); - prm_write_mod_reg(0, CORE_MOD, PM_WKDEP); - if (cpu_is_omap2430()) - prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP); - /* * Set CORE powerdomain memory banks to retain their contents * during RETENTION @@ -384,8 +382,12 @@ static void __init prcm_setup_regs(void) pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); omap2_clkdm_sleep(gfx_clkdm); - /* Enable clockdomain hardware-supervised control for all clkdms */ - clkdm_for_each(_pm_clkdm_enable_hwsup, NULL); + /* + * Clear clockdomain wakeup dependencies and enable + * hardware-supervised idle for all clkdms + */ + clkdm_for_each(clkdms_setup, NULL); + clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); /* Enable clock autoidle for all domains */ cm_write_mod_reg(OMAP24XX_AUTO_CAM | @@ -481,7 +483,7 @@ static int __init omap2_pm_init(void) l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET); printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); - /* Look up important powerdomains, clockdomains */ + /* Look up important powerdomains */ mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); if (!mpu_pwrdm) @@ -491,9 +493,19 @@ static int __init omap2_pm_init(void) if (!core_pwrdm) pr_err("PM: core_pwrdm not found\n"); + /* Look up important clockdomains */ + + mpu_clkdm = clkdm_lookup("mpu_clkdm"); + if (!mpu_clkdm) + pr_err("PM: mpu_clkdm not found\n"); + + wkup_clkdm = clkdm_lookup("wkup_clkdm"); + if (!wkup_clkdm) + pr_err("PM: wkup_clkdm not found\n"); + dsp_clkdm = clkdm_lookup("dsp_clkdm"); if (!dsp_clkdm) - pr_err("PM: mpu_clkdm not found\n"); + pr_err("PM: dsp_clkdm not found\n"); gfx_clkdm = clkdm_lookup("gfx_clkdm"); if (!gfx_clkdm) diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 910a7acf542d..5087b153b093 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -685,7 +685,7 @@ static void __init omap3_iva_idle(void) prm_write_mod_reg(OMAP3430_RST1_IVA2 | OMAP3430_RST2_IVA2 | OMAP3430_RST3_IVA2, - OMAP3430_IVA2_MOD, RM_RSTCTRL); + OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); /* Enable IVA2 clock */ cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2, @@ -696,7 +696,7 @@ static void __init omap3_iva_idle(void) OMAP343X_CONTROL_IVA2_BOOTMOD); /* Un-reset IVA2 */ - prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL); + prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); /* Disable IVA2 clock */ cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); @@ -705,7 +705,7 @@ static void __init omap3_iva_idle(void) prm_write_mod_reg(OMAP3430_RST1_IVA2 | OMAP3430_RST2_IVA2 | OMAP3430_RST3_IVA2, - OMAP3430_IVA2_MOD, RM_RSTCTRL); + OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); } static void __init omap3_d2d_idle(void) @@ -728,8 +728,8 @@ static void __init omap3_d2d_idle(void) /* reset modem */ prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON | OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST, - CORE_MOD, RM_RSTCTRL); - prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL); + CORE_MOD, OMAP2_RM_RSTCTRL); + prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); } static void __init prcm_setup_regs(void) @@ -916,13 +916,13 @@ static void __init prcm_setup_regs(void) prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); /* Clear any pending 'reset' flags */ - prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); + prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); + prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); + prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); + prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); + prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); + prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); + prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); /* Clear any pending PRCM interrupts */ prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); @@ -998,6 +998,9 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) */ static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) { + clkdm_clear_all_wkdeps(clkdm); + clkdm_clear_all_sleepdeps(clkdm); + if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) omap2_clkdm_allow_idle(clkdm); else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && @@ -1018,6 +1021,7 @@ void omap_push_sram_idle(void) static int __init omap3_pm_init(void) { struct power_state *pwrst, *tmp; + struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm; int ret; if (!cpu_is_omap34xx()) @@ -1057,6 +1061,11 @@ static int __init omap3_pm_init(void) core_pwrdm = pwrdm_lookup("core_pwrdm"); cam_pwrdm = pwrdm_lookup("cam_pwrdm"); + neon_clkdm = clkdm_lookup("neon_clkdm"); + mpu_clkdm = clkdm_lookup("mpu_clkdm"); + per_clkdm = clkdm_lookup("per_clkdm"); + core_clkdm = clkdm_lookup("core_clkdm"); + omap_push_sram_idle(); #ifdef CONFIG_SUSPEND suspend_set_ops(&omap_pm_ops); @@ -1065,14 +1074,14 @@ static int __init omap3_pm_init(void) pm_idle = omap3_pm_idle; omap3_idle_init(); - pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm); + clkdm_add_wkdep(neon_clkdm, mpu_clkdm); /* * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for * IO-pad wakeup. Otherwise it will unnecessarily waste power * waking up PER with every CORE wakeup - see * http://marc.info/?l=linux-omap&m=121852150710062&w=2 */ - pwrdm_add_wkdep(per_pwrdm, core_pwrdm); + clkdm_add_wkdep(per_clkdm, core_clkdm); if (omap_type() != OMAP2_DEVICE_TYPE_GP) { omap3_secure_ram_storage = diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 26b3f3ee82a3..dc03289d5dea 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -2,10 +2,12 @@ * OMAP powerdomain control * * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2008 Nokia Corporation + * Copyright (C) 2007-2009 Nokia Corporation * * Written by Paul Walmsley * + * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com> + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -26,12 +28,15 @@ #include "cm.h" #include "cm-regbits-34xx.h" +#include "cm-regbits-44xx.h" #include "prm.h" #include "prm-regbits-34xx.h" +#include "prm-regbits-44xx.h" #include <plat/cpu.h> #include <plat/powerdomain.h> #include <plat/clockdomain.h> +#include <plat/prcm.h> #include "pm.h" @@ -40,28 +45,42 @@ enum { PWRDM_STATE_PREV, }; -/* pwrdm_list contains all registered struct powerdomains */ -static LIST_HEAD(pwrdm_list); +/* Variable holding value of the CPU dependent PWRSTCTRL Register Offset */ +static u16 pwrstctrl_reg_offs; -/* - * pwrdm_rwlock protects pwrdm_list add and del ops - also reused to - * protect pwrdm_clkdms[] during clkdm add/del ops +/* Variable holding value of the CPU dependent PWRSTST Register Offset */ +static u16 pwrstst_reg_offs; + +/* OMAP3 and OMAP4 specific register bit initialisations + * Notice that the names here are not according to each power + * domain but the bit mapping used applies to all of them */ -static DEFINE_RWLOCK(pwrdm_rwlock); +/* OMAP3 and OMAP4 Memory Onstate Masks (common across all power domains) */ +#define OMAP_MEM0_ONSTATE_MASK OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK +#define OMAP_MEM1_ONSTATE_MASK OMAP3430_L1FLATMEMONSTATE_MASK +#define OMAP_MEM2_ONSTATE_MASK OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK +#define OMAP_MEM3_ONSTATE_MASK OMAP3430_L2FLATMEMONSTATE_MASK +#define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK -/* Private functions */ +/* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */ +#define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE +#define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE +#define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE +#define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE +#define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK -static u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) -{ - u32 v; +/* OMAP3 and OMAP4 Memory Status bits */ +#define OMAP_MEM0_STATEST_MASK OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK +#define OMAP_MEM1_STATEST_MASK OMAP3430_L1FLATMEMSTATEST_MASK +#define OMAP_MEM2_STATEST_MASK OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK +#define OMAP_MEM3_STATEST_MASK OMAP3430_L2FLATMEMSTATEST_MASK +#define OMAP_MEM4_STATEST_MASK OMAP4430_OCP_NRET_BANK_STATEST_MASK - v = prm_read_mod_reg(domain, idx); - v &= mask; - v >>= __ffs(mask); +/* pwrdm_list contains all registered struct powerdomains */ +static LIST_HEAD(pwrdm_list); - return v; -} +/* Private functions */ static struct powerdomain *_pwrdm_lookup(const char *name) { @@ -79,32 +98,40 @@ static struct powerdomain *_pwrdm_lookup(const char *name) return pwrdm; } -/* _pwrdm_deps_lookup - look up the specified powerdomain in a pwrdm list */ -static struct powerdomain *_pwrdm_deps_lookup(struct powerdomain *pwrdm, - struct pwrdm_dep *deps) +/** + * _pwrdm_register - register a powerdomain + * @pwrdm: struct powerdomain * to register + * + * Adds a powerdomain to the internal powerdomain list. Returns + * -EINVAL if given a null pointer, -EEXIST if a powerdomain is + * already registered by the provided name, or 0 upon success. + */ +static int _pwrdm_register(struct powerdomain *pwrdm) { - struct pwrdm_dep *pd; + int i; - if (!pwrdm || !deps || !omap_chip_is(pwrdm->omap_chip)) - return ERR_PTR(-EINVAL); + if (!pwrdm) + return -EINVAL; - for (pd = deps; pd->pwrdm_name; pd++) { + if (!omap_chip_is(pwrdm->omap_chip)) + return -EINVAL; - if (!omap_chip_is(pd->omap_chip)) - continue; + if (_pwrdm_lookup(pwrdm->name)) + return -EEXIST; - if (!pd->pwrdm && pd->pwrdm_name) - pd->pwrdm = pwrdm_lookup(pd->pwrdm_name); + list_add(&pwrdm->node, &pwrdm_list); - if (pd->pwrdm == pwrdm) - break; + /* Initialize the powerdomain's state counter */ + for (i = 0; i < PWRDM_MAX_PWRSTS; i++) + pwrdm->state_counter[i] = 0; - } + pwrdm_wait_transition(pwrdm); + pwrdm->state = pwrdm_read_pwrst(pwrdm); + pwrdm->state_counter[pwrdm->state] = 1; - if (!pd->pwrdm_name) - return ERR_PTR(-ENOENT); + pr_debug("powerdomain: registered %s\n", pwrdm->name); - return pd->pwrdm; + return 0; } static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag) @@ -154,134 +181,71 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused) return 0; } -static __init void _pwrdm_setup(struct powerdomain *pwrdm) -{ - int i; - - for (i = 0; i < PWRDM_MAX_PWRSTS; i++) - pwrdm->state_counter[i] = 0; - - pwrdm_wait_transition(pwrdm); - pwrdm->state = pwrdm_read_pwrst(pwrdm); - pwrdm->state_counter[pwrdm->state] = 1; - -} - /* Public functions */ /** * pwrdm_init - set up the powerdomain layer + * @pwrdm_list: array of struct powerdomain pointers to register * - * Loop through the list of powerdomains, registering all that are - * available on the current CPU. If pwrdm_list is supplied and not - * null, all of the referenced powerdomains will be registered. No - * return value. + * Loop through the array of powerdomains @pwrdm_list, registering all + * that are available on the current CPU. If pwrdm_list is supplied + * and not null, all of the referenced powerdomains will be + * registered. No return value. XXX pwrdm_list is not really a + * "list"; it is an array. Rename appropriately. */ void pwrdm_init(struct powerdomain **pwrdm_list) { struct powerdomain **p = NULL; - if (pwrdm_list) { - for (p = pwrdm_list; *p; p++) { - pwrdm_register(*p); - _pwrdm_setup(*p); - } + if (cpu_is_omap24xx() | cpu_is_omap34xx()) { + pwrstctrl_reg_offs = OMAP2_PM_PWSTCTRL; + pwrstst_reg_offs = OMAP2_PM_PWSTST; + } else if (cpu_is_omap44xx()) { + pwrstctrl_reg_offs = OMAP4_PM_PWSTCTRL; + pwrstst_reg_offs = OMAP4_PM_PWSTST; + } else { + printk(KERN_ERR "Power Domain struct not supported for " \ + "this CPU\n"); + return; } -} -/** - * pwrdm_register - register a powerdomain - * @pwrdm: struct powerdomain * to register - * - * Adds a powerdomain to the internal powerdomain list. Returns - * -EINVAL if given a null pointer, -EEXIST if a powerdomain is - * already registered by the provided name, or 0 upon success. - */ -int pwrdm_register(struct powerdomain *pwrdm) -{ - unsigned long flags; - int ret = -EINVAL; - - if (!pwrdm) - return -EINVAL; - - if (!omap_chip_is(pwrdm->omap_chip)) - return -EINVAL; - - write_lock_irqsave(&pwrdm_rwlock, flags); - if (_pwrdm_lookup(pwrdm->name)) { - ret = -EEXIST; - goto pr_unlock; + if (pwrdm_list) { + for (p = pwrdm_list; *p; p++) + _pwrdm_register(*p); } - - list_add(&pwrdm->node, &pwrdm_list); - - pr_debug("powerdomain: registered %s\n", pwrdm->name); - ret = 0; - -pr_unlock: - write_unlock_irqrestore(&pwrdm_rwlock, flags); - - return ret; -} - -/** - * pwrdm_unregister - unregister a powerdomain - * @pwrdm: struct powerdomain * to unregister - * - * Removes a powerdomain from the internal powerdomain list. Returns - * -EINVAL if pwrdm argument is NULL. - */ -int pwrdm_unregister(struct powerdomain *pwrdm) -{ - unsigned long flags; - - if (!pwrdm) - return -EINVAL; - - write_lock_irqsave(&pwrdm_rwlock, flags); - list_del(&pwrdm->node); - write_unlock_irqrestore(&pwrdm_rwlock, flags); - - pr_debug("powerdomain: unregistered %s\n", pwrdm->name); - - return 0; } /** * pwrdm_lookup - look up a powerdomain by name, return a pointer * @name: name of powerdomain * - * Find a registered powerdomain by its name. Returns a pointer to the - * struct powerdomain if found, or NULL otherwise. + * Find a registered powerdomain by its name @name. Returns a pointer + * to the struct powerdomain if found, or NULL otherwise. */ struct powerdomain *pwrdm_lookup(const char *name) { struct powerdomain *pwrdm; - unsigned long flags; if (!name) return NULL; - read_lock_irqsave(&pwrdm_rwlock, flags); pwrdm = _pwrdm_lookup(name); - read_unlock_irqrestore(&pwrdm_rwlock, flags); return pwrdm; } /** - * pwrdm_for_each_nolock - call function on each registered clockdomain + * pwrdm_for_each - call function on each registered clockdomain * @fn: callback function * * - * Call the supplied function for each registered powerdomain. The - * callback function can return anything but 0 to bail out early from - * the iterator. Returns the last return value of the callback function, which - * should be 0 for success or anything else to indicate failure; or -EINVAL if - * the function pointer is null. + * Call the supplied function @fn for each registered powerdomain. + * The callback function @fn can return anything but 0 to bail out + * early from the iterator. Returns the last return value of the + * callback function, which should be 0 for success or anything else + * to indicate failure; or -EINVAL if the function pointer is null. */ -int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user), - void *user) +int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), + void *user) { struct powerdomain *temp_pwrdm; int ret = 0; @@ -299,40 +263,17 @@ int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user), } /** - * pwrdm_for_each - call function on each registered clockdomain - * @fn: callback function * - * - * This function is the same as 'pwrdm_for_each_nolock()', but keeps the - * &pwrdm_rwlock locked for reading, so no powerdomain structure manipulation - * functions should be called from the callback, although hardware powerdomain - * control functions are fine. - */ -int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), - void *user) -{ - unsigned long flags; - int ret; - - read_lock_irqsave(&pwrdm_rwlock, flags); - ret = pwrdm_for_each_nolock(fn, user); - read_unlock_irqrestore(&pwrdm_rwlock, flags); - - return ret; -} - -/** * pwrdm_add_clkdm - add a clockdomain to a powerdomain * @pwrdm: struct powerdomain * to add the clockdomain to * @clkdm: struct clockdomain * to associate with a powerdomain * - * Associate the clockdomain 'clkdm' with a powerdomain 'pwrdm'. This + * Associate the clockdomain @clkdm with a powerdomain @pwrdm. This * enables the use of pwrdm_for_each_clkdm(). Returns -EINVAL if * presented with invalid pointers; -ENOMEM if memory could not be allocated; * or 0 upon success. */ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm) { - unsigned long flags; int i; int ret = -EINVAL; @@ -342,8 +283,6 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm) pr_debug("powerdomain: associating clockdomain %s with powerdomain " "%s\n", clkdm->name, pwrdm->name); - write_lock_irqsave(&pwrdm_rwlock, flags); - for (i = 0; i < PWRDM_MAX_CLKDMS; i++) { if (!pwrdm->pwrdm_clkdms[i]) break; @@ -368,8 +307,6 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm) ret = 0; pac_exit: - write_unlock_irqrestore(&pwrdm_rwlock, flags); - return ret; } @@ -378,14 +315,13 @@ pac_exit: * @pwrdm: struct powerdomain * to add the clockdomain to * @clkdm: struct clockdomain * to associate with a powerdomain * - * Dissociate the clockdomain 'clkdm' from the powerdomain - * 'pwrdm'. Returns -EINVAL if presented with invalid pointers; - * -ENOENT if the clkdm was not associated with the powerdomain, or 0 - * upon success. + * Dissociate the clockdomain @clkdm from the powerdomain + * @pwrdm. Returns -EINVAL if presented with invalid pointers; -ENOENT + * if @clkdm was not associated with the powerdomain, or 0 upon + * success. */ int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm) { - unsigned long flags; int ret = -EINVAL; int i; @@ -395,8 +331,6 @@ int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm) pr_debug("powerdomain: dissociating clockdomain %s from powerdomain " "%s\n", clkdm->name, pwrdm->name); - write_lock_irqsave(&pwrdm_rwlock, flags); - for (i = 0; i < PWRDM_MAX_CLKDMS; i++) if (pwrdm->pwrdm_clkdms[i] == clkdm) break; @@ -413,8 +347,6 @@ int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm) ret = 0; pdc_exit: - write_unlock_irqrestore(&pwrdm_rwlock, flags); - return ret; } @@ -423,259 +355,34 @@ pdc_exit: * @pwrdm: struct powerdomain * to iterate over * @fn: callback function * * - * Call the supplied function for each clockdomain in the powerdomain - * 'pwrdm'. The callback function can return anything but 0 to bail - * out early from the iterator. The callback function is called with - * the pwrdm_rwlock held for reading, so no powerdomain structure - * manipulation functions should be called from the callback, although - * hardware powerdomain control functions are fine. Returns -EINVAL - * if presented with invalid pointers; or passes along the last return - * value of the callback function, which should be 0 for success or - * anything else to indicate failure. + * Call the supplied function @fn for each clockdomain in the powerdomain + * @pwrdm. The callback function can return anything but 0 to bail + * out early from the iterator. Returns -EINVAL if presented with + * invalid pointers; or passes along the last return value of the + * callback function, which should be 0 for success or anything else + * to indicate failure. */ int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, int (*fn)(struct powerdomain *pwrdm, struct clockdomain *clkdm)) { - unsigned long flags; int ret = 0; int i; if (!fn) return -EINVAL; - read_lock_irqsave(&pwrdm_rwlock, flags); - for (i = 0; i < PWRDM_MAX_CLKDMS && !ret; i++) ret = (*fn)(pwrdm, pwrdm->pwrdm_clkdms[i]); - read_unlock_irqrestore(&pwrdm_rwlock, flags); - return ret; } - -/** - * pwrdm_add_wkdep - add a wakeup dependency from pwrdm2 to pwrdm1 - * @pwrdm1: wake this struct powerdomain * up (dependent) - * @pwrdm2: when this struct powerdomain * wakes up (source) - * - * When the powerdomain represented by pwrdm2 wakes up (due to an - * interrupt), wake up pwrdm1. Implemented in hardware on the OMAP, - * this feature is designed to reduce wakeup latency of the dependent - * powerdomain. Returns -EINVAL if presented with invalid powerdomain - * pointers, -ENOENT if pwrdm2 cannot wake up pwrdm1 in hardware, or - * 0 upon success. - */ -int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) -{ - struct powerdomain *p; - - if (!pwrdm1) - return -EINVAL; - - p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->wkdep_srcs); - if (IS_ERR(p)) { - pr_debug("powerdomain: hardware cannot set/clear wake up of " - "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name); - return PTR_ERR(p); - } - - pr_debug("powerdomain: hardware will wake up %s when %s wakes up\n", - pwrdm1->name, pwrdm2->name); - - prm_set_mod_reg_bits((1 << pwrdm2->dep_bit), - pwrdm1->prcm_offs, PM_WKDEP); - - return 0; -} - -/** - * pwrdm_del_wkdep - remove a wakeup dependency from pwrdm2 to pwrdm1 - * @pwrdm1: wake this struct powerdomain * up (dependent) - * @pwrdm2: when this struct powerdomain * wakes up (source) - * - * Remove a wakeup dependency that causes pwrdm1 to wake up when pwrdm2 - * wakes up. Returns -EINVAL if presented with invalid powerdomain - * pointers, -ENOENT if pwrdm2 cannot wake up pwrdm1 in hardware, or - * 0 upon success. - */ -int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) -{ - struct powerdomain *p; - - if (!pwrdm1) - return -EINVAL; - - p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->wkdep_srcs); - if (IS_ERR(p)) { - pr_debug("powerdomain: hardware cannot set/clear wake up of " - "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name); - return PTR_ERR(p); - } - - pr_debug("powerdomain: hardware will no longer wake up %s after %s " - "wakes up\n", pwrdm1->name, pwrdm2->name); - - prm_clear_mod_reg_bits((1 << pwrdm2->dep_bit), - pwrdm1->prcm_offs, PM_WKDEP); - - return 0; -} - -/** - * pwrdm_read_wkdep - read wakeup dependency state from pwrdm2 to pwrdm1 - * @pwrdm1: wake this struct powerdomain * up (dependent) - * @pwrdm2: when this struct powerdomain * wakes up (source) - * - * Return 1 if a hardware wakeup dependency exists wherein pwrdm1 will be - * awoken when pwrdm2 wakes up; 0 if dependency is not set; -EINVAL - * if either powerdomain pointer is invalid; or -ENOENT if the hardware - * is incapable. - * - * REVISIT: Currently this function only represents software-controllable - * wakeup dependencies. Wakeup dependencies fixed in hardware are not - * yet handled here. - */ -int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) -{ - struct powerdomain *p; - - if (!pwrdm1) - return -EINVAL; - - p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->wkdep_srcs); - if (IS_ERR(p)) { - pr_debug("powerdomain: hardware cannot set/clear wake up of " - "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name); - return PTR_ERR(p); - } - - return prm_read_mod_bits_shift(pwrdm1->prcm_offs, PM_WKDEP, - (1 << pwrdm2->dep_bit)); -} - -/** - * pwrdm_add_sleepdep - add a sleep dependency from pwrdm2 to pwrdm1 - * @pwrdm1: prevent this struct powerdomain * from sleeping (dependent) - * @pwrdm2: when this struct powerdomain * is active (source) - * - * Prevent pwrdm1 from automatically going inactive (and then to - * retention or off) if pwrdm2 is still active. Returns -EINVAL if - * presented with invalid powerdomain pointers or called on a machine - * that does not support software-configurable hardware sleep dependencies, - * -ENOENT if the specified dependency cannot be set in hardware, or - * 0 upon success. - */ -int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) -{ - struct powerdomain *p; - - if (!cpu_is_omap34xx()) - return -EINVAL; - - if (!pwrdm1) - return -EINVAL; - - p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs); - if (IS_ERR(p)) { - pr_debug("powerdomain: hardware cannot set/clear sleep " - "dependency affecting %s from %s\n", pwrdm1->name, - pwrdm2->name); - return PTR_ERR(p); - } - - pr_debug("powerdomain: will prevent %s from sleeping if %s is active\n", - pwrdm1->name, pwrdm2->name); - - cm_set_mod_reg_bits((1 << pwrdm2->dep_bit), - pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP); - - return 0; -} - -/** - * pwrdm_del_sleepdep - remove a sleep dependency from pwrdm2 to pwrdm1 - * @pwrdm1: prevent this struct powerdomain * from sleeping (dependent) - * @pwrdm2: when this struct powerdomain * is active (source) - * - * Allow pwrdm1 to automatically go inactive (and then to retention or - * off), independent of the activity state of pwrdm2. Returns -EINVAL - * if presented with invalid powerdomain pointers or called on a machine - * that does not support software-configurable hardware sleep dependencies, - * -ENOENT if the specified dependency cannot be cleared in hardware, or - * 0 upon success. - */ -int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) -{ - struct powerdomain *p; - - if (!cpu_is_omap34xx()) - return -EINVAL; - - if (!pwrdm1) - return -EINVAL; - - p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs); - if (IS_ERR(p)) { - pr_debug("powerdomain: hardware cannot set/clear sleep " - "dependency affecting %s from %s\n", pwrdm1->name, - pwrdm2->name); - return PTR_ERR(p); - } - - pr_debug("powerdomain: will no longer prevent %s from sleeping if " - "%s is active\n", pwrdm1->name, pwrdm2->name); - - cm_clear_mod_reg_bits((1 << pwrdm2->dep_bit), - pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP); - - return 0; -} - -/** - * pwrdm_read_sleepdep - read sleep dependency state from pwrdm2 to pwrdm1 - * @pwrdm1: prevent this struct powerdomain * from sleeping (dependent) - * @pwrdm2: when this struct powerdomain * is active (source) - * - * Return 1 if a hardware sleep dependency exists wherein pwrdm1 will - * not be allowed to automatically go inactive if pwrdm2 is active; - * 0 if pwrdm1's automatic power state inactivity transition is independent - * of pwrdm2's; -EINVAL if either powerdomain pointer is invalid or called - * on a machine that does not support software-configurable hardware sleep - * dependencies; or -ENOENT if the hardware is incapable. - * - * REVISIT: Currently this function only represents software-controllable - * sleep dependencies. Sleep dependencies fixed in hardware are not - * yet handled here. - */ -int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) -{ - struct powerdomain *p; - - if (!cpu_is_omap34xx()) - return -EINVAL; - - if (!pwrdm1) - return -EINVAL; - - p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs); - if (IS_ERR(p)) { - pr_debug("powerdomain: hardware cannot set/clear sleep " - "dependency affecting %s from %s\n", pwrdm1->name, - pwrdm2->name); - return PTR_ERR(p); - } - - return prm_read_mod_bits_shift(pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP, - (1 << pwrdm2->dep_bit)); -} - /** * pwrdm_get_mem_bank_count - get number of memory banks in this powerdomain * @pwrdm: struct powerdomain * * - * Return the number of controllable memory banks in powerdomain pwrdm, + * Return the number of controllable memory banks in powerdomain @pwrdm, * starting with 1. Returns -EINVAL if the powerdomain pointer is null. */ int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm) @@ -691,7 +398,7 @@ int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm) * @pwrdm: struct powerdomain * to set * @pwrst: one of the PWRDM_POWER_* macros * - * Set the powerdomain pwrdm's next power state to pwrst. The powerdomain + * Set the powerdomain @pwrdm's next power state to @pwrst. The powerdomain * may not enter this state immediately if the preconditions for this state * have not been satisfied. Returns -EINVAL if the powerdomain pointer is * null or if the power state is invalid for the powerdomin, or returns 0 @@ -710,7 +417,7 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, (pwrst << OMAP_POWERSTATE_SHIFT), - pwrdm->prcm_offs, PM_PWSTCTRL); + pwrdm->prcm_offs, pwrstctrl_reg_offs); return 0; } @@ -719,7 +426,7 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) * pwrdm_read_next_pwrst - get next powerdomain power state * @pwrdm: struct powerdomain * to get power state * - * Return the powerdomain pwrdm's next power state. Returns -EINVAL + * Return the powerdomain @pwrdm's next power state. Returns -EINVAL * if the powerdomain pointer is null or returns the next power state * upon success. */ @@ -728,15 +435,15 @@ int pwrdm_read_next_pwrst(struct powerdomain *pwrdm) if (!pwrdm) return -EINVAL; - return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTCTRL, - OMAP_POWERSTATE_MASK); + return prm_read_mod_bits_shift(pwrdm->prcm_offs, + pwrstctrl_reg_offs, OMAP_POWERSTATE_MASK); } /** * pwrdm_read_pwrst - get current powerdomain power state * @pwrdm: struct powerdomain * to get power state * - * Return the powerdomain pwrdm's current power state. Returns -EINVAL + * Return the powerdomain @pwrdm's current power state. Returns -EINVAL * if the powerdomain pointer is null or returns the current power state * upon success. */ @@ -745,15 +452,15 @@ int pwrdm_read_pwrst(struct powerdomain *pwrdm) if (!pwrdm) return -EINVAL; - return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST, - OMAP_POWERSTATEST_MASK); + return prm_read_mod_bits_shift(pwrdm->prcm_offs, + pwrstst_reg_offs, OMAP_POWERSTATEST_MASK); } /** * pwrdm_read_prev_pwrst - get previous powerdomain power state * @pwrdm: struct powerdomain * to get previous power state * - * Return the powerdomain pwrdm's previous power state. Returns -EINVAL + * Return the powerdomain @pwrdm's previous power state. Returns -EINVAL * if the powerdomain pointer is null or returns the previous power state * upon success. */ @@ -771,11 +478,11 @@ int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) * @pwrdm: struct powerdomain * to set * @pwrst: one of the PWRDM_POWER_* macros * - * Set the next power state that the logic portion of the powerdomain - * pwrdm will enter when the powerdomain enters retention. This will - * be either RETENTION or OFF, if supported. Returns -EINVAL if the - * powerdomain pointer is null or the target power state is not not - * supported, or returns 0 upon success. + * Set the next power state @pwrst that the logic portion of the + * powerdomain @pwrdm will enter when the powerdomain enters retention. + * This will be either RETENTION or OFF, if supported. Returns + * -EINVAL if the powerdomain pointer is null or the target power + * state is not not supported, or returns 0 upon success. */ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) { @@ -796,7 +503,7 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) */ prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE, (pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE)), - pwrdm->prcm_offs, PM_PWSTCTRL); + pwrdm->prcm_offs, pwrstctrl_reg_offs); return 0; } @@ -807,13 +514,14 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) * @bank: memory bank number to set (0-3) * @pwrst: one of the PWRDM_POWER_* macros * - * Set the next power state that memory bank x of the powerdomain - * pwrdm will enter when the powerdomain enters the ON state. Bank - * will be a number from 0 to 3, and represents different types of - * memory, depending on the powerdomain. Returns -EINVAL if the - * powerdomain pointer is null or the target power state is not not - * supported for this memory bank, -EEXIST if the target memory bank - * does not exist or is not controllable, or returns 0 upon success. + * Set the next power state @pwrst that memory bank @bank of the + * powerdomain @pwrdm will enter when the powerdomain enters the ON + * state. @bank will be a number from 0 to 3, and represents different + * types of memory, depending on the powerdomain. Returns -EINVAL if + * the powerdomain pointer is null or the target power state is not + * not supported for this memory bank, -EEXIST if the target memory + * bank does not exist or is not controllable, or returns 0 upon + * success. */ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) { @@ -839,16 +547,19 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) */ switch (bank) { case 0: - m = OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK; + m = OMAP_MEM0_ONSTATE_MASK; break; case 1: - m = OMAP3430_L1FLATMEMONSTATE_MASK; + m = OMAP_MEM1_ONSTATE_MASK; break; case 2: - m = OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK; + m = OMAP_MEM2_ONSTATE_MASK; break; case 3: - m = OMAP3430_L2FLATMEMONSTATE_MASK; + m = OMAP_MEM3_ONSTATE_MASK; + break; + case 4: + m = OMAP_MEM4_ONSTATE_MASK; break; default: WARN_ON(1); /* should never happen */ @@ -856,7 +567,7 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) } prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), - pwrdm->prcm_offs, PM_PWSTCTRL); + pwrdm->prcm_offs, pwrstctrl_reg_offs); return 0; } @@ -867,14 +578,15 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) * @bank: memory bank number to set (0-3) * @pwrst: one of the PWRDM_POWER_* macros * - * Set the next power state that memory bank x of the powerdomain - * pwrdm will enter when the powerdomain enters the RETENTION state. - * Bank will be a number from 0 to 3, and represents different types - * of memory, depending on the powerdomain. pwrst will be either - * RETENTION or OFF, if supported. Returns -EINVAL if the powerdomain - * pointer is null or the target power state is not not supported for - * this memory bank, -EEXIST if the target memory bank does not exist - * or is not controllable, or returns 0 upon success. + * Set the next power state @pwrst that memory bank @bank of the + * powerdomain @pwrdm will enter when the powerdomain enters the + * RETENTION state. Bank will be a number from 0 to 3, and represents + * different types of memory, depending on the powerdomain. @pwrst + * will be either RETENTION or OFF, if supported. Returns -EINVAL if + * the powerdomain pointer is null or the target power state is not + * not supported for this memory bank, -EEXIST if the target memory + * bank does not exist or is not controllable, or returns 0 upon + * success. */ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) { @@ -900,16 +612,19 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) */ switch (bank) { case 0: - m = OMAP3430_SHAREDL1CACHEFLATRETSTATE; + m = OMAP_MEM0_RETSTATE_MASK; break; case 1: - m = OMAP3430_L1FLATMEMRETSTATE; + m = OMAP_MEM1_RETSTATE_MASK; break; case 2: - m = OMAP3430_SHAREDL2CACHEFLATRETSTATE; + m = OMAP_MEM2_RETSTATE_MASK; break; case 3: - m = OMAP3430_L2FLATMEMRETSTATE; + m = OMAP_MEM3_RETSTATE_MASK; + break; + case 4: + m = OMAP_MEM4_RETSTATE_MASK; break; default: WARN_ON(1); /* should never happen */ @@ -917,7 +632,7 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) } prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, - PM_PWSTCTRL); + pwrstctrl_reg_offs); return 0; } @@ -926,27 +641,27 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) * pwrdm_read_logic_pwrst - get current powerdomain logic retention power state * @pwrdm: struct powerdomain * to get current logic retention power state * - * Return the current power state that the logic portion of - * powerdomain pwrdm will enter - * Returns -EINVAL if the powerdomain pointer is null or returns the - * current logic retention power state upon success. + * Return the power state that the logic portion of powerdomain @pwrdm + * will enter when the powerdomain enters retention. Returns -EINVAL + * if the powerdomain pointer is null or returns the logic retention + * power state upon success. */ int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) { if (!pwrdm) return -EINVAL; - return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST, - OMAP3430_LOGICSTATEST); + return prm_read_mod_bits_shift(pwrdm->prcm_offs, + pwrstst_reg_offs, OMAP3430_LOGICSTATEST); } /** * pwrdm_read_prev_logic_pwrst - get previous powerdomain logic power state * @pwrdm: struct powerdomain * to get previous logic power state * - * Return the powerdomain pwrdm's logic power state. Returns -EINVAL - * if the powerdomain pointer is null or returns the previous logic - * power state upon success. + * Return the powerdomain @pwrdm's previous logic power state. Returns + * -EINVAL if the powerdomain pointer is null or returns the previous + * logic power state upon success. */ int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) { @@ -968,8 +683,8 @@ int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) * @pwrdm: struct powerdomain * to get current memory bank power state * @bank: memory bank number (0-3) * - * Return the powerdomain pwrdm's current memory power state for bank - * x. Returns -EINVAL if the powerdomain pointer is null, -EEXIST if + * Return the powerdomain @pwrdm's current memory power state for bank + * @bank. Returns -EINVAL if the powerdomain pointer is null, -EEXIST if * the target memory bank does not exist or is not controllable, or * returns the current memory power state upon success. */ @@ -994,23 +709,27 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) */ switch (bank) { case 0: - m = OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK; + m = OMAP_MEM0_STATEST_MASK; break; case 1: - m = OMAP3430_L1FLATMEMSTATEST_MASK; + m = OMAP_MEM1_STATEST_MASK; break; case 2: - m = OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK; + m = OMAP_MEM2_STATEST_MASK; break; case 3: - m = OMAP3430_L2FLATMEMSTATEST_MASK; + m = OMAP_MEM3_STATEST_MASK; + break; + case 4: + m = OMAP_MEM4_STATEST_MASK; break; default: WARN_ON(1); /* should never happen */ return -EEXIST; } - return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST, m); + return prm_read_mod_bits_shift(pwrdm->prcm_offs, + pwrstst_reg_offs, m); } /** @@ -1018,10 +737,11 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) * @pwrdm: struct powerdomain * to get previous memory bank power state * @bank: memory bank number (0-3) * - * Return the powerdomain pwrdm's previous memory power state for bank - * x. Returns -EINVAL if the powerdomain pointer is null, -EEXIST if - * the target memory bank does not exist or is not controllable, or - * returns the previous memory power state upon success. + * Return the powerdomain @pwrdm's previous memory power state for + * bank @bank. Returns -EINVAL if the powerdomain pointer is null, + * -EEXIST if the target memory bank does not exist or is not + * controllable, or returns the previous memory power state upon + * success. */ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) { @@ -1068,10 +788,10 @@ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) * pwrdm_clear_all_prev_pwrst - clear previous powerstate register for a pwrdm * @pwrdm: struct powerdomain * to clear * - * Clear the powerdomain's previous power state register. Clears the - * entire register, including logic and memory bank previous power states. - * Returns -EINVAL if the powerdomain pointer is null, or returns 0 upon - * success. + * Clear the powerdomain's previous power state register @pwrdm. + * Clears the entire register, including logic and memory bank + * previous power states. Returns -EINVAL if the powerdomain pointer + * is null, or returns 0 upon success. */ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) { @@ -1096,11 +816,11 @@ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) * @pwrdm: struct powerdomain * * * Enable automatic context save-and-restore upon power state change - * for some devices in a powerdomain. Warning: this only affects a - * subset of devices in a powerdomain; check the TRM closely. Returns - * -EINVAL if the powerdomain pointer is null or if the powerdomain - * does not support automatic save-and-restore, or returns 0 upon - * success. + * for some devices in the powerdomain @pwrdm. Warning: this only + * affects a subset of devices in a powerdomain; check the TRM + * closely. Returns -EINVAL if the powerdomain pointer is null or if + * the powerdomain does not support automatic save-and-restore, or + * returns 0 upon success. */ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) { @@ -1114,7 +834,7 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) pwrdm->name); prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, - pwrdm->prcm_offs, PM_PWSTCTRL); + pwrdm->prcm_offs, pwrstctrl_reg_offs); return 0; } @@ -1124,11 +844,11 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) * @pwrdm: struct powerdomain * * * Disable automatic context save-and-restore upon power state change - * for some devices in a powerdomain. Warning: this only affects a - * subset of devices in a powerdomain; check the TRM closely. Returns - * -EINVAL if the powerdomain pointer is null or if the powerdomain - * does not support automatic save-and-restore, or returns 0 upon - * success. + * for some devices in the powerdomain @pwrdm. Warning: this only + * affects a subset of devices in a powerdomain; check the TRM + * closely. Returns -EINVAL if the powerdomain pointer is null or if + * the powerdomain does not support automatic save-and-restore, or + * returns 0 upon success. */ int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) { @@ -1142,7 +862,7 @@ int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) pwrdm->name); prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0, - pwrdm->prcm_offs, PM_PWSTCTRL); + pwrdm->prcm_offs, pwrstctrl_reg_offs); return 0; } @@ -1151,7 +871,7 @@ int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) * pwrdm_has_hdwr_sar - test whether powerdomain supports hardware SAR * @pwrdm: struct powerdomain * * - * Returns 1 if powerdomain 'pwrdm' supports hardware save-and-restore + * Returns 1 if powerdomain @pwrdm supports hardware save-and-restore * for some devices, or 0 if it does not. */ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm) @@ -1163,7 +883,7 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm) * pwrdm_wait_transition - wait for powerdomain power transition to finish * @pwrdm: struct powerdomain * to wait for * - * If the powerdomain pwrdm is in the process of a state transition, + * If the powerdomain @pwrdm is in the process of a state transition, * spin until it completes the power transition, or until an iteration * bailout value is reached. Returns -EINVAL if the powerdomain * pointer is null, -EAGAIN if the bailout value was reached, or @@ -1183,10 +903,10 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm) */ /* XXX Is this udelay() value meaningful? */ - while ((prm_read_mod_reg(pwrdm->prcm_offs, PM_PWSTST) & + while ((prm_read_mod_reg(pwrdm->prcm_offs, pwrstst_reg_offs) & OMAP_INTRANSITION) && (c++ < PWRDM_TRANSITION_BAILOUT)) - udelay(1); + udelay(1); if (c > PWRDM_TRANSITION_BAILOUT) { printk(KERN_ERR "powerdomain: waited too long for " @@ -1213,12 +933,6 @@ int pwrdm_clkdm_state_switch(struct clockdomain *clkdm) return -EINVAL; } -int pwrdm_clk_state_switch(struct clk *clk) -{ - if (clk != NULL && clk->clkdm != NULL) - return pwrdm_clkdm_state_switch(clk->clkdm); - return -EINVAL; -} int pwrdm_pre_transition(void) { diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h index 057b2e3e2c35..105cbcaefd3b 100644 --- a/arch/arm/mach-omap2/powerdomains.h +++ b/arch/arm/mach-omap2/powerdomains.h @@ -1,8 +1,8 @@ /* * OMAP2/3 common powerdomain definitions * - * Copyright (C) 2007-8 Texas Instruments, Inc. - * Copyright (C) 2007-8 Nokia Corporation + * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2009 Nokia Corporation * * Written by Paul Walmsley * Debugging and integration fixes by Jouni Högander @@ -12,26 +12,21 @@ * published by the Free Software Foundation. */ +/* + * To Do List + * -> Move the Sleep/Wakeup dependencies from Power Domain framework to + * Clock Domain Framework + */ + #ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS #define ARCH_ARM_MACH_OMAP2_POWERDOMAINS /* * This file contains all of the powerdomains that have some element - * of software control for the OMAP24xx and OMAP34XX chips. - * - * A few notes: + * of software control for the OMAP24xx and OMAP34xx chips. * * This is not an exhaustive listing of powerdomains on the chips; only * powerdomains that can be controlled in software. - * - * A useful validation rule for struct powerdomain: - * Any powerdomain referenced by a wkdep_srcs or sleepdep_srcs array - * must have a dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really - * just software-controllable dependencies. Non-software-controllable - * dependencies do exist, but they are not encoded below (yet). - * - * 24xx does not support programmable sleep dependencies (SLEEPDEP) - * */ /* @@ -41,26 +36,17 @@ * * On the 2420, this is a 'C55 DSP called, simply, the DSP. Its * powerdomain is called the "DSP power domain." On the 2430, the - * on-board DSP is a 'C64 DSP, now called the IVA2 or IVA2.1. Its - * powerdomain is still called the "DSP power domain." On the 3430, - * the DSP is a 'C64 DSP like the 2430, also known as the IVA2; but - * its powerdomain is now called the "IVA2 power domain." + * on-board DSP is a 'C64 DSP, now called (along with its hardware + * accelerators) the IVA2 or IVA2.1. Its powerdomain is still called + * the "DSP power domain." On the 3430, the DSP is a 'C64 DSP like the + * 2430, also known as the IVA2; but its powerdomain is now called the + * "IVA2 power domain." * * The 2420 also has something called the IVA, which is a separate ARM * core, and has nothing to do with the DSP/IVA2. * * Ideally the DSP/IVA2 could just be the same powerdomain, but the PRCM * address offset is different between the C55 and C64 DSPs. - * - * The overly-specific dep_bit names are due to a bit name collision - * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift - * value are the same for all powerdomains: 2 - */ - -/* - * XXX should dep_bit be a mask, so we can test to see if it is 0 as a - * sanity check? - * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE */ #include <plat/powerdomain.h> @@ -68,69 +54,23 @@ #include "prcm-common.h" #include "prm.h" #include "cm.h" - -/* OMAP2/3-common powerdomains and wakeup dependencies */ - -/* - * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP - * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE - * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE - */ -static struct pwrdm_dep gfx_sgx_wkdeps[] = { - { - .pwrdm_name = "core_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .pwrdm_name = "iva2_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .pwrdm_name = "mpu_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | - CHIP_IS_OMAP3430) - }, - { - .pwrdm_name = "wkup_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | - CHIP_IS_OMAP3430) - }, - { NULL }, -}; - -/* - * 3430: CM_SLEEPDEP_CAM: MPU - * 3430ES1: CM_SLEEPDEP_GFX: MPU - * 3430ES2: CM_SLEEPDEP_SGX: MPU - */ -static struct pwrdm_dep cam_gfx_sleepdeps[] = { - { - .pwrdm_name = "mpu_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { NULL }, -}; - - #include "powerdomains24xx.h" #include "powerdomains34xx.h" +#include "powerdomains44xx.h" +/* OMAP2/3-common powerdomains */ -/* - * OMAP2/3 common powerdomains - */ +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) /* * The GFX powerdomain is not present on 3430ES2, but currently we do not * have a macro to filter it out at compile-time. */ -static struct powerdomain gfx_pwrdm = { +static struct powerdomain gfx_omap2_pwrdm = { .name = "gfx_pwrdm", .prcm_offs = GFX_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430ES1), - .wkdep_srcs = gfx_sgx_wkdeps, - .sleepdep_srcs = cam_gfx_sleepdeps, .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRDM_POWER_RET, .banks = 1, @@ -142,22 +82,24 @@ static struct powerdomain gfx_pwrdm = { }, }; -static struct powerdomain wkup_pwrdm = { +static struct powerdomain wkup_omap2_pwrdm = { .name = "wkup_pwrdm", .prcm_offs = WKUP_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), - .dep_bit = OMAP_EN_WKUP_SHIFT, }; +#endif /* As powerdomains are added or removed above, this list must also be changed */ static struct powerdomain *powerdomains_omap[] __initdata = { - &gfx_pwrdm, - &wkup_pwrdm, +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) + &wkup_omap2_pwrdm, + &gfx_omap2_pwrdm, +#endif -#ifdef CONFIG_ARCH_OMAP24XX +#ifdef CONFIG_ARCH_OMAP2 &dsp_pwrdm, &mpu_24xx_pwrdm, &core_24xx_pwrdm, @@ -167,12 +109,12 @@ static struct powerdomain *powerdomains_omap[] __initdata = { &mdm_pwrdm, #endif -#ifdef CONFIG_ARCH_OMAP34XX +#ifdef CONFIG_ARCH_OMAP3 &iva2_pwrdm, - &mpu_34xx_pwrdm, + &mpu_3xxx_pwrdm, &neon_pwrdm, - &core_34xx_pre_es3_1_pwrdm, - &core_34xx_es3_1_pwrdm, + &core_3xxx_pre_es3_1_pwrdm, + &core_3xxx_es3_1_pwrdm, &cam_pwrdm, &dss_pwrdm, &per_pwrdm, @@ -186,6 +128,24 @@ static struct powerdomain *powerdomains_omap[] __initdata = { &dpll5_pwrdm, #endif +#ifdef CONFIG_ARCH_OMAP4 + &core_44xx_pwrdm, + &gfx_44xx_pwrdm, + &abe_44xx_pwrdm, + &dss_44xx_pwrdm, + &tesla_44xx_pwrdm, + &wkup_44xx_pwrdm, + &cpu0_44xx_pwrdm, + &cpu1_44xx_pwrdm, + &emu_44xx_pwrdm, + &mpu_44xx_pwrdm, + &ivahd_44xx_pwrdm, + &cam_44xx_pwrdm, + &l3init_44xx_pwrdm, + &l4per_44xx_pwrdm, + &always_on_core_44xx_pwrdm, + &cefuse_44xx_pwrdm, +#endif NULL }; diff --git a/arch/arm/mach-omap2/powerdomains24xx.h b/arch/arm/mach-omap2/powerdomains24xx.h index bd249a495aa9..775093add9b6 100644 --- a/arch/arm/mach-omap2/powerdomains24xx.h +++ b/arch/arm/mach-omap2/powerdomains24xx.h @@ -2,7 +2,7 @@ * OMAP24XX powerdomain definitions * * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2008 Nokia Corporation + * Copyright (C) 2007-2009 Nokia Corporation * * Written by Paul Walmsley * Debugging and integration fixes by Jouni Högander @@ -30,83 +30,7 @@ /* 24XX powerdomains and dependencies */ -#ifdef CONFIG_ARCH_OMAP24XX - - -/* Wakeup dependency source arrays */ - -/* - * 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP - * 2430 PM_WKDEP_MDM: same as above - */ -static struct pwrdm_dep dsp_mdm_24xx_wkdeps[] = { - { - .pwrdm_name = "core_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .pwrdm_name = "mpu_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .pwrdm_name = "wkup_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { NULL }, -}; - -/* - * 2420 PM_WKDEP_MPU: CORE, DSP, WKUP - * 2430 adds MDM - */ -static struct pwrdm_dep mpu_24xx_wkdeps[] = { - { - .pwrdm_name = "core_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .pwrdm_name = "dsp_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .pwrdm_name = "wkup_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .pwrdm_name = "mdm_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) - }, - { NULL }, -}; - -/* - * 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP - * 2430 adds MDM - */ -static struct pwrdm_dep core_24xx_wkdeps[] = { - { - .pwrdm_name = "dsp_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .pwrdm_name = "gfx_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .pwrdm_name = "mpu_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .pwrdm_name = "wkup_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) - }, - { - .pwrdm_name = "mdm_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) - }, - { NULL }, -}; - +#ifdef CONFIG_ARCH_OMAP2 /* Powerdomains */ @@ -114,8 +38,6 @@ static struct powerdomain dsp_pwrdm = { .name = "dsp_pwrdm", .prcm_offs = OMAP24XX_DSP_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), - .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT, - .wkdep_srcs = dsp_mdm_24xx_wkdeps, .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRDM_POWER_RET, .banks = 1, @@ -131,8 +53,6 @@ static struct powerdomain mpu_24xx_pwrdm = { .name = "mpu_pwrdm", .prcm_offs = MPU_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), - .dep_bit = OMAP24XX_EN_MPU_SHIFT, - .wkdep_srcs = mpu_24xx_wkdeps, .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .banks = 1, @@ -148,9 +68,7 @@ static struct powerdomain core_24xx_pwrdm = { .name = "core_pwrdm", .prcm_offs = CORE_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), - .wkdep_srcs = core_24xx_wkdeps, .pwrsts = PWRSTS_OFF_RET_ON, - .dep_bit = OMAP24XX_EN_CORE_SHIFT, .banks = 3, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ @@ -164,7 +82,7 @@ static struct powerdomain core_24xx_pwrdm = { }, }; -#endif /* CONFIG_ARCH_OMAP24XX */ +#endif /* CONFIG_ARCH_OMAP2 */ @@ -176,13 +94,10 @@ static struct powerdomain core_24xx_pwrdm = { /* XXX 2430 KILLDOMAINWKUP bit? No current users apparently */ -/* Another case of bit name collisions between several registers: EN_MDM */ static struct powerdomain mdm_pwrdm = { .name = "mdm_pwrdm", .prcm_offs = OMAP2430_MDM_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), - .dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT, - .wkdep_srcs = dsp_mdm_24xx_wkdeps, .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRDM_POWER_RET, .banks = 1, diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h index 588f7e07d0ea..186c0132466b 100644 --- a/arch/arm/mach-omap2/powerdomains34xx.h +++ b/arch/arm/mach-omap2/powerdomains34xx.h @@ -1,8 +1,8 @@ /* - * OMAP34XX powerdomain definitions + * OMAP3 powerdomain definitions * * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2008 Nokia Corporation + * Copyright (C) 2007-2010 Nokia Corporation * * Written by Paul Walmsley * Debugging and integration fixes by Jouni Högander @@ -32,128 +32,7 @@ * 34XX-specific powerdomains, dependencies */ -#ifdef CONFIG_ARCH_OMAP34XX - -/* - * 3430: PM_WKDEP_{PER,USBHOST}: CORE, IVA2, MPU, WKUP - * (USBHOST is ES2 only) - */ -static struct pwrdm_dep per_usbhost_wkdeps[] = { - { - .pwrdm_name = "core_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .pwrdm_name = "iva2_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .pwrdm_name = "mpu_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .pwrdm_name = "wkup_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { NULL }, -}; - -/* - * 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER - */ -static struct pwrdm_dep mpu_34xx_wkdeps[] = { - { - .pwrdm_name = "core_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .pwrdm_name = "iva2_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .pwrdm_name = "dss_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .pwrdm_name = "per_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { NULL }, -}; - -/* - * 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER - */ -static struct pwrdm_dep iva2_wkdeps[] = { - { - .pwrdm_name = "core_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .pwrdm_name = "mpu_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .pwrdm_name = "wkup_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .pwrdm_name = "dss_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .pwrdm_name = "per_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { NULL }, -}; - - -/* 3430 PM_WKDEP_{CAM,DSS}: IVA2, MPU, WKUP */ -static struct pwrdm_dep cam_dss_wkdeps[] = { - { - .pwrdm_name = "iva2_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .pwrdm_name = "mpu_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .pwrdm_name = "wkup_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { NULL }, -}; - -/* 3430: PM_WKDEP_NEON: MPU */ -static struct pwrdm_dep neon_wkdeps[] = { - { - .pwrdm_name = "mpu_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { NULL }, -}; - - -/* Sleep dependency source arrays for 34xx-specific pwrdms - 34XX only */ - -/* - * 3430: CM_SLEEPDEP_{DSS,PER}: MPU, IVA - * 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA - */ -static struct pwrdm_dep dss_per_usbhost_sleepdeps[] = { - { - .pwrdm_name = "mpu_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { - .pwrdm_name = "iva2_pwrdm", - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }, - { NULL }, -}; - +#ifdef CONFIG_ARCH_OMAP3 /* * Powerdomains @@ -163,8 +42,6 @@ static struct powerdomain iva2_pwrdm = { .name = "iva2_pwrdm", .prcm_offs = OMAP3430_IVA2_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), - .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT, - .wkdep_srcs = iva2_wkdeps, .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .banks = 4, @@ -182,12 +59,10 @@ static struct powerdomain iva2_pwrdm = { }, }; -static struct powerdomain mpu_34xx_pwrdm = { +static struct powerdomain mpu_3xxx_pwrdm = { .name = "mpu_pwrdm", .prcm_offs = MPU_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), - .dep_bit = OMAP3430_EN_MPU_SHIFT, - .wkdep_srcs = mpu_34xx_wkdeps, .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .flags = PWRDM_HAS_MPU_QUIRK, @@ -200,15 +75,13 @@ static struct powerdomain mpu_34xx_pwrdm = { }, }; -/* No wkdeps or sleepdeps for 34xx core apparently */ -static struct powerdomain core_34xx_pre_es3_1_pwrdm = { +static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { .name = "core_pwrdm", .prcm_offs = CORE_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | CHIP_IS_OMAP3430ES2 | CHIP_IS_OMAP3430ES3_0), .pwrsts = PWRSTS_OFF_RET_ON, - .dep_bit = OMAP3430_EN_CORE_SHIFT, .banks = 2, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ @@ -220,13 +93,11 @@ static struct powerdomain core_34xx_pre_es3_1_pwrdm = { }, }; -/* No wkdeps or sleepdeps for 34xx core apparently */ -static struct powerdomain core_34xx_es3_1_pwrdm = { +static struct powerdomain core_3xxx_es3_1_pwrdm = { .name = "core_pwrdm", .prcm_offs = CORE_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1), .pwrsts = PWRSTS_OFF_RET_ON, - .dep_bit = OMAP3430_EN_CORE_SHIFT, .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ .banks = 2, .pwrsts_mem_ret = { @@ -239,14 +110,10 @@ static struct powerdomain core_34xx_es3_1_pwrdm = { }, }; -/* Another case of bit name collisions between several registers: EN_DSS */ static struct powerdomain dss_pwrdm = { .name = "dss_pwrdm", .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), .prcm_offs = OMAP3430_DSS_MOD, - .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT, - .wkdep_srcs = cam_dss_wkdeps, - .sleepdep_srcs = dss_per_usbhost_sleepdeps, .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRDM_POWER_RET, .banks = 1, @@ -267,8 +134,6 @@ static struct powerdomain sgx_pwrdm = { .name = "sgx_pwrdm", .prcm_offs = OMAP3430ES2_SGX_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), - .wkdep_srcs = gfx_sgx_wkdeps, - .sleepdep_srcs = cam_gfx_sleepdeps, /* XXX This is accurate for 3430 SGX, but what about GFX? */ .pwrsts = PWRSTS_OFF_ON, .pwrsts_logic_ret = PWRDM_POWER_RET, @@ -285,8 +150,6 @@ static struct powerdomain cam_pwrdm = { .name = "cam_pwrdm", .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), .prcm_offs = OMAP3430_CAM_MOD, - .wkdep_srcs = cam_dss_wkdeps, - .sleepdep_srcs = cam_gfx_sleepdeps, .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRDM_POWER_RET, .banks = 1, @@ -302,9 +165,6 @@ static struct powerdomain per_pwrdm = { .name = "per_pwrdm", .prcm_offs = OMAP3430_PER_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), - .dep_bit = OMAP3430_EN_PER_SHIFT, - .wkdep_srcs = per_usbhost_wkdeps, - .sleepdep_srcs = dss_per_usbhost_sleepdeps, .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .banks = 1, @@ -326,7 +186,6 @@ static struct powerdomain neon_pwrdm = { .name = "neon_pwrdm", .prcm_offs = OMAP3430_NEON_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), - .wkdep_srcs = neon_wkdeps, .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRDM_POWER_RET, }; @@ -335,8 +194,6 @@ static struct powerdomain usbhost_pwrdm = { .name = "usbhost_pwrdm", .prcm_offs = OMAP3430ES2_USBHOST_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), - .wkdep_srcs = per_usbhost_wkdeps, - .sleepdep_srcs = dss_per_usbhost_sleepdeps, .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRDM_POWER_RET, /* @@ -386,7 +243,7 @@ static struct powerdomain dpll5_pwrdm = { }; -#endif /* CONFIG_ARCH_OMAP34XX */ +#endif /* CONFIG_ARCH_OMAP3 */ #endif diff --git a/arch/arm/mach-omap2/powerdomains44xx.h b/arch/arm/mach-omap2/powerdomains44xx.h new file mode 100644 index 000000000000..c1015147d579 --- /dev/null +++ b/arch/arm/mach-omap2/powerdomains44xx.h @@ -0,0 +1,310 @@ +/* + * OMAP4 Power domains framework + * + * Copyright (C) 2009 Texas Instruments, Inc. + * Copyright (C) 2009 Nokia Corporation + * + * Abhijit Pagare (abhijitpagare@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * Paul Walmsley + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H +#define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H + +#include <plat/powerdomain.h> + +#include "prcm-common.h" +#include "cm.h" +#include "cm-regbits-44xx.h" +#include "prm.h" +#include "prm-regbits-44xx.h" + +#if defined(CONFIG_ARCH_OMAP4) + +/* core_44xx_pwrdm: CORE power domain */ +static struct powerdomain core_44xx_pwrdm = { + .name = "core_pwrdm", + .prcm_offs = OMAP4430_PRM_CORE_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 5, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* core_nret_bank */ + [1] = PWRSTS_OFF_RET, /* core_ocmram */ + [2] = PWRDM_POWER_RET, /* core_other_bank */ + [3] = PWRSTS_OFF_RET, /* ducati_l2ram */ + [4] = PWRSTS_OFF_RET, /* ducati_unicache */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* core_nret_bank */ + [1] = PWRSTS_OFF_RET, /* core_ocmram */ + [2] = PWRDM_POWER_ON, /* core_other_bank */ + [3] = PWRDM_POWER_ON, /* ducati_l2ram */ + [4] = PWRDM_POWER_ON, /* ducati_unicache */ + }, +}; + +/* gfx_44xx_pwrdm: 3D accelerator power domain */ +static struct powerdomain gfx_44xx_pwrdm = { + .name = "gfx_pwrdm", + .prcm_offs = OMAP4430_PRM_GFX_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* gfx_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* gfx_mem */ + }, +}; + +/* abe_44xx_pwrdm: Audio back end power domain */ +static struct powerdomain abe_44xx_pwrdm = { + .name = "abe_pwrdm", + .prcm_offs = OMAP4430_PRM_ABE_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRDM_POWER_OFF, + .banks = 2, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_RET, /* aessmem */ + [1] = PWRDM_POWER_OFF, /* periphmem */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* aessmem */ + [1] = PWRDM_POWER_ON, /* periphmem */ + }, +}; + +/* dss_44xx_pwrdm: Display subsystem power domain */ +static struct powerdomain dss_44xx_pwrdm = { + .name = "dss_pwrdm", + .prcm_offs = OMAP4430_PRM_DSS_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* dss_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* dss_mem */ + }, +}; + +/* tesla_44xx_pwrdm: Tesla processor power domain */ +static struct powerdomain tesla_44xx_pwrdm = { + .name = "tesla_pwrdm", + .prcm_offs = OMAP4430_PRM_TESLA_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 3, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_RET, /* tesla_edma */ + [1] = PWRSTS_OFF_RET, /* tesla_l1 */ + [2] = PWRSTS_OFF_RET, /* tesla_l2 */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* tesla_edma */ + [1] = PWRDM_POWER_ON, /* tesla_l1 */ + [2] = PWRDM_POWER_ON, /* tesla_l2 */ + }, +}; + +/* wkup_44xx_pwrdm: Wake-up power domain */ +static struct powerdomain wkup_44xx_pwrdm = { + .name = "wkup_pwrdm", + .prcm_offs = OMAP4430_PRM_WKUP_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRDM_POWER_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* wkup_bank */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* wkup_bank */ + }, +}; + +/* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ +static struct powerdomain cpu0_44xx_pwrdm = { + .name = "cpu0_pwrdm", + .prcm_offs = OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* cpu0_l1 */ + }, +}; + +/* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ +static struct powerdomain cpu1_44xx_pwrdm = { + .name = "cpu1_pwrdm", + .prcm_offs = OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* cpu1_l1 */ + }, +}; + +/* emu_44xx_pwrdm: Emulation power domain */ +static struct powerdomain emu_44xx_pwrdm = { + .name = "emu_pwrdm", + .prcm_offs = OMAP4430_PRM_EMU_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* emu_bank */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* emu_bank */ + }, +}; + +/* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */ +static struct powerdomain mpu_44xx_pwrdm = { + .name = "mpu_pwrdm", + .prcm_offs = OMAP4430_PRM_MPU_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 3, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* mpu_l1 */ + [1] = PWRSTS_OFF_RET, /* mpu_l2 */ + [2] = PWRDM_POWER_RET, /* mpu_ram */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* mpu_l1 */ + [1] = PWRDM_POWER_ON, /* mpu_l2 */ + [2] = PWRDM_POWER_ON, /* mpu_ram */ + }, +}; + +/* ivahd_44xx_pwrdm: IVA-HD power domain */ +static struct powerdomain ivahd_44xx_pwrdm = { + .name = "ivahd_pwrdm", + .prcm_offs = OMAP4430_PRM_IVAHD_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRDM_POWER_OFF, + .banks = 4, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* hwa_mem */ + [1] = PWRSTS_OFF_RET, /* sl2_mem */ + [2] = PWRSTS_OFF_RET, /* tcm1_mem */ + [3] = PWRSTS_OFF_RET, /* tcm2_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* hwa_mem */ + [1] = PWRDM_POWER_ON, /* sl2_mem */ + [2] = PWRDM_POWER_ON, /* tcm1_mem */ + [3] = PWRDM_POWER_ON, /* tcm2_mem */ + }, +}; + +/* cam_44xx_pwrdm: Camera subsystem power domain */ +static struct powerdomain cam_44xx_pwrdm = { + .name = "cam_pwrdm", + .prcm_offs = OMAP4430_PRM_CAM_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* cam_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* cam_mem */ + }, +}; + +/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */ +static struct powerdomain l3init_44xx_pwrdm = { + .name = "l3init_pwrdm", + .prcm_offs = OMAP4430_PRM_L3INIT_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* l3init_bank1 */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* l3init_bank1 */ + }, +}; + +/* l4per_44xx_pwrdm: Target peripherals power domain */ +static struct powerdomain l4per_44xx_pwrdm = { + .name = "l4per_pwrdm", + .prcm_offs = OMAP4430_PRM_L4PER_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 2, + .pwrsts_mem_ret = { + [0] = PWRDM_POWER_OFF, /* nonretained_bank */ + [1] = PWRDM_POWER_RET, /* retained_bank */ + }, + .pwrsts_mem_on = { + [0] = PWRDM_POWER_ON, /* nonretained_bank */ + [1] = PWRDM_POWER_ON, /* retained_bank */ + }, +}; + +/* + * always_on_core_44xx_pwrdm: Always ON logic that sits in VDD_CORE voltage + * domain + */ +static struct powerdomain always_on_core_44xx_pwrdm = { + .name = "always_on_core_pwrdm", + .prcm_offs = OMAP4430_PRM_ALWAYS_ON_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRDM_POWER_ON, +}; + +/* cefuse_44xx_pwrdm: Customer efuse controller power domain */ +static struct powerdomain cefuse_44xx_pwrdm = { + .name = "cefuse_pwrdm", + .prcm_offs = OMAP4430_PRM_CEFUSE_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), + .pwrsts = PWRSTS_OFF_ON, +}; + +/* + * The following power domains are not under SW control + * + * always_on_iva + * always_on_mpu + * stdefuse + */ + +#endif + +#endif diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 61ac2a418bd0..90f603d434c6 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -119,6 +119,15 @@ #define OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD 0x0400 #define OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD 0x0800 +/* Base Addresses for the OMAP4 */ + +#define OMAP4430_CM1_BASE 0x4a004000 +#define OMAP4430_CM2_BASE 0x4a008000 +#define OMAP4430_PRM_BASE 0x4a306000 +#define OMAP4430_SCRM_BASE 0x4a30a000 +#define OMAP4430_CHIRONSS_BASE 0x48243000 + + /* 24XX register bits shared between CM & PRM registers */ /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index cf466ea1dffc..e8e121a41d6d 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -11,6 +11,7 @@ * Rajendra Nayak <rnayak@ti.com> * * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc. + * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -28,6 +29,7 @@ #include <plat/control.h> #include "clock.h" +#include "clock2xxx.h" #include "cm.h" #include "prm.h" #include "prm-regbits-24xx.h" @@ -121,7 +123,10 @@ struct omap3_prcm_regs prcm_context; u32 omap_prcm_get_reset_sources(void) { /* XXX This presumably needs modification for 34XX */ - return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f; + if (cpu_is_omap24xx() | cpu_is_omap34xx()) + return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f; + if (cpu_is_omap44xx()) + return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f; } EXPORT_SYMBOL(omap_prcm_get_reset_sources); @@ -129,11 +134,12 @@ EXPORT_SYMBOL(omap_prcm_get_reset_sources); void omap_prcm_arch_reset(char mode) { s16 prcm_offs; - omap2_clk_prepare_for_reboot(); - if (cpu_is_omap24xx()) + if (cpu_is_omap24xx()) { + omap2xxx_clk_prepare_for_reboot(); + prcm_offs = WKUP_MOD; - else if (cpu_is_omap34xx()) { + } else if (cpu_is_omap34xx()) { u32 l; prcm_offs = OMAP3430_GR_MOD; @@ -144,10 +150,17 @@ void omap_prcm_arch_reset(char mode) * cf. OMAP34xx TRM, Initialization / Software Booting * Configuration. */ omap_writel(l, OMAP343X_SCRATCHPAD + 4); - } else + } else if (cpu_is_omap44xx()) + prcm_offs = OMAP4430_PRM_DEVICE_MOD; + else WARN_ON(1); - prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL); + if (cpu_is_omap24xx() | cpu_is_omap34xx()) + prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, + OMAP2_RM_RSTCTRL); + if (cpu_is_omap44xx()) + prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, + OMAP4_RM_RSTCTRL); } static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg) @@ -188,6 +201,18 @@ u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) return v; } +/* Read a PRM register, AND it, and shift the result down to bit 0 */ +u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) +{ + u32 v; + + v = prm_read_mod_reg(domain, idx); + v &= mask; + v >>= __ffs(mask); + + return v; +} + /* Read a register in a CM module */ u32 cm_read_mod_reg(s16 module, u16 idx) { @@ -280,7 +305,7 @@ void omap3_prcm_save_context(void) prcm_context.emu_cm_clksel = cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); prcm_context.emu_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSTCTRL); + cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL); prcm_context.pll_cm_autoidle2 = cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); prcm_context.pll_cm_clksel4 = @@ -333,23 +358,25 @@ void omap3_prcm_save_context(void) prcm_context.mpu_cm_autoidle2 = cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); prcm_context.iva2_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL); + cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL); prcm_context.mpu_cm_clkstctrl = - cm_read_mod_reg(MPU_MOD, CM_CLKSTCTRL); + cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL); prcm_context.core_cm_clkstctrl = - cm_read_mod_reg(CORE_MOD, CM_CLKSTCTRL); + cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL); prcm_context.sgx_cm_clkstctrl = - cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSTCTRL); + cm_read_mod_reg(OMAP3430ES2_SGX_MOD, + OMAP2_CM_CLKSTCTRL); prcm_context.dss_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSTCTRL); + cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL); prcm_context.cam_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSTCTRL); + cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL); prcm_context.per_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSTCTRL); + cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL); prcm_context.neon_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_NEON_MOD, CM_CLKSTCTRL); + cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL); prcm_context.usbhost_cm_clkstctrl = - cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL); + cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, + OMAP2_CM_CLKSTCTRL); prcm_context.core_cm_autoidle1 = cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); prcm_context.core_cm_autoidle2 = @@ -432,7 +459,7 @@ void omap3_prcm_restore_context(void) cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD, CM_CLKSEL1); cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, - CM_CLKSTCTRL); + OMAP2_CM_CLKSTCTRL); cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD, CM_AUTOIDLE2); cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD, @@ -478,22 +505,23 @@ void omap3_prcm_restore_context(void) CM_AUTOIDLE2); cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2); cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, - CM_CLKSTCTRL); - cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL); + OMAP2_CM_CLKSTCTRL); + cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, + OMAP2_CM_CLKSTCTRL); cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD, - CM_CLKSTCTRL); + OMAP2_CM_CLKSTCTRL); cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD, - CM_CLKSTCTRL); + OMAP2_CM_CLKSTCTRL); cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD, - CM_CLKSTCTRL); + OMAP2_CM_CLKSTCTRL); cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD, - CM_CLKSTCTRL); + OMAP2_CM_CLKSTCTRL); cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD, - CM_CLKSTCTRL); + OMAP2_CM_CLKSTCTRL); cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD, - CM_CLKSTCTRL); + OMAP2_CM_CLKSTCTRL); cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl, - OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL); + OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL); cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD, CM_AUTOIDLE1); cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD, diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h index 301c810fb269..597be4a2b9ff 100644 --- a/arch/arm/mach-omap2/prm-regbits-44xx.h +++ b/arch/arm/mach-omap2/prm-regbits-44xx.h @@ -29,412 +29,412 @@ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ -#define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT (1 << 1) +#define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT 1 #define OMAP4430_ABBOFF_ACT_EXPORT_MASK BITFIELD(1, 1) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ -#define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT (1 << 2) +#define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT 2 #define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK BITFIELD(2, 2) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_ABB_IVA_DONE_EN_SHIFT (1 << 31) +#define OMAP4430_ABB_IVA_DONE_EN_SHIFT 31 #define OMAP4430_ABB_IVA_DONE_EN_MASK BITFIELD(31, 31) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_ABB_IVA_DONE_ST_SHIFT (1 << 31) +#define OMAP4430_ABB_IVA_DONE_ST_SHIFT 31 #define OMAP4430_ABB_IVA_DONE_ST_MASK BITFIELD(31, 31) /* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_ABB_MPU_DONE_EN_SHIFT (1 << 7) +#define OMAP4430_ABB_MPU_DONE_EN_SHIFT 7 #define OMAP4430_ABB_MPU_DONE_EN_MASK BITFIELD(7, 7) /* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_ABB_MPU_DONE_ST_SHIFT (1 << 7) +#define OMAP4430_ABB_MPU_DONE_ST_SHIFT 7 #define OMAP4430_ABB_MPU_DONE_ST_MASK BITFIELD(7, 7) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ -#define OMAP4430_ACTIVE_FBB_SEL_SHIFT (1 << 2) +#define OMAP4430_ACTIVE_FBB_SEL_SHIFT 2 #define OMAP4430_ACTIVE_FBB_SEL_MASK BITFIELD(2, 2) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ -#define OMAP4430_ACTIVE_RBB_SEL_SHIFT (1 << 1) +#define OMAP4430_ACTIVE_RBB_SEL_SHIFT 1 #define OMAP4430_ACTIVE_RBB_SEL_MASK BITFIELD(1, 1) /* Used by PM_ABE_PWRSTCTRL */ -#define OMAP4430_AESSMEM_ONSTATE_SHIFT (1 << 16) +#define OMAP4430_AESSMEM_ONSTATE_SHIFT 16 #define OMAP4430_AESSMEM_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_ABE_PWRSTCTRL */ -#define OMAP4430_AESSMEM_RETSTATE_SHIFT (1 << 8) +#define OMAP4430_AESSMEM_RETSTATE_SHIFT 8 #define OMAP4430_AESSMEM_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_ABE_PWRSTST */ -#define OMAP4430_AESSMEM_STATEST_SHIFT (1 << 4) +#define OMAP4430_AESSMEM_STATEST_SHIFT 4 #define OMAP4430_AESSMEM_STATEST_MASK BITFIELD(4, 5) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ -#define OMAP4430_AIPOFF_SHIFT (1 << 8) +#define OMAP4430_AIPOFF_SHIFT 8 #define OMAP4430_AIPOFF_MASK BITFIELD(8, 8) /* Used by PRM_VOLTCTRL */ -#define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT (1 << 0) +#define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT 0 #define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK BITFIELD(0, 1) /* Used by PRM_VOLTCTRL */ -#define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT (1 << 4) +#define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT 4 #define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK BITFIELD(4, 5) /* Used by PRM_VOLTCTRL */ -#define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT (1 << 2) +#define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT 2 #define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK BITFIELD(2, 3) /* Used by PM_CAM_PWRSTCTRL */ -#define OMAP4430_CAM_MEM_ONSTATE_SHIFT (1 << 16) +#define OMAP4430_CAM_MEM_ONSTATE_SHIFT 16 #define OMAP4430_CAM_MEM_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_CAM_PWRSTST */ -#define OMAP4430_CAM_MEM_STATEST_SHIFT (1 << 4) +#define OMAP4430_CAM_MEM_STATEST_SHIFT 4 #define OMAP4430_CAM_MEM_STATEST_MASK BITFIELD(4, 5) /* Used by PRM_CLKREQCTRL */ -#define OMAP4430_CLKREQ_COND_SHIFT (1 << 0) +#define OMAP4430_CLKREQ_COND_SHIFT 0 #define OMAP4430_CLKREQ_COND_MASK BITFIELD(0, 2) /* Used by PRM_VC_VAL_SMPS_RA_CMD */ -#define OMAP4430_CMDRA_VDD_CORE_L_SHIFT (1 << 0) +#define OMAP4430_CMDRA_VDD_CORE_L_SHIFT 0 #define OMAP4430_CMDRA_VDD_CORE_L_MASK BITFIELD(0, 7) /* Used by PRM_VC_VAL_SMPS_RA_CMD */ -#define OMAP4430_CMDRA_VDD_IVA_L_SHIFT (1 << 8) +#define OMAP4430_CMDRA_VDD_IVA_L_SHIFT 8 #define OMAP4430_CMDRA_VDD_IVA_L_MASK BITFIELD(8, 15) /* Used by PRM_VC_VAL_SMPS_RA_CMD */ -#define OMAP4430_CMDRA_VDD_MPU_L_SHIFT (1 << 16) +#define OMAP4430_CMDRA_VDD_MPU_L_SHIFT 16 #define OMAP4430_CMDRA_VDD_MPU_L_MASK BITFIELD(16, 23) /* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_CMD_VDD_CORE_L_SHIFT (1 << 4) +#define OMAP4430_CMD_VDD_CORE_L_SHIFT 4 #define OMAP4430_CMD_VDD_CORE_L_MASK BITFIELD(4, 4) /* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_CMD_VDD_IVA_L_SHIFT (1 << 12) +#define OMAP4430_CMD_VDD_IVA_L_SHIFT 12 #define OMAP4430_CMD_VDD_IVA_L_MASK BITFIELD(12, 12) /* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_CMD_VDD_MPU_L_SHIFT (1 << 17) +#define OMAP4430_CMD_VDD_MPU_L_SHIFT 17 #define OMAP4430_CMD_VDD_MPU_L_MASK BITFIELD(17, 17) /* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT (1 << 18) +#define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18 #define OMAP4430_CORE_OCMRAM_ONSTATE_MASK BITFIELD(18, 19) /* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT (1 << 9) +#define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9 #define OMAP4430_CORE_OCMRAM_RETSTATE_MASK BITFIELD(9, 9) /* Used by PM_CORE_PWRSTST */ -#define OMAP4430_CORE_OCMRAM_STATEST_SHIFT (1 << 6) +#define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6 #define OMAP4430_CORE_OCMRAM_STATEST_MASK BITFIELD(6, 7) /* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT (1 << 16) +#define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16 #define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT (1 << 8) +#define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8 #define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_CORE_PWRSTST */ -#define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT (1 << 4) +#define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4 #define OMAP4430_CORE_OTHER_BANK_STATEST_MASK BITFIELD(4, 5) /* Used by PRM_VC_VAL_BYPASS */ -#define OMAP4430_DATA_SHIFT (1 << 16) +#define OMAP4430_DATA_SHIFT 16 #define OMAP4430_DATA_MASK BITFIELD(16, 23) /* Used by PRM_DEVICE_OFF_CTRL */ -#define OMAP4430_DEVICE_OFF_ENABLE_SHIFT (1 << 0) +#define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0 #define OMAP4430_DEVICE_OFF_ENABLE_MASK BITFIELD(0, 0) /* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP4430_DFILTEREN_SHIFT (1 << 6) +#define OMAP4430_DFILTEREN_SHIFT 6 #define OMAP4430_DFILTEREN_MASK BITFIELD(6, 6) /* Used by PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ -#define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT (1 << 4) +#define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4 #define OMAP4430_DPLL_ABE_RECAL_EN_MASK BITFIELD(4, 4) /* Used by PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ -#define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT (1 << 4) +#define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4 #define OMAP4430_DPLL_ABE_RECAL_ST_MASK BITFIELD(4, 4) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT (1 << 0) +#define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0 #define OMAP4430_DPLL_CORE_RECAL_EN_MASK BITFIELD(0, 0) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT (1 << 0) +#define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0 #define OMAP4430_DPLL_CORE_RECAL_ST_MASK BITFIELD(0, 0) /* Used by PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT (1 << 6) +#define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6 #define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK BITFIELD(6, 6) /* Used by PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT (1 << 6) +#define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6 #define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK BITFIELD(6, 6) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ -#define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT (1 << 2) +#define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2 #define OMAP4430_DPLL_IVA_RECAL_EN_MASK BITFIELD(2, 2) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ -#define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT (1 << 2) +#define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2 #define OMAP4430_DPLL_IVA_RECAL_ST_MASK BITFIELD(2, 2) /* Used by PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT (1 << 1) +#define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1 #define OMAP4430_DPLL_MPU_RECAL_EN_MASK BITFIELD(1, 1) /* Used by PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT (1 << 1) +#define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1 #define OMAP4430_DPLL_MPU_RECAL_ST_MASK BITFIELD(1, 1) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_PER_RECAL_EN_SHIFT (1 << 3) +#define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3 #define OMAP4430_DPLL_PER_RECAL_EN_MASK BITFIELD(3, 3) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_PER_RECAL_ST_SHIFT (1 << 3) +#define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3 #define OMAP4430_DPLL_PER_RECAL_ST_MASK BITFIELD(3, 3) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT (1 << 7) +#define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7 #define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK BITFIELD(7, 7) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT (1 << 7) +#define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7 #define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK BITFIELD(7, 7) /* Used by PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_USB_RECAL_EN_SHIFT (1 << 5) +#define OMAP4430_DPLL_USB_RECAL_EN_SHIFT 5 #define OMAP4430_DPLL_USB_RECAL_EN_MASK BITFIELD(5, 5) /* Used by PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_USB_RECAL_ST_SHIFT (1 << 5) +#define OMAP4430_DPLL_USB_RECAL_ST_SHIFT 5 #define OMAP4430_DPLL_USB_RECAL_ST_MASK BITFIELD(5, 5) /* Used by PM_DSS_PWRSTCTRL */ -#define OMAP4430_DSS_MEM_ONSTATE_SHIFT (1 << 16) +#define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16 #define OMAP4430_DSS_MEM_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_DSS_PWRSTCTRL */ -#define OMAP4430_DSS_MEM_RETSTATE_SHIFT (1 << 8) +#define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8 #define OMAP4430_DSS_MEM_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_DSS_PWRSTST */ -#define OMAP4430_DSS_MEM_STATEST_SHIFT (1 << 4) +#define OMAP4430_DSS_MEM_STATEST_SHIFT 4 #define OMAP4430_DSS_MEM_STATEST_MASK BITFIELD(4, 5) /* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT (1 << 20) +#define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20 #define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK BITFIELD(20, 21) /* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT (1 << 10) +#define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10 #define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK BITFIELD(10, 10) /* Used by PM_CORE_PWRSTST */ -#define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT (1 << 8) +#define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8 #define OMAP4430_DUCATI_L2RAM_STATEST_MASK BITFIELD(8, 9) /* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT (1 << 22) +#define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22 #define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK BITFIELD(22, 23) /* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT (1 << 11) +#define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11 #define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK BITFIELD(11, 11) /* Used by PM_CORE_PWRSTST */ -#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT (1 << 10) +#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10 #define OMAP4430_DUCATI_UNICACHE_STATEST_MASK BITFIELD(10, 11) /* Used by RM_MPU_RSTST */ -#define OMAP4430_EMULATION_RST_SHIFT (1 << 0) +#define OMAP4430_EMULATION_RST_SHIFT 0 #define OMAP4430_EMULATION_RST_MASK BITFIELD(0, 0) /* Used by RM_DUCATI_RSTST */ -#define OMAP4430_EMULATION_RST1ST_SHIFT (1 << 3) +#define OMAP4430_EMULATION_RST1ST_SHIFT 3 #define OMAP4430_EMULATION_RST1ST_MASK BITFIELD(3, 3) /* Used by RM_DUCATI_RSTST */ -#define OMAP4430_EMULATION_RST2ST_SHIFT (1 << 4) +#define OMAP4430_EMULATION_RST2ST_SHIFT 4 #define OMAP4430_EMULATION_RST2ST_MASK BITFIELD(4, 4) /* Used by RM_IVAHD_RSTST */ -#define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT (1 << 3) +#define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3 #define OMAP4430_EMULATION_SEQ1_RST1ST_MASK BITFIELD(3, 3) /* Used by RM_IVAHD_RSTST */ -#define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT (1 << 4) +#define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4 #define OMAP4430_EMULATION_SEQ2_RST2ST_MASK BITFIELD(4, 4) /* Used by PM_EMU_PWRSTCTRL */ -#define OMAP4430_EMU_BANK_ONSTATE_SHIFT (1 << 16) +#define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16 #define OMAP4430_EMU_BANK_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_EMU_PWRSTST */ -#define OMAP4430_EMU_BANK_STATEST_SHIFT (1 << 4) +#define OMAP4430_EMU_BANK_STATEST_SHIFT 4 #define OMAP4430_EMU_BANK_STATEST_MASK BITFIELD(4, 5) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP */ -#define OMAP4430_ENABLE_RTA_EXPORT_SHIFT (1 << 0) +#define OMAP4430_ENABLE_RTA_EXPORT_SHIFT 0 #define OMAP4430_ENABLE_RTA_EXPORT_MASK BITFIELD(0, 0) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ -#define OMAP4430_ENFUNC1_SHIFT (1 << 3) +#define OMAP4430_ENFUNC1_SHIFT 3 #define OMAP4430_ENFUNC1_MASK BITFIELD(3, 3) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ -#define OMAP4430_ENFUNC3_SHIFT (1 << 5) +#define OMAP4430_ENFUNC3_SHIFT 5 #define OMAP4430_ENFUNC3_MASK BITFIELD(5, 5) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ -#define OMAP4430_ENFUNC4_SHIFT (1 << 6) +#define OMAP4430_ENFUNC4_SHIFT 6 #define OMAP4430_ENFUNC4_MASK BITFIELD(6, 6) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ -#define OMAP4430_ENFUNC5_SHIFT (1 << 7) +#define OMAP4430_ENFUNC5_SHIFT 7 #define OMAP4430_ENFUNC5_MASK BITFIELD(7, 7) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_ERRORGAIN_SHIFT (1 << 16) +#define OMAP4430_ERRORGAIN_SHIFT 16 #define OMAP4430_ERRORGAIN_MASK BITFIELD(16, 23) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_ERROROFFSET_SHIFT (1 << 24) +#define OMAP4430_ERROROFFSET_SHIFT 24 #define OMAP4430_ERROROFFSET_MASK BITFIELD(24, 31) /* Used by PRM_RSTST */ -#define OMAP4430_EXTERNAL_WARM_RST_SHIFT (1 << 5) +#define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 #define OMAP4430_EXTERNAL_WARM_RST_MASK BITFIELD(5, 5) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_FORCEUPDATE_SHIFT (1 << 1) +#define OMAP4430_FORCEUPDATE_SHIFT 1 #define OMAP4430_FORCEUPDATE_MASK BITFIELD(1, 1) /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ -#define OMAP4430_FORCEUPDATEWAIT_SHIFT (1 << 8) +#define OMAP4430_FORCEUPDATEWAIT_SHIFT 8 #define OMAP4430_FORCEUPDATEWAIT_MASK BITFIELD(8, 31) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */ -#define OMAP4430_FORCEWKUP_EN_SHIFT (1 << 10) +#define OMAP4430_FORCEWKUP_EN_SHIFT 10 #define OMAP4430_FORCEWKUP_EN_MASK BITFIELD(10, 10) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */ -#define OMAP4430_FORCEWKUP_ST_SHIFT (1 << 10) +#define OMAP4430_FORCEWKUP_ST_SHIFT 10 #define OMAP4430_FORCEWKUP_ST_MASK BITFIELD(10, 10) /* Used by PM_GFX_PWRSTCTRL */ -#define OMAP4430_GFX_MEM_ONSTATE_SHIFT (1 << 16) +#define OMAP4430_GFX_MEM_ONSTATE_SHIFT 16 #define OMAP4430_GFX_MEM_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_GFX_PWRSTST */ -#define OMAP4430_GFX_MEM_STATEST_SHIFT (1 << 4) +#define OMAP4430_GFX_MEM_STATEST_SHIFT 4 #define OMAP4430_GFX_MEM_STATEST_MASK BITFIELD(4, 5) /* Used by PRM_RSTST */ -#define OMAP4430_GLOBAL_COLD_RST_SHIFT (1 << 0) +#define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 #define OMAP4430_GLOBAL_COLD_RST_MASK BITFIELD(0, 0) /* Used by PRM_RSTST */ -#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT (1 << 1) +#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 #define OMAP4430_GLOBAL_WARM_SW_RST_MASK BITFIELD(1, 1) /* Used by PRM_IO_PMCTRL */ -#define OMAP4430_GLOBAL_WUEN_SHIFT (1 << 16) +#define OMAP4430_GLOBAL_WUEN_SHIFT 16 #define OMAP4430_GLOBAL_WUEN_MASK BITFIELD(16, 16) /* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP4430_HSMCODE_SHIFT (1 << 0) +#define OMAP4430_HSMCODE_SHIFT 0 #define OMAP4430_HSMCODE_MASK BITFIELD(0, 2) /* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP4430_HSMODEEN_SHIFT (1 << 3) +#define OMAP4430_HSMODEEN_SHIFT 3 #define OMAP4430_HSMODEEN_MASK BITFIELD(3, 3) /* Used by PRM_VC_CFG_I2C_CLK */ -#define OMAP4430_HSSCLH_SHIFT (1 << 16) +#define OMAP4430_HSSCLH_SHIFT 16 #define OMAP4430_HSSCLH_MASK BITFIELD(16, 23) /* Used by PRM_VC_CFG_I2C_CLK */ -#define OMAP4430_HSSCLL_SHIFT (1 << 24) +#define OMAP4430_HSSCLL_SHIFT 24 #define OMAP4430_HSSCLL_MASK BITFIELD(24, 31) /* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_HWA_MEM_ONSTATE_SHIFT (1 << 16) +#define OMAP4430_HWA_MEM_ONSTATE_SHIFT 16 #define OMAP4430_HWA_MEM_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_HWA_MEM_RETSTATE_SHIFT (1 << 8) +#define OMAP4430_HWA_MEM_RETSTATE_SHIFT 8 #define OMAP4430_HWA_MEM_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_IVAHD_PWRSTST */ -#define OMAP4430_HWA_MEM_STATEST_SHIFT (1 << 4) +#define OMAP4430_HWA_MEM_STATEST_SHIFT 4 #define OMAP4430_HWA_MEM_STATEST_MASK BITFIELD(4, 5) /* Used by RM_MPU_RSTST */ -#define OMAP4430_ICECRUSHER_MPU_RST_SHIFT (1 << 1) +#define OMAP4430_ICECRUSHER_MPU_RST_SHIFT 1 #define OMAP4430_ICECRUSHER_MPU_RST_MASK BITFIELD(1, 1) /* Used by RM_DUCATI_RSTST */ -#define OMAP4430_ICECRUSHER_RST1ST_SHIFT (1 << 5) +#define OMAP4430_ICECRUSHER_RST1ST_SHIFT 5 #define OMAP4430_ICECRUSHER_RST1ST_MASK BITFIELD(5, 5) /* Used by RM_DUCATI_RSTST */ -#define OMAP4430_ICECRUSHER_RST2ST_SHIFT (1 << 6) +#define OMAP4430_ICECRUSHER_RST2ST_SHIFT 6 #define OMAP4430_ICECRUSHER_RST2ST_MASK BITFIELD(6, 6) /* Used by RM_IVAHD_RSTST */ -#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT (1 << 5) +#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT 5 #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK BITFIELD(5, 5) /* Used by RM_IVAHD_RSTST */ -#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT (1 << 6) +#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT 6 #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK BITFIELD(6, 6) /* Used by PRM_RSTST */ -#define OMAP4430_ICEPICK_RST_SHIFT (1 << 9) +#define OMAP4430_ICEPICK_RST_SHIFT 9 #define OMAP4430_ICEPICK_RST_MASK BITFIELD(9, 9) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_INITVDD_SHIFT (1 << 2) +#define OMAP4430_INITVDD_SHIFT 2 #define OMAP4430_INITVDD_MASK BITFIELD(2, 2) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_INITVOLTAGE_SHIFT (1 << 8) +#define OMAP4430_INITVOLTAGE_SHIFT 8 #define OMAP4430_INITVOLTAGE_MASK BITFIELD(8, 15) /* @@ -442,47 +442,47 @@ * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST */ -#define OMAP4430_INTRANSITION_SHIFT (1 << 20) +#define OMAP4430_INTRANSITION_SHIFT 20 #define OMAP4430_INTRANSITION_MASK BITFIELD(20, 20) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_IO_EN_SHIFT (1 << 9) +#define OMAP4430_IO_EN_SHIFT 9 #define OMAP4430_IO_EN_MASK BITFIELD(9, 9) /* Used by PRM_IO_PMCTRL */ -#define OMAP4430_IO_ON_STATUS_SHIFT (1 << 5) +#define OMAP4430_IO_ON_STATUS_SHIFT 5 #define OMAP4430_IO_ON_STATUS_MASK BITFIELD(5, 5) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_IO_ST_SHIFT (1 << 9) +#define OMAP4430_IO_ST_SHIFT 9 #define OMAP4430_IO_ST_MASK BITFIELD(9, 9) /* Used by PRM_IO_PMCTRL */ -#define OMAP4430_ISOCLK_OVERRIDE_SHIFT (1 << 0) +#define OMAP4430_ISOCLK_OVERRIDE_SHIFT 0 #define OMAP4430_ISOCLK_OVERRIDE_MASK BITFIELD(0, 0) /* Used by PRM_IO_PMCTRL */ -#define OMAP4430_ISOCLK_STATUS_SHIFT (1 << 1) +#define OMAP4430_ISOCLK_STATUS_SHIFT 1 #define OMAP4430_ISOCLK_STATUS_MASK BITFIELD(1, 1) /* Used by PRM_IO_PMCTRL */ -#define OMAP4430_ISOOVR_EXTEND_SHIFT (1 << 4) +#define OMAP4430_ISOOVR_EXTEND_SHIFT 4 #define OMAP4430_ISOOVR_EXTEND_MASK BITFIELD(4, 4) /* Used by PRM_IO_COUNT */ -#define OMAP4430_ISO_2_ON_TIME_SHIFT (1 << 0) +#define OMAP4430_ISO_2_ON_TIME_SHIFT 0 #define OMAP4430_ISO_2_ON_TIME_MASK BITFIELD(0, 7) /* Used by PM_L3INIT_PWRSTCTRL */ -#define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT (1 << 16) +#define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT 16 #define OMAP4430_L3INIT_BANK1_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_L3INIT_PWRSTCTRL */ -#define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT (1 << 8) +#define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT 8 #define OMAP4430_L3INIT_BANK1_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_L3INIT_PWRSTST */ -#define OMAP4430_L3INIT_BANK1_STATEST_SHIFT (1 << 4) +#define OMAP4430_L3INIT_BANK1_STATEST_SHIFT 4 #define OMAP4430_L3INIT_BANK1_STATEST_MASK BITFIELD(4, 5) /* @@ -490,7 +490,7 @@ * PM_MPU_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, * PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_LOGICRETSTATE_SHIFT (1 << 2) +#define OMAP4430_LOGICRETSTATE_SHIFT 2 #define OMAP4430_LOGICRETSTATE_MASK BITFIELD(2, 2) /* @@ -498,7 +498,7 @@ * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST */ -#define OMAP4430_LOGICSTATEST_SHIFT (1 << 2) +#define OMAP4430_LOGICSTATEST_SHIFT 2 #define OMAP4430_LOGICSTATEST_MASK BITFIELD(2, 2) /* @@ -537,7 +537,7 @@ * RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT, * RM_TESLA_TESLA_CONTEXT, RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT */ -#define OMAP4430_LOSTCONTEXT_DFF_SHIFT (1 << 0) +#define OMAP4430_LOSTCONTEXT_DFF_SHIFT 0 #define OMAP4430_LOSTCONTEXT_DFF_MASK BITFIELD(0, 0) /* @@ -558,58 +558,58 @@ * RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, RM_L4SEC_DES3DES_CONTEXT, * RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, RM_TESLA_TESLA_CONTEXT */ -#define OMAP4430_LOSTCONTEXT_RFF_SHIFT (1 << 1) +#define OMAP4430_LOSTCONTEXT_RFF_SHIFT 1 #define OMAP4430_LOSTCONTEXT_RFF_MASK BITFIELD(1, 1) /* Used by RM_ABE_AESS_CONTEXT */ -#define OMAP4430_LOSTMEM_AESSMEM_SHIFT (1 << 8) +#define OMAP4430_LOSTMEM_AESSMEM_SHIFT 8 #define OMAP4430_LOSTMEM_AESSMEM_MASK BITFIELD(8, 8) /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ -#define OMAP4430_LOSTMEM_CAM_MEM_SHIFT (1 << 8) +#define OMAP4430_LOSTMEM_CAM_MEM_SHIFT 8 #define OMAP4430_LOSTMEM_CAM_MEM_MASK BITFIELD(8, 8) /* Used by RM_L3INSTR_OCP_WP1_CONTEXT */ -#define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT (1 << 8) +#define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT 8 #define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK BITFIELD(8, 8) /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */ -#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT (1 << 9) +#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT 9 #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK BITFIELD(9, 9) /* Used by RM_L3_2_OCMC_RAM_CONTEXT */ -#define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT (1 << 8) +#define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT 8 #define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK BITFIELD(8, 8) /* * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT, * RM_SDMA_SDMA_CONTEXT */ -#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT (1 << 8) +#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK BITFIELD(8, 8) /* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */ -#define OMAP4430_LOSTMEM_DSS_MEM_SHIFT (1 << 8) +#define OMAP4430_LOSTMEM_DSS_MEM_SHIFT 8 #define OMAP4430_LOSTMEM_DSS_MEM_MASK BITFIELD(8, 8) /* Used by RM_DUCATI_DUCATI_CONTEXT */ -#define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT (1 << 9) +#define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT 9 #define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK BITFIELD(9, 9) /* Used by RM_DUCATI_DUCATI_CONTEXT */ -#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT (1 << 8) +#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT 8 #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK BITFIELD(8, 8) /* Used by RM_EMU_DEBUGSS_CONTEXT */ -#define OMAP4430_LOSTMEM_EMU_BANK_SHIFT (1 << 8) +#define OMAP4430_LOSTMEM_EMU_BANK_SHIFT 8 #define OMAP4430_LOSTMEM_EMU_BANK_MASK BITFIELD(8, 8) /* Used by RM_GFX_GFX_CONTEXT */ -#define OMAP4430_LOSTMEM_GFX_MEM_SHIFT (1 << 8) +#define OMAP4430_LOSTMEM_GFX_MEM_SHIFT 8 #define OMAP4430_LOSTMEM_GFX_MEM_MASK BITFIELD(8, 8) /* Used by RM_IVAHD_IVAHD_CONTEXT */ -#define OMAP4430_LOSTMEM_HWA_MEM_SHIFT (1 << 10) +#define OMAP4430_LOSTMEM_HWA_MEM_SHIFT 10 #define OMAP4430_LOSTMEM_HWA_MEM_MASK BITFIELD(10, 10) /* @@ -619,19 +619,19 @@ * RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT */ -#define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT (1 << 8) +#define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT 8 #define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK BITFIELD(8, 8) /* Used by RM_MPU_MPU_CONTEXT */ -#define OMAP4430_LOSTMEM_MPU_L1_SHIFT (1 << 8) +#define OMAP4430_LOSTMEM_MPU_L1_SHIFT 8 #define OMAP4430_LOSTMEM_MPU_L1_MASK BITFIELD(8, 8) /* Used by RM_MPU_MPU_CONTEXT */ -#define OMAP4430_LOSTMEM_MPU_L2_SHIFT (1 << 9) +#define OMAP4430_LOSTMEM_MPU_L2_SHIFT 9 #define OMAP4430_LOSTMEM_MPU_L2_MASK BITFIELD(9, 9) /* Used by RM_MPU_MPU_CONTEXT */ -#define OMAP4430_LOSTMEM_MPU_RAM_SHIFT (1 << 10) +#define OMAP4430_LOSTMEM_MPU_RAM_SHIFT 10 #define OMAP4430_LOSTMEM_MPU_RAM_MASK BITFIELD(10, 10) /* @@ -639,14 +639,14 @@ * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT */ -#define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT (1 << 8) +#define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT 8 #define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK BITFIELD(8, 8) /* * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT */ -#define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT (1 << 8) +#define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT 8 #define OMAP4430_LOSTMEM_PERIHPMEM_MASK BITFIELD(8, 8) /* @@ -654,35 +654,35 @@ * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, * RM_L4SEC_CRYPTODMA_CONTEXT */ -#define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT (1 << 8) +#define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT 8 #define OMAP4430_LOSTMEM_RETAINED_BANK_MASK BITFIELD(8, 8) /* Used by RM_IVAHD_SL2_CONTEXT */ -#define OMAP4430_LOSTMEM_SL2_MEM_SHIFT (1 << 8) +#define OMAP4430_LOSTMEM_SL2_MEM_SHIFT 8 #define OMAP4430_LOSTMEM_SL2_MEM_MASK BITFIELD(8, 8) /* Used by RM_IVAHD_IVAHD_CONTEXT */ -#define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT (1 << 8) +#define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT 8 #define OMAP4430_LOSTMEM_TCM1_MEM_MASK BITFIELD(8, 8) /* Used by RM_IVAHD_IVAHD_CONTEXT */ -#define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT (1 << 9) +#define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT 9 #define OMAP4430_LOSTMEM_TCM2_MEM_MASK BITFIELD(9, 9) /* Used by RM_TESLA_TESLA_CONTEXT */ -#define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT (1 << 10) +#define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT 10 #define OMAP4430_LOSTMEM_TESLA_EDMA_MASK BITFIELD(10, 10) /* Used by RM_TESLA_TESLA_CONTEXT */ -#define OMAP4430_LOSTMEM_TESLA_L1_SHIFT (1 << 8) +#define OMAP4430_LOSTMEM_TESLA_L1_SHIFT 8 #define OMAP4430_LOSTMEM_TESLA_L1_MASK BITFIELD(8, 8) /* Used by RM_TESLA_TESLA_CONTEXT */ -#define OMAP4430_LOSTMEM_TESLA_L2_SHIFT (1 << 9) +#define OMAP4430_LOSTMEM_TESLA_L2_SHIFT 9 #define OMAP4430_LOSTMEM_TESLA_L2_MASK BITFIELD(9, 9) /* Used by RM_WKUP_SARRAM_CONTEXT */ -#define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT (1 << 8) +#define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT 8 #define OMAP4430_LOSTMEM_WKUP_BANK_MASK BITFIELD(8, 8) /* @@ -690,164 +690,164 @@ * PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, * PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_LOWPOWERSTATECHANGE_SHIFT (1 << 4) +#define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 #define OMAP4430_LOWPOWERSTATECHANGE_MASK BITFIELD(4, 4) /* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_MEMORYCHANGE_SHIFT (1 << 3) +#define OMAP4430_MEMORYCHANGE_SHIFT 3 #define OMAP4430_MEMORYCHANGE_MASK BITFIELD(3, 3) /* Used by PRM_MODEM_IF_CTRL */ -#define OMAP4430_MODEM_READY_SHIFT (1 << 1) +#define OMAP4430_MODEM_READY_SHIFT 1 #define OMAP4430_MODEM_READY_MASK BITFIELD(1, 1) /* Used by PRM_MODEM_IF_CTRL */ -#define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT (1 << 9) +#define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9 #define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK BITFIELD(9, 9) /* Used by PRM_MODEM_IF_CTRL */ -#define OMAP4430_MODEM_SLEEP_ST_SHIFT (1 << 16) +#define OMAP4430_MODEM_SLEEP_ST_SHIFT 16 #define OMAP4430_MODEM_SLEEP_ST_MASK BITFIELD(16, 16) /* Used by PRM_MODEM_IF_CTRL */ -#define OMAP4430_MODEM_WAKE_IRQ_SHIFT (1 << 8) +#define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8 #define OMAP4430_MODEM_WAKE_IRQ_MASK BITFIELD(8, 8) /* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_L1_ONSTATE_SHIFT (1 << 16) +#define OMAP4430_MPU_L1_ONSTATE_SHIFT 16 #define OMAP4430_MPU_L1_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_L1_RETSTATE_SHIFT (1 << 8) +#define OMAP4430_MPU_L1_RETSTATE_SHIFT 8 #define OMAP4430_MPU_L1_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_MPU_PWRSTST */ -#define OMAP4430_MPU_L1_STATEST_SHIFT (1 << 4) +#define OMAP4430_MPU_L1_STATEST_SHIFT 4 #define OMAP4430_MPU_L1_STATEST_MASK BITFIELD(4, 5) /* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_L2_ONSTATE_SHIFT (1 << 18) +#define OMAP4430_MPU_L2_ONSTATE_SHIFT 18 #define OMAP4430_MPU_L2_ONSTATE_MASK BITFIELD(18, 19) /* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_L2_RETSTATE_SHIFT (1 << 9) +#define OMAP4430_MPU_L2_RETSTATE_SHIFT 9 #define OMAP4430_MPU_L2_RETSTATE_MASK BITFIELD(9, 9) /* Used by PM_MPU_PWRSTST */ -#define OMAP4430_MPU_L2_STATEST_SHIFT (1 << 6) +#define OMAP4430_MPU_L2_STATEST_SHIFT 6 #define OMAP4430_MPU_L2_STATEST_MASK BITFIELD(6, 7) /* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_RAM_ONSTATE_SHIFT (1 << 20) +#define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20 #define OMAP4430_MPU_RAM_ONSTATE_MASK BITFIELD(20, 21) /* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_RAM_RETSTATE_SHIFT (1 << 10) +#define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10 #define OMAP4430_MPU_RAM_RETSTATE_MASK BITFIELD(10, 10) /* Used by PM_MPU_PWRSTST */ -#define OMAP4430_MPU_RAM_STATEST_SHIFT (1 << 8) +#define OMAP4430_MPU_RAM_STATEST_SHIFT 8 #define OMAP4430_MPU_RAM_STATEST_MASK BITFIELD(8, 9) /* Used by PRM_RSTST */ -#define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT (1 << 2) +#define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 #define OMAP4430_MPU_SECURITY_VIOL_RST_MASK BITFIELD(2, 2) /* Used by PRM_RSTST */ -#define OMAP4430_MPU_WDT_RST_SHIFT (1 << 3) +#define OMAP4430_MPU_WDT_RST_SHIFT 3 #define OMAP4430_MPU_WDT_RST_MASK BITFIELD(3, 3) /* Used by PM_L4PER_PWRSTCTRL */ -#define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT (1 << 18) +#define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18 #define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK BITFIELD(18, 19) /* Used by PM_L4PER_PWRSTCTRL */ -#define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT (1 << 9) +#define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9 #define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK BITFIELD(9, 9) /* Used by PM_L4PER_PWRSTST */ -#define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT (1 << 6) +#define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6 #define OMAP4430_NONRETAINED_BANK_STATEST_MASK BITFIELD(6, 7) /* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT (1 << 24) +#define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24 #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK BITFIELD(24, 25) /* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT (1 << 12) +#define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12 #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK BITFIELD(12, 12) /* Used by PM_CORE_PWRSTST */ -#define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT (1 << 12) +#define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT 12 #define OMAP4430_OCP_NRET_BANK_STATEST_MASK BITFIELD(12, 13) /* * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, * PRM_VC_VAL_CMD_VDD_MPU_L */ -#define OMAP4430_OFF_SHIFT (1 << 0) +#define OMAP4430_OFF_SHIFT 0 #define OMAP4430_OFF_MASK BITFIELD(0, 7) /* Used by PRM_LDO_BANDGAP_CTRL */ -#define OMAP4430_OFF_ENABLE_SHIFT (1 << 0) +#define OMAP4430_OFF_ENABLE_SHIFT 0 #define OMAP4430_OFF_ENABLE_MASK BITFIELD(0, 0) /* * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, * PRM_VC_VAL_CMD_VDD_MPU_L */ -#define OMAP4430_ON_SHIFT (1 << 24) +#define OMAP4430_ON_SHIFT 24 #define OMAP4430_ON_MASK BITFIELD(24, 31) /* * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, * PRM_VC_VAL_CMD_VDD_MPU_L */ -#define OMAP4430_ONLP_SHIFT (1 << 16) +#define OMAP4430_ONLP_SHIFT 16 #define OMAP4430_ONLP_MASK BITFIELD(16, 23) /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ -#define OMAP4430_OPP_CHANGE_SHIFT (1 << 2) +#define OMAP4430_OPP_CHANGE_SHIFT 2 #define OMAP4430_OPP_CHANGE_MASK BITFIELD(2, 2) /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ -#define OMAP4430_OPP_SEL_SHIFT (1 << 0) +#define OMAP4430_OPP_SEL_SHIFT 0 #define OMAP4430_OPP_SEL_MASK BITFIELD(0, 1) /* Used by PRM_SRAM_COUNT */ -#define OMAP4430_PCHARGECNT_VALUE_SHIFT (1 << 0) +#define OMAP4430_PCHARGECNT_VALUE_SHIFT 0 #define OMAP4430_PCHARGECNT_VALUE_MASK BITFIELD(0, 5) /* Used by PRM_PSCON_COUNT */ -#define OMAP4430_PCHARGE_TIME_SHIFT (1 << 0) +#define OMAP4430_PCHARGE_TIME_SHIFT 0 #define OMAP4430_PCHARGE_TIME_MASK BITFIELD(0, 7) /* Used by PM_ABE_PWRSTCTRL */ -#define OMAP4430_PERIPHMEM_ONSTATE_SHIFT (1 << 20) +#define OMAP4430_PERIPHMEM_ONSTATE_SHIFT 20 #define OMAP4430_PERIPHMEM_ONSTATE_MASK BITFIELD(20, 21) /* Used by PM_ABE_PWRSTCTRL */ -#define OMAP4430_PERIPHMEM_RETSTATE_SHIFT (1 << 10) +#define OMAP4430_PERIPHMEM_RETSTATE_SHIFT 10 #define OMAP4430_PERIPHMEM_RETSTATE_MASK BITFIELD(10, 10) /* Used by PM_ABE_PWRSTST */ -#define OMAP4430_PERIPHMEM_STATEST_SHIFT (1 << 8) +#define OMAP4430_PERIPHMEM_STATEST_SHIFT 8 #define OMAP4430_PERIPHMEM_STATEST_MASK BITFIELD(8, 9) /* Used by PRM_PHASE1_CNDP */ -#define OMAP4430_PHASE1_CNDP_SHIFT (1 << 0) +#define OMAP4430_PHASE1_CNDP_SHIFT 0 #define OMAP4430_PHASE1_CNDP_MASK BITFIELD(0, 31) /* Used by PRM_PHASE2A_CNDP */ -#define OMAP4430_PHASE2A_CNDP_SHIFT (1 << 0) +#define OMAP4430_PHASE2A_CNDP_SHIFT 0 #define OMAP4430_PHASE2A_CNDP_MASK BITFIELD(0, 31) /* Used by PRM_PHASE2B_CNDP */ -#define OMAP4430_PHASE2B_CNDP_SHIFT (1 << 0) +#define OMAP4430_PHASE2B_CNDP_SHIFT 0 #define OMAP4430_PHASE2B_CNDP_MASK BITFIELD(0, 31) /* Used by PRM_PSCON_COUNT */ -#define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT (1 << 8) +#define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT 8 #define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK BITFIELD(8, 15) /* @@ -856,7 +856,7 @@ * PM_CEFUSE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, * PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_POWERSTATE_SHIFT (1 << 0) +#define OMAP4430_POWERSTATE_SHIFT 0 #define OMAP4430_POWERSTATE_MASK BITFIELD(0, 1) /* @@ -864,35 +864,35 @@ * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST */ -#define OMAP4430_POWERSTATEST_SHIFT (1 << 0) +#define OMAP4430_POWERSTATEST_SHIFT 0 #define OMAP4430_POWERSTATEST_MASK BITFIELD(0, 1) /* Used by PRM_PWRREQCTRL */ -#define OMAP4430_PWRREQ_COND_SHIFT (1 << 0) +#define OMAP4430_PWRREQ_COND_SHIFT 0 #define OMAP4430_PWRREQ_COND_MASK BITFIELD(0, 1) /* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RACEN_VDD_CORE_L_SHIFT (1 << 3) +#define OMAP4430_RACEN_VDD_CORE_L_SHIFT 3 #define OMAP4430_RACEN_VDD_CORE_L_MASK BITFIELD(3, 3) /* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RACEN_VDD_IVA_L_SHIFT (1 << 11) +#define OMAP4430_RACEN_VDD_IVA_L_SHIFT 11 #define OMAP4430_RACEN_VDD_IVA_L_MASK BITFIELD(11, 11) /* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RACEN_VDD_MPU_L_SHIFT (1 << 20) +#define OMAP4430_RACEN_VDD_MPU_L_SHIFT 20 #define OMAP4430_RACEN_VDD_MPU_L_MASK BITFIELD(20, 20) /* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAC_VDD_CORE_L_SHIFT (1 << 2) +#define OMAP4430_RAC_VDD_CORE_L_SHIFT 2 #define OMAP4430_RAC_VDD_CORE_L_MASK BITFIELD(2, 2) /* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAC_VDD_IVA_L_SHIFT (1 << 10) +#define OMAP4430_RAC_VDD_IVA_L_SHIFT 10 #define OMAP4430_RAC_VDD_IVA_L_MASK BITFIELD(10, 10) /* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAC_VDD_MPU_L_SHIFT (1 << 19) +#define OMAP4430_RAC_VDD_MPU_L_SHIFT 19 #define OMAP4430_RAC_VDD_MPU_L_MASK BITFIELD(19, 19) /* @@ -900,7 +900,7 @@ * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, * PRM_VOLTSETUP_MPU_RET_SLEEP */ -#define OMAP4430_RAMP_DOWN_COUNT_SHIFT (1 << 16) +#define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 #define OMAP4430_RAMP_DOWN_COUNT_MASK BITFIELD(16, 21) /* @@ -908,7 +908,7 @@ * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, * PRM_VOLTSETUP_MPU_RET_SLEEP */ -#define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT (1 << 24) +#define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT 24 #define OMAP4430_RAMP_DOWN_PRESCAL_MASK BITFIELD(24, 25) /* @@ -916,7 +916,7 @@ * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, * PRM_VOLTSETUP_MPU_RET_SLEEP */ -#define OMAP4430_RAMP_UP_COUNT_SHIFT (1 << 0) +#define OMAP4430_RAMP_UP_COUNT_SHIFT 0 #define OMAP4430_RAMP_UP_COUNT_MASK BITFIELD(0, 5) /* @@ -924,1282 +924,1282 @@ * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, * PRM_VOLTSETUP_MPU_RET_SLEEP */ -#define OMAP4430_RAMP_UP_PRESCAL_SHIFT (1 << 8) +#define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 #define OMAP4430_RAMP_UP_PRESCAL_MASK BITFIELD(8, 9) /* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAV_VDD_CORE_L_SHIFT (1 << 1) +#define OMAP4430_RAV_VDD_CORE_L_SHIFT 1 #define OMAP4430_RAV_VDD_CORE_L_MASK BITFIELD(1, 1) /* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAV_VDD_IVA_L_SHIFT (1 << 9) +#define OMAP4430_RAV_VDD_IVA_L_SHIFT 9 #define OMAP4430_RAV_VDD_IVA_L_MASK BITFIELD(9, 9) /* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAV_VDD_MPU_L_SHIFT (1 << 18) +#define OMAP4430_RAV_VDD_MPU_L_SHIFT 18 #define OMAP4430_RAV_VDD_MPU_L_MASK BITFIELD(18, 18) /* Used by PRM_VC_VAL_BYPASS */ -#define OMAP4430_REGADDR_SHIFT (1 << 8) +#define OMAP4430_REGADDR_SHIFT 8 #define OMAP4430_REGADDR_MASK BITFIELD(8, 15) /* * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, * PRM_VC_VAL_CMD_VDD_MPU_L */ -#define OMAP4430_RET_SHIFT (1 << 8) +#define OMAP4430_RET_SHIFT 8 #define OMAP4430_RET_MASK BITFIELD(8, 15) /* Used by PM_L4PER_PWRSTCTRL */ -#define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT (1 << 16) +#define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT 16 #define OMAP4430_RETAINED_BANK_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_L4PER_PWRSTCTRL */ -#define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT (1 << 8) +#define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT 8 #define OMAP4430_RETAINED_BANK_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_L4PER_PWRSTST */ -#define OMAP4430_RETAINED_BANK_STATEST_SHIFT (1 << 4) +#define OMAP4430_RETAINED_BANK_STATEST_SHIFT 4 #define OMAP4430_RETAINED_BANK_STATEST_MASK BITFIELD(4, 5) /* * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, * PRM_LDO_SRAM_MPU_CTRL */ -#define OMAP4430_RETMODE_ENABLE_SHIFT (1 << 0) +#define OMAP4430_RETMODE_ENABLE_SHIFT 0 #define OMAP4430_RETMODE_ENABLE_MASK BITFIELD(0, 0) /* Used by REVISION_PRM */ -#define OMAP4430_REV_SHIFT (1 << 0) +#define OMAP4430_REV_SHIFT 0 #define OMAP4430_REV_MASK BITFIELD(0, 7) /* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */ -#define OMAP4430_RST1_SHIFT (1 << 0) +#define OMAP4430_RST1_SHIFT 0 #define OMAP4430_RST1_MASK BITFIELD(0, 0) /* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ -#define OMAP4430_RST1ST_SHIFT (1 << 0) +#define OMAP4430_RST1ST_SHIFT 0 #define OMAP4430_RST1ST_MASK BITFIELD(0, 0) /* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */ -#define OMAP4430_RST2_SHIFT (1 << 1) +#define OMAP4430_RST2_SHIFT 1 #define OMAP4430_RST2_MASK BITFIELD(1, 1) /* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ -#define OMAP4430_RST2ST_SHIFT (1 << 1) +#define OMAP4430_RST2ST_SHIFT 1 #define OMAP4430_RST2ST_MASK BITFIELD(1, 1) /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */ -#define OMAP4430_RST3_SHIFT (1 << 2) +#define OMAP4430_RST3_SHIFT 2 #define OMAP4430_RST3_MASK BITFIELD(2, 2) /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */ -#define OMAP4430_RST3ST_SHIFT (1 << 2) +#define OMAP4430_RST3ST_SHIFT 2 #define OMAP4430_RST3ST_MASK BITFIELD(2, 2) /* Used by PRM_RSTTIME */ -#define OMAP4430_RSTTIME1_SHIFT (1 << 0) +#define OMAP4430_RSTTIME1_SHIFT 0 #define OMAP4430_RSTTIME1_MASK BITFIELD(0, 9) /* Used by PRM_RSTTIME */ -#define OMAP4430_RSTTIME2_SHIFT (1 << 10) +#define OMAP4430_RSTTIME2_SHIFT 10 #define OMAP4430_RSTTIME2_MASK BITFIELD(10, 14) /* Used by PRM_RSTCTRL */ -#define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT (1 << 1) +#define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT 1 #define OMAP4430_RST_GLOBAL_COLD_SW_MASK BITFIELD(1, 1) /* Used by PRM_RSTCTRL */ -#define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT (1 << 0) +#define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT 0 #define OMAP4430_RST_GLOBAL_WARM_SW_MASK BITFIELD(0, 0) /* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_SA_VDD_CORE_L_SHIFT (1 << 0) +#define OMAP4430_SA_VDD_CORE_L_SHIFT 0 #define OMAP4430_SA_VDD_CORE_L_MASK BITFIELD(0, 0) /* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */ -#define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT (1 << 0) +#define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT 0 #define OMAP4430_SA_VDD_CORE_L_0_6_MASK BITFIELD(0, 6) /* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_SA_VDD_IVA_L_SHIFT (1 << 8) +#define OMAP4430_SA_VDD_IVA_L_SHIFT 8 #define OMAP4430_SA_VDD_IVA_L_MASK BITFIELD(8, 8) /* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */ -#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT (1 << 8) +#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT 8 #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK BITFIELD(8, 14) /* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_SA_VDD_MPU_L_SHIFT (1 << 16) +#define OMAP4430_SA_VDD_MPU_L_SHIFT 16 #define OMAP4430_SA_VDD_MPU_L_MASK BITFIELD(16, 16) /* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */ -#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT (1 << 16) +#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT 16 #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK BITFIELD(16, 22) /* Used by PRM_VC_CFG_I2C_CLK */ -#define OMAP4430_SCLH_SHIFT (1 << 0) +#define OMAP4430_SCLH_SHIFT 0 #define OMAP4430_SCLH_MASK BITFIELD(0, 7) /* Used by PRM_VC_CFG_I2C_CLK */ -#define OMAP4430_SCLL_SHIFT (1 << 8) +#define OMAP4430_SCLL_SHIFT 8 #define OMAP4430_SCLL_MASK BITFIELD(8, 15) /* Used by PRM_RSTST */ -#define OMAP4430_SECURE_WDT_RST_SHIFT (1 << 4) +#define OMAP4430_SECURE_WDT_RST_SHIFT 4 #define OMAP4430_SECURE_WDT_RST_MASK BITFIELD(4, 4) /* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_SL2_MEM_ONSTATE_SHIFT (1 << 18) +#define OMAP4430_SL2_MEM_ONSTATE_SHIFT 18 #define OMAP4430_SL2_MEM_ONSTATE_MASK BITFIELD(18, 19) /* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_SL2_MEM_RETSTATE_SHIFT (1 << 9) +#define OMAP4430_SL2_MEM_RETSTATE_SHIFT 9 #define OMAP4430_SL2_MEM_RETSTATE_MASK BITFIELD(9, 9) /* Used by PM_IVAHD_PWRSTST */ -#define OMAP4430_SL2_MEM_STATEST_SHIFT (1 << 6) +#define OMAP4430_SL2_MEM_STATEST_SHIFT 6 #define OMAP4430_SL2_MEM_STATEST_MASK BITFIELD(6, 7) /* Used by PRM_VC_VAL_BYPASS */ -#define OMAP4430_SLAVEADDR_SHIFT (1 << 0) +#define OMAP4430_SLAVEADDR_SHIFT 0 #define OMAP4430_SLAVEADDR_MASK BITFIELD(0, 6) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ -#define OMAP4430_SLEEP_RBB_SEL_SHIFT (1 << 3) +#define OMAP4430_SLEEP_RBB_SEL_SHIFT 3 #define OMAP4430_SLEEP_RBB_SEL_MASK BITFIELD(3, 3) /* Used by PRM_SRAM_COUNT */ -#define OMAP4430_SLPCNT_VALUE_SHIFT (1 << 16) +#define OMAP4430_SLPCNT_VALUE_SHIFT 16 #define OMAP4430_SLPCNT_VALUE_MASK BITFIELD(16, 23) /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ -#define OMAP4430_SMPSWAITTIMEMAX_SHIFT (1 << 8) +#define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 #define OMAP4430_SMPSWAITTIMEMAX_MASK BITFIELD(8, 23) /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ -#define OMAP4430_SMPSWAITTIMEMIN_SHIFT (1 << 8) +#define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 #define OMAP4430_SMPSWAITTIMEMIN_MASK BITFIELD(8, 23) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ -#define OMAP4430_SR2EN_SHIFT (1 << 0) +#define OMAP4430_SR2EN_SHIFT 0 #define OMAP4430_SR2EN_MASK BITFIELD(0, 0) /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ -#define OMAP4430_SR2_IN_TRANSITION_SHIFT (1 << 6) +#define OMAP4430_SR2_IN_TRANSITION_SHIFT 6 #define OMAP4430_SR2_IN_TRANSITION_MASK BITFIELD(6, 6) /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ -#define OMAP4430_SR2_STATUS_SHIFT (1 << 3) +#define OMAP4430_SR2_STATUS_SHIFT 3 #define OMAP4430_SR2_STATUS_MASK BITFIELD(3, 4) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ -#define OMAP4430_SR2_WTCNT_VALUE_SHIFT (1 << 8) +#define OMAP4430_SR2_WTCNT_VALUE_SHIFT 8 #define OMAP4430_SR2_WTCNT_VALUE_MASK BITFIELD(8, 15) /* * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, * PRM_LDO_SRAM_MPU_CTRL */ -#define OMAP4430_SRAMLDO_STATUS_SHIFT (1 << 8) +#define OMAP4430_SRAMLDO_STATUS_SHIFT 8 #define OMAP4430_SRAMLDO_STATUS_MASK BITFIELD(8, 8) /* * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, * PRM_LDO_SRAM_MPU_CTRL */ -#define OMAP4430_SRAM_IN_TRANSITION_SHIFT (1 << 9) +#define OMAP4430_SRAM_IN_TRANSITION_SHIFT 9 #define OMAP4430_SRAM_IN_TRANSITION_MASK BITFIELD(9, 9) /* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP4430_SRMODEEN_SHIFT (1 << 4) +#define OMAP4430_SRMODEEN_SHIFT 4 #define OMAP4430_SRMODEEN_MASK BITFIELD(4, 4) /* Used by PRM_VOLTSETUP_WARMRESET */ -#define OMAP4430_STABLE_COUNT_SHIFT (1 << 0) +#define OMAP4430_STABLE_COUNT_SHIFT 0 #define OMAP4430_STABLE_COUNT_MASK BITFIELD(0, 5) /* Used by PRM_VOLTSETUP_WARMRESET */ -#define OMAP4430_STABLE_PRESCAL_SHIFT (1 << 8) +#define OMAP4430_STABLE_PRESCAL_SHIFT 8 #define OMAP4430_STABLE_PRESCAL_MASK BITFIELD(8, 9) /* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_TCM1_MEM_ONSTATE_SHIFT (1 << 20) +#define OMAP4430_TCM1_MEM_ONSTATE_SHIFT 20 #define OMAP4430_TCM1_MEM_ONSTATE_MASK BITFIELD(20, 21) /* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_TCM1_MEM_RETSTATE_SHIFT (1 << 10) +#define OMAP4430_TCM1_MEM_RETSTATE_SHIFT 10 #define OMAP4430_TCM1_MEM_RETSTATE_MASK BITFIELD(10, 10) /* Used by PM_IVAHD_PWRSTST */ -#define OMAP4430_TCM1_MEM_STATEST_SHIFT (1 << 8) +#define OMAP4430_TCM1_MEM_STATEST_SHIFT 8 #define OMAP4430_TCM1_MEM_STATEST_MASK BITFIELD(8, 9) /* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_TCM2_MEM_ONSTATE_SHIFT (1 << 22) +#define OMAP4430_TCM2_MEM_ONSTATE_SHIFT 22 #define OMAP4430_TCM2_MEM_ONSTATE_MASK BITFIELD(22, 23) /* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_TCM2_MEM_RETSTATE_SHIFT (1 << 11) +#define OMAP4430_TCM2_MEM_RETSTATE_SHIFT 11 #define OMAP4430_TCM2_MEM_RETSTATE_MASK BITFIELD(11, 11) /* Used by PM_IVAHD_PWRSTST */ -#define OMAP4430_TCM2_MEM_STATEST_SHIFT (1 << 10) +#define OMAP4430_TCM2_MEM_STATEST_SHIFT 10 #define OMAP4430_TCM2_MEM_STATEST_MASK BITFIELD(10, 11) /* Used by RM_TESLA_RSTST */ -#define OMAP4430_TESLASS_EMU_RSTST_SHIFT (1 << 2) +#define OMAP4430_TESLASS_EMU_RSTST_SHIFT 2 #define OMAP4430_TESLASS_EMU_RSTST_MASK BITFIELD(2, 2) /* Used by RM_TESLA_RSTST */ -#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT (1 << 3) +#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT 3 #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK BITFIELD(3, 3) /* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT (1 << 20) +#define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT 20 #define OMAP4430_TESLA_EDMA_ONSTATE_MASK BITFIELD(20, 21) /* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT (1 << 10) +#define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT 10 #define OMAP4430_TESLA_EDMA_RETSTATE_MASK BITFIELD(10, 10) /* Used by PM_TESLA_PWRSTST */ -#define OMAP4430_TESLA_EDMA_STATEST_SHIFT (1 << 8) +#define OMAP4430_TESLA_EDMA_STATEST_SHIFT 8 #define OMAP4430_TESLA_EDMA_STATEST_MASK BITFIELD(8, 9) /* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_L1_ONSTATE_SHIFT (1 << 16) +#define OMAP4430_TESLA_L1_ONSTATE_SHIFT 16 #define OMAP4430_TESLA_L1_ONSTATE_MASK BITFIELD(16, 17) /* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_L1_RETSTATE_SHIFT (1 << 8) +#define OMAP4430_TESLA_L1_RETSTATE_SHIFT 8 #define OMAP4430_TESLA_L1_RETSTATE_MASK BITFIELD(8, 8) /* Used by PM_TESLA_PWRSTST */ -#define OMAP4430_TESLA_L1_STATEST_SHIFT (1 << 4) +#define OMAP4430_TESLA_L1_STATEST_SHIFT 4 #define OMAP4430_TESLA_L1_STATEST_MASK BITFIELD(4, 5) /* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_L2_ONSTATE_SHIFT (1 << 18) +#define OMAP4430_TESLA_L2_ONSTATE_SHIFT 18 #define OMAP4430_TESLA_L2_ONSTATE_MASK BITFIELD(18, 19) /* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_L2_RETSTATE_SHIFT (1 << 9) +#define OMAP4430_TESLA_L2_RETSTATE_SHIFT 9 #define OMAP4430_TESLA_L2_RETSTATE_MASK BITFIELD(9, 9) /* Used by PM_TESLA_PWRSTST */ -#define OMAP4430_TESLA_L2_STATEST_SHIFT (1 << 6) +#define OMAP4430_TESLA_L2_STATEST_SHIFT 6 #define OMAP4430_TESLA_L2_STATEST_MASK BITFIELD(6, 7) /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ -#define OMAP4430_TIMEOUT_SHIFT (1 << 0) +#define OMAP4430_TIMEOUT_SHIFT 0 #define OMAP4430_TIMEOUT_MASK BITFIELD(0, 15) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_TIMEOUTEN_SHIFT (1 << 3) +#define OMAP4430_TIMEOUTEN_SHIFT 3 #define OMAP4430_TIMEOUTEN_MASK BITFIELD(3, 3) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_TRANSITION_EN_SHIFT (1 << 8) +#define OMAP4430_TRANSITION_EN_SHIFT 8 #define OMAP4430_TRANSITION_EN_MASK BITFIELD(8, 8) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_TRANSITION_ST_SHIFT (1 << 8) +#define OMAP4430_TRANSITION_ST_SHIFT 8 #define OMAP4430_TRANSITION_ST_MASK BITFIELD(8, 8) /* Used by PRM_VC_VAL_BYPASS */ -#define OMAP4430_VALID_SHIFT (1 << 24) +#define OMAP4430_VALID_SHIFT 24 #define OMAP4430_VALID_MASK BITFIELD(24, 24) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_BYPASSACK_EN_SHIFT (1 << 14) +#define OMAP4430_VC_BYPASSACK_EN_SHIFT 14 #define OMAP4430_VC_BYPASSACK_EN_MASK BITFIELD(14, 14) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_BYPASSACK_ST_SHIFT (1 << 14) +#define OMAP4430_VC_BYPASSACK_ST_SHIFT 14 #define OMAP4430_VC_BYPASSACK_ST_MASK BITFIELD(14, 14) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_IVA_VPACK_EN_SHIFT (1 << 30) +#define OMAP4430_VC_IVA_VPACK_EN_SHIFT 30 #define OMAP4430_VC_IVA_VPACK_EN_MASK BITFIELD(30, 30) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_IVA_VPACK_ST_SHIFT (1 << 30) +#define OMAP4430_VC_IVA_VPACK_ST_SHIFT 30 #define OMAP4430_VC_IVA_VPACK_ST_MASK BITFIELD(30, 30) /* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VC_MPU_VPACK_EN_SHIFT (1 << 6) +#define OMAP4430_VC_MPU_VPACK_EN_SHIFT 6 #define OMAP4430_VC_MPU_VPACK_EN_MASK BITFIELD(6, 6) /* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VC_MPU_VPACK_ST_SHIFT (1 << 6) +#define OMAP4430_VC_MPU_VPACK_ST_SHIFT 6 #define OMAP4430_VC_MPU_VPACK_ST_MASK BITFIELD(6, 6) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_RAERR_EN_SHIFT (1 << 12) +#define OMAP4430_VC_RAERR_EN_SHIFT 12 #define OMAP4430_VC_RAERR_EN_MASK BITFIELD(12, 12) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_RAERR_ST_SHIFT (1 << 12) +#define OMAP4430_VC_RAERR_ST_SHIFT 12 #define OMAP4430_VC_RAERR_ST_MASK BITFIELD(12, 12) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_SAERR_EN_SHIFT (1 << 11) +#define OMAP4430_VC_SAERR_EN_SHIFT 11 #define OMAP4430_VC_SAERR_EN_MASK BITFIELD(11, 11) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_SAERR_ST_SHIFT (1 << 11) +#define OMAP4430_VC_SAERR_ST_SHIFT 11 #define OMAP4430_VC_SAERR_ST_MASK BITFIELD(11, 11) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_TOERR_EN_SHIFT (1 << 13) +#define OMAP4430_VC_TOERR_EN_SHIFT 13 #define OMAP4430_VC_TOERR_EN_MASK BITFIELD(13, 13) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_TOERR_ST_SHIFT (1 << 13) +#define OMAP4430_VC_TOERR_ST_SHIFT 13 #define OMAP4430_VC_TOERR_ST_MASK BITFIELD(13, 13) /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ -#define OMAP4430_VDDMAX_SHIFT (1 << 24) +#define OMAP4430_VDDMAX_SHIFT 24 #define OMAP4430_VDDMAX_MASK BITFIELD(24, 31) /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ -#define OMAP4430_VDDMIN_SHIFT (1 << 16) +#define OMAP4430_VDDMIN_SHIFT 16 #define OMAP4430_VDDMIN_MASK BITFIELD(16, 23) /* Used by PRM_VOLTCTRL */ -#define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT (1 << 12) +#define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT 12 #define OMAP4430_VDD_CORE_I2C_DISABLE_MASK BITFIELD(12, 12) /* Used by PRM_RSTST */ -#define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT (1 << 8) +#define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 #define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK BITFIELD(8, 8) /* Used by PRM_VOLTCTRL */ -#define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT (1 << 14) +#define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT 14 #define OMAP4430_VDD_IVA_I2C_DISABLE_MASK BITFIELD(14, 14) /* Used by PRM_VOLTCTRL */ -#define OMAP4430_VDD_IVA_PRESENCE_SHIFT (1 << 9) +#define OMAP4430_VDD_IVA_PRESENCE_SHIFT 9 #define OMAP4430_VDD_IVA_PRESENCE_MASK BITFIELD(9, 9) /* Used by PRM_RSTST */ -#define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT (1 << 7) +#define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 #define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK BITFIELD(7, 7) /* Used by PRM_VOLTCTRL */ -#define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT (1 << 13) +#define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT 13 #define OMAP4430_VDD_MPU_I2C_DISABLE_MASK BITFIELD(13, 13) /* Used by PRM_VOLTCTRL */ -#define OMAP4430_VDD_MPU_PRESENCE_SHIFT (1 << 8) +#define OMAP4430_VDD_MPU_PRESENCE_SHIFT 8 #define OMAP4430_VDD_MPU_PRESENCE_MASK BITFIELD(8, 8) /* Used by PRM_RSTST */ -#define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT (1 << 6) +#define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 #define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK BITFIELD(6, 6) /* Used by PRM_VC_VAL_SMPS_RA_VOL */ -#define OMAP4430_VOLRA_VDD_CORE_L_SHIFT (1 << 0) +#define OMAP4430_VOLRA_VDD_CORE_L_SHIFT 0 #define OMAP4430_VOLRA_VDD_CORE_L_MASK BITFIELD(0, 7) /* Used by PRM_VC_VAL_SMPS_RA_VOL */ -#define OMAP4430_VOLRA_VDD_IVA_L_SHIFT (1 << 8) +#define OMAP4430_VOLRA_VDD_IVA_L_SHIFT 8 #define OMAP4430_VOLRA_VDD_IVA_L_MASK BITFIELD(8, 15) /* Used by PRM_VC_VAL_SMPS_RA_VOL */ -#define OMAP4430_VOLRA_VDD_MPU_L_SHIFT (1 << 16) +#define OMAP4430_VOLRA_VDD_MPU_L_SHIFT 16 #define OMAP4430_VOLRA_VDD_MPU_L_MASK BITFIELD(16, 23) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_VPENABLE_SHIFT (1 << 0) +#define OMAP4430_VPENABLE_SHIFT 0 #define OMAP4430_VPENABLE_MASK BITFIELD(0, 0) /* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */ -#define OMAP4430_VPINIDLE_SHIFT (1 << 0) +#define OMAP4430_VPINIDLE_SHIFT 0 #define OMAP4430_VPINIDLE_MASK BITFIELD(0, 0) /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ -#define OMAP4430_VPVOLTAGE_SHIFT (1 << 0) +#define OMAP4430_VPVOLTAGE_SHIFT 0 #define OMAP4430_VPVOLTAGE_MASK BITFIELD(0, 7) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT (1 << 20) +#define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT 20 #define OMAP4430_VP_CORE_EQVALUE_EN_MASK BITFIELD(20, 20) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT (1 << 20) +#define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT 20 #define OMAP4430_VP_CORE_EQVALUE_ST_MASK BITFIELD(20, 20) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT (1 << 18) +#define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT 18 #define OMAP4430_VP_CORE_MAXVDD_EN_MASK BITFIELD(18, 18) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT (1 << 18) +#define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT 18 #define OMAP4430_VP_CORE_MAXVDD_ST_MASK BITFIELD(18, 18) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_MINVDD_EN_SHIFT (1 << 17) +#define OMAP4430_VP_CORE_MINVDD_EN_SHIFT 17 #define OMAP4430_VP_CORE_MINVDD_EN_MASK BITFIELD(17, 17) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_MINVDD_ST_SHIFT (1 << 17) +#define OMAP4430_VP_CORE_MINVDD_ST_SHIFT 17 #define OMAP4430_VP_CORE_MINVDD_ST_MASK BITFIELD(17, 17) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT (1 << 19) +#define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT 19 #define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK BITFIELD(19, 19) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT (1 << 19) +#define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT 19 #define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK BITFIELD(19, 19) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT (1 << 16) +#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK BITFIELD(16, 16) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT (1 << 16) +#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK BITFIELD(16, 16) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT (1 << 21) +#define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT 21 #define OMAP4430_VP_CORE_TRANXDONE_EN_MASK BITFIELD(21, 21) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT (1 << 21) +#define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT 21 #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK BITFIELD(21, 21) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT (1 << 28) +#define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT 28 #define OMAP4430_VP_IVA_EQVALUE_EN_MASK BITFIELD(28, 28) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT (1 << 28) +#define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT 28 #define OMAP4430_VP_IVA_EQVALUE_ST_MASK BITFIELD(28, 28) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT (1 << 26) +#define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT 26 #define OMAP4430_VP_IVA_MAXVDD_EN_MASK BITFIELD(26, 26) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT (1 << 26) +#define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT 26 #define OMAP4430_VP_IVA_MAXVDD_ST_MASK BITFIELD(26, 26) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_MINVDD_EN_SHIFT (1 << 25) +#define OMAP4430_VP_IVA_MINVDD_EN_SHIFT 25 #define OMAP4430_VP_IVA_MINVDD_EN_MASK BITFIELD(25, 25) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_MINVDD_ST_SHIFT (1 << 25) +#define OMAP4430_VP_IVA_MINVDD_ST_SHIFT 25 #define OMAP4430_VP_IVA_MINVDD_ST_MASK BITFIELD(25, 25) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT (1 << 27) +#define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT 27 #define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK BITFIELD(27, 27) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT (1 << 27) +#define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT 27 #define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK BITFIELD(27, 27) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT (1 << 24) +#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT 24 #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK BITFIELD(24, 24) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT (1 << 24) +#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT 24 #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK BITFIELD(24, 24) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT (1 << 29) +#define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT 29 #define OMAP4430_VP_IVA_TRANXDONE_EN_MASK BITFIELD(29, 29) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT (1 << 29) +#define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT 29 #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK BITFIELD(29, 29) /* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT (1 << 4) +#define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT 4 #define OMAP4430_VP_MPU_EQVALUE_EN_MASK BITFIELD(4, 4) /* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT (1 << 4) +#define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT 4 #define OMAP4430_VP_MPU_EQVALUE_ST_MASK BITFIELD(4, 4) /* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT (1 << 2) +#define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT 2 #define OMAP4430_VP_MPU_MAXVDD_EN_MASK BITFIELD(2, 2) /* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT (1 << 2) +#define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT 2 #define OMAP4430_VP_MPU_MAXVDD_ST_MASK BITFIELD(2, 2) /* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_MINVDD_EN_SHIFT (1 << 1) +#define OMAP4430_VP_MPU_MINVDD_EN_SHIFT 1 #define OMAP4430_VP_MPU_MINVDD_EN_MASK BITFIELD(1, 1) /* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_MINVDD_ST_SHIFT (1 << 1) +#define OMAP4430_VP_MPU_MINVDD_ST_SHIFT 1 #define OMAP4430_VP_MPU_MINVDD_ST_MASK BITFIELD(1, 1) /* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT (1 << 3) +#define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT 3 #define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK BITFIELD(3, 3) /* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT (1 << 3) +#define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT 3 #define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK BITFIELD(3, 3) /* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT (1 << 0) +#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK BITFIELD(0, 0) /* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT (1 << 0) +#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK BITFIELD(0, 0) /* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT (1 << 5) +#define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT 5 #define OMAP4430_VP_MPU_TRANXDONE_EN_MASK BITFIELD(5, 5) /* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT (1 << 5) +#define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT 5 #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK BITFIELD(5, 5) /* Used by PRM_SRAM_COUNT */ -#define OMAP4430_VSETUPCNT_VALUE_SHIFT (1 << 8) +#define OMAP4430_VSETUPCNT_VALUE_SHIFT 8 #define OMAP4430_VSETUPCNT_VALUE_MASK BITFIELD(8, 15) /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ -#define OMAP4430_VSTEPMAX_SHIFT (1 << 0) +#define OMAP4430_VSTEPMAX_SHIFT 0 #define OMAP4430_VSTEPMAX_MASK BITFIELD(0, 7) /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ -#define OMAP4430_VSTEPMIN_SHIFT (1 << 0) +#define OMAP4430_VSTEPMIN_SHIFT 0 #define OMAP4430_VSTEPMIN_MASK BITFIELD(0, 7) /* Used by PRM_MODEM_IF_CTRL */ -#define OMAP4430_WAKE_MODEM_SHIFT (1 << 0) +#define OMAP4430_WAKE_MODEM_SHIFT 0 #define OMAP4430_WAKE_MODEM_MASK BITFIELD(0, 0) /* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_DISPC_MPU_MASK BITFIELD(0, 0) /* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT (1 << 3) +#define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT 3 #define OMAP4430_WKUPDEP_DISPC_SDMA_MASK BITFIELD(3, 3) /* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT (1 << 2) +#define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT 2 #define OMAP4430_WKUPDEP_DISPC_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT (1 << 7) +#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT (1 << 6) +#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT 6 #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK BITFIELD(6, 6) /* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT (1 << 2) +#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT 2 #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_DMTIMER10_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_DMTIMER11_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_DMTIMER11_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_DMTIMER2_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_DMTIMER3_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_DMTIMER3_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_DMTIMER4_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_DMTIMER4_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_DMTIMER9_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_DMTIMER9_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK BITFIELD(0, 0) /* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT (1 << 5) +#define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT 5 #define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK BITFIELD(5, 5) /* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT (1 << 4) +#define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT 4 #define OMAP4430_WKUPDEP_DSI1_MPU_MASK BITFIELD(4, 4) /* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT (1 << 7) +#define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT 7 #define OMAP4430_WKUPDEP_DSI1_SDMA_MASK BITFIELD(7, 7) /* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT (1 << 6) +#define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT 6 #define OMAP4430_WKUPDEP_DSI1_TESLA_MASK BITFIELD(6, 6) /* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT (1 << 9) +#define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT 9 #define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK BITFIELD(9, 9) /* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT (1 << 8) +#define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT 8 #define OMAP4430_WKUPDEP_DSI2_MPU_MASK BITFIELD(8, 8) /* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT (1 << 11) +#define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT 11 #define OMAP4430_WKUPDEP_DSI2_SDMA_MASK BITFIELD(11, 11) /* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT (1 << 10) +#define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT 10 #define OMAP4430_WKUPDEP_DSI2_TESLA_MASK BITFIELD(10, 10) /* Used by PM_WKUP_GPIO1_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_WKUP_GPIO1_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK BITFIELD(0, 0) /* Used by PM_WKUP_GPIO1_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT (1 << 6) +#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT 6 #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_GPIO2_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_GPIO2_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_GPIO2_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT (1 << 6) +#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT 6 #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_GPIO3_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_GPIO3_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT (1 << 6) +#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT 6 #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_GPIO4_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_GPIO4_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT (1 << 6) +#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT 6 #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_GPIO5_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_GPIO5_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT (1 << 6) +#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT 6 #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_GPIO6_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_GPIO6_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT (1 << 6) +#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT 6 #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK BITFIELD(6, 6) /* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT (1 << 19) +#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK BITFIELD(19, 19) /* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT (1 << 13) +#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT 13 #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK BITFIELD(13, 13) /* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT (1 << 12) +#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK BITFIELD(12, 12) /* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT (1 << 14) +#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT 14 #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK BITFIELD(14, 14) /* Used by PM_L4PER_HECC1_WKDEP */ -#define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_HECC1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_HECC2_WKDEP */ -#define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_HECC2_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_HSI_WKDEP */ -#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT (1 << 6) +#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT 6 #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L3INIT_HSI_WKDEP */ -#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_HSI_WKDEP */ -#define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_I2C1_WKDEP */ -#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT (1 << 7) +#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_I2C1_WKDEP */ -#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_I2C1_WKDEP */ -#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_I2C2_WKDEP */ -#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT (1 << 7) +#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_I2C2_WKDEP */ -#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_I2C2_WKDEP */ -#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_I2C3_WKDEP */ -#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT (1 << 7) +#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_I2C3_WKDEP */ -#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_I2C3_WKDEP */ -#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_I2C4_WKDEP */ -#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT (1 << 7) +#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_I2C4_WKDEP */ -#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_I2C4_WKDEP */ -#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_I2C5_WKDEP */ -#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT (1 << 7) +#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT 7 #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_I2C5_WKDEP */ -#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_WKUP_KEYBOARD_WKDEP */ -#define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT (1 << 7) +#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 7 #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT (1 << 6) +#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT 6 #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK BITFIELD(6, 6) /* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT (1 << 2) +#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT 2 #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_MCASP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT (1 << 7) +#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 7 #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_MCASP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT (1 << 6) +#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT 6 #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_MCASP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MCASP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT (1 << 2) +#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT 2 #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_MCASP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT (1 << 7) +#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 7 #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_MCASP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT (1 << 6) +#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT 6 #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_MCASP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MCASP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT (1 << 2) +#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT 2 #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_MCBSP1_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_MCBSP1_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT (1 << 3) +#define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT 3 #define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK BITFIELD(3, 3) /* Used by PM_ABE_MCBSP1_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT (1 << 2) +#define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT 2 #define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_MCBSP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_MCBSP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT (1 << 3) +#define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT 3 #define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK BITFIELD(3, 3) /* Used by PM_ABE_MCBSP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT (1 << 2) +#define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT 2 #define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_MCBSP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_MCBSP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT (1 << 3) +#define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT 3 #define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK BITFIELD(3, 3) /* Used by PM_ABE_MCBSP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT (1 << 2) +#define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT 2 #define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_MCBSP4_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MCBSP4_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT (1 << 3) +#define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT 3 #define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_MCBSP4_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT (1 << 2) +#define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT 2 #define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT (1 << 3) +#define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT 3 #define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT (1 << 2) +#define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT 2 #define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_MCSPI2_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_MCSPI2_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MCSPI2_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT (1 << 3) +#define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT 3 #define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_MCSPI3_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MCSPI3_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT (1 << 3) +#define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT 3 #define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_MCSPI4_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MCSPI4_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT (1 << 3) +#define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT 3 #define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_MMC1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT (1 << 3) +#define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT 3 #define OMAP4430_WKUPDEP_MMC1_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT (1 << 2) +#define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT 2 #define OMAP4430_WKUPDEP_MMC1_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_MMC2_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT (1 << 3) +#define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT 3 #define OMAP4430_WKUPDEP_MMC2_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT (1 << 2) +#define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT 2 #define OMAP4430_WKUPDEP_MMC2_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L3INIT_MMC6_WKDEP */ -#define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_MMC6_WKDEP */ -#define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_MMC6_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_MMC6_WKDEP */ -#define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT (1 << 2) +#define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT 2 #define OMAP4430_WKUPDEP_MMC6_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_MMCSD3_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_MMCSD3_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MMCSD3_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT (1 << 3) +#define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT 3 #define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_MMCSD4_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_MMCSD4_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MMCSD4_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT (1 << 3) +#define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT 3 #define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_MMCSD5_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_MMCSD5_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_MMCSD5_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT (1 << 3) +#define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT 3 #define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L3INIT_PCIESS_WKDEP */ -#define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_PCIESS_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_PCIESS_WKDEP */ -#define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT (1 << 2) +#define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT 2 #define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_PDM_WKDEP */ -#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT (1 << 7) +#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT 7 #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_ABE_PDM_WKDEP */ -#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT (1 << 6) +#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT 6 #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK BITFIELD(6, 6) /* Used by PM_ABE_PDM_WKDEP */ -#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_PDM_WKDEP */ -#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT (1 << 2) +#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT 2 #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK BITFIELD(2, 2) /* Used by PM_WKUP_RTC_WKDEP */ -#define OMAP4430_WKUPDEP_RTC_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_RTC_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_RTC_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_SATA_WKDEP */ -#define OMAP4430_WKUPDEP_SATA_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_SATA_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_SATA_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_SATA_WKDEP */ -#define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT (1 << 2) +#define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT 2 #define OMAP4430_WKUPDEP_SATA_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_SLIMBUS_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT (1 << 7) +#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_ABE_SLIMBUS_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT (1 << 6) +#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT 6 #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK BITFIELD(6, 6) /* Used by PM_ABE_SLIMBUS_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_SLIMBUS_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT (1 << 2) +#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT 2 #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_SLIMBUS2_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT (1 << 7) +#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT 7 #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK BITFIELD(7, 7) /* Used by PM_L4PER_SLIMBUS2_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT (1 << 6) +#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT 6 #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK BITFIELD(6, 6) /* Used by PM_L4PER_SLIMBUS2_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_SLIMBUS2_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT (1 << 2) +#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT 2 #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ALWON_SR_CORE_WKDEP */ -#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_ALWON_SR_CORE_WKDEP */ -#define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK BITFIELD(0, 0) /* Used by PM_ALWON_SR_IVA_WKDEP */ -#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_ALWON_SR_IVA_WKDEP */ -#define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK BITFIELD(0, 0) /* Used by PM_ALWON_SR_MPU_WKDEP */ -#define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK BITFIELD(0, 0) /* Used by PM_WKUP_TIMER12_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_TIMER12_MPU_MASK BITFIELD(0, 0) /* Used by PM_WKUP_TIMER1_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_TIMER1_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_TIMER5_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_TIMER5_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_TIMER5_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT (1 << 2) +#define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT 2 #define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_TIMER6_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_TIMER6_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_TIMER6_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT (1 << 2) +#define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT 2 #define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_TIMER7_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_TIMER7_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_TIMER7_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT (1 << 2) +#define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT 2 #define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK BITFIELD(2, 2) /* Used by PM_ABE_TIMER8_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_TIMER8_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_TIMER8_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT (1 << 2) +#define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT 2 #define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_UART1_WKDEP */ -#define OMAP4430_WKUPDEP_UART1_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_UART1_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_UART1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_UART1_WKDEP */ -#define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT (1 << 3) +#define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT 3 #define OMAP4430_WKUPDEP_UART1_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_UART2_WKDEP */ -#define OMAP4430_WKUPDEP_UART2_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_UART2_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_UART2_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_UART2_WKDEP */ -#define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT (1 << 3) +#define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT 3 #define OMAP4430_WKUPDEP_UART2_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_UART3_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP4430_WKUPDEP_UART3_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_UART3_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_UART3_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT (1 << 3) +#define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT 3 #define OMAP4430_WKUPDEP_UART3_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT (1 << 2) +#define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT 2 #define OMAP4430_WKUPDEP_UART3_TESLA_MASK BITFIELD(2, 2) /* Used by PM_L4PER_UART4_WKDEP */ -#define OMAP4430_WKUPDEP_UART4_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_UART4_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_UART4_MPU_MASK BITFIELD(0, 0) /* Used by PM_L4PER_UART4_WKDEP */ -#define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT (1 << 3) +#define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT 3 #define OMAP4430_WKUPDEP_UART4_SDMA_MASK BITFIELD(3, 3) /* Used by PM_L3INIT_UNIPRO1_WKDEP */ -#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_UNIPRO1_WKDEP */ -#define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_USB_HOST_WKDEP */ -#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ -#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ -#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_USB_HOST_WKDEP */ -#define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_USB_OTG_WKDEP */ -#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_USB_OTG_WKDEP */ -#define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_USB_TLL_WKDEP */ -#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_L3INIT_USB_TLL_WKDEP */ -#define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK BITFIELD(0, 0) /* Used by PM_WKUP_USIM_WKDEP */ -#define OMAP4430_WKUPDEP_USIM_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_USIM_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_USIM_MPU_MASK BITFIELD(0, 0) /* Used by PM_WKUP_USIM_WKDEP */ -#define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT (1 << 3) +#define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT 3 #define OMAP4430_WKUPDEP_USIM_SDMA_MASK BITFIELD(3, 3) /* Used by PM_WKUP_WDT2_WKDEP */ -#define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK BITFIELD(1, 1) /* Used by PM_WKUP_WDT2_WKDEP */ -#define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_WDT2_MPU_MASK BITFIELD(0, 0) /* Used by PM_ABE_WDT3_WKDEP */ -#define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT (1 << 0) +#define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT 0 #define OMAP4430_WKUPDEP_WDT3_MPU_MASK BITFIELD(0, 0) /* Used by PM_L3INIT_HSI_WKDEP */ -#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT (1 << 8) +#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT 8 #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK BITFIELD(8, 8) /* Used by PM_L3INIT_XHPI_WKDEP */ -#define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT (1 << 1) +#define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT 1 #define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK BITFIELD(1, 1) /* Used by PRM_IO_PMCTRL */ -#define OMAP4430_WUCLK_CTRL_SHIFT (1 << 8) +#define OMAP4430_WUCLK_CTRL_SHIFT 8 #define OMAP4430_WUCLK_CTRL_MASK BITFIELD(8, 8) /* Used by PRM_IO_PMCTRL */ -#define OMAP4430_WUCLK_STATUS_SHIFT (1 << 9) +#define OMAP4430_WUCLK_STATUS_SHIFT 9 #define OMAP4430_WUCLK_STATUS_MASK BITFIELD(9, 9) #endif diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index 40f006285163..5fba2aa8932c 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -179,9 +179,11 @@ /* Registers appearing on both 24xx and 34xx */ -#define RM_RSTCTRL 0x0050 -#define RM_RSTTIME 0x0054 -#define RM_RSTST 0x0058 +#define OMAP2_RM_RSTCTRL 0x0050 +#define OMAP2_RM_RSTTIME 0x0054 +#define OMAP2_RM_RSTST 0x0058 +#define OMAP2_PM_PWSTCTRL 0x00e0 +#define OMAP2_PM_PWSTST 0x00e4 #define PM_WKEN 0x00a0 #define PM_WKEN1 PM_WKEN @@ -191,8 +193,6 @@ #define PM_EVGENCTRL 0x00d4 #define PM_EVGENONTIM 0x00d8 #define PM_EVGENOFFTIM 0x00dc -#define PM_PWSTCTRL 0x00e0 -#define PM_PWSTST 0x00e4 /* Omap2 specific registers */ #define OMAP24XX_PM_WKEN2 0x00a4 @@ -220,6 +220,13 @@ #define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8 #define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc +/* Omap4 specific registers */ +#define OMAP4_RM_RSTCTRL 0x0000 +#define OMAP4_RM_RSTTIME 0x0004 +#define OMAP4_RM_RSTST 0x0008 +#define OMAP4_PM_PWSTCTRL 0x0000 +#define OMAP4_PM_PWSTST 0x0004 + #ifndef __ASSEMBLER__ diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index e10a02df6e1d..5f3035ec0d6f 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -80,7 +80,6 @@ static LIST_HEAD(uart_list); static struct plat_serial8250_port serial_platform_data0[] = { { - .mapbase = OMAP_UART1_BASE, .irq = 72, .flags = UPF_BOOT_AUTOCONF, .iotype = UPIO_MEM, @@ -93,7 +92,6 @@ static struct plat_serial8250_port serial_platform_data0[] = { static struct plat_serial8250_port serial_platform_data1[] = { { - .mapbase = OMAP_UART2_BASE, .irq = 73, .flags = UPF_BOOT_AUTOCONF, .iotype = UPIO_MEM, @@ -106,7 +104,6 @@ static struct plat_serial8250_port serial_platform_data1[] = { static struct plat_serial8250_port serial_platform_data2[] = { { - .mapbase = OMAP_UART3_BASE, .irq = 74, .flags = UPF_BOOT_AUTOCONF, .iotype = UPIO_MEM, @@ -117,10 +114,9 @@ static struct plat_serial8250_port serial_platform_data2[] = { } }; -#ifdef CONFIG_ARCH_OMAP4 +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) static struct plat_serial8250_port serial_platform_data3[] = { { - .mapbase = OMAP_UART4_BASE, .irq = 70, .flags = UPF_BOOT_AUTOCONF, .iotype = UPIO_MEM, @@ -130,7 +126,26 @@ static struct plat_serial8250_port serial_platform_data3[] = { .flags = 0 } }; + +static inline void omap2_set_globals_uart4(struct omap_globals *omap2_globals) +{ + serial_platform_data3[0].mapbase = omap2_globals->uart4_phys; +} +#else +static inline void omap2_set_globals_uart4(struct omap_globals *omap2_globals) +{ +} #endif + +void __init omap2_set_globals_uart(struct omap_globals *omap2_globals) +{ + serial_platform_data0[0].mapbase = omap2_globals->uart1_phys; + serial_platform_data1[0].mapbase = omap2_globals->uart2_phys; + serial_platform_data2[0].mapbase = omap2_globals->uart3_phys; + if (cpu_is_omap3630() || cpu_is_omap44xx()) + omap2_set_globals_uart4(omap2_globals); +} + static inline unsigned int __serial_read_reg(struct uart_port *up, int offset) { @@ -574,7 +589,7 @@ static struct omap_uart_state omap_uart[] = { }, }, }, -#ifdef CONFIG_ARCH_OMAP4 +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) { .pdev = { .name = "serial8250", @@ -701,15 +716,16 @@ void __init omap_serial_init_port(int port) DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout); } - /* omap44xx: Never read empty UART fifo - * omap3xxx: Never read empty UART fifo on UARTs - * with IP rev >=0x52 - */ - if (cpu_is_omap44xx()) - uart->p->serial_in = serial_in_override; - else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) - >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) - uart->p->serial_in = serial_in_override; + /* + * omap44xx: Never read empty UART fifo + * omap3xxx: Never read empty UART fifo on UARTs + * with IP rev >=0x52 + */ + if (cpu_is_omap44xx()) + uart->p->serial_in = serial_in_override; + else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) + >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) + uart->p->serial_in = serial_in_override; } /** @@ -721,8 +737,13 @@ void __init omap_serial_init_port(int port) */ void __init omap_serial_init(void) { - int i; + int i, nr_ports; + + if (!(cpu_is_omap3630() || cpu_is_omap4430())) + nr_ports = 3; + else + nr_ports = ARRAY_SIZE(omap_uart); - for (i = 0; i < ARRAY_SIZE(omap_uart); i++) + for (i = 0; i < nr_ports; i++) omap_serial_init_port(i); } diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index c3626ea48143..22fcc14e63be 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -38,7 +38,7 @@ #define PM_PREPWSTST_CORE_P 0x48306AE8 #define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \ OMAP3430_PM_PREPWSTST) -#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + PM_PWSTCTRL +#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) #define SRAM_BASE_P 0x40200000 #define CONTROL_STAT 0x480022F0 diff --git a/arch/arm/mach-orion5x/include/mach/debug-macro.S b/arch/arm/mach-orion5x/include/mach/debug-macro.S index c7f808bfe272..91e0e39bb23f 100644 --- a/arch/arm/mach-orion5x/include/mach/debug-macro.S +++ b/arch/arm/mach-orion5x/include/mach/debug-macro.S @@ -10,7 +10,7 @@ #include <mach/orion5x.h> - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? ldreq \rx, =ORION5X_REGS_PHYS_BASE diff --git a/arch/arm/mach-pnx4008/include/mach/debug-macro.S b/arch/arm/mach-pnx4008/include/mach/debug-macro.S index 6d1407f319f8..6ca8bd30bf46 100644 --- a/arch/arm/mach-pnx4008/include/mach/debug-macro.S +++ b/arch/arm/mach-pnx4008/include/mach/debug-macro.S @@ -11,7 +11,7 @@ * */ - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? mov \rx, #0x00090000 diff --git a/arch/arm/mach-pxa/include/mach/debug-macro.S b/arch/arm/mach-pxa/include/mach/debug-macro.S index 55d6a175ab19..01cf81393fe2 100644 --- a/arch/arm/mach-pxa/include/mach/debug-macro.S +++ b/arch/arm/mach-pxa/include/mach/debug-macro.S @@ -13,7 +13,7 @@ #include "hardware.h" - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? moveq \rx, #0x40000000 @ physical diff --git a/arch/arm/mach-realview/include/mach/debug-macro.S b/arch/arm/mach-realview/include/mach/debug-macro.S index 932d8af18062..86622289b74e 100644 --- a/arch/arm/mach-realview/include/mach/debug-macro.S +++ b/arch/arm/mach-realview/include/mach/debug-macro.S @@ -33,7 +33,7 @@ #error "Unknown RealView platform" #endif - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? moveq \rx, #0x10000000 diff --git a/arch/arm/mach-rpc/include/mach/debug-macro.S b/arch/arm/mach-rpc/include/mach/debug-macro.S index b2a939ffdcde..6fc8d66395dc 100644 --- a/arch/arm/mach-rpc/include/mach/debug-macro.S +++ b/arch/arm/mach-rpc/include/mach/debug-macro.S @@ -11,7 +11,7 @@ * */ - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? moveq \rx, #0x03000000 diff --git a/arch/arm/mach-s3c2410/include/mach/debug-macro.S b/arch/arm/mach-s3c2410/include/mach/debug-macro.S index 4c29a89ad077..0eef78b4a6ed 100644 --- a/arch/arm/mach-s3c2410/include/mach/debug-macro.S +++ b/arch/arm/mach-s3c2410/include/mach/debug-macro.S @@ -19,7 +19,7 @@ #define S3C2410_UART1_OFF (0x4000) #define SHIFT_2440TXF (14-9) - .macro addruart, rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 ldreq \rx, = S3C24XX_PA_UART diff --git a/arch/arm/mach-s3c24a0/include/mach/debug-macro.S b/arch/arm/mach-s3c24a0/include/mach/debug-macro.S index f0ef0ab475f6..239476b81f3b 100644 --- a/arch/arm/mach-s3c24a0/include/mach/debug-macro.S +++ b/arch/arm/mach-s3c24a0/include/mach/debug-macro.S @@ -10,7 +10,7 @@ #include <mach/map.h> #include <plat/regs-serial.h> - .macro addruart, rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 ldreq \rx, = S3C24XX_PA_UART diff --git a/arch/arm/mach-s3c6400/include/mach/debug-macro.S b/arch/arm/mach-s3c6400/include/mach/debug-macro.S index b18ac5266dfc..5c88875d6a3f 100644 --- a/arch/arm/mach-s3c6400/include/mach/debug-macro.S +++ b/arch/arm/mach-s3c6400/include/mach/debug-macro.S @@ -21,7 +21,7 @@ * aligned and add in the offset when we load the value here. */ - .macro addruart, rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 ldreq \rx, = S3C_PA_UART diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S index 9d142ccf654b..e181f5789482 100644 --- a/arch/arm/mach-s5pc100/include/mach/debug-macro.S +++ b/arch/arm/mach-s5pc100/include/mach/debug-macro.S @@ -22,7 +22,7 @@ * aligned and add in the offset when we load the value here. */ - .macro addruart, rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 ldreq \rx, = S3C_PA_UART diff --git a/arch/arm/mach-sa1100/include/mach/debug-macro.S b/arch/arm/mach-sa1100/include/mach/debug-macro.S index 1f0634d92702..336adccea542 100644 --- a/arch/arm/mach-sa1100/include/mach/debug-macro.S +++ b/arch/arm/mach-sa1100/include/mach/debug-macro.S @@ -12,7 +12,7 @@ */ #include <mach/hardware.h> - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? moveq \rx, #0x80000000 @ physical base address diff --git a/arch/arm/mach-shark/include/mach/debug-macro.S b/arch/arm/mach-shark/include/mach/debug-macro.S index f97a7626bd58..50f071c5bf4d 100644 --- a/arch/arm/mach-shark/include/mach/debug-macro.S +++ b/arch/arm/mach-shark/include/mach/debug-macro.S @@ -11,7 +11,7 @@ * */ - .macro addruart,rx + .macro addruart, rx, tmp mov \rx, #0xe0000000 orr \rx, \rx, #0x000003f8 .endm diff --git a/arch/arm/mach-u300/include/mach/debug-macro.S b/arch/arm/mach-u300/include/mach/debug-macro.S index f3a1cbbeeab3..ca4a028c2661 100644 --- a/arch/arm/mach-u300/include/mach/debug-macro.S +++ b/arch/arm/mach-u300/include/mach/debug-macro.S @@ -10,7 +10,7 @@ */ #include <mach/hardware.h> - .macro addruart,rx + .macro addruart, rx, tmp /* If we move the adress using MMU, use this. */ mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S index 8f21b6a95dce..494408b96785 100644 --- a/arch/arm/mach-ux500/include/mach/debug-macro.S +++ b/arch/arm/mach-ux500/include/mach/debug-macro.S @@ -8,7 +8,7 @@ * published by the Free Software Foundation. * */ - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @MMU enabled? moveq \rx, #0x80000000 @MMU off, Physical address diff --git a/arch/arm/mach-versatile/include/mach/debug-macro.S b/arch/arm/mach-versatile/include/mach/debug-macro.S index b4ac00eacf68..6fea7199c626 100644 --- a/arch/arm/mach-versatile/include/mach/debug-macro.S +++ b/arch/arm/mach-versatile/include/mach/debug-macro.S @@ -11,7 +11,7 @@ * */ - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? moveq \rx, #0x10000000 diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index 15b2b148a105..5a6ae1b9e1e8 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -52,7 +52,7 @@ #define UART_PADDR MXC91231_UART2_BASE_ADDR #define UART_VADDR MXC91231_AIPS1_IO_ADDRESS(MXC91231_UART2_BASE_ADDR) #endif - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? ldreq \rx, =UART_PADDR @ physical diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index e2ea04a4c8a1..97d0c79ffd2b 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -7,27 +7,36 @@ config ARCH_OMAP_OTG choice prompt "OMAP System Type" - default ARCH_OMAP1 + default ARCH_OMAP2PLUS config ARCH_OMAP1 bool "TI OMAP1" select COMMON_CLKDEV + help + "Systems based on omap7xx, omap15xx or omap16xx" + +config ARCH_OMAP2PLUS + bool "TI OMAP2/3/4" + select COMMON_CLKDEV + help + "Systems based on omap24xx, omap34xx or omap44xx" config ARCH_OMAP2 bool "TI OMAP2" + depends on ARCH_OMAP2PLUS select CPU_V6 - select COMMON_CLKDEV config ARCH_OMAP3 bool "TI OMAP3" + depends on ARCH_OMAP2PLUS select CPU_V7 - select COMMON_CLKDEV + select USB_ARCH_HAS_EHCI config ARCH_OMAP4 bool "TI OMAP4" + depends on ARCH_OMAP2PLUS select CPU_V7 select ARM_GIC - select COMMON_CLKDEV endchoice @@ -116,7 +125,7 @@ config OMAP_MPU_TIMER config OMAP_32K_TIMER bool "Use 32KHz timer" - depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX || ARCH_OMAP4 + depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS help Select this option if you want to enable the OMAP 32KHz timer. This timer saves power compared to the OMAP_MPU_TIMER, and has @@ -137,29 +146,10 @@ config OMAP_32K_TIMER_HZ config OMAP_DM_TIMER bool "Use dual-mode timer" - depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX || ARCH_OMAP4 + depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS help Select this option if you want to use OMAP Dual-Mode timers. -choice - prompt "Low-level debug console UART" - depends on ARCH_OMAP - default OMAP_LL_DEBUG_NONE - -config OMAP_LL_DEBUG_UART1 - bool "UART1" - -config OMAP_LL_DEBUG_UART2 - bool "UART2" - -config OMAP_LL_DEBUG_UART3 - bool "UART3" - -config OMAP_LL_DEBUG_NONE - bool "None" - -endchoice - config OMAP_SERIAL_WAKE bool "Enable wake-up events for serial ports" depends on ARCH_OMAP1 && OMAP_MUX diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 4becbdd1935c..e3b58afa5dcf 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -173,7 +173,7 @@ EXPORT_SYMBOL(clk_get_parent); * OMAP specific clock functions shared between omap1 and omap2 *-------------------------------------------------------------------------*/ -unsigned int __initdata mpurate; +int __initdata mpurate; /* * By default we use the rate set by the bootloader. @@ -199,6 +199,17 @@ unsigned long followparent_recalc(struct clk *clk) return clk->parent->rate; } +/* + * Used for clocks that have the same value as the parent clock, + * divided by some factor + */ +unsigned long omap_fixed_divisor_recalc(struct clk *clk) +{ + WARN_ON(!clk->fixed_div); + + return clk->parent->rate / clk->fixed_div; +} + void clk_reparent(struct clk *child, struct clk *parent) { list_del_init(&child->sibling); diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index dddc0273bc8b..4f29e8c0f539 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -34,6 +34,7 @@ #include <plat/control.h> #include <plat/mux.h> #include <plat/fpga.h> +#include <plat/serial.h> #include <plat/clock.h> @@ -126,7 +127,7 @@ static cycle_t omap2430_32k_read(struct clocksource *cs) #define omap2430_32k_read NULL #endif -#ifdef CONFIG_ARCH_OMAP34XX +#ifdef CONFIG_ARCH_OMAP3 static cycle_t omap34xx_32k_read(struct clocksource *cs) { return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10); @@ -245,6 +246,7 @@ static void __init __omap2_set_globals(struct omap_globals *omap2_globals) omap2_set_globals_sdrc(omap2_globals); omap2_set_globals_control(omap2_globals); omap2_set_globals_prcm(omap2_globals); + omap2_set_globals_uart(omap2_globals); } #endif @@ -259,6 +261,9 @@ static struct omap_globals omap242x_globals = { .ctrl = OMAP2_L4_IO_ADDRESS(OMAP2420_CTRL_BASE), .prm = OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE), .cm = OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), + .uart1_phys = OMAP2_UART1_BASE, + .uart2_phys = OMAP2_UART2_BASE, + .uart3_phys = OMAP2_UART3_BASE, }; void __init omap2_set_globals_242x(void) @@ -277,6 +282,9 @@ static struct omap_globals omap243x_globals = { .ctrl = OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE), .prm = OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE), .cm = OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), + .uart1_phys = OMAP2_UART1_BASE, + .uart2_phys = OMAP2_UART2_BASE, + .uart3_phys = OMAP2_UART3_BASE, }; void __init omap2_set_globals_243x(void) @@ -285,9 +293,9 @@ void __init omap2_set_globals_243x(void) } #endif -#if defined(CONFIG_ARCH_OMAP3430) +#if defined(CONFIG_ARCH_OMAP3) -static struct omap_globals omap343x_globals = { +static struct omap_globals omap3_globals = { .class = OMAP343X_CLASS, .tap = OMAP2_L4_IO_ADDRESS(0x4830A000), .sdrc = OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), @@ -295,11 +303,21 @@ static struct omap_globals omap343x_globals = { .ctrl = OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), .prm = OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE), .cm = OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), + .uart1_phys = OMAP3_UART1_BASE, + .uart2_phys = OMAP3_UART2_BASE, + .uart3_phys = OMAP3_UART3_BASE, }; void __init omap2_set_globals_343x(void) { - __omap2_set_globals(&omap343x_globals); + __omap2_set_globals(&omap3_globals); +} + +void __init omap2_set_globals_36xx(void) +{ + omap3_globals.uart4_phys = OMAP3_UART4_BASE; + + __omap2_set_globals(&omap3_globals); } #endif @@ -311,6 +329,10 @@ static struct omap_globals omap4_globals = { .prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE), .cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE), .cm2 = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE), + .uart1_phys = OMAP4_UART1_BASE, + .uart2_phys = OMAP4_UART2_BASE, + .uart3_phys = OMAP4_UART3_BASE, + .uart4_phys = OMAP4_UART4_BASE, }; void __init omap2_set_globals_443x(void) @@ -318,6 +340,7 @@ void __init omap2_set_globals_443x(void) omap2_set_globals_tap(&omap4_globals); omap2_set_globals_control(&omap4_globals); omap2_set_globals_prcm(&omap4_globals); + omap2_set_globals_uart(&omap4_globals); } #endif diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index 30b5db73017a..3a3e357fff3c 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c @@ -28,6 +28,7 @@ #include <plat/menelaus.h> #include <plat/mcbsp.h> #include <plat/dsp_common.h> +#include <plat/omap44xx.h> #if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) @@ -192,6 +193,41 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, /*-------------------------------------------------------------------------*/ +#if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \ + defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE) + +static struct resource mcpdm_resources[] = { + { + .name = "mcpdm_mem", + .start = OMAP44XX_MCPDM_BASE, + .end = OMAP44XX_MCPDM_BASE + SZ_4K, + .flags = IORESOURCE_MEM, + }, + { + .name = "mcpdm_irq", + .start = INT_44XX_MCPDM_IRQ, + .end = INT_44XX_MCPDM_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device omap_mcpdm_device = { + .name = "omap-mcpdm", + .id = -1, + .num_resources = ARRAY_SIZE(mcpdm_resources), + .resource = mcpdm_resources, +}; + +static void omap_init_mcpdm(void) +{ + (void) platform_device_register(&omap_mcpdm_device); +} +#else +static inline void omap_init_mcpdm(void) {} +#endif + +/*-------------------------------------------------------------------------*/ + #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) @@ -244,7 +280,7 @@ fail: #if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE) -#ifdef CONFIG_ARCH_OMAP24XX +#ifdef CONFIG_ARCH_OMAP2 #define OMAP_RNG_BASE 0x480A0000 #else #define OMAP_RNG_BASE 0xfffe5000 @@ -385,6 +421,7 @@ static int __init omap_init_devices(void) omap_init_dsp(); omap_init_kp(); omap_init_rng(); + omap_init_mcpdm(); omap_init_uwire(); omap_init_wdt(); return 0; diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 728c64204184..30ff525fe33c 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -1870,8 +1870,7 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id) #define omap1_dma_irq_handler NULL #endif -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) +#ifdef CONFIG_ARCH_OMAP2PLUS static int omap2_dma_handle_ch(int ch) { diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 08ccf8922520..24bf692fe65e 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -153,8 +153,7 @@ struct omap_dm_timer { unsigned long phys_base; int irq; -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) +#ifdef CONFIG_ARCH_OMAP2PLUS struct clk *iclk, *fclk; #endif void __iomem *io_base; @@ -163,20 +162,9 @@ struct omap_dm_timer { unsigned posted:1; }; -#ifdef CONFIG_ARCH_OMAP1 - -#define omap_dm_clk_enable(x) -#define omap_dm_clk_disable(x) -#define omap2_dm_timers NULL -#define omap2_dm_source_names NULL -#define omap2_dm_source_clocks NULL -#define omap3_dm_timers NULL -#define omap3_dm_source_names NULL -#define omap3_dm_source_clocks NULL -#define omap4_dm_timers NULL -#define omap4_dm_source_names NULL -#define omap4_dm_source_clocks NULL +static int dm_timer_count; +#ifdef CONFIG_ARCH_OMAP1 static struct omap_dm_timer omap1_dm_timers[] = { { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 }, { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 }, @@ -188,20 +176,14 @@ static struct omap_dm_timer omap1_dm_timers[] = { { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 }, }; -static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers); - -#elif defined(CONFIG_ARCH_OMAP2) +static const int omap1_dm_timer_count = ARRAY_SIZE(omap1_dm_timers); -#define omap_dm_clk_enable(x) clk_enable(x) -#define omap_dm_clk_disable(x) clk_disable(x) +#else #define omap1_dm_timers NULL -#define omap3_dm_timers NULL -#define omap3_dm_source_names NULL -#define omap3_dm_source_clocks NULL -#define omap4_dm_timers NULL -#define omap4_dm_source_names NULL -#define omap4_dm_source_clocks NULL +#define omap1_dm_timer_count 0 +#endif /* CONFIG_ARCH_OMAP1 */ +#ifdef CONFIG_ARCH_OMAP2 static struct omap_dm_timer omap2_dm_timers[] = { { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 }, { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 }, @@ -225,20 +207,16 @@ static const char *omap2_dm_source_names[] __initdata = { }; static struct clk *omap2_dm_source_clocks[3]; -static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers); +static const int omap2_dm_timer_count = ARRAY_SIZE(omap2_dm_timers); -#elif defined(CONFIG_ARCH_OMAP3) - -#define omap_dm_clk_enable(x) clk_enable(x) -#define omap_dm_clk_disable(x) clk_disable(x) -#define omap1_dm_timers NULL +#else #define omap2_dm_timers NULL +#define omap2_dm_timer_count 0 #define omap2_dm_source_names NULL #define omap2_dm_source_clocks NULL -#define omap4_dm_timers NULL -#define omap4_dm_source_names NULL -#define omap4_dm_source_clocks NULL +#endif /* CONFIG_ARCH_OMAP2 */ +#ifdef CONFIG_ARCH_OMAP3 static struct omap_dm_timer omap3_dm_timers[] = { { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 }, { .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 }, @@ -261,20 +239,16 @@ static const char *omap3_dm_source_names[] __initdata = { }; static struct clk *omap3_dm_source_clocks[2]; -static const int dm_timer_count = ARRAY_SIZE(omap3_dm_timers); - -#elif defined(CONFIG_ARCH_OMAP4) +static const int omap3_dm_timer_count = ARRAY_SIZE(omap3_dm_timers); -#define omap_dm_clk_enable(x) clk_enable(x) -#define omap_dm_clk_disable(x) clk_disable(x) -#define omap1_dm_timers NULL -#define omap2_dm_timers NULL -#define omap2_dm_source_names NULL -#define omap2_dm_source_clocks NULL +#else #define omap3_dm_timers NULL +#define omap3_dm_timer_count 0 #define omap3_dm_source_names NULL #define omap3_dm_source_clocks NULL +#endif /* CONFIG_ARCH_OMAP3 */ +#ifdef CONFIG_ARCH_OMAP4 static struct omap_dm_timer omap4_dm_timers[] = { { .phys_base = 0x4a318000, .irq = INT_44XX_GPTIMER1 }, { .phys_base = 0x48032000, .irq = INT_44XX_GPTIMER2 }, @@ -295,13 +269,14 @@ static const char *omap4_dm_source_names[] __initdata = { NULL }; static struct clk *omap4_dm_source_clocks[2]; -static const int dm_timer_count = ARRAY_SIZE(omap4_dm_timers); +static const int omap4_dm_timer_count = ARRAY_SIZE(omap4_dm_timers); #else - -#error OMAP architecture not supported! - -#endif +#define omap4_dm_timers NULL +#define omap4_dm_timer_count 0 +#define omap4_dm_source_names NULL +#define omap4_dm_source_clocks NULL +#endif /* CONFIG_ARCH_OMAP4 */ static struct omap_dm_timer *dm_timers; static const char **dm_source_names; @@ -450,8 +425,12 @@ void omap_dm_timer_enable(struct omap_dm_timer *timer) if (timer->enabled) return; - omap_dm_clk_enable(timer->fclk); - omap_dm_clk_enable(timer->iclk); +#ifdef CONFIG_ARCH_OMAP2PLUS + if (cpu_class_is_omap2()) { + clk_enable(timer->fclk); + clk_enable(timer->iclk); + } +#endif timer->enabled = 1; } @@ -462,8 +441,12 @@ void omap_dm_timer_disable(struct omap_dm_timer *timer) if (!timer->enabled) return; - omap_dm_clk_disable(timer->iclk); - omap_dm_clk_disable(timer->fclk); +#ifdef CONFIG_ARCH_OMAP2PLUS + if (cpu_class_is_omap2()) { + clk_disable(timer->iclk); + clk_disable(timer->fclk); + } +#endif timer->enabled = 0; } @@ -506,8 +489,7 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) } EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); -#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) +#else struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) { @@ -551,8 +533,7 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer) if (l & OMAP_TIMER_CTRL_ST) { l &= ~0x1; omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) +#ifdef CONFIG_ARCH_OMAP2PLUS /* Readback to make sure write has completed */ omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); /* @@ -764,17 +745,21 @@ int __init omap_dm_timer_init(void) if (cpu_class_is_omap1()) { dm_timers = omap1_dm_timers; + dm_timer_count = omap1_dm_timer_count; map_size = SZ_2K; } else if (cpu_is_omap24xx()) { dm_timers = omap2_dm_timers; + dm_timer_count = omap2_dm_timer_count; dm_source_names = omap2_dm_source_names; dm_source_clocks = omap2_dm_source_clocks; } else if (cpu_is_omap34xx()) { dm_timers = omap3_dm_timers; + dm_timer_count = omap3_dm_timer_count; dm_source_names = omap3_dm_source_names; dm_source_clocks = omap3_dm_source_clocks; } else if (cpu_is_omap44xx()) { dm_timers = omap4_dm_timers; + dm_timer_count = omap4_dm_timer_count; dm_source_names = omap4_dm_source_names; dm_source_clocks = omap4_dm_source_clocks; } @@ -793,8 +778,7 @@ int __init omap_dm_timer_init(void) timer->io_base = ioremap(timer->phys_base, map_size); BUG_ON(!timer->io_base); -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) +#ifdef CONFIG_ARCH_OMAP2PLUS if (cpu_class_is_omap2()) { char clk_name[16]; sprintf(clk_name, "gpt%d_ick", i + 1); diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index d2422c766cca..6055028dff1e 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -177,13 +177,11 @@ struct gpio_bank { u16 irq; u16 virtual_irq_start; int method; -#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ - defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4) +#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) u32 suspend_wakeup; u32 saved_wakeup; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ - defined(CONFIG_ARCH_OMAP4) +#ifdef CONFIG_ARCH_OMAP2PLUS u32 non_wakeup_gpios; u32 enabled_non_wakeup_gpios; @@ -204,6 +202,7 @@ struct gpio_bank { #define METHOD_GPIO_1610 2 #define METHOD_GPIO_7XX 3 #define METHOD_GPIO_24XX 5 +#define METHOD_GPIO_44XX 6 #ifdef CONFIG_ARCH_OMAP16XX static struct gpio_bank gpio_bank_1610[5] = { @@ -248,7 +247,7 @@ static struct gpio_bank gpio_bank_7xx[7] = { }; #endif -#ifdef CONFIG_ARCH_OMAP24XX +#ifdef CONFIG_ARCH_OMAP2 static struct gpio_bank gpio_bank_242x[4] = { { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, @@ -276,7 +275,7 @@ static struct gpio_bank gpio_bank_243x[5] = { #endif -#ifdef CONFIG_ARCH_OMAP34XX +#ifdef CONFIG_ARCH_OMAP3 static struct gpio_bank gpio_bank_34xx[6] = { { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, @@ -314,17 +313,17 @@ static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS]; #ifdef CONFIG_ARCH_OMAP4 static struct gpio_bank gpio_bank_44xx[6] = { { OMAP44XX_GPIO1_BASE, NULL, INT_44XX_GPIO_BANK1, IH_GPIO_BASE, - METHOD_GPIO_24XX }, + METHOD_GPIO_44XX }, { OMAP44XX_GPIO2_BASE, NULL, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32, - METHOD_GPIO_24XX }, + METHOD_GPIO_44XX }, { OMAP44XX_GPIO3_BASE, NULL, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64, - METHOD_GPIO_24XX }, + METHOD_GPIO_44XX }, { OMAP44XX_GPIO4_BASE, NULL, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96, - METHOD_GPIO_24XX }, + METHOD_GPIO_44XX }, { OMAP44XX_GPIO5_BASE, NULL, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, - METHOD_GPIO_24XX }, + METHOD_GPIO_44XX }, { OMAP44XX_GPIO6_BASE, NULL, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, - METHOD_GPIO_24XX }, + METHOD_GPIO_44XX }, }; #endif @@ -426,13 +425,13 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) reg += OMAP7XX_GPIO_DIR_CONTROL; break; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) case METHOD_GPIO_24XX: reg += OMAP24XX_GPIO_OE; break; #endif #if defined(CONFIG_ARCH_OMAP4) - case METHOD_GPIO_24XX: + case METHOD_GPIO_44XX: reg += OMAP4_GPIO_OE; break; #endif @@ -493,7 +492,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) l &= ~(1 << gpio); break; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) case METHOD_GPIO_24XX: if (enable) reg += OMAP24XX_GPIO_SETDATAOUT; @@ -503,7 +502,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) break; #endif #ifdef CONFIG_ARCH_OMAP4 - case METHOD_GPIO_24XX: + case METHOD_GPIO_44XX: if (enable) reg += OMAP4_GPIO_SETDATAOUT; else @@ -546,13 +545,13 @@ static int _get_gpio_datain(struct gpio_bank *bank, int gpio) reg += OMAP7XX_GPIO_DATA_INPUT; break; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) case METHOD_GPIO_24XX: reg += OMAP24XX_GPIO_DATAIN; break; #endif #ifdef CONFIG_ARCH_OMAP4 - case METHOD_GPIO_24XX: + case METHOD_GPIO_44XX: reg += OMAP4_GPIO_DATAIN; break; #endif @@ -592,9 +591,9 @@ static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) reg += OMAP7XX_GPIO_DATA_OUTPUT; break; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ - defined(CONFIG_ARCH_OMAP4) +#ifdef CONFIG_ARCH_OMAP2PLUS case METHOD_GPIO_24XX: + case METHOD_GPIO_44XX: reg += OMAP24XX_GPIO_DATAOUT; break; #endif @@ -625,11 +624,12 @@ void omap_set_gpio_debounce(int gpio, int enable) bank = get_gpio_bank(gpio); reg = bank->base; -#ifdef CONFIG_ARCH_OMAP4 - reg += OMAP4_GPIO_DEBOUNCENABLE; -#else - reg += OMAP24XX_GPIO_DEBOUNCE_EN; -#endif + + if (cpu_is_omap44xx()) + reg += OMAP4_GPIO_DEBOUNCENABLE; + else + reg += OMAP24XX_GPIO_DEBOUNCE_EN; + if (!(bank->mod_usage & l)) { printk(KERN_ERR "GPIO %d not requested\n", gpio); return; @@ -675,17 +675,17 @@ void omap_set_gpio_debounce_time(int gpio, int enc_time) } enc_time &= 0xff; -#ifdef CONFIG_ARCH_OMAP4 - reg += OMAP4_GPIO_DEBOUNCINGTIME; -#else - reg += OMAP24XX_GPIO_DEBOUNCE_VAL; -#endif + + if (cpu_is_omap44xx()) + reg += OMAP4_GPIO_DEBOUNCINGTIME; + else + reg += OMAP24XX_GPIO_DEBOUNCE_VAL; + __raw_writel(enc_time, reg); } EXPORT_SYMBOL(omap_set_gpio_debounce_time); -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ - defined(CONFIG_ARCH_OMAP4) +#ifdef CONFIG_ARCH_OMAP2PLUS static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) { @@ -856,9 +856,9 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) goto bad; break; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ - defined(CONFIG_ARCH_OMAP4) +#ifdef CONFIG_ARCH_OMAP2PLUS case METHOD_GPIO_24XX: + case METHOD_GPIO_44XX: set_24xx_gpio_triggering(bank, gpio, trigger); break; #endif @@ -937,13 +937,13 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) reg += OMAP7XX_GPIO_INT_STATUS; break; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) case METHOD_GPIO_24XX: reg += OMAP24XX_GPIO_IRQSTATUS1; break; #endif #if defined(CONFIG_ARCH_OMAP4) - case METHOD_GPIO_24XX: + case METHOD_GPIO_44XX: reg += OMAP4_GPIO_IRQSTATUS0; break; #endif @@ -954,12 +954,11 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) __raw_writel(gpio_mask, reg); /* Workaround for clearing DSP GPIO interrupts to allow retention */ -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) - reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; -#endif -#if defined(CONFIG_ARCH_OMAP4) - reg = bank->base + OMAP4_GPIO_IRQSTATUS1; -#endif + if (cpu_is_omap24xx() || cpu_is_omap34xx()) + reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; + else if (cpu_is_omap44xx()) + reg = bank->base + OMAP4_GPIO_IRQSTATUS1; + if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) { __raw_writel(gpio_mask, reg); @@ -1008,14 +1007,14 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) inv = 1; break; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) case METHOD_GPIO_24XX: reg += OMAP24XX_GPIO_IRQENABLE1; mask = 0xffffffff; break; #endif #if defined(CONFIG_ARCH_OMAP4) - case METHOD_GPIO_24XX: + case METHOD_GPIO_44XX: reg += OMAP4_GPIO_IRQSTATUSSET0; mask = 0xffffffff; break; @@ -1077,7 +1076,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab l |= gpio_mask; break; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) case METHOD_GPIO_24XX: if (enable) reg += OMAP24XX_GPIO_SETIRQENABLE1; @@ -1087,7 +1086,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab break; #endif #ifdef CONFIG_ARCH_OMAP4 - case METHOD_GPIO_24XX: + case METHOD_GPIO_44XX: if (enable) reg += OMAP4_GPIO_IRQSTATUSSET0; else @@ -1131,9 +1130,9 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) spin_unlock_irqrestore(&bank->lock, flags); return 0; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ - defined(CONFIG_ARCH_OMAP4) +#ifdef CONFIG_ARCH_OMAP2PLUS case METHOD_GPIO_24XX: + case METHOD_GPIO_44XX: if (bank->non_wakeup_gpios & (1 << gpio)) { printk(KERN_ERR "Unable to modify wakeup on " "non-wakeup GPIO%d\n", @@ -1227,9 +1226,9 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) __raw_writel(1 << offset, reg); } #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ - defined(CONFIG_ARCH_OMAP4) - if (bank->method == METHOD_GPIO_24XX) { +#ifdef CONFIG_ARCH_OMAP2PLUS + if ((bank->method == METHOD_GPIO_24XX) || + (bank->method == METHOD_GPIO_44XX)) { /* Disable wake-up during idle for dynamic tick */ void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; __raw_writel(1 << offset, reg); @@ -1286,12 +1285,12 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) if (bank->method == METHOD_GPIO_7XX) isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) if (bank->method == METHOD_GPIO_24XX) isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; #endif #if defined(CONFIG_ARCH_OMAP4) - if (bank->method == METHOD_GPIO_24XX) + if (bank->method == METHOD_GPIO_44XX) isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0; #endif while(1) { @@ -1571,6 +1570,7 @@ static int gpio_is_input(struct gpio_bank *bank, int mask) reg += OMAP7XX_GPIO_DIR_CONTROL; break; case METHOD_GPIO_24XX: + case METHOD_GPIO_44XX: reg += OMAP24XX_GPIO_OE; break; } @@ -1630,7 +1630,7 @@ static int gpio_2irq(struct gpio_chip *chip, unsigned offset) /*---------------------------------------------------------------------*/ static int initialized; -#if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)) +#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2) static struct clk * gpio_ick; #endif @@ -1756,7 +1756,7 @@ static int __init _omap_gpio_init(void) bank_size = SZ_2K; } #endif -#ifdef CONFIG_ARCH_OMAP24XX +#ifdef CONFIG_ARCH_OMAP2 if (cpu_is_omap242x()) { gpio_bank_count = 4; gpio_bank = gpio_bank_242x; @@ -1766,7 +1766,7 @@ static int __init _omap_gpio_init(void) gpio_bank = gpio_bank_243x; } #endif -#ifdef CONFIG_ARCH_OMAP34XX +#ifdef CONFIG_ARCH_OMAP3 if (cpu_is_omap34xx()) { gpio_bank_count = OMAP34XX_NR_GPIOS; gpio_bank = gpio_bank_34xx; @@ -1809,30 +1809,42 @@ static int __init _omap_gpio_init(void) gpio_count = 32; /* 7xx has 32-bit GPIOs */ } -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ - defined(CONFIG_ARCH_OMAP4) - if (bank->method == METHOD_GPIO_24XX) { +#ifdef CONFIG_ARCH_OMAP2PLUS + if ((bank->method == METHOD_GPIO_24XX) || + (bank->method == METHOD_GPIO_44XX)) { static const u32 non_wakeup_gpios[] = { 0xe203ffc0, 0x08700040 }; - if (cpu_is_omap44xx()) { - __raw_writel(0xffffffff, bank->base + + + if (cpu_is_omap44xx()) { + __raw_writel(0xffffffff, bank->base + OMAP4_GPIO_IRQSTATUSCLR0); - __raw_writew(0x0015, bank->base + + __raw_writew(0x0015, bank->base + OMAP4_GPIO_SYSCONFIG); - __raw_writel(0x00000000, bank->base + + __raw_writel(0x00000000, bank->base + OMAP4_GPIO_DEBOUNCENABLE); - /* Initialize interface clock ungated, module enabled */ - __raw_writel(0, bank->base + OMAP4_GPIO_CTRL); - } else { - __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1); - __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1); - __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG); - __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN); - - /* Initialize interface clock ungated, module enabled */ - __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); - } + /* + * Initialize interface clock ungated, + * module enabled + */ + __raw_writel(0, bank->base + OMAP4_GPIO_CTRL); + } else { + __raw_writel(0x00000000, bank->base + + OMAP24XX_GPIO_IRQENABLE1); + __raw_writel(0xffffffff, bank->base + + OMAP24XX_GPIO_IRQSTATUS1); + __raw_writew(0x0015, bank->base + + OMAP24XX_GPIO_SYSCONFIG); + __raw_writel(0x00000000, bank->base + + OMAP24XX_GPIO_DEBOUNCE_EN); + + /* + * Initialize interface clock ungated, + * module enabled + */ + __raw_writel(0, bank->base + + OMAP24XX_GPIO_CTRL); + } if (i < ARRAY_SIZE(non_wakeup_gpios)) bank->non_wakeup_gpios = non_wakeup_gpios[i]; gpio_count = 32; @@ -1903,8 +1915,7 @@ static int __init _omap_gpio_init(void) return 0; } -#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ - defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4) +#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) { int i; @@ -1927,7 +1938,7 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; break; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) case METHOD_GPIO_24XX: wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; @@ -1935,7 +1946,7 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) break; #endif #ifdef CONFIG_ARCH_OMAP4 - case METHOD_GPIO_24XX: + case METHOD_GPIO_44XX: wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0; wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; @@ -1975,14 +1986,14 @@ static int omap_gpio_resume(struct sys_device *dev) wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; break; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) case METHOD_GPIO_24XX: wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; break; #endif #ifdef CONFIG_ARCH_OMAP4 - case METHOD_GPIO_24XX: + case METHOD_GPIO_44XX: wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; break; @@ -2013,8 +2024,7 @@ static struct sys_device omap_gpio_device = { #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ - defined(CONFIG_ARCH_OMAP4) +#ifdef CONFIG_ARCH_OMAP2PLUS static int workaround_enabled; @@ -2030,29 +2040,42 @@ void omap2_gpio_prepare_for_retention(void) if (!(bank->enabled_non_wakeup_gpios)) continue; -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) - bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); - l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); - l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); -#endif -#ifdef CONFIG_ARCH_OMAP4 - bank->saved_datain = __raw_readl(bank->base + - OMAP4_GPIO_DATAIN); - l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT); - l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT); -#endif + + if (cpu_is_omap24xx() || cpu_is_omap34xx()) { + bank->saved_datain = __raw_readl(bank->base + + OMAP24XX_GPIO_DATAIN); + l1 = __raw_readl(bank->base + + OMAP24XX_GPIO_FALLINGDETECT); + l2 = __raw_readl(bank->base + + OMAP24XX_GPIO_RISINGDETECT); + } + + if (cpu_is_omap44xx()) { + bank->saved_datain = __raw_readl(bank->base + + OMAP4_GPIO_DATAIN); + l1 = __raw_readl(bank->base + + OMAP4_GPIO_FALLINGDETECT); + l2 = __raw_readl(bank->base + + OMAP4_GPIO_RISINGDETECT); + } + bank->saved_fallingdetect = l1; bank->saved_risingdetect = l2; l1 &= ~bank->enabled_non_wakeup_gpios; l2 &= ~bank->enabled_non_wakeup_gpios; -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) - __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT); - __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT); -#endif -#ifdef CONFIG_ARCH_OMAP4 - __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT); - __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT); -#endif + + if (cpu_is_omap24xx() || cpu_is_omap34xx()) { + __raw_writel(l1, bank->base + + OMAP24XX_GPIO_FALLINGDETECT); + __raw_writel(l2, bank->base + + OMAP24XX_GPIO_RISINGDETECT); + } + + if (cpu_is_omap44xx()) { + __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT); + __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT); + } + c++; } if (!c) { @@ -2074,20 +2097,23 @@ void omap2_gpio_resume_after_retention(void) if (!(bank->enabled_non_wakeup_gpios)) continue; -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) - __raw_writel(bank->saved_fallingdetect, + + if (cpu_is_omap24xx() || cpu_is_omap34xx()) { + __raw_writel(bank->saved_fallingdetect, bank->base + OMAP24XX_GPIO_FALLINGDETECT); - __raw_writel(bank->saved_risingdetect, + __raw_writel(bank->saved_risingdetect, bank->base + OMAP24XX_GPIO_RISINGDETECT); - l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); -#endif -#ifdef CONFIG_ARCH_OMAP4 - __raw_writel(bank->saved_fallingdetect, + l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); + } + + if (cpu_is_omap44xx()) { + __raw_writel(bank->saved_fallingdetect, bank->base + OMAP4_GPIO_FALLINGDETECT); - __raw_writel(bank->saved_risingdetect, + __raw_writel(bank->saved_risingdetect, bank->base + OMAP4_GPIO_RISINGDETECT); - l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN); -#endif + l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN); + } + /* Check if any of the non-wakeup interrupt GPIOs have changed * state. If so, generate an IRQ by software. This is * horribly racy, but it's the best we can do to work around @@ -2113,30 +2139,36 @@ void omap2_gpio_resume_after_retention(void) if (gen) { u32 old0, old1; -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) - old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); - old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); + + if (cpu_is_omap24xx() || cpu_is_omap44xx()) { + old0 = __raw_readl(bank->base + + OMAP24XX_GPIO_LEVELDETECT0); + old1 = __raw_readl(bank->base + + OMAP24XX_GPIO_LEVELDETECT1); __raw_writel(old0 | gen, bank->base + OMAP24XX_GPIO_LEVELDETECT0); __raw_writel(old1 | gen, bank->base + OMAP24XX_GPIO_LEVELDETECT1); - __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0); - __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1); -#endif -#ifdef CONFIG_ARCH_OMAP4 - old0 = __raw_readl(bank->base + + __raw_writel(old0, bank->base + + OMAP24XX_GPIO_LEVELDETECT0); + __raw_writel(old1, bank->base + + OMAP24XX_GPIO_LEVELDETECT1); + } + + if (cpu_is_omap44xx()) { + old0 = __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0); - old1 = __raw_readl(bank->base + + old1 = __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1); - __raw_writel(old0 | l, bank->base + + __raw_writel(old0 | l, bank->base + OMAP4_GPIO_LEVELDETECT0); - __raw_writel(old1 | l, bank->base + + __raw_writel(old1 | l, bank->base + OMAP4_GPIO_LEVELDETECT1); - __raw_writel(old0, bank->base + + __raw_writel(old0, bank->base + OMAP4_GPIO_LEVELDETECT0); - __raw_writel(old1, bank->base + + __raw_writel(old1, bank->base + OMAP4_GPIO_LEVELDETECT1); -#endif + } } } @@ -2144,7 +2176,7 @@ void omap2_gpio_resume_after_retention(void) #endif -#ifdef CONFIG_ARCH_OMAP34XX +#ifdef CONFIG_ARCH_OMAP3 /* save the registers of bank 2-6 */ void omap_gpio_save_context(void) { @@ -2240,8 +2272,7 @@ static int __init omap_gpio_sysinit(void) mpuio_init(); -#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ - defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4) +#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) if (cpu_is_omap16xx() || cpu_class_is_omap2()) { if (ret == 0) { ret = sysdev_class_register(&omap_gpio_sysclass); @@ -2300,8 +2331,7 @@ static int dbg_gpio_show(struct seq_file *s, void *unused) /* FIXME for at least omap2, show pullup/pulldown state */ irqstat = irq_desc[irq].status; -#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ - defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4) +#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) if (is_in && ((bank->suspend_wakeup & mask) || irqstat & IRQ_TYPE_SENSE_MASK)) { char *trigger = NULL; diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c index 33fff4ef382d..96d2781ac4f5 100644 --- a/arch/arm/plat-omap/i2c.c +++ b/arch/arm/plat-omap/i2c.c @@ -50,10 +50,10 @@ static const char name[] = "i2c_omap"; static struct resource i2c_resources[][2] = { { I2C_RESOURCE_BUILDER(0, 0) }, -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, INT_24XX_I2C2_IRQ) }, #endif -#if defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP3) { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, INT_34XX_I2C3_IRQ) }, #endif }; @@ -72,10 +72,10 @@ static struct resource i2c_resources[][2] = { static u32 i2c_rate[ARRAY_SIZE(i2c_resources)]; static struct platform_device omap_i2c_devices[] = { I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_rate[0]), -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_rate[1]), #endif -#if defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP3) I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_rate[2]), #endif }; diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h index 35b36caf5f91..bb937f3fabed 100644 --- a/arch/arm/plat-omap/include/plat/clkdev_omap.h +++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h @@ -25,17 +25,25 @@ struct omap_clk { }, \ } - +/* Platform flags for the clkdev-OMAP integration code */ #define CK_310 (1 << 0) -#define CK_7XX (1 << 1) +#define CK_7XX (1 << 1) /* 7xx, 850 */ #define CK_1510 (1 << 2) -#define CK_16XX (1 << 3) -#define CK_243X (1 << 4) -#define CK_242X (1 << 5) -#define CK_343X (1 << 6) -#define CK_3430ES1 (1 << 7) -#define CK_3430ES2 (1 << 8) -#define CK_443X (1 << 9) +#define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */ +#define CK_242X (1 << 4) +#define CK_243X (1 << 5) +#define CK_3XXX (1 << 6) /* OMAP3 + AM3 common clocks*/ +#define CK_343X (1 << 7) /* OMAP34xx common clocks */ +#define CK_3430ES1 (1 << 8) /* 34xxES1 only */ +#define CK_3430ES2 (1 << 9) /* 34xxES2, ES3, non-Sitara 35xx only */ +#define CK_3505 (1 << 10) +#define CK_3517 (1 << 11) +#define CK_36XX (1 << 12) /* OMAP36xx/37xx-specific clocks */ +#define CK_443X (1 << 13) + +#define CK_AM35XX (CK_3505 | CK_3517) /* all Sitara AM35xx */ + + #endif diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index 94fe2a0ce40a..8a86df4ad99c 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -26,8 +26,7 @@ struct clkops { void (*find_companion)(struct clk *, void __iomem **, u8 *); }; -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) +#ifdef CONFIG_ARCH_OMAP2PLUS struct clksel_rate { u32 val; @@ -88,9 +87,8 @@ struct clk { void (*init)(struct clk *); __u8 enable_bit; __s8 usecount; -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) u8 fixed_div; +#ifdef CONFIG_ARCH_OMAP2PLUS void __iomem *clksel_reg; u32 clksel_mask; const struct clksel *clksel; @@ -123,7 +121,7 @@ struct clk_functions { #endif }; -extern unsigned int mpurate; +extern int mpurate; extern int clk_init(struct clk_functions *custom_clocks); extern void clk_preinit(struct clk *clk); @@ -134,6 +132,7 @@ extern void propagate_rate(struct clk *clk); extern void recalculate_root_clocks(void); extern unsigned long followparent_recalc(struct clk *clk); extern void clk_enable_init_clocks(void); +unsigned long omap_fixed_divisor_recalc(struct clk *clk); #ifdef CONFIG_CPU_FREQ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table); extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table); diff --git a/arch/arm/plat-omap/include/plat/clockdomain.h b/arch/arm/plat-omap/include/plat/clockdomain.h index eb734826e64e..ba0a6c07c0fe 100644 --- a/arch/arm/plat-omap/include/plat/clockdomain.h +++ b/arch/arm/plat-omap/include/plat/clockdomain.h @@ -4,7 +4,7 @@ * OMAP2/3 clockdomain framework functions * * Copyright (C) 2008 Texas Instruments, Inc. - * Copyright (C) 2008 Nokia Corporation + * Copyright (C) 2008-2009 Nokia Corporation * * Written by Paul Walmsley * @@ -40,65 +40,95 @@ #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2 #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3 -/* - * struct clkdm_pwrdm_autodep - a powerdomain that should have wkdeps - * and sleepdeps added when a powerdomain should stay active in hwsup mode; - * and conversely, removed when the powerdomain should be allowed to go - * inactive in hwsup mode. +/** + * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode + * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only + * @omap_chip: OMAP chip types that this autodep is valid on + * + * A clockdomain that should have wkdeps and sleepdeps added when a + * clockdomain should stay active in hwsup mode; and conversely, + * removed when the clockdomain should be allowed to go inactive in + * hwsup mode. + * + * Autodeps are deprecated and should be removed after + * omap_hwmod-based fine-grained module idle control is added. */ -struct clkdm_pwrdm_autodep { - +struct clkdm_autodep { union { - /* Name of the powerdomain to add a wkdep/sleepdep on */ const char *name; - - /* Powerdomain pointer (looked up at clkdm_init() time) */ - struct powerdomain *ptr; - } pwrdm; - - /* OMAP chip types that this clockdomain dep is valid on */ + struct clockdomain *ptr; + } clkdm; const struct omap_chip_id omap_chip; +}; +/** + * struct clkdm_dep - encode dependencies between clockdomains + * @clkdm_name: clockdomain name + * @clkdm: pointer to the struct clockdomain of @clkdm_name + * @omap_chip: OMAP chip types that this dependency is valid on + * @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake + * @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle + * + * Statically defined. @clkdm is resolved from @clkdm_name at runtime and + * should not be pre-initialized. + * + * XXX Should also include hardware (fixed) dependencies. + */ +struct clkdm_dep { + const char *clkdm_name; + struct clockdomain *clkdm; + atomic_t wkdep_usecount; + atomic_t sleepdep_usecount; + const struct omap_chip_id omap_chip; }; +/** + * struct clockdomain - OMAP clockdomain + * @name: clockdomain name + * @pwrdm: powerdomain containing this clockdomain + * @clktrctrl_reg: CLKSTCTRL reg for the given clock domain + * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg + * @flags: Clockdomain capability flags + * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit + * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up + * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact + * @omap_chip: OMAP chip types that this clockdomain is valid on + * @usecount: Usecount tracking + * @node: list_head to link all clockdomains together + */ struct clockdomain { - - /* Clockdomain name */ const char *name; - union { - /* Powerdomain enclosing this clockdomain */ const char *name; - - /* Powerdomain pointer assigned at clkdm_register() */ struct powerdomain *ptr; } pwrdm; - - /* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */ + void __iomem *clkstctrl_reg; const u16 clktrctrl_mask; - - /* Clockdomain capability flags */ const u8 flags; - - /* OMAP chip types that this clockdomain is valid on */ + const u8 dep_bit; + struct clkdm_dep *wkdep_srcs; + struct clkdm_dep *sleepdep_srcs; const struct omap_chip_id omap_chip; - - /* Usecount tracking */ atomic_t usecount; - struct list_head node; - }; -void clkdm_init(struct clockdomain **clkdms, struct clkdm_pwrdm_autodep *autodeps); -int clkdm_register(struct clockdomain *clkdm); -int clkdm_unregister(struct clockdomain *clkdm); +void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps); struct clockdomain *clkdm_lookup(const char *name); int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user), void *user); struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm); +int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_clear_all_wkdeps(struct clockdomain *clkdm); +int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm); + void omap2_clkdm_allow_idle(struct clockdomain *clkdm); void omap2_clkdm_deny_idle(struct clockdomain *clkdm); diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h index 32c22272425d..e04a58ec53a2 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/include/plat/common.h @@ -47,11 +47,16 @@ struct omap_globals { void __iomem *prm; /* Power and Reset Management */ void __iomem *cm; /* Clock Management */ void __iomem *cm2; + unsigned long uart1_phys; + unsigned long uart2_phys; + unsigned long uart3_phys; + unsigned long uart4_phys; }; void omap2_set_globals_242x(void); void omap2_set_globals_243x(void); void omap2_set_globals_343x(void); +void omap2_set_globals_36xx(void); void omap2_set_globals_443x(void); /* These get called from omap2_set_globals_xxxx(), do not call these */ @@ -59,6 +64,7 @@ void omap2_set_globals_tap(struct omap_globals *); void omap2_set_globals_sdrc(struct omap_globals *); void omap2_set_globals_control(struct omap_globals *); void omap2_set_globals_prcm(struct omap_globals *); +void omap2_set_globals_uart(struct omap_globals *); /** * omap_test_timeout - busy-loop, testing a condition diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h index a745d62fad0d..207447399ad3 100644 --- a/arch/arm/plat-omap/include/plat/control.h +++ b/arch/arm/plat-omap/include/plat/control.h @@ -160,6 +160,14 @@ #define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0) #define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4) +/* AM35XX only CONTROL_GENERAL register offsets */ +#define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038) +#define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310) +#define AM35XX_CONTROL_DEVCONF3 (OMAP2_CONTROL_GENERAL + 0x0314) +#define AM35XX_CONTROL_CBA_PRIORITY (OMAP2_CONTROL_GENERAL + 0x0320) +#define AM35XX_CONTROL_LVL_INTR_CLEAR (OMAP2_CONTROL_GENERAL + 0x0324) +#define AM35XX_CONTROL_IP_SW_RESET (OMAP2_CONTROL_GENERAL + 0x0328) +#define AM35XX_CONTROL_IPSS_CLK_CTRL (OMAP2_CONTROL_GENERAL + 0x032C) /* 34xx PADCONF register offsets */ #define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \ @@ -257,6 +265,32 @@ #define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) #define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C +/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ +#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 +#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 +#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 +#define AM35XX_HECC_VBUSP_CLK_SHIFT 3 +#define AM35XX_USBOTG_FCLK_SHIFT 8 +#define AM35XX_CPGMAC_FCLK_SHIFT 9 +#define AM35XX_VPFE_FCLK_SHIFT 10 + +/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/ +#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) +#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) +#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) +#define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3) +#define AM35XX_USBOTGSS_INT_CLR BIT(4) +#define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5) +#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) +#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) + +/*AM35XX CONTROL_IP_SW_RESET bits*/ +#define AM35XX_USBOTGSS_SW_RST BIT(0) +#define AM35XX_CPGMACSS_SW_RST BIT(1) +#define AM35XX_VPFE_VBUSP_SW_RST BIT(2) +#define AM35XX_HECC_SW_RST BIT(3) +#define AM35XX_VPFE_PCLK_SW_RST BIT(4) + /* * CONTROL OMAP STATUS register to identify OMAP3 features */ @@ -292,8 +326,7 @@ #ifndef __ASSEMBLY__ -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) +#ifdef CONFIG_ARCH_OMAP2PLUS extern void __iomem *omap_ctrl_base_get(void); extern u8 omap_ctrl_readb(u16 offset); extern u16 omap_ctrl_readw(u16 offset); diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index a162f585b1e3..b80151c1ee61 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -31,6 +31,7 @@ #define __ASM_ARCH_OMAP_CPU_H #include <linux/bitops.h> +#include <plat/multi.h> /* * Omap device type i.e. EMU/HS/TST/GP/BAD @@ -44,7 +45,7 @@ int omap_type(void); struct omap_chip_id { - u8 oc; + u16 oc; u8 type; }; @@ -76,75 +77,6 @@ unsigned int omap_rev(void); #define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff) /* - * Test if multicore OMAP support is needed - */ -#undef MULTI_OMAP1 -#undef MULTI_OMAP2 -#undef OMAP_NAME - -#ifdef CONFIG_ARCH_OMAP730 -# ifdef OMAP_NAME -# undef MULTI_OMAP1 -# define MULTI_OMAP1 -# else -# define OMAP_NAME omap730 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP850 -# ifdef OMAP_NAME -# undef MULTI_OMAP1 -# define MULTI_OMAP1 -# else -# define OMAP_NAME omap850 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP15XX -# ifdef OMAP_NAME -# undef MULTI_OMAP1 -# define MULTI_OMAP1 -# else -# define OMAP_NAME omap1510 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP16XX -# ifdef OMAP_NAME -# undef MULTI_OMAP1 -# define MULTI_OMAP1 -# else -# define OMAP_NAME omap16xx -# endif -#endif -#if (defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)) -# if (defined(OMAP_NAME) || defined(MULTI_OMAP1)) -# error "OMAP1 and OMAP2 can't be selected at the same time" -# endif -#endif -#ifdef CONFIG_ARCH_OMAP2420 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap2420 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP2430 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap2430 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP3430 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap3430 -# endif -#endif - -/* * Macros to group OMAP into cpu classes. * These can be used in most places. * cpu_is_omap7xx(): True for OMAP730, OMAP850 @@ -154,6 +86,7 @@ unsigned int omap_rev(void); * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423 * cpu_is_omap243x(): True for OMAP2430 * cpu_is_omap343x(): True for OMAP3430 + * cpu_is_omap443x(): True for OMAP4430 */ #define GET_OMAP_CLASS (omap_rev() & 0xff) @@ -232,7 +165,7 @@ IS_OMAP_SUBCLASS(443x, 0x443) #endif #if defined(MULTI_OMAP2) -# if defined(CONFIG_ARCH_OMAP24XX) +# if defined(CONFIG_ARCH_OMAP2) # undef cpu_is_omap24xx # undef cpu_is_omap242x # undef cpu_is_omap243x @@ -240,14 +173,14 @@ IS_OMAP_SUBCLASS(443x, 0x443) # define cpu_is_omap242x() is_omap242x() # define cpu_is_omap243x() is_omap243x() # endif -# if defined(CONFIG_ARCH_OMAP34XX) +# if defined(CONFIG_ARCH_OMAP3) # undef cpu_is_omap34xx # undef cpu_is_omap343x # define cpu_is_omap34xx() is_omap34xx() # define cpu_is_omap343x() is_omap343x() # endif #else -# if defined(CONFIG_ARCH_OMAP24XX) +# if defined(CONFIG_ARCH_OMAP2) # undef cpu_is_omap24xx # define cpu_is_omap24xx() 1 # endif @@ -259,7 +192,7 @@ IS_OMAP_SUBCLASS(443x, 0x443) # undef cpu_is_omap243x # define cpu_is_omap243x() 1 # endif -# if defined(CONFIG_ARCH_OMAP34XX) +# if defined(CONFIG_ARCH_OMAP3) # undef cpu_is_omap34xx # define cpu_is_omap34xx() 1 # endif @@ -286,6 +219,7 @@ IS_OMAP_SUBCLASS(443x, 0x443) * cpu_is_omap2423(): True for OMAP2423 * cpu_is_omap2430(): True for OMAP2430 * cpu_is_omap3430(): True for OMAP3430 + * cpu_is_omap4430(): True for OMAP4430 * cpu_is_omap3505(): True for OMAP3505 * cpu_is_omap3517(): True for OMAP3517 */ @@ -334,6 +268,7 @@ IS_OMAP_TYPE(3517, 0x3517) #define cpu_is_omap3505() 0 #define cpu_is_omap3517() 0 #define cpu_is_omap3430() 0 +#define cpu_is_omap4430() 0 #define cpu_is_omap3630() 0 /* @@ -371,7 +306,7 @@ IS_OMAP_TYPE(3517, 0x3517) # define cpu_is_omap1710() is_omap1710() #endif -#if defined(CONFIG_ARCH_OMAP24XX) +#if defined(CONFIG_ARCH_OMAP2) # undef cpu_is_omap2420 # undef cpu_is_omap2422 # undef cpu_is_omap2423 @@ -382,7 +317,7 @@ IS_OMAP_TYPE(3517, 0x3517) # define cpu_is_omap2430() is_omap2430() #endif -#if defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP3) # undef cpu_is_omap3430 # undef cpu_is_omap3503 # undef cpu_is_omap3515 @@ -471,9 +406,12 @@ IS_OMAP_TYPE(3517, 0x3517) #define CHIP_IS_OMAP3430ES3_0 (1 << 5) #define CHIP_IS_OMAP3430ES3_1 (1 << 6) #define CHIP_IS_OMAP3630ES1 (1 << 7) +#define CHIP_IS_OMAP4430ES1 (1 << 8) #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) +#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1) + /* * "GE" here represents "greater than or equal to" in terms of ES * levels. So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430 diff --git a/arch/arm/plat-omap/include/plat/flash.h b/arch/arm/plat-omap/include/plat/flash.h new file mode 100644 index 000000000000..3e6327016b40 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/flash.h @@ -0,0 +1,16 @@ +/* + * Flash support for OMAP1 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __OMAP_FLASH_H +#define __OMAP_FLASH_H + +#include <linux/mtd/map.h> + +extern void omap1_set_vpp(struct map_info *map, int enable); + +#endif diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index e081338e0b23..145838a81ef6 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h @@ -27,6 +27,8 @@ #define GPMC_CONFIG 0x50 #define GPMC_STATUS 0x54 +#define GPMC_CS0_BASE 0x60 +#define GPMC_CS_SIZE 0x30 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) @@ -110,6 +112,6 @@ extern void gpmc_prefetch_reset(void); extern int gpmc_prefetch_status(void); extern void omap3_gpmc_save_context(void); extern void omap3_gpmc_restore_context(void); -extern void __init gpmc_init(void); +extern void gpmc_init(void); #endif diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h index a3e7b471bcba..eef914d53971 100644 --- a/arch/arm/plat-omap/include/plat/io.h +++ b/arch/arm/plat-omap/include/plat/io.h @@ -268,7 +268,38 @@ struct omap_sdrc_params; extern void omap1_map_common_io(void); extern void omap1_init_common_hw(void); -extern void omap2_map_common_io(void); +#ifdef CONFIG_ARCH_OMAP2420 +extern void omap242x_map_common_io(void); +#else +static inline void omap242x_map_common_io(void) +{ +} +#endif + +#ifdef CONFIG_ARCH_OMAP2430 +extern void omap243x_map_common_io(void); +#else +static inline void omap243x_map_common_io(void) +{ +} +#endif + +#ifdef CONFIG_ARCH_OMAP3 +extern void omap34xx_map_common_io(void); +#else +static inline void omap34xx_map_common_io(void) +{ +} +#endif + +#ifdef CONFIG_ARCH_OMAP4 +extern void omap44xx_map_common_io(void); +#else +static inline void omap44xx_map_common_io(void) +{ +} +#endif + extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1); diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h index c0ab7c80f72e..e8205c13a27a 100644 --- a/arch/arm/plat-omap/include/plat/irqs.h +++ b/arch/arm/plat-omap/include/plat/irqs.h @@ -344,6 +344,16 @@ #define INT_34XX_BENCH_MPU_EMUL 3 +#define INT_35XX_HECC0_IRQ 24 +#define INT_35XX_HECC1_IRQ 28 +#define INT_35XX_EMAC_C0_RXTHRESH_IRQ 67 +#define INT_35XX_EMAC_C0_RX_PULSE_IRQ 68 +#define INT_35XX_EMAC_C0_TX_PULSE_IRQ 69 +#define INT_35XX_EMAC_C0_MISC_PULSE_IRQ 70 +#define INT_35XX_USBOTG_IRQ 71 +#define INT_35XX_CCDC_VD0_IRQ 88 +#define INT_35XX_CCDC_VD1_IRQ 92 +#define INT_35XX_CCDC_VD2_IRQ 93 #define IRQ_GIC_START 32 #define INT_44XX_LOCALTIMER_IRQ 29 @@ -432,7 +442,7 @@ #define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START) #define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START) #define INT_44XX_MMC4_IRQ (96 + IRQ_GIC_START) - +#define INT_44XX_MCPDM_IRQ (112 + IRQ_GIC_START) /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and * 16 MPUIO lines */ diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index 4f22e5bb7ff7..4df957b1d252 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -103,8 +103,7 @@ #define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX #define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX -#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ - defined(CONFIG_ARCH_OMAP4) +#else #define OMAP_MCBSP_REG_DRR2 0x00 #define OMAP_MCBSP_REG_DRR1 0x04 @@ -374,7 +373,7 @@ struct omap_mcbsp_platform_data { u8 dma_rx_sync, dma_tx_sync; u16 rx_irq, tx_irq; struct omap_mcbsp_ops *ops; -#ifdef CONFIG_ARCH_OMAP34XX +#ifdef CONFIG_ARCH_OMAP3 u16 buffer_size; #endif }; @@ -410,20 +409,21 @@ struct omap_mcbsp { struct omap_mcbsp_platform_data *pdata; struct clk *iclk; struct clk *fclk; -#ifdef CONFIG_ARCH_OMAP34XX +#ifdef CONFIG_ARCH_OMAP3 int dma_op_mode; u16 max_tx_thres; u16 max_rx_thres; #endif + void *reg_cache; }; extern struct omap_mcbsp **mcbsp_ptr; -extern int omap_mcbsp_count; +extern int omap_mcbsp_count, omap_mcbsp_cache_size; int omap_mcbsp_init(void); void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, int size); void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); -#ifdef CONFIG_ARCH_OMAP34XX +#ifdef CONFIG_ARCH_OMAP3 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold); void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold); u16 omap_mcbsp_get_max_tx_threshold(unsigned int id); diff --git a/arch/arm/plat-omap/include/plat/memory.h b/arch/arm/plat-omap/include/plat/memory.h index 3325f7b49eaa..d5306bee44b2 100644 --- a/arch/arm/plat-omap/include/plat/memory.h +++ b/arch/arm/plat-omap/include/plat/memory.h @@ -38,8 +38,7 @@ */ #if defined(CONFIG_ARCH_OMAP1) #define PHYS_OFFSET UL(0x10000000) -#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) +#else #define PHYS_OFFSET UL(0x80000000) #endif diff --git a/arch/arm/plat-omap/include/plat/menelaus.h b/arch/arm/plat-omap/include/plat/menelaus.h index 3122bf68c7ce..4a970ec62dd1 100644 --- a/arch/arm/plat-omap/include/plat/menelaus.h +++ b/arch/arm/plat-omap/include/plat/menelaus.h @@ -40,7 +40,7 @@ extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV); extern int menelaus_set_regulator_sleep(int enable, u32 val); -#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS) +#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_MENELAUS) #define omap_has_menelaus() 1 #else #define omap_has_menelaus() 0 diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index 29937137bf3e..a1bac07c89eb 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -55,12 +55,12 @@ struct omap_mmc_platform_data { unsigned int max_freq; /* switch the bus to a new slot */ - int (* switch_slot)(struct device *dev, int slot); + int (*switch_slot)(struct device *dev, int slot); /* initialize board-specific MMC functionality, can be NULL if * not supported */ - int (* init)(struct device *dev); - void (* cleanup)(struct device *dev); - void (* shutdown)(struct device *dev); + int (*init)(struct device *dev); + void (*cleanup)(struct device *dev); + void (*shutdown)(struct device *dev); /* To handle board related suspend/resume functionality for MMC */ int (*suspend)(struct device *dev, int slot); @@ -96,14 +96,28 @@ struct omap_mmc_platform_data { /* Try to sleep or power off when possible */ unsigned power_saving:1; + /* If using power_saving and the MMC power is not to go off */ + unsigned no_off:1; + + /* Regulator off remapped to sleep */ + unsigned vcc_aux_disable_is_sleep:1; + int switch_pin; /* gpio (card detect) */ int gpio_wp; /* gpio (write protect) */ - int (* set_bus_mode)(struct device *dev, int slot, int bus_mode); - int (* set_power)(struct device *dev, int slot, int power_on, int vdd); - int (* get_ro)(struct device *dev, int slot); + int (*set_bus_mode)(struct device *dev, int slot, int bus_mode); + int (*set_power)(struct device *dev, int slot, + int power_on, int vdd); + int (*get_ro)(struct device *dev, int slot); int (*set_sleep)(struct device *dev, int slot, int sleep, int vdd, int cardsleep); + void (*remux)(struct device *dev, int slot, int power_on); + /* Call back before enabling / disabling regulators */ + void (*before_set_reg)(struct device *dev, int slot, + int power_on, int vdd); + /* Call back after enabling / disabling regulators */ + void (*after_set_reg)(struct device *dev, int slot, + int power_on, int vdd); /* return MMC cover switch state, can be NULL if not supported. * @@ -111,14 +125,14 @@ struct omap_mmc_platform_data { * 0 - closed * 1 - open */ - int (* get_cover_state)(struct device *dev, int slot); + int (*get_cover_state)(struct device *dev, int slot); const char *name; u32 ocr_mask; /* Card detection IRQs */ int card_detect_irq; - int (* card_detect)(int irq); + int (*card_detect)(struct device *dev, int slot); unsigned int ban_openended:1; @@ -126,7 +140,8 @@ struct omap_mmc_platform_data { }; /* called from board-specific card detection service routine */ -extern void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed); +extern void omap_mmc_notify_cover_event(struct device *dev, int slot, + int is_closed); #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h new file mode 100644 index 000000000000..f235d32cd942 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/multi.h @@ -0,0 +1,94 @@ +/* + * Support for compiling in multiple OMAP processors + * + * Copyright (C) 2010 Nokia Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __PLAT_OMAP_MULTI_H +#define __PLAT_OMAP_MULTI_H + +/* + * Test if multicore OMAP support is needed + */ +#undef MULTI_OMAP1 +#undef MULTI_OMAP2 +#undef OMAP_NAME + +#ifdef CONFIG_ARCH_OMAP730 +# ifdef OMAP_NAME +# undef MULTI_OMAP1 +# define MULTI_OMAP1 +# else +# define OMAP_NAME omap730 +# endif +#endif +#ifdef CONFIG_ARCH_OMAP850 +# ifdef OMAP_NAME +# undef MULTI_OMAP1 +# define MULTI_OMAP1 +# else +# define OMAP_NAME omap850 +# endif +#endif +#ifdef CONFIG_ARCH_OMAP15XX +# ifdef OMAP_NAME +# undef MULTI_OMAP1 +# define MULTI_OMAP1 +# else +# define OMAP_NAME omap1510 +# endif +#endif +#ifdef CONFIG_ARCH_OMAP16XX +# ifdef OMAP_NAME +# undef MULTI_OMAP1 +# define MULTI_OMAP1 +# else +# define OMAP_NAME omap16xx +# endif +#endif +#if (defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)) +# if (defined(OMAP_NAME) || defined(MULTI_OMAP1)) +# error "OMAP1 and OMAP2 can't be selected at the same time" +# endif +#endif +#ifdef CONFIG_ARCH_OMAP2420 +# ifdef OMAP_NAME +# undef MULTI_OMAP2 +# define MULTI_OMAP2 +# else +# define OMAP_NAME omap2420 +# endif +#endif +#ifdef CONFIG_ARCH_OMAP2430 +# ifdef OMAP_NAME +# undef MULTI_OMAP2 +# define MULTI_OMAP2 +# else +# define OMAP_NAME omap2430 +# endif +#endif +#ifdef CONFIG_ARCH_OMAP3430 +# ifdef OMAP_NAME +# undef MULTI_OMAP2 +# define MULTI_OMAP2 +# else +# define OMAP_NAME omap3430 +# endif +#endif + +#endif /* __PLAT_OMAP_MULTI_H */ diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h index 692c90e89ac3..c7472a28ce24 100644 --- a/arch/arm/plat-omap/include/plat/mux.h +++ b/arch/arm/plat-omap/include/plat/mux.h @@ -135,7 +135,7 @@ struct pin_config { const unsigned int mux_reg; unsigned char debug; -#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX) +#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2) const unsigned char mask_offset; const unsigned char mask; diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h index 631a7bed1eef..6ba88d2630d9 100644 --- a/arch/arm/plat-omap/include/plat/nand.h +++ b/arch/arm/plat-omap/include/plat/nand.h @@ -15,10 +15,18 @@ struct omap_nand_platform_data { int cs; int gpio_irq; struct mtd_partition *parts; + struct gpmc_timings *gpmc_t; int nr_parts; - int (*nand_setup)(void __iomem *); + int (*nand_setup)(void); int (*dev_ready)(struct omap_nand_platform_data *); int dma_channel; + unsigned long phys_base; void __iomem *gpmc_cs_baseaddr; void __iomem *gpmc_baseaddr; + int devsize; }; + +/* size (4 KiB) for IO mapping */ +#define NAND_IO_SIZE SZ_4K + +extern int gpmc_nand_init(struct omap_nand_platform_data *d); diff --git a/arch/arm/plat-omap/include/plat/omap16xx.h b/arch/arm/plat-omap/include/plat/omap16xx.h index 7560b4d583a3..e69e1d857b45 100644 --- a/arch/arm/plat-omap/include/plat/omap16xx.h +++ b/arch/arm/plat-omap/include/plat/omap16xx.h @@ -125,43 +125,43 @@ #define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160) /* UART3 Registers Mapping through MPU bus */ -#define UART3_RHR (OMAP_UART3_BASE + 0) -#define UART3_THR (OMAP_UART3_BASE + 0) -#define UART3_DLL (OMAP_UART3_BASE + 0) -#define UART3_IER (OMAP_UART3_BASE + 4) -#define UART3_DLH (OMAP_UART3_BASE + 4) -#define UART3_IIR (OMAP_UART3_BASE + 8) -#define UART3_FCR (OMAP_UART3_BASE + 8) -#define UART3_EFR (OMAP_UART3_BASE + 8) -#define UART3_LCR (OMAP_UART3_BASE + 0x0C) -#define UART3_MCR (OMAP_UART3_BASE + 0x10) -#define UART3_XON1_ADDR1 (OMAP_UART3_BASE + 0x10) -#define UART3_XON2_ADDR2 (OMAP_UART3_BASE + 0x14) -#define UART3_LSR (OMAP_UART3_BASE + 0x14) -#define UART3_TCR (OMAP_UART3_BASE + 0x18) -#define UART3_MSR (OMAP_UART3_BASE + 0x18) -#define UART3_XOFF1 (OMAP_UART3_BASE + 0x18) -#define UART3_XOFF2 (OMAP_UART3_BASE + 0x1C) -#define UART3_SPR (OMAP_UART3_BASE + 0x1C) -#define UART3_TLR (OMAP_UART3_BASE + 0x1C) -#define UART3_MDR1 (OMAP_UART3_BASE + 0x20) -#define UART3_MDR2 (OMAP_UART3_BASE + 0x24) -#define UART3_SFLSR (OMAP_UART3_BASE + 0x28) -#define UART3_TXFLL (OMAP_UART3_BASE + 0x28) -#define UART3_RESUME (OMAP_UART3_BASE + 0x2C) -#define UART3_TXFLH (OMAP_UART3_BASE + 0x2C) -#define UART3_SFREGL (OMAP_UART3_BASE + 0x30) -#define UART3_RXFLL (OMAP_UART3_BASE + 0x30) -#define UART3_SFREGH (OMAP_UART3_BASE + 0x34) -#define UART3_RXFLH (OMAP_UART3_BASE + 0x34) -#define UART3_BLR (OMAP_UART3_BASE + 0x38) -#define UART3_ACREG (OMAP_UART3_BASE + 0x3C) -#define UART3_DIV16 (OMAP_UART3_BASE + 0x3C) -#define UART3_SCR (OMAP_UART3_BASE + 0x40) -#define UART3_SSR (OMAP_UART3_BASE + 0x44) -#define UART3_EBLR (OMAP_UART3_BASE + 0x48) -#define UART3_OSC_12M_SEL (OMAP_UART3_BASE + 0x4C) -#define UART3_MVR (OMAP_UART3_BASE + 0x50) +#define UART3_RHR (OMAP1_UART3_BASE + 0) +#define UART3_THR (OMAP1_UART3_BASE + 0) +#define UART3_DLL (OMAP1_UART3_BASE + 0) +#define UART3_IER (OMAP1_UART3_BASE + 4) +#define UART3_DLH (OMAP1_UART3_BASE + 4) +#define UART3_IIR (OMAP1_UART3_BASE + 8) +#define UART3_FCR (OMAP1_UART3_BASE + 8) +#define UART3_EFR (OMAP1_UART3_BASE + 8) +#define UART3_LCR (OMAP1_UART3_BASE + 0x0C) +#define UART3_MCR (OMAP1_UART3_BASE + 0x10) +#define UART3_XON1_ADDR1 (OMAP1_UART3_BASE + 0x10) +#define UART3_XON2_ADDR2 (OMAP1_UART3_BASE + 0x14) +#define UART3_LSR (OMAP1_UART3_BASE + 0x14) +#define UART3_TCR (OMAP1_UART3_BASE + 0x18) +#define UART3_MSR (OMAP1_UART3_BASE + 0x18) +#define UART3_XOFF1 (OMAP1_UART3_BASE + 0x18) +#define UART3_XOFF2 (OMAP1_UART3_BASE + 0x1C) +#define UART3_SPR (OMAP1_UART3_BASE + 0x1C) +#define UART3_TLR (OMAP1_UART3_BASE + 0x1C) +#define UART3_MDR1 (OMAP1_UART3_BASE + 0x20) +#define UART3_MDR2 (OMAP1_UART3_BASE + 0x24) +#define UART3_SFLSR (OMAP1_UART3_BASE + 0x28) +#define UART3_TXFLL (OMAP1_UART3_BASE + 0x28) +#define UART3_RESUME (OMAP1_UART3_BASE + 0x2C) +#define UART3_TXFLH (OMAP1_UART3_BASE + 0x2C) +#define UART3_SFREGL (OMAP1_UART3_BASE + 0x30) +#define UART3_RXFLL (OMAP1_UART3_BASE + 0x30) +#define UART3_SFREGH (OMAP1_UART3_BASE + 0x34) +#define UART3_RXFLH (OMAP1_UART3_BASE + 0x34) +#define UART3_BLR (OMAP1_UART3_BASE + 0x38) +#define UART3_ACREG (OMAP1_UART3_BASE + 0x3C) +#define UART3_DIV16 (OMAP1_UART3_BASE + 0x3C) +#define UART3_SCR (OMAP1_UART3_BASE + 0x40) +#define UART3_SSR (OMAP1_UART3_BASE + 0x44) +#define UART3_EBLR (OMAP1_UART3_BASE + 0x48) +#define UART3_OSC_12M_SEL (OMAP1_UART3_BASE + 0x4C) +#define UART3_MVR (OMAP1_UART3_BASE + 0x50) /* * --------------------------------------------------------------------------- diff --git a/arch/arm/plat-omap/include/plat/omap24xx.h b/arch/arm/plat-omap/include/plat/omap24xx.h index 696edfc145a6..7055672a8c68 100644 --- a/arch/arm/plat-omap/include/plat/omap24xx.h +++ b/arch/arm/plat-omap/include/plat/omap24xx.h @@ -23,8 +23,8 @@ * */ -#ifndef __ASM_ARCH_OMAP24XX_H -#define __ASM_ARCH_OMAP24XX_H +#ifndef __ASM_ARCH_OMAP2_H +#define __ASM_ARCH_OMAP2_H /* * Please place only base defines here and put the rest in device @@ -85,5 +85,5 @@ #define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000) #define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000) -#endif /* __ASM_ARCH_OMAP24XX_H */ +#endif /* __ASM_ARCH_OMAP2_H */ diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h index 077f05979f86..2845fdc658b0 100644 --- a/arch/arm/plat-omap/include/plat/omap34xx.h +++ b/arch/arm/plat-omap/include/plat/omap34xx.h @@ -21,8 +21,8 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef __ASM_ARCH_OMAP34XX_H -#define __ASM_ARCH_OMAP34XX_H +#ifndef __ASM_ARCH_OMAP3_H +#define __ASM_ARCH_OMAP3_H /* * Please place only base defines here and put the rest in device @@ -82,5 +82,5 @@ #define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000) -#endif /* __ASM_ARCH_OMAP34XX_H */ +#endif /* __ASM_ARCH_OMAP3_H */ diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h index ef870de43c29..2068b39f76bb 100644 --- a/arch/arm/plat-omap/include/plat/omap44xx.h +++ b/arch/arm/plat-omap/include/plat/omap44xx.h @@ -41,6 +41,8 @@ #define OMAP44XX_SCU_BASE 0x48240000 #define OMAP44XX_LOCAL_TWD_BASE 0x48240600 #define OMAP44XX_WKUPGEN_BASE 0x48281000 +#define OMAP44XX_MCPDM_BASE 0x40132000 +#define OMAP44XX_MCPDM_L3_BASE 0x49032000 #define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000) diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h index dc1fac1d805c..76d49171fed9 100644 --- a/arch/arm/plat-omap/include/plat/omap_device.h +++ b/arch/arm/plat-omap/include/plat/omap_device.h @@ -131,11 +131,15 @@ int omap_device_enable_clocks(struct omap_device *od); */ struct omap_device_pm_latency { u32 deactivate_lat; + u32 deactivate_lat_worst; int (*deactivate_func)(struct omap_device *od); u32 activate_lat; + u32 activate_lat_worst; int (*activate_func)(struct omap_device *od); + u32 flags; }; +#define OMAP_DEVICE_LATENCY_AUTO_ADJUST BIT(1) /* Get omap_device pointer from platform_device pointer */ #define to_omap_device(x) container_of((x), struct omap_device, pdev) diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 33933256a226..921990e2a29a 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -441,6 +441,8 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh); int omap_hwmod_enable_clocks(struct omap_hwmod *oh); int omap_hwmod_disable_clocks(struct omap_hwmod *oh); +int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode); + int omap_hwmod_reset(struct omap_hwmod *oh); void omap_hwmod_ocp_barrier(struct omap_hwmod *oh); diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h index 0b960051eaed..e15c7e9da975 100644 --- a/arch/arm/plat-omap/include/plat/powerdomain.h +++ b/arch/arm/plat-omap/include/plat/powerdomain.h @@ -1,8 +1,8 @@ /* * OMAP2/3 powerdomain control * - * Copyright (C) 2007-8 Texas Instruments, Inc. - * Copyright (C) 2007-8 Nokia Corporation + * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2009 Nokia Corporation * * Written by Paul Walmsley * @@ -37,6 +37,9 @@ #define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \ (1 << PWRDM_POWER_RET)) +#define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \ + (1 << PWRDM_POWER_ON)) + #define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON)) @@ -48,16 +51,16 @@ */ /* - * Number of memory banks that are power-controllable. On OMAP3430, the - * maximum is 4. + * Number of memory banks that are power-controllable. On OMAP4430, the + * maximum is 5. */ -#define PWRDM_MAX_MEM_BANKS 4 +#define PWRDM_MAX_MEM_BANKS 5 /* * Maximum number of clockdomains that can be associated with a powerdomain. - * CORE powerdomain on OMAP3 is the worst case + * CORE powerdomain on OMAP4 is the worst case */ -#define PWRDM_MAX_CLKDMS 4 +#define PWRDM_MAX_CLKDMS 9 /* XXX A completely arbitrary number. What is reasonable here? */ #define PWRDM_TRANSITION_BAILOUT 100000 @@ -65,63 +68,36 @@ struct clockdomain; struct powerdomain; -/* Encodes dependencies between powerdomains - statically defined */ -struct pwrdm_dep { - - /* Powerdomain name */ - const char *pwrdm_name; - - /* Powerdomain pointer - resolved by the powerdomain code */ - struct powerdomain *pwrdm; - - /* Flags to mark OMAP chip restrictions, etc. */ - const struct omap_chip_id omap_chip; - -}; - +/** + * struct powerdomain - OMAP powerdomain + * @name: Powerdomain name + * @omap_chip: represents the OMAP chip types containing this pwrdm + * @prcm_offs: the address offset from CM_BASE/PRM_BASE + * @pwrsts: Possible powerdomain power states + * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION + * @flags: Powerdomain flags + * @banks: Number of software-controllable memory banks in this powerdomain + * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION + * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON + * @pwrdm_clkdms: Clockdomains in this powerdomain + * @node: list_head linking all powerdomains + * @state: + * @state_counter: + * @timer: + * @state_timer: + */ struct powerdomain { - - /* Powerdomain name */ const char *name; - - /* the address offset from CM_BASE/PRM_BASE */ - const s16 prcm_offs; - - /* Used to represent the OMAP chip types containing this pwrdm */ const struct omap_chip_id omap_chip; - - /* Powerdomains that can be told to wake this powerdomain up */ - struct pwrdm_dep *wkdep_srcs; - - /* Powerdomains that can be told to keep this pwrdm from inactivity */ - struct pwrdm_dep *sleepdep_srcs; - - /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */ - const u8 dep_bit; - - /* Possible powerdomain power states */ + const s16 prcm_offs; const u8 pwrsts; - - /* Possible logic power states when pwrdm in RETENTION */ const u8 pwrsts_logic_ret; - - /* Powerdomain flags */ const u8 flags; - - /* Number of software-controllable memory banks in this powerdomain */ const u8 banks; - - /* Possible memory bank pwrstates when pwrdm in RETENTION */ const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS]; - - /* Possible memory bank pwrstates when pwrdm is ON */ const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS]; - - /* Clockdomains in this powerdomain */ struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS]; - struct list_head node; - int state; unsigned state_counter[PWRDM_MAX_PWRSTS]; @@ -134,8 +110,6 @@ struct powerdomain { void pwrdm_init(struct powerdomain **pwrdm_list); -int pwrdm_register(struct powerdomain *pwrdm); -int pwrdm_unregister(struct powerdomain *pwrdm); struct powerdomain *pwrdm_lookup(const char *name); int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), @@ -149,13 +123,6 @@ int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, int (*fn)(struct powerdomain *pwrdm, struct clockdomain *clkdm)); -int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); -int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); -int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); -int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); -int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); -int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); - int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h index e63e94e18975..66938a9f8dae 100644 --- a/arch/arm/plat-omap/include/plat/prcm.h +++ b/arch/arm/plat-omap/include/plat/prcm.h @@ -33,6 +33,14 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name); void omap3_prcm_save_context(void); void omap3_prcm_restore_context(void); +u32 prm_read_mod_reg(s16 module, u16 idx); +void prm_write_mod_reg(u32 val, s16 module, u16 idx); +u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); +u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); +u32 cm_read_mod_reg(s16 module, u16 idx); +void cm_write_mod_reg(u32 val, s16 module, u16 idx); +u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); + #endif diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h index f5a4a92393ef..83dce4c4f7e6 100644 --- a/arch/arm/plat-omap/include/plat/serial.h +++ b/arch/arm/plat-omap/include/plat/serial.h @@ -15,37 +15,65 @@ #include <linux/init.h> -#if defined(CONFIG_ARCH_OMAP1) /* OMAP1 serial ports */ -#define OMAP_UART1_BASE 0xfffb0000 -#define OMAP_UART2_BASE 0xfffb0800 -#define OMAP_UART3_BASE 0xfffb9800 -#elif defined(CONFIG_ARCH_OMAP2) +#define OMAP1_UART1_BASE 0xfffb0000 +#define OMAP1_UART2_BASE 0xfffb0800 +#define OMAP1_UART3_BASE 0xfffb9800 + /* OMAP2 serial ports */ -#define OMAP_UART1_BASE 0x4806a000 -#define OMAP_UART2_BASE 0x4806c000 -#define OMAP_UART3_BASE 0x4806e000 -#elif defined(CONFIG_ARCH_OMAP3) +#define OMAP2_UART1_BASE 0x4806a000 +#define OMAP2_UART2_BASE 0x4806c000 +#define OMAP2_UART3_BASE 0x4806e000 + /* OMAP3 serial ports */ -#define OMAP_UART1_BASE 0x4806a000 -#define OMAP_UART2_BASE 0x4806c000 -#define OMAP_UART3_BASE 0x49020000 -#elif defined(CONFIG_ARCH_OMAP4) +#define OMAP3_UART1_BASE OMAP2_UART1_BASE +#define OMAP3_UART2_BASE OMAP2_UART2_BASE +#define OMAP3_UART3_BASE 0x49020000 +#define OMAP3_UART4_BASE 0x49042000 /* Only on 36xx */ + /* OMAP4 serial ports */ -#define OMAP_UART1_BASE 0x4806a000 -#define OMAP_UART2_BASE 0x4806c000 -#define OMAP_UART3_BASE 0x48020000 -#define OMAP_UART4_BASE 0x4806e000 -#endif +#define OMAP4_UART1_BASE OMAP2_UART1_BASE +#define OMAP4_UART2_BASE OMAP2_UART2_BASE +#define OMAP4_UART3_BASE 0x48020000 +#define OMAP4_UART4_BASE 0x4806e000 + +/* External port on Zoom2/3 */ +#define ZOOM_UART_BASE 0x10000000 +#define ZOOM_UART_VIRT 0xfb000000 + +#define OMAP_PORT_SHIFT 2 +#define OMAP7XX_PORT_SHIFT 0 +#define ZOOM_PORT_SHIFT 1 #define OMAP1510_BASE_BAUD (12000000/16) #define OMAP16XX_BASE_BAUD (48000000/16) #define OMAP24XX_BASE_BAUD (48000000/16) +/* + * DEBUG_LL port encoding stored into the UART1 scratchpad register by + * decomp_setup in uncompress.h + */ +#define OMAP1UART1 11 +#define OMAP1UART2 12 +#define OMAP1UART3 13 +#define OMAP2UART1 21 +#define OMAP2UART2 22 +#define OMAP2UART3 23 +#define OMAP3UART1 OMAP2UART1 +#define OMAP3UART2 OMAP2UART2 +#define OMAP3UART3 33 +#define OMAP3UART4 34 /* Only on 36xx */ +#define OMAP4UART1 OMAP2UART1 +#define OMAP4UART2 OMAP2UART2 +#define OMAP4UART3 43 +#define OMAP4UART4 44 +#define ZOOM_UART 95 /* Only on zoom2/3 */ + +/* This is only used by 8250.c for omap1510 */ #define is_omap_port(pt) ({int __ret = 0; \ - if ((pt)->port.mapbase == OMAP_UART1_BASE || \ - (pt)->port.mapbase == OMAP_UART2_BASE || \ - (pt)->port.mapbase == OMAP_UART3_BASE) \ + if ((pt)->port.mapbase == OMAP1_UART1_BASE || \ + (pt)->port.mapbase == OMAP1_UART2_BASE || \ + (pt)->port.mapbase == OMAP1_UART3_BASE) \ __ret = 1; \ __ret; \ }) diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index 13c305d62127..81d9ec540fcf 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h @@ -19,62 +19,38 @@ #include <linux/types.h> #include <linux/serial_reg.h> + +#include <asm/mach-types.h> + #include <plat/serial.h> -unsigned int system_rev; +static volatile u8 *uart1_base; +static int uart1_shift; -#define UART_OMAP_MDR1 0x08 /* mode definition register */ -#define OMAP_ID_730 0x355F -#define OMAP_ID_850 0x362C -#define ID_MASK 0x7fff -#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0) -#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK +static volatile u8 *uart_base; +static int uart_shift; -static void putc(int c) +/* + * Store the DEBUG_LL uart number into UART1 scratchpad register. + * See also debug-macro.S, and serial.c for related code. + * + * Please note that we currently assume that: + * - UART1 clocks are enabled for register access + * - UART1 scratchpad register can be used + */ +static void set_uart1_scratchpad(unsigned char port) { - volatile u8 * uart = 0; - int shift = 2; - -#ifdef CONFIG_MACH_OMAP_PALMTE - return; -#endif - -#ifdef CONFIG_ARCH_OMAP -#ifdef CONFIG_OMAP_LL_DEBUG_UART3 - uart = (volatile u8 *)(OMAP_UART3_BASE); -#elif defined(CONFIG_OMAP_LL_DEBUG_UART2) - uart = (volatile u8 *)(OMAP_UART2_BASE); -#elif defined(CONFIG_OMAP_LL_DEBUG_UART1) - uart = (volatile u8 *)(OMAP_UART1_BASE); -#elif defined(CONFIG_OMAP_LL_DEBUG_NONE) - return; -#else - return; -#endif - -#ifdef CONFIG_ARCH_OMAP1 - /* Determine which serial port to use */ - do { - /* MMU is not on, so cpu_is_omapXXXX() won't work here */ - unsigned int omap_id = omap_get_id(); - - if (omap_id == OMAP_ID_730 || omap_id == OMAP_ID_850) - shift = 0; + uart1_base[UART_SCR << uart1_shift] = port; +} - if (check_port(uart, shift)) - break; - /* Silent boot if no serial ports are enabled. */ +static void putc(int c) +{ + if (!uart_base) return; - } while (0); -#endif /* CONFIG_ARCH_OMAP1 */ -#endif - /* - * Now, xmit each character - */ - while (!(uart[UART_LSR << shift] & UART_LSR_THRE)) + while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE)) barrier(); - uart[UART_TX << shift] = c; + uart_base[UART_TX << uart_shift] = c; } static inline void flush(void) @@ -82,7 +58,116 @@ static inline void flush(void) } /* + * Macros to configure UART1 and debug UART + */ +#define _DEBUG_LL_ENTRY(mach, uart1_phys, uart1_shft, \ + dbg_uart, dbg_shft, dbg_id) \ + if (machine_is_##mach()) { \ + uart1_base = (volatile u8 *)(uart1_phys); \ + uart1_shift = (uart1_shft); \ + uart_base = (volatile u8 *)(dbg_uart); \ + uart_shift = (dbg_shft); \ + port = (dbg_id); \ + set_uart1_scratchpad(port); \ + break; \ + } + +#define DEBUG_LL_OMAP7XX(p, mach) \ + _DEBUG_LL_ENTRY(mach, OMAP1_UART1_BASE, OMAP7XX_PORT_SHIFT, \ + OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, OMAP1UART##p) + +#define DEBUG_LL_OMAP1(p, mach) \ + _DEBUG_LL_ENTRY(mach, OMAP1_UART1_BASE, OMAP_PORT_SHIFT, \ + OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP1UART##p) + +#define DEBUG_LL_OMAP2(p, mach) \ + _DEBUG_LL_ENTRY(mach, OMAP2_UART1_BASE, OMAP_PORT_SHIFT, \ + OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP2UART##p) + +#define DEBUG_LL_OMAP3(p, mach) \ + _DEBUG_LL_ENTRY(mach, OMAP3_UART1_BASE, OMAP_PORT_SHIFT, \ + OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP3UART##p) + +#define DEBUG_LL_OMAP4(p, mach) \ + _DEBUG_LL_ENTRY(mach, OMAP4_UART1_BASE, OMAP_PORT_SHIFT, \ + OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP4UART##p) + +/* Zoom2/3 shift is different for UART1 and external port */ +#define DEBUG_LL_ZOOM(mach) \ + _DEBUG_LL_ENTRY(mach, OMAP2_UART1_BASE, OMAP_PORT_SHIFT, \ + ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART) + +static inline void __arch_decomp_setup(unsigned long arch_id) +{ + int port = 0; + + /* + * Initialize the port based on the machine ID from the bootloader. + * Note that we're using macros here instead of switch statement + * as machine_is functions are optimized out for the boards that + * are not selected. + */ + do { + /* omap7xx/8xx based boards using UART1 with shift 0 */ + DEBUG_LL_OMAP7XX(1, herald); + DEBUG_LL_OMAP7XX(1, omap_perseus2); + + /* omap15xx/16xx based boards using UART1 */ + DEBUG_LL_OMAP1(1, ams_delta); + DEBUG_LL_OMAP1(1, nokia770); + DEBUG_LL_OMAP1(1, omap_h2); + DEBUG_LL_OMAP1(1, omap_h3); + DEBUG_LL_OMAP1(1, omap_innovator); + DEBUG_LL_OMAP1(1, omap_osk); + DEBUG_LL_OMAP1(1, omap_palmte); + DEBUG_LL_OMAP1(1, omap_palmz71); + + /* omap15xx/16xx based boards using UART2 */ + DEBUG_LL_OMAP1(2, omap_palmtt); + + /* omap15xx/16xx based boards using UART3 */ + DEBUG_LL_OMAP1(3, sx1); + + /* omap2 based boards using UART1 */ + DEBUG_LL_OMAP2(1, omap2evm); + DEBUG_LL_OMAP2(1, omap_2430sdp); + DEBUG_LL_OMAP2(1, omap_apollon); + DEBUG_LL_OMAP2(1, omap_h4); + + /* omap2 based boards using UART3 */ + DEBUG_LL_OMAP2(3, nokia_n800); + DEBUG_LL_OMAP2(3, nokia_n810); + DEBUG_LL_OMAP2(3, nokia_n810_wimax); + + /* omap3 based boards using UART1 */ + DEBUG_LL_OMAP2(1, omap3evm); + DEBUG_LL_OMAP3(1, omap_3430sdp); + DEBUG_LL_OMAP3(1, omap_3630sdp); + + /* omap3 based boards using UART3 */ + DEBUG_LL_OMAP3(3, cm_t35); + DEBUG_LL_OMAP3(3, igep0020); + DEBUG_LL_OMAP3(3, nokia_rx51); + DEBUG_LL_OMAP3(3, omap3517evm); + DEBUG_LL_OMAP3(3, omap3_beagle); + DEBUG_LL_OMAP3(3, omap3_pandora); + DEBUG_LL_OMAP3(3, omap_ldp); + DEBUG_LL_OMAP3(3, overo); + DEBUG_LL_OMAP3(3, touchbook); + + /* omap4 based boards using UART3 */ + DEBUG_LL_OMAP4(3, omap_4430sdp); + + /* zoom2/3 external uart */ + DEBUG_LL_ZOOM(omap_zoom2); + DEBUG_LL_ZOOM(omap_zoom3); + + } while (0); +} + +#define arch_decomp_setup() __arch_decomp_setup(arch_id) + +/* * nothing to do */ -#define arch_decomp_setup() #define arch_decomp_wdog() diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c index 463d6386aff2..905ed832df56 100644 --- a/arch/arm/plat-omap/iommu.c +++ b/arch/arm/plat-omap/iommu.c @@ -1,7 +1,7 @@ /* * omap iommu: tlb and pagetable primitives * - * Copyright (C) 2008-2009 Nokia Corporation + * Copyright (C) 2008-2010 Nokia Corporation * * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, * Paul Mundt and Toshihiro Kobayashi @@ -646,7 +646,7 @@ static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da) if (*iopte & IOPTE_LARGE) { nent *= 16; /* rewind to the 1st entry */ - iopte = (u32 *)((u32)iopte & IOLARGE_MASK); + iopte = iopte_offset(iopgd, (da & IOLARGE_MASK)); } bytes *= nent; memset(iopte, 0, nent * sizeof(*iopte)); @@ -667,7 +667,7 @@ static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da) if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) { nent *= 16; /* rewind to the 1st entry */ - iopgd = (u32 *)((u32)iopgd & IOSUPER_MASK); + iopgd = iopgd_offset(obj, (da & IOSUPER_MASK)); } bytes *= nent; } diff --git a/arch/arm/plat-omap/iopgtable.h b/arch/arm/plat-omap/iopgtable.h index 37dac434c7a1..ab23b6a140fd 100644 --- a/arch/arm/plat-omap/iopgtable.h +++ b/arch/arm/plat-omap/iopgtable.h @@ -1,7 +1,7 @@ /* * omap iommu: pagetable definitions * - * Copyright (C) 2008-2009 Nokia Corporation + * Copyright (C) 2008-2010 Nokia Corporation * * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> * @@ -13,26 +13,52 @@ #ifndef __PLAT_OMAP_IOMMU_H #define __PLAT_OMAP_IOMMU_H +/* + * "L2 table" address mask and size definitions. + */ #define IOPGD_SHIFT 20 -#define IOPGD_SIZE (1 << IOPGD_SHIFT) +#define IOPGD_SIZE (1UL << IOPGD_SHIFT) #define IOPGD_MASK (~(IOPGD_SIZE - 1)) -#define IOSECTION_MASK IOPGD_MASK -#define PTRS_PER_IOPGD (1 << (32 - IOPGD_SHIFT)) -#define IOPGD_TABLE_SIZE (PTRS_PER_IOPGD * sizeof(u32)) -#define IOSUPER_SIZE (IOPGD_SIZE << 4) +/* + * "section" address mask and size definitions. + */ +#define IOSECTION_SHIFT 20 +#define IOSECTION_SIZE (1UL << IOSECTION_SHIFT) +#define IOSECTION_MASK (~(IOSECTION_SIZE - 1)) + +/* + * "supersection" address mask and size definitions. + */ +#define IOSUPER_SHIFT 24 +#define IOSUPER_SIZE (1UL << IOSUPER_SHIFT) #define IOSUPER_MASK (~(IOSUPER_SIZE - 1)) +#define PTRS_PER_IOPGD (1UL << (32 - IOPGD_SHIFT)) +#define IOPGD_TABLE_SIZE (PTRS_PER_IOPGD * sizeof(u32)) + +/* + * "small page" address mask and size definitions. + */ #define IOPTE_SHIFT 12 -#define IOPTE_SIZE (1 << IOPTE_SHIFT) +#define IOPTE_SIZE (1UL << IOPTE_SHIFT) #define IOPTE_MASK (~(IOPTE_SIZE - 1)) -#define IOPAGE_MASK IOPTE_MASK -#define PTRS_PER_IOPTE (1 << (IOPGD_SHIFT - IOPTE_SHIFT)) -#define IOPTE_TABLE_SIZE (PTRS_PER_IOPTE * sizeof(u32)) -#define IOLARGE_SIZE (IOPTE_SIZE << 4) +/* + * "large page" address mask and size definitions. + */ +#define IOLARGE_SHIFT 16 +#define IOLARGE_SIZE (1UL << IOLARGE_SHIFT) #define IOLARGE_MASK (~(IOLARGE_SIZE - 1)) +#define PTRS_PER_IOPTE (1UL << (IOPGD_SHIFT - IOPTE_SHIFT)) +#define IOPTE_TABLE_SIZE (PTRS_PER_IOPTE * sizeof(u32)) + +#define IOPAGE_MASK IOPTE_MASK + +/* + * some descriptor attributes. + */ #define IOPGD_TABLE (1 << 0) #define IOPGD_SECTION (2 << 0) #define IOPGD_SUPER (1 << 18 | 2 << 0) @@ -40,12 +66,14 @@ #define IOPTE_SMALL (2 << 0) #define IOPTE_LARGE (1 << 0) +/* to find an entry in a page-table-directory */ #define iopgd_index(da) (((da) >> IOPGD_SHIFT) & (PTRS_PER_IOPGD - 1)) #define iopgd_offset(obj, da) ((obj)->iopgd + iopgd_index(da)) #define iopte_paddr(iopgd) (*iopgd & ~((1 << 10) - 1)) #define iopte_vaddr(iopgd) ((u32 *)phys_to_virt(iopte_paddr(iopgd))) +/* to find an entry in the second-level page table. */ #define iopte_index(da) (((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1)) #define iopte_offset(iopgd, da) (iopte_vaddr(iopgd) + iopte_index(da)) diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index f75767278fc3..473be3dc2cf5 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -28,28 +28,42 @@ #include <plat/mcbsp.h> struct omap_mcbsp **mcbsp_ptr; -int omap_mcbsp_count; +int omap_mcbsp_count, omap_mcbsp_cache_size; -void omap_mcbsp_write(void __iomem *io_base, u16 reg, u32 val) +void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) { - if (cpu_class_is_omap1() || cpu_is_omap2420()) - __raw_writew((u16)val, io_base + reg); - else - __raw_writel(val, io_base + reg); + if (cpu_class_is_omap1()) { + ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val; + __raw_writew((u16)val, mcbsp->io_base + reg); + } else if (cpu_is_omap2420()) { + ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val; + __raw_writew((u16)val, mcbsp->io_base + reg); + } else { + ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val; + __raw_writel(val, mcbsp->io_base + reg); + } } -int omap_mcbsp_read(void __iomem *io_base, u16 reg) +int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache) { - if (cpu_class_is_omap1() || cpu_is_omap2420()) - return __raw_readw(io_base + reg); - else - return __raw_readl(io_base + reg); + if (cpu_class_is_omap1()) { + return !from_cache ? __raw_readw(mcbsp->io_base + reg) : + ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)]; + } else if (cpu_is_omap2420()) { + return !from_cache ? __raw_readw(mcbsp->io_base + reg) : + ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)]; + } else { + return !from_cache ? __raw_readl(mcbsp->io_base + reg) : + ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)]; + } } -#define OMAP_MCBSP_READ(base, reg) \ - omap_mcbsp_read(base, OMAP_MCBSP_REG_##reg) -#define OMAP_MCBSP_WRITE(base, reg, val) \ - omap_mcbsp_write(base, OMAP_MCBSP_REG_##reg, val) +#define MCBSP_READ(mcbsp, reg) \ + omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0) +#define MCBSP_WRITE(mcbsp, reg, val) \ + omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val) +#define MCBSP_READ_CACHE(mcbsp, reg) \ + omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1) #define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count) #define id_to_mcbsp_ptr(id) mcbsp_ptr[id]; @@ -60,31 +74,31 @@ static void omap_mcbsp_dump_reg(u8 id) dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id); dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n", - OMAP_MCBSP_READ(mcbsp->io_base, DRR2)); + MCBSP_READ(mcbsp, DRR2)); dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n", - OMAP_MCBSP_READ(mcbsp->io_base, DRR1)); + MCBSP_READ(mcbsp, DRR1)); dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n", - OMAP_MCBSP_READ(mcbsp->io_base, DXR2)); + MCBSP_READ(mcbsp, DXR2)); dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n", - OMAP_MCBSP_READ(mcbsp->io_base, DXR1)); + MCBSP_READ(mcbsp, DXR1)); dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n", - OMAP_MCBSP_READ(mcbsp->io_base, SPCR2)); + MCBSP_READ(mcbsp, SPCR2)); dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n", - OMAP_MCBSP_READ(mcbsp->io_base, SPCR1)); + MCBSP_READ(mcbsp, SPCR1)); dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n", - OMAP_MCBSP_READ(mcbsp->io_base, RCR2)); + MCBSP_READ(mcbsp, RCR2)); dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n", - OMAP_MCBSP_READ(mcbsp->io_base, RCR1)); + MCBSP_READ(mcbsp, RCR1)); dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n", - OMAP_MCBSP_READ(mcbsp->io_base, XCR2)); + MCBSP_READ(mcbsp, XCR2)); dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n", - OMAP_MCBSP_READ(mcbsp->io_base, XCR1)); + MCBSP_READ(mcbsp, XCR1)); dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n", - OMAP_MCBSP_READ(mcbsp->io_base, SRGR2)); + MCBSP_READ(mcbsp, SRGR2)); dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n", - OMAP_MCBSP_READ(mcbsp->io_base, SRGR1)); + MCBSP_READ(mcbsp, SRGR1)); dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n", - OMAP_MCBSP_READ(mcbsp->io_base, PCR0)); + MCBSP_READ(mcbsp, PCR0)); dev_dbg(mcbsp->dev, "***********************\n"); } @@ -93,15 +107,15 @@ static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id) struct omap_mcbsp *mcbsp_tx = dev_id; u16 irqst_spcr2; - irqst_spcr2 = OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2); + irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2); dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2); if (irqst_spcr2 & XSYNC_ERR) { dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n", irqst_spcr2); /* Writing zero to XSYNC_ERR clears the IRQ */ - OMAP_MCBSP_WRITE(mcbsp_tx->io_base, SPCR2, - irqst_spcr2 & ~(XSYNC_ERR)); + MCBSP_WRITE(mcbsp_tx, SPCR2, + MCBSP_READ_CACHE(mcbsp_tx, SPCR2) & ~(XSYNC_ERR)); } else { complete(&mcbsp_tx->tx_irq_completion); } @@ -114,15 +128,15 @@ static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id) struct omap_mcbsp *mcbsp_rx = dev_id; u16 irqst_spcr1; - irqst_spcr1 = OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR1); + irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1); dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1); if (irqst_spcr1 & RSYNC_ERR) { dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n", irqst_spcr1); /* Writing zero to RSYNC_ERR clears the IRQ */ - OMAP_MCBSP_WRITE(mcbsp_rx->io_base, SPCR1, - irqst_spcr1 & ~(RSYNC_ERR)); + MCBSP_WRITE(mcbsp_rx, SPCR1, + MCBSP_READ_CACHE(mcbsp_rx, SPCR1) & ~(RSYNC_ERR)); } else { complete(&mcbsp_rx->tx_irq_completion); } @@ -135,7 +149,7 @@ static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data) struct omap_mcbsp *mcbsp_dma_tx = data; dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n", - OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2)); + MCBSP_READ(mcbsp_dma_tx, SPCR2)); /* We can free the channels */ omap_free_dma(mcbsp_dma_tx->dma_tx_lch); @@ -149,7 +163,7 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data) struct omap_mcbsp *mcbsp_dma_rx = data; dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n", - OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2)); + MCBSP_READ(mcbsp_dma_rx, SPCR2)); /* We can free the channels */ omap_free_dma(mcbsp_dma_rx->dma_rx_lch); @@ -167,7 +181,6 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data) void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config) { struct omap_mcbsp *mcbsp; - void __iomem *io_base; if (!omap_mcbsp_check_valid_id(id)) { printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); @@ -175,30 +188,29 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config) } mcbsp = id_to_mcbsp_ptr(id); - io_base = mcbsp->io_base; dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n", mcbsp->id, mcbsp->phys_base); /* We write the given config */ - OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2); - OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1); - OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2); - OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1); - OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2); - OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1); - OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2); - OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1); - OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2); - OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1); - OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0); + MCBSP_WRITE(mcbsp, SPCR2, config->spcr2); + MCBSP_WRITE(mcbsp, SPCR1, config->spcr1); + MCBSP_WRITE(mcbsp, RCR2, config->rcr2); + MCBSP_WRITE(mcbsp, RCR1, config->rcr1); + MCBSP_WRITE(mcbsp, XCR2, config->xcr2); + MCBSP_WRITE(mcbsp, XCR1, config->xcr1); + MCBSP_WRITE(mcbsp, SRGR2, config->srgr2); + MCBSP_WRITE(mcbsp, SRGR1, config->srgr1); + MCBSP_WRITE(mcbsp, MCR2, config->mcr2); + MCBSP_WRITE(mcbsp, MCR1, config->mcr1); + MCBSP_WRITE(mcbsp, PCR0, config->pcr0); if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { - OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr); - OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr); + MCBSP_WRITE(mcbsp, XCCR, config->xccr); + MCBSP_WRITE(mcbsp, RCCR, config->rccr); } } EXPORT_SYMBOL(omap_mcbsp_config); -#ifdef CONFIG_ARCH_OMAP34XX +#ifdef CONFIG_ARCH_OMAP3 /* * omap_mcbsp_set_tx_threshold configures how to deal * with transmit threshold. the threshold value and handler can be @@ -207,7 +219,6 @@ EXPORT_SYMBOL(omap_mcbsp_config); void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold) { struct omap_mcbsp *mcbsp; - void __iomem *io_base; if (!cpu_is_omap34xx()) return; @@ -217,9 +228,8 @@ void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold) return; } mcbsp = id_to_mcbsp_ptr(id); - io_base = mcbsp->io_base; - OMAP_MCBSP_WRITE(io_base, THRSH2, threshold); + MCBSP_WRITE(mcbsp, THRSH2, threshold); } EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold); @@ -231,7 +241,6 @@ EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold); void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold) { struct omap_mcbsp *mcbsp; - void __iomem *io_base; if (!cpu_is_omap34xx()) return; @@ -241,9 +250,8 @@ void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold) return; } mcbsp = id_to_mcbsp_ptr(id); - io_base = mcbsp->io_base; - OMAP_MCBSP_WRITE(io_base, THRSH1, threshold); + MCBSP_WRITE(mcbsp, THRSH1, threshold); } EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold); @@ -313,19 +321,18 @@ static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) if (cpu_is_omap34xx()) { u16 syscon; - syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON); + syscon = MCBSP_READ(mcbsp, SYSCON); syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03)); if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) { syscon |= (ENAWAKEUP | SIDLEMODE(0x02) | CLOCKACTIVITY(0x02)); - OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN, - XRDYEN | RRDYEN); + MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN); } else { syscon |= SIDLEMODE(0x01); } - OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon); + MCBSP_WRITE(mcbsp, SYSCON, syscon); } } @@ -337,7 +344,7 @@ static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) if (cpu_is_omap34xx()) { u16 syscon; - syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON); + syscon = MCBSP_READ(mcbsp, SYSCON); syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03)); /* * HW bug workaround - If no_idle mode is taken, we need to @@ -345,12 +352,12 @@ static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) * device will not hit retention anymore. */ syscon |= SIDLEMODE(0x02); - OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon); + MCBSP_WRITE(mcbsp, SYSCON, syscon); syscon &= ~(SIDLEMODE(0x03)); - OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon); + MCBSP_WRITE(mcbsp, SYSCON, syscon); - OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN, 0); + MCBSP_WRITE(mcbsp, WAKEUPEN, 0); } } #else @@ -392,6 +399,7 @@ EXPORT_SYMBOL(omap_mcbsp_set_io_type); int omap_mcbsp_request(unsigned int id) { struct omap_mcbsp *mcbsp; + void *reg_cache; int err; if (!omap_mcbsp_check_valid_id(id)) { @@ -400,15 +408,21 @@ int omap_mcbsp_request(unsigned int id) } mcbsp = id_to_mcbsp_ptr(id); + reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL); + if (!reg_cache) { + return -ENOMEM; + } + spin_lock(&mcbsp->lock); if (!mcbsp->free) { dev_err(mcbsp->dev, "McBSP%d is currently in use\n", mcbsp->id); - spin_unlock(&mcbsp->lock); - return -EBUSY; + err = -EBUSY; + goto err_kfree; } mcbsp->free = 0; + mcbsp->reg_cache = reg_cache; spin_unlock(&mcbsp->lock); if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request) @@ -424,8 +438,8 @@ int omap_mcbsp_request(unsigned int id) * Make sure that transmitter, receiver and sample-rate generator are * not running before activating IRQs. */ - OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR1, 0); - OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR2, 0); + MCBSP_WRITE(mcbsp, SPCR1, 0); + MCBSP_WRITE(mcbsp, SPCR2, 0); if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { /* We need to get IRQs here */ @@ -436,7 +450,7 @@ int omap_mcbsp_request(unsigned int id) dev_err(mcbsp->dev, "Unable to request TX IRQ %d " "for McBSP%d\n", mcbsp->tx_irq, mcbsp->id); - goto error; + goto err_clk_disable; } init_completion(&mcbsp->rx_irq_completion); @@ -446,16 +460,16 @@ int omap_mcbsp_request(unsigned int id) dev_err(mcbsp->dev, "Unable to request RX IRQ %d " "for McBSP%d\n", mcbsp->rx_irq, mcbsp->id); - goto tx_irq; + goto err_free_irq; } } return 0; -tx_irq: +err_free_irq: free_irq(mcbsp->tx_irq, (void *)mcbsp); -error: +err_clk_disable: if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free) - mcbsp->pdata->ops->free(id); + mcbsp->pdata->ops->free(id); /* Do procedure specific to omap34xx arch, if applicable */ omap34xx_mcbsp_free(mcbsp); @@ -463,7 +477,12 @@ error: clk_disable(mcbsp->fclk); clk_disable(mcbsp->iclk); + spin_lock(&mcbsp->lock); mcbsp->free = 1; + mcbsp->reg_cache = NULL; +err_kfree: + spin_unlock(&mcbsp->lock); + kfree(reg_cache); return err; } @@ -472,6 +491,7 @@ EXPORT_SYMBOL(omap_mcbsp_request); void omap_mcbsp_free(unsigned int id) { struct omap_mcbsp *mcbsp; + void *reg_cache; if (!omap_mcbsp_check_valid_id(id)) { printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); @@ -494,16 +514,18 @@ void omap_mcbsp_free(unsigned int id) free_irq(mcbsp->tx_irq, (void *)mcbsp); } - spin_lock(&mcbsp->lock); - if (mcbsp->free) { - dev_err(mcbsp->dev, "McBSP%d was not reserved\n", - mcbsp->id); - spin_unlock(&mcbsp->lock); - return; - } + reg_cache = mcbsp->reg_cache; - mcbsp->free = 1; + spin_lock(&mcbsp->lock); + if (mcbsp->free) + dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id); + else + mcbsp->free = 1; + mcbsp->reg_cache = NULL; spin_unlock(&mcbsp->lock); + + if (reg_cache) + kfree(reg_cache); } EXPORT_SYMBOL(omap_mcbsp_free); @@ -515,7 +537,6 @@ EXPORT_SYMBOL(omap_mcbsp_free); void omap_mcbsp_start(unsigned int id, int tx, int rx) { struct omap_mcbsp *mcbsp; - void __iomem *io_base; int idle; u16 w; @@ -524,28 +545,27 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx) return; } mcbsp = id_to_mcbsp_ptr(id); - io_base = mcbsp->io_base; - mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7; - mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7; + mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7; + mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7; - idle = !((OMAP_MCBSP_READ(io_base, SPCR2) | - OMAP_MCBSP_READ(io_base, SPCR1)) & 1); + idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | + MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); if (idle) { /* Start the sample generator */ - w = OMAP_MCBSP_READ(io_base, SPCR2); - OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6)); + w = MCBSP_READ_CACHE(mcbsp, SPCR2); + MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6)); } /* Enable transmitter and receiver */ tx &= 1; - w = OMAP_MCBSP_READ(io_base, SPCR2); - OMAP_MCBSP_WRITE(io_base, SPCR2, w | tx); + w = MCBSP_READ_CACHE(mcbsp, SPCR2); + MCBSP_WRITE(mcbsp, SPCR2, w | tx); rx &= 1; - w = OMAP_MCBSP_READ(io_base, SPCR1); - OMAP_MCBSP_WRITE(io_base, SPCR1, w | rx); + w = MCBSP_READ_CACHE(mcbsp, SPCR1); + MCBSP_WRITE(mcbsp, SPCR1, w | rx); /* * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec @@ -557,18 +577,18 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx) if (idle) { /* Start frame sync */ - w = OMAP_MCBSP_READ(io_base, SPCR2); - OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7)); + w = MCBSP_READ_CACHE(mcbsp, SPCR2); + MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); } if (cpu_is_omap2430() || cpu_is_omap34xx()) { /* Release the transmitter and receiver */ - w = OMAP_MCBSP_READ(io_base, XCCR); + w = MCBSP_READ_CACHE(mcbsp, XCCR); w &= ~(tx ? XDISABLE : 0); - OMAP_MCBSP_WRITE(io_base, XCCR, w); - w = OMAP_MCBSP_READ(io_base, RCCR); + MCBSP_WRITE(mcbsp, XCCR, w); + w = MCBSP_READ_CACHE(mcbsp, RCCR); w &= ~(rx ? RDISABLE : 0); - OMAP_MCBSP_WRITE(io_base, RCCR, w); + MCBSP_WRITE(mcbsp, RCCR, w); } /* Dump McBSP Regs */ @@ -579,7 +599,6 @@ EXPORT_SYMBOL(omap_mcbsp_start); void omap_mcbsp_stop(unsigned int id, int tx, int rx) { struct omap_mcbsp *mcbsp; - void __iomem *io_base; int idle; u16 w; @@ -589,35 +608,34 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx) } mcbsp = id_to_mcbsp_ptr(id); - io_base = mcbsp->io_base; /* Reset transmitter */ tx &= 1; if (cpu_is_omap2430() || cpu_is_omap34xx()) { - w = OMAP_MCBSP_READ(io_base, XCCR); + w = MCBSP_READ_CACHE(mcbsp, XCCR); w |= (tx ? XDISABLE : 0); - OMAP_MCBSP_WRITE(io_base, XCCR, w); + MCBSP_WRITE(mcbsp, XCCR, w); } - w = OMAP_MCBSP_READ(io_base, SPCR2); - OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~tx); + w = MCBSP_READ_CACHE(mcbsp, SPCR2); + MCBSP_WRITE(mcbsp, SPCR2, w & ~tx); /* Reset receiver */ rx &= 1; if (cpu_is_omap2430() || cpu_is_omap34xx()) { - w = OMAP_MCBSP_READ(io_base, RCCR); + w = MCBSP_READ_CACHE(mcbsp, RCCR); w |= (rx ? RDISABLE : 0); - OMAP_MCBSP_WRITE(io_base, RCCR, w); + MCBSP_WRITE(mcbsp, RCCR, w); } - w = OMAP_MCBSP_READ(io_base, SPCR1); - OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~rx); + w = MCBSP_READ_CACHE(mcbsp, SPCR1); + MCBSP_WRITE(mcbsp, SPCR1, w & ~rx); - idle = !((OMAP_MCBSP_READ(io_base, SPCR2) | - OMAP_MCBSP_READ(io_base, SPCR1)) & 1); + idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | + MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); if (idle) { /* Reset the sample rate generator */ - w = OMAP_MCBSP_READ(io_base, SPCR2); - OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6)); + w = MCBSP_READ_CACHE(mcbsp, SPCR2); + MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6)); } } EXPORT_SYMBOL(omap_mcbsp_stop); @@ -626,7 +644,6 @@ EXPORT_SYMBOL(omap_mcbsp_stop); int omap_mcbsp_pollwrite(unsigned int id, u16 buf) { struct omap_mcbsp *mcbsp; - void __iomem *base; if (!omap_mcbsp_check_valid_id(id)) { printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); @@ -634,28 +651,27 @@ int omap_mcbsp_pollwrite(unsigned int id, u16 buf) } mcbsp = id_to_mcbsp_ptr(id); - base = mcbsp->io_base; - writew(buf, base + OMAP_MCBSP_REG_DXR1); + MCBSP_WRITE(mcbsp, DXR1, buf); /* if frame sync error - clear the error */ - if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) { + if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) { /* clear error */ - writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR), - base + OMAP_MCBSP_REG_SPCR2); + MCBSP_WRITE(mcbsp, SPCR2, + MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XSYNC_ERR)); /* resend */ return -1; } else { /* wait for transmit confirmation */ int attemps = 0; - while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) { + while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) { if (attemps++ > 1000) { - writew(readw(base + OMAP_MCBSP_REG_SPCR2) & - (~XRST), - base + OMAP_MCBSP_REG_SPCR2); + MCBSP_WRITE(mcbsp, SPCR2, + MCBSP_READ_CACHE(mcbsp, SPCR2) & + (~XRST)); udelay(10); - writew(readw(base + OMAP_MCBSP_REG_SPCR2) | - (XRST), - base + OMAP_MCBSP_REG_SPCR2); + MCBSP_WRITE(mcbsp, SPCR2, + MCBSP_READ_CACHE(mcbsp, SPCR2) | + (XRST)); udelay(10); dev_err(mcbsp->dev, "Could not write to" " McBSP%d Register\n", mcbsp->id); @@ -671,7 +687,6 @@ EXPORT_SYMBOL(omap_mcbsp_pollwrite); int omap_mcbsp_pollread(unsigned int id, u16 *buf) { struct omap_mcbsp *mcbsp; - void __iomem *base; if (!omap_mcbsp_check_valid_id(id)) { printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); @@ -679,26 +694,25 @@ int omap_mcbsp_pollread(unsigned int id, u16 *buf) } mcbsp = id_to_mcbsp_ptr(id); - base = mcbsp->io_base; /* if frame sync error - clear the error */ - if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) { + if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) { /* clear error */ - writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR), - base + OMAP_MCBSP_REG_SPCR1); + MCBSP_WRITE(mcbsp, SPCR1, + MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RSYNC_ERR)); /* resend */ return -1; } else { /* wait for recieve confirmation */ int attemps = 0; - while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) { + while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) { if (attemps++ > 1000) { - writew(readw(base + OMAP_MCBSP_REG_SPCR1) & - (~RRST), - base + OMAP_MCBSP_REG_SPCR1); + MCBSP_WRITE(mcbsp, SPCR1, + MCBSP_READ_CACHE(mcbsp, SPCR1) & + (~RRST)); udelay(10); - writew(readw(base + OMAP_MCBSP_REG_SPCR1) | - (RRST), - base + OMAP_MCBSP_REG_SPCR1); + MCBSP_WRITE(mcbsp, SPCR1, + MCBSP_READ_CACHE(mcbsp, SPCR1) | + (RRST)); udelay(10); dev_err(mcbsp->dev, "Could not read from" " McBSP%d Register\n", mcbsp->id); @@ -706,7 +720,7 @@ int omap_mcbsp_pollread(unsigned int id, u16 *buf) } } } - *buf = readw(base + OMAP_MCBSP_REG_DRR1); + *buf = MCBSP_READ(mcbsp, DRR1); return 0; } @@ -718,7 +732,6 @@ EXPORT_SYMBOL(omap_mcbsp_pollread); void omap_mcbsp_xmit_word(unsigned int id, u32 word) { struct omap_mcbsp *mcbsp; - void __iomem *io_base; omap_mcbsp_word_length word_length; if (!omap_mcbsp_check_valid_id(id)) { @@ -727,21 +740,19 @@ void omap_mcbsp_xmit_word(unsigned int id, u32 word) } mcbsp = id_to_mcbsp_ptr(id); - io_base = mcbsp->io_base; word_length = mcbsp->tx_word_length; wait_for_completion(&mcbsp->tx_irq_completion); if (word_length > OMAP_MCBSP_WORD_16) - OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16); - OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff); + MCBSP_WRITE(mcbsp, DXR2, word >> 16); + MCBSP_WRITE(mcbsp, DXR1, word & 0xffff); } EXPORT_SYMBOL(omap_mcbsp_xmit_word); u32 omap_mcbsp_recv_word(unsigned int id) { struct omap_mcbsp *mcbsp; - void __iomem *io_base; u16 word_lsb, word_msb = 0; omap_mcbsp_word_length word_length; @@ -752,13 +763,12 @@ u32 omap_mcbsp_recv_word(unsigned int id) mcbsp = id_to_mcbsp_ptr(id); word_length = mcbsp->rx_word_length; - io_base = mcbsp->io_base; wait_for_completion(&mcbsp->rx_irq_completion); if (word_length > OMAP_MCBSP_WORD_16) - word_msb = OMAP_MCBSP_READ(io_base, DRR2); - word_lsb = OMAP_MCBSP_READ(io_base, DRR1); + word_msb = MCBSP_READ(mcbsp, DRR2); + word_lsb = MCBSP_READ(mcbsp, DRR1); return (word_lsb | (word_msb << 16)); } @@ -767,7 +777,6 @@ EXPORT_SYMBOL(omap_mcbsp_recv_word); int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word) { struct omap_mcbsp *mcbsp; - void __iomem *io_base; omap_mcbsp_word_length tx_word_length; omap_mcbsp_word_length rx_word_length; u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0; @@ -777,7 +786,6 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word) return -ENODEV; } mcbsp = id_to_mcbsp_ptr(id); - io_base = mcbsp->io_base; tx_word_length = mcbsp->tx_word_length; rx_word_length = mcbsp->rx_word_length; @@ -785,14 +793,16 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word) return -EINVAL; /* First we wait for the transmitter to be ready */ - spcr2 = OMAP_MCBSP_READ(io_base, SPCR2); + spcr2 = MCBSP_READ(mcbsp, SPCR2); while (!(spcr2 & XRDY)) { - spcr2 = OMAP_MCBSP_READ(io_base, SPCR2); + spcr2 = MCBSP_READ(mcbsp, SPCR2); if (attempts++ > 1000) { /* We must reset the transmitter */ - OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST)); + MCBSP_WRITE(mcbsp, SPCR2, + MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST)); udelay(10); - OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST); + MCBSP_WRITE(mcbsp, SPCR2, + MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST); udelay(10); dev_err(mcbsp->dev, "McBSP%d transmitter not " "ready\n", mcbsp->id); @@ -802,18 +812,20 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word) /* Now we can push the data */ if (tx_word_length > OMAP_MCBSP_WORD_16) - OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16); - OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff); + MCBSP_WRITE(mcbsp, DXR2, word >> 16); + MCBSP_WRITE(mcbsp, DXR1, word & 0xffff); /* We wait for the receiver to be ready */ - spcr1 = OMAP_MCBSP_READ(io_base, SPCR1); + spcr1 = MCBSP_READ(mcbsp, SPCR1); while (!(spcr1 & RRDY)) { - spcr1 = OMAP_MCBSP_READ(io_base, SPCR1); + spcr1 = MCBSP_READ(mcbsp, SPCR1); if (attempts++ > 1000) { /* We must reset the receiver */ - OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST)); + MCBSP_WRITE(mcbsp, SPCR1, + MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST)); udelay(10); - OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST); + MCBSP_WRITE(mcbsp, SPCR1, + MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST); udelay(10); dev_err(mcbsp->dev, "McBSP%d receiver not " "ready\n", mcbsp->id); @@ -823,8 +835,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word) /* Receiver is ready, let's read the dummy data */ if (rx_word_length > OMAP_MCBSP_WORD_16) - word_msb = OMAP_MCBSP_READ(io_base, DRR2); - word_lsb = OMAP_MCBSP_READ(io_base, DRR1); + word_msb = MCBSP_READ(mcbsp, DRR2); + word_lsb = MCBSP_READ(mcbsp, DRR1); return 0; } @@ -834,7 +846,6 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word) { struct omap_mcbsp *mcbsp; u32 clock_word = 0; - void __iomem *io_base; omap_mcbsp_word_length tx_word_length; omap_mcbsp_word_length rx_word_length; u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0; @@ -845,7 +856,6 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word) } mcbsp = id_to_mcbsp_ptr(id); - io_base = mcbsp->io_base; tx_word_length = mcbsp->tx_word_length; rx_word_length = mcbsp->rx_word_length; @@ -854,14 +864,16 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word) return -EINVAL; /* First we wait for the transmitter to be ready */ - spcr2 = OMAP_MCBSP_READ(io_base, SPCR2); + spcr2 = MCBSP_READ(mcbsp, SPCR2); while (!(spcr2 & XRDY)) { - spcr2 = OMAP_MCBSP_READ(io_base, SPCR2); + spcr2 = MCBSP_READ(mcbsp, SPCR2); if (attempts++ > 1000) { /* We must reset the transmitter */ - OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST)); + MCBSP_WRITE(mcbsp, SPCR2, + MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST)); udelay(10); - OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST); + MCBSP_WRITE(mcbsp, SPCR2, + MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST); udelay(10); dev_err(mcbsp->dev, "McBSP%d transmitter not " "ready\n", mcbsp->id); @@ -871,18 +883,20 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word) /* We first need to enable the bus clock */ if (tx_word_length > OMAP_MCBSP_WORD_16) - OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16); - OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff); + MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16); + MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff); /* We wait for the receiver to be ready */ - spcr1 = OMAP_MCBSP_READ(io_base, SPCR1); + spcr1 = MCBSP_READ(mcbsp, SPCR1); while (!(spcr1 & RRDY)) { - spcr1 = OMAP_MCBSP_READ(io_base, SPCR1); + spcr1 = MCBSP_READ(mcbsp, SPCR1); if (attempts++ > 1000) { /* We must reset the receiver */ - OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST)); + MCBSP_WRITE(mcbsp, SPCR1, + MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST)); udelay(10); - OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST); + MCBSP_WRITE(mcbsp, SPCR1, + MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST); udelay(10); dev_err(mcbsp->dev, "McBSP%d receiver not " "ready\n", mcbsp->id); @@ -892,8 +906,8 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word) /* Receiver is ready, there is something for us */ if (rx_word_length > OMAP_MCBSP_WORD_16) - word_msb = OMAP_MCBSP_READ(io_base, DRR2); - word_lsb = OMAP_MCBSP_READ(io_base, DRR1); + word_msb = MCBSP_READ(mcbsp, DRR2); + word_lsb = MCBSP_READ(mcbsp, DRR1); word[0] = (word_lsb | (word_msb << 16)); @@ -1107,7 +1121,7 @@ void omap_mcbsp_set_spi_mode(unsigned int id, } EXPORT_SYMBOL(omap_mcbsp_set_spi_mode); -#ifdef CONFIG_ARCH_OMAP34XX +#ifdef CONFIG_ARCH_OMAP3 #define max_thres(m) (mcbsp->pdata->buffer_size) #define valid_threshold(m, val) ((val) <= max_thres(m)) #define THRESHOLD_PROP_BUILDER(prop) \ @@ -1246,7 +1260,7 @@ static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) #else static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {} static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {} -#endif /* CONFIG_ARCH_OMAP34XX */ +#endif /* CONFIG_ARCH_OMAP3 */ /* * McBSP1 and McBSP3 are directly mapped on 1610 and 1510. diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index 2ed72013c2e2..5195dbb1a397 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c @@ -138,10 +138,22 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat) "%llu nsec\n", od->pdev.name, od->pm_lat_level, act_lat); - WARN(act_lat > odpl->activate_lat, "omap_device: %s.%d: " - "activate step %d took longer than expected (%llu > %d)\n", - od->pdev.name, od->pdev.id, od->pm_lat_level, - act_lat, odpl->activate_lat); + if (act_lat > odpl->activate_lat) { + odpl->activate_lat_worst = act_lat; + if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) { + odpl->activate_lat = act_lat; + pr_warning("omap_device: %s.%d: new worst case " + "activate latency %d: %llu\n", + od->pdev.name, od->pdev.id, + od->pm_lat_level, act_lat); + } else + pr_warning("omap_device: %s.%d: activate " + "latency %d higher than exptected. " + "(%llu > %d)\n", + od->pdev.name, od->pdev.id, + od->pm_lat_level, act_lat, + odpl->activate_lat); + } od->dev_wakeup_lat -= odpl->activate_lat; } @@ -194,10 +206,23 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat) "%llu nsec\n", od->pdev.name, od->pm_lat_level, deact_lat); - WARN(deact_lat > odpl->deactivate_lat, "omap_device: %s.%d: " - "deactivate step %d took longer than expected " - "(%llu > %d)\n", od->pdev.name, od->pdev.id, - od->pm_lat_level, deact_lat, odpl->deactivate_lat); + if (deact_lat > odpl->deactivate_lat) { + odpl->deactivate_lat_worst = deact_lat; + if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) { + odpl->deactivate_lat = deact_lat; + pr_warning("omap_device: %s.%d: new worst case " + "deactivate latency %d: %llu\n", + od->pdev.name, od->pdev.id, + od->pm_lat_level, deact_lat); + } else + pr_warning("omap_device: %s.%d: deactivate " + "latency %d higher than exptected. " + "(%llu > %d)\n", + od->pdev.name, od->pdev.id, + od->pm_lat_level, deact_lat, + odpl->deactivate_lat); + } + od->dev_wakeup_lat += odpl->activate_lat; diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index d8d5094b37ed..51f4dfb82e2b 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -53,7 +53,7 @@ #define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) #define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000) -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) #define SRAM_BOOTLOADER_SZ 0x00 #else #define SRAM_BOOTLOADER_SZ 0x80 diff --git a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S index fb3b969bf0a2..1b9348bf0e49 100644 --- a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S +++ b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S @@ -16,7 +16,7 @@ * http://www.gnu.org/copyleft/gpl.html */ - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? moveq \rx, #0x80000000 @ physical base address diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig index 87060266ef91..c0df30faa66a 100644 --- a/drivers/char/hw_random/Kconfig +++ b/drivers/char/hw_random/Kconfig @@ -114,7 +114,7 @@ config HW_RANDOM_IXP4XX config HW_RANDOM_OMAP tristate "OMAP Random Number Generator support" - depends on HW_RANDOM && (ARCH_OMAP16XX || ARCH_OMAP24XX) + depends on HW_RANDOM && (ARCH_OMAP16XX || ARCH_OMAP2) default HW_RANDOM ---help--- This driver provides kernel-side support for the Random Number diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 87829789243e..1380e1c44e4b 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -94,7 +94,7 @@ config TPS65010 config MENELAUS bool "Texas Instruments TWL92330/Menelaus PM chip" - depends on I2C=y && ARCH_OMAP24XX + depends on I2C=y && ARCH_OMAP2 help If you say yes here you get support for the Texas Instruments TWL92330/Menelaus Power Management chip. This include voltage diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index 4b2322518909..83f0affadcae 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -30,6 +30,8 @@ #include <linux/mmc/core.h> #include <linux/io.h> #include <linux/semaphore.h> +#include <linux/gpio.h> +#include <linux/regulator/consumer.h> #include <plat/dma.h> #include <mach/hardware.h> #include <plat/board.h> @@ -146,6 +148,15 @@ struct omap_hsmmc_host { struct clk *fclk; struct clk *iclk; struct clk *dbclk; + /* + * vcc == configured supply + * vcc_aux == optional + * - MMC1, supply for DAT4..DAT7 + * - MMC2/MMC2, external level shifter voltage supply, for + * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) + */ + struct regulator *vcc; + struct regulator *vcc_aux; struct semaphore sem; struct work_struct mmc_carddetect_work; void __iomem *base; @@ -171,10 +182,337 @@ struct omap_hsmmc_host { int vdd; int protect_card; int reqs_blocked; + int use_reg; struct omap_mmc_platform_data *pdata; }; +static int omap_hsmmc_card_detect(struct device *dev, int slot) +{ + struct omap_mmc_platform_data *mmc = dev->platform_data; + + /* NOTE: assumes card detect signal is active-low */ + return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); +} + +static int omap_hsmmc_get_wp(struct device *dev, int slot) +{ + struct omap_mmc_platform_data *mmc = dev->platform_data; + + /* NOTE: assumes write protect signal is active-high */ + return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); +} + +static int omap_hsmmc_get_cover_state(struct device *dev, int slot) +{ + struct omap_mmc_platform_data *mmc = dev->platform_data; + + /* NOTE: assumes card detect signal is active-low */ + return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); +} + +#ifdef CONFIG_PM + +static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) +{ + struct omap_mmc_platform_data *mmc = dev->platform_data; + + disable_irq(mmc->slots[0].card_detect_irq); + return 0; +} + +static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) +{ + struct omap_mmc_platform_data *mmc = dev->platform_data; + + enable_irq(mmc->slots[0].card_detect_irq); + return 0; +} + +#else + +#define omap_hsmmc_suspend_cdirq NULL +#define omap_hsmmc_resume_cdirq NULL + +#endif + +#ifdef CONFIG_REGULATOR + +static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on, + int vdd) +{ + struct omap_hsmmc_host *host = + platform_get_drvdata(to_platform_device(dev)); + int ret; + + if (mmc_slot(host).before_set_reg) + mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); + + if (power_on) + ret = mmc_regulator_set_ocr(host->vcc, vdd); + else + ret = mmc_regulator_set_ocr(host->vcc, 0); + + if (mmc_slot(host).after_set_reg) + mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); + + return ret; +} + +static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on, + int vdd) +{ + struct omap_hsmmc_host *host = + platform_get_drvdata(to_platform_device(dev)); + int ret = 0; + + /* + * If we don't see a Vcc regulator, assume it's a fixed + * voltage always-on regulator. + */ + if (!host->vcc) + return 0; + + if (mmc_slot(host).before_set_reg) + mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); + + /* + * Assume Vcc regulator is used only to power the card ... OMAP + * VDDS is used to power the pins, optionally with a transceiver to + * support cards using voltages other than VDDS (1.8V nominal). When a + * transceiver is used, DAT3..7 are muxed as transceiver control pins. + * + * In some cases this regulator won't support enable/disable; + * e.g. it's a fixed rail for a WLAN chip. + * + * In other cases vcc_aux switches interface power. Example, for + * eMMC cards it represents VccQ. Sometimes transceivers or SDIO + * chips/cards need an interface voltage rail too. + */ + if (power_on) { + ret = mmc_regulator_set_ocr(host->vcc, vdd); + /* Enable interface voltage rail, if needed */ + if (ret == 0 && host->vcc_aux) { + ret = regulator_enable(host->vcc_aux); + if (ret < 0) + ret = mmc_regulator_set_ocr(host->vcc, 0); + } + } else { + if (host->vcc_aux) + ret = regulator_disable(host->vcc_aux); + if (ret == 0) + ret = mmc_regulator_set_ocr(host->vcc, 0); + } + + if (mmc_slot(host).after_set_reg) + mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); + + return ret; +} + +static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep, + int vdd, int cardsleep) +{ + struct omap_hsmmc_host *host = + platform_get_drvdata(to_platform_device(dev)); + int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; + + return regulator_set_mode(host->vcc, mode); +} + +static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep, + int vdd, int cardsleep) +{ + struct omap_hsmmc_host *host = + platform_get_drvdata(to_platform_device(dev)); + int err, mode; + + /* + * If we don't see a Vcc regulator, assume it's a fixed + * voltage always-on regulator. + */ + if (!host->vcc) + return 0; + + mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; + + if (!host->vcc_aux) + return regulator_set_mode(host->vcc, mode); + + if (cardsleep) { + /* VCC can be turned off if card is asleep */ + if (sleep) + err = mmc_regulator_set_ocr(host->vcc, 0); + else + err = mmc_regulator_set_ocr(host->vcc, vdd); + } else + err = regulator_set_mode(host->vcc, mode); + if (err) + return err; + + if (!mmc_slot(host).vcc_aux_disable_is_sleep) + return regulator_set_mode(host->vcc_aux, mode); + + if (sleep) + return regulator_disable(host->vcc_aux); + else + return regulator_enable(host->vcc_aux); +} + +static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) +{ + struct regulator *reg; + int ret = 0; + + switch (host->id) { + case OMAP_MMC1_DEVID: + /* On-chip level shifting via PBIAS0/PBIAS1 */ + mmc_slot(host).set_power = omap_hsmmc_1_set_power; + mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep; + break; + case OMAP_MMC2_DEVID: + case OMAP_MMC3_DEVID: + /* Off-chip level shifting, or none */ + mmc_slot(host).set_power = omap_hsmmc_23_set_power; + mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep; + break; + default: + pr_err("MMC%d configuration not supported!\n", host->id); + return -EINVAL; + } + + reg = regulator_get(host->dev, "vmmc"); + if (IS_ERR(reg)) { + dev_dbg(host->dev, "vmmc regulator missing\n"); + /* + * HACK: until fixed.c regulator is usable, + * we don't require a main regulator + * for MMC2 or MMC3 + */ + if (host->id == OMAP_MMC1_DEVID) { + ret = PTR_ERR(reg); + goto err; + } + } else { + host->vcc = reg; + mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg); + + /* Allow an aux regulator */ + reg = regulator_get(host->dev, "vmmc_aux"); + host->vcc_aux = IS_ERR(reg) ? NULL : reg; + + /* + * UGLY HACK: workaround regulator framework bugs. + * When the bootloader leaves a supply active, it's + * initialized with zero usecount ... and we can't + * disable it without first enabling it. Until the + * framework is fixed, we need a workaround like this + * (which is safe for MMC, but not in general). + */ + if (regulator_is_enabled(host->vcc) > 0) { + regulator_enable(host->vcc); + regulator_disable(host->vcc); + } + if (host->vcc_aux) { + if (regulator_is_enabled(reg) > 0) { + regulator_enable(reg); + regulator_disable(reg); + } + } + } + + return 0; + +err: + mmc_slot(host).set_power = NULL; + mmc_slot(host).set_sleep = NULL; + return ret; +} + +static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) +{ + regulator_put(host->vcc); + regulator_put(host->vcc_aux); + mmc_slot(host).set_power = NULL; + mmc_slot(host).set_sleep = NULL; +} + +static inline int omap_hsmmc_have_reg(void) +{ + return 1; +} + +#else + +static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) +{ + return -EINVAL; +} + +static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) +{ +} + +static inline int omap_hsmmc_have_reg(void) +{ + return 0; +} + +#endif + +static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) +{ + int ret; + + if (gpio_is_valid(pdata->slots[0].switch_pin)) { + pdata->suspend = omap_hsmmc_suspend_cdirq; + pdata->resume = omap_hsmmc_resume_cdirq; + if (pdata->slots[0].cover) + pdata->slots[0].get_cover_state = + omap_hsmmc_get_cover_state; + else + pdata->slots[0].card_detect = omap_hsmmc_card_detect; + pdata->slots[0].card_detect_irq = + gpio_to_irq(pdata->slots[0].switch_pin); + ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); + if (ret) + return ret; + ret = gpio_direction_input(pdata->slots[0].switch_pin); + if (ret) + goto err_free_sp; + } else + pdata->slots[0].switch_pin = -EINVAL; + + if (gpio_is_valid(pdata->slots[0].gpio_wp)) { + pdata->slots[0].get_ro = omap_hsmmc_get_wp; + ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); + if (ret) + goto err_free_cd; + ret = gpio_direction_input(pdata->slots[0].gpio_wp); + if (ret) + goto err_free_wp; + } else + pdata->slots[0].gpio_wp = -EINVAL; + + return 0; + +err_free_wp: + gpio_free(pdata->slots[0].gpio_wp); +err_free_cd: + if (gpio_is_valid(pdata->slots[0].switch_pin)) +err_free_sp: + gpio_free(pdata->slots[0].switch_pin); + return ret; +} + +static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) +{ + if (gpio_is_valid(pdata->slots[0].gpio_wp)) + gpio_free(pdata->slots[0].gpio_wp); + if (gpio_is_valid(pdata->slots[0].switch_pin)) + gpio_free(pdata->slots[0].switch_pin); +} + /* * Stop clock to the card */ @@ -835,7 +1173,7 @@ static void omap_hsmmc_detect(struct work_struct *work) sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); if (slot->card_detect) - carddetect = slot->card_detect(slot->card_detect_irq); + carddetect = slot->card_detect(host->dev, host->slot_id); else { omap_hsmmc_protect_card(host); carddetect = -ENOSYS; @@ -1242,7 +1580,7 @@ static int omap_hsmmc_get_cd(struct mmc_host *mmc) if (!mmc_slot(host).card_detect) return -ENOSYS; - return mmc_slot(host).card_detect(mmc_slot(host).card_detect_irq); + return mmc_slot(host).card_detect(host->dev, host->slot_id); } static int omap_hsmmc_get_ro(struct mmc_host *mmc) @@ -1311,7 +1649,7 @@ static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host) if (host->power_mode == MMC_POWER_OFF) return 0; - return msecs_to_jiffies(OMAP_MMC_SLEEP_TIMEOUT); + return OMAP_MMC_SLEEP_TIMEOUT; } /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */ @@ -1347,11 +1685,14 @@ static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host) dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n", host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); + if (mmc_slot(host).no_off) + return 0; + if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || mmc_slot(host).card_detect || (mmc_slot(host).get_cover_state && mmc_slot(host).get_cover_state(host->dev, host->slot_id))) - return msecs_to_jiffies(OMAP_MMC_OFF_TIMEOUT); + return OMAP_MMC_OFF_TIMEOUT; return 0; } @@ -1362,6 +1703,9 @@ static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host) if (!mmc_try_claim_host(host->mmc)) return 0; + if (mmc_slot(host).no_off) + return 0; + if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) || mmc_slot(host).card_detect || (mmc_slot(host).get_cover_state && @@ -1616,7 +1960,7 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev) struct mmc_host *mmc; struct omap_hsmmc_host *host = NULL; struct resource *res; - int ret = 0, irq; + int ret, irq; if (pdata == NULL) { dev_err(&pdev->dev, "Platform Data is missing\n"); @@ -1638,10 +1982,14 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev) if (res == NULL) return -EBUSY; + ret = omap_hsmmc_gpio_init(pdata); + if (ret) + goto err; + mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); if (!mmc) { ret = -ENOMEM; - goto err; + goto err_alloc; } host = mmc_priv(mmc); @@ -1656,7 +2004,7 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev) host->slot_id = 0; host->mapbase = res->start; host->base = ioremap(host->mapbase, SZ_4K); - host->power_mode = -1; + host->power_mode = MMC_POWER_OFF; platform_set_drvdata(pdev, host); INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect); @@ -1666,6 +2014,13 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev) else mmc->ops = &omap_hsmmc_ops; + /* + * If regulator_disable can only put vcc_aux to sleep then there is + * no off state. + */ + if (mmc_slot(host).vcc_aux_disable_is_sleep) + mmc_slot(host).no_off = 1; + mmc->f_min = 400000; mmc->f_max = 52000000; @@ -1781,7 +2136,6 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev) goto err_irq; } - /* initialize power supplies, gpios, etc */ if (pdata->init != NULL) { if (pdata->init(&pdev->dev) != 0) { dev_dbg(mmc_dev(host->mmc), @@ -1789,6 +2143,14 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev) goto err_irq_cd_init; } } + + if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { + ret = omap_hsmmc_reg_get(host); + if (ret) + goto err_reg; + host->use_reg = 1; + } + mmc->ocr_avail = mmc_slot(host).ocr_mask; /* Request IRQ for card detect */ @@ -1823,19 +2185,22 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev) ret = device_create_file(&mmc->class_dev, &dev_attr_cover_switch); if (ret < 0) - goto err_cover_switch; + goto err_slot_name; } omap_hsmmc_debugfs(mmc); return 0; -err_cover_switch: - device_remove_file(&mmc->class_dev, &dev_attr_cover_switch); err_slot_name: mmc_remove_host(mmc); -err_irq_cd: free_irq(mmc_slot(host).card_detect_irq, host); +err_irq_cd: + if (host->use_reg) + omap_hsmmc_reg_put(host); +err_reg: + if (host->pdata->cleanup) + host->pdata->cleanup(&pdev->dev); err_irq_cd_init: free_irq(host->irq, host); err_irq: @@ -1847,14 +2212,14 @@ err_irq: clk_disable(host->dbclk); clk_put(host->dbclk); } - err1: iounmap(host->base); + platform_set_drvdata(pdev, NULL); + mmc_free_host(mmc); +err_alloc: + omap_hsmmc_gpio_free(pdata); err: - dev_dbg(mmc_dev(host->mmc), "Probe Failed\n"); release_mem_region(res->start, res->end - res->start + 1); - if (host) - mmc_free_host(mmc); return ret; } @@ -1866,6 +2231,8 @@ static int omap_hsmmc_remove(struct platform_device *pdev) if (host) { mmc_host_enable(host->mmc); mmc_remove_host(host->mmc); + if (host->use_reg) + omap_hsmmc_reg_put(host); if (host->pdata->cleanup) host->pdata->cleanup(&pdev->dev); free_irq(host->irq, host); @@ -1884,6 +2251,7 @@ static int omap_hsmmc_remove(struct platform_device *pdev) mmc_free_host(host->mmc); iounmap(host->base); + omap_hsmmc_gpio_free(pdev->dev.platform_data); } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig index 2de0cc823d60..9605cb87c746 100644 --- a/drivers/mtd/maps/Kconfig +++ b/drivers/mtd/maps/Kconfig @@ -428,15 +428,6 @@ config MTD_H720X This enables access to the flash chips on the Hynix evaluation boards. If you have such a board, say 'Y'. -config MTD_OMAP_NOR - tristate "TI OMAP board mappings" - depends on MTD_CFI && ARCH_OMAP - help - This enables access to the NOR flash chips on TI OMAP-based - boards defining flash platform devices and flash platform data. - These boards include the Innovator, H2, H3, OSK, Perseus2, and - more. If you have such a board, say 'Y'. - # This needs CFI or JEDEC, depending on the cards found. config MTD_PCI tristate "PCI MTD driver" diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile index ce315214ff2b..faa9fef19585 100644 --- a/drivers/mtd/maps/Makefile +++ b/drivers/mtd/maps/Makefile @@ -55,7 +55,6 @@ obj-$(CONFIG_MTD_IXP2000) += ixp2000.o obj-$(CONFIG_MTD_WRSBC8260) += wr_sbc82xx_flash.o obj-$(CONFIG_MTD_DMV182) += dmv182.o obj-$(CONFIG_MTD_PLATRAM) += plat-ram.o -obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o obj-$(CONFIG_MTD_INTEL_VR_NOR) += intel_vr_nor.o obj-$(CONFIG_MTD_BFIN_ASYNC) += bfin-async-flash.o obj-$(CONFIG_MTD_RBTX4939) += rbtx4939-flash.o diff --git a/drivers/mtd/maps/omap_nor.c b/drivers/mtd/maps/omap_nor.c index ead0b2fab670..e69de29bb2d1 100644 --- a/drivers/mtd/maps/omap_nor.c +++ b/drivers/mtd/maps/omap_nor.c @@ -1,188 +0,0 @@ -/* - * Flash memory support for various TI OMAP boards - * - * Copyright (C) 2001-2002 MontaVista Software Inc. - * Copyright (C) 2003-2004 Texas Instruments - * Copyright (C) 2004 Nokia Corporation - * - * Assembled using driver code copyright the companies above - * and written by David Brownell, Jian Zhang <jzhang@ti.com>, - * Tony Lindgren <tony@atomide.com> and others. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <linux/platform_device.h> -#include <linux/module.h> -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/ioport.h> -#include <linux/slab.h> - -#include <linux/mtd/mtd.h> -#include <linux/mtd/map.h> -#include <linux/mtd/partitions.h> - -#include <asm/io.h> -#include <mach/hardware.h> -#include <asm/mach/flash.h> -#include <plat/tc.h> - -#ifdef CONFIG_MTD_PARTITIONS -static const char *part_probes[] = { /* "RedBoot", */ "cmdlinepart", NULL }; -#endif - -struct omapflash_info { - struct mtd_partition *parts; - struct mtd_info *mtd; - struct map_info map; -}; - -static void omap_set_vpp(struct map_info *map, int enable) -{ - static int count; - u32 l; - - if (cpu_class_is_omap1()) { - if (enable) { - if (count++ == 0) { - l = omap_readl(EMIFS_CONFIG); - l |= OMAP_EMIFS_CONFIG_WP; - omap_writel(l, EMIFS_CONFIG); - } - } else { - if (count && (--count == 0)) { - l = omap_readl(EMIFS_CONFIG); - l &= ~OMAP_EMIFS_CONFIG_WP; - omap_writel(l, EMIFS_CONFIG); - } - } - } -} - -static int __init omapflash_probe(struct platform_device *pdev) -{ - int err; - struct omapflash_info *info; - struct flash_platform_data *pdata = pdev->dev.platform_data; - struct resource *res = pdev->resource; - unsigned long size = res->end - res->start + 1; - - info = kzalloc(sizeof(struct omapflash_info), GFP_KERNEL); - if (!info) - return -ENOMEM; - - if (!request_mem_region(res->start, size, "flash")) { - err = -EBUSY; - goto out_free_info; - } - - info->map.virt = ioremap(res->start, size); - if (!info->map.virt) { - err = -ENOMEM; - goto out_release_mem_region; - } - info->map.name = dev_name(&pdev->dev); - info->map.phys = res->start; - info->map.size = size; - info->map.bankwidth = pdata->width; - info->map.set_vpp = omap_set_vpp; - - simple_map_init(&info->map); - info->mtd = do_map_probe(pdata->map_name, &info->map); - if (!info->mtd) { - err = -EIO; - goto out_iounmap; - } - info->mtd->owner = THIS_MODULE; - - info->mtd->dev.parent = &pdev->dev; - -#ifdef CONFIG_MTD_PARTITIONS - err = parse_mtd_partitions(info->mtd, part_probes, &info->parts, 0); - if (err > 0) - add_mtd_partitions(info->mtd, info->parts, err); - else if (err <= 0 && pdata->parts) - add_mtd_partitions(info->mtd, pdata->parts, pdata->nr_parts); - else -#endif - add_mtd_device(info->mtd); - - platform_set_drvdata(pdev, info); - - return 0; - -out_iounmap: - iounmap(info->map.virt); -out_release_mem_region: - release_mem_region(res->start, size); -out_free_info: - kfree(info); - - return err; -} - -static int __exit omapflash_remove(struct platform_device *pdev) -{ - struct omapflash_info *info = platform_get_drvdata(pdev); - - platform_set_drvdata(pdev, NULL); - - if (info) { - if (info->parts) { - del_mtd_partitions(info->mtd); - kfree(info->parts); - } else - del_mtd_device(info->mtd); - map_destroy(info->mtd); - release_mem_region(info->map.phys, info->map.size); - iounmap((void __iomem *) info->map.virt); - kfree(info); - } - - return 0; -} - -static struct platform_driver omapflash_driver = { - .remove = __exit_p(omapflash_remove), - .driver = { - .name = "omapflash", - .owner = THIS_MODULE, - }, -}; - -static int __init omapflash_init(void) -{ - return platform_driver_probe(&omapflash_driver, omapflash_probe); -} - -static void __exit omapflash_exit(void) -{ - platform_driver_unregister(&omapflash_driver); -} - -module_init(omapflash_init); -module_exit(omapflash_exit); - -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("MTD NOR map driver for TI OMAP boards"); -MODULE_ALIAS("platform:omapflash"); diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index 1bb799f0125c..26aec0080184 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -30,12 +30,8 @@ #define DRIVER_NAME "omap2-nand" -/* size (4 KiB) for IO mapping */ -#define NAND_IO_SIZE SZ_4K - #define NAND_WP_OFF 0 #define NAND_WP_BIT 0x00000010 -#define WR_RD_PIN_MONITORING 0x00600000 #define GPMC_BUF_FULL 0x00000001 #define GPMC_BUF_EMPTY 0x00000000 @@ -882,8 +878,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) struct omap_nand_info *info; struct omap_nand_platform_data *pdata; int err; - unsigned long val; - pdata = pdev->dev.platform_data; if (pdata == NULL) { @@ -905,28 +899,14 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) info->gpmc_cs = pdata->cs; info->gpmc_baseaddr = pdata->gpmc_baseaddr; info->gpmc_cs_baseaddr = pdata->gpmc_cs_baseaddr; + info->phys_base = pdata->phys_base; info->mtd.priv = &info->nand; info->mtd.name = dev_name(&pdev->dev); info->mtd.owner = THIS_MODULE; - err = gpmc_cs_request(info->gpmc_cs, NAND_IO_SIZE, &info->phys_base); - if (err < 0) { - dev_err(&pdev->dev, "Cannot request GPMC CS\n"); - goto out_free_info; - } - - /* Enable RD PIN Monitoring Reg */ - if (pdata->dev_ready) { - val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1); - val |= WR_RD_PIN_MONITORING; - gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG1, val); - } - - val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG7); - val &= ~(0xf << 8); - val |= (0xc & 0xf) << 8; - gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG7, val); + info->nand.options |= pdata->devsize ? NAND_BUSWIDTH_16 : 0; + info->nand.options |= NAND_SKIP_BBTSCAN; /* NAND write protect off */ omap_nand_wp(&info->mtd, NAND_WP_OFF); @@ -934,7 +914,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) if (!request_mem_region(info->phys_base, NAND_IO_SIZE, pdev->dev.driver->name)) { err = -EBUSY; - goto out_free_cs; + goto out_free_info; } info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE); @@ -963,11 +943,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) info->nand.chip_delay = 50; } - info->nand.options |= NAND_SKIP_BBTSCAN; - if ((gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1) & 0x3000) - == 0x1000) - info->nand.options |= NAND_BUSWIDTH_16; - if (use_prefetch) { /* copy the virtual address of nand base for fifo access */ info->nand_pref_fifo_add = info->nand.IO_ADDR_R; @@ -1043,8 +1018,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) out_release_mem_region: release_mem_region(info->phys_base, NAND_IO_SIZE); -out_free_cs: - gpmc_cs_free(info->gpmc_cs); out_free_info: kfree(info); diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h index 05adb6a666cf..3269292efecc 100644 --- a/drivers/net/smc911x.h +++ b/drivers/net/smc911x.h @@ -42,12 +42,12 @@ #define SMC_USE_16BIT 0 #define SMC_USE_32BIT 1 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW -#elif defined(CONFIG_ARCH_OMAP34XX) +#elif defined(CONFIG_ARCH_OMAP3) #define SMC_USE_16BIT 0 #define SMC_USE_32BIT 1 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW #define SMC_MEM_RESERVED 1 -#elif defined(CONFIG_ARCH_OMAP24XX) +#elif defined(CONFIG_ARCH_OMAP2) #define SMC_USE_16BIT 0 #define SMC_USE_32BIT 1 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index f55eb0107336..66c35d74a76b 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -164,7 +164,7 @@ config SPI_OMAP_UWIRE config SPI_OMAP24XX tristate "McSPI driver for OMAP24xx/OMAP34xx" - depends on ARCH_OMAP24XX || ARCH_OMAP34XX + depends on ARCH_OMAP2 || ARCH_OMAP3 help SPI master controller for OMAP24xx/OMAP34xx Multichannel SPI (McSPI) modules. diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c index bf5f95a19413..715c518b1b68 100644 --- a/drivers/spi/omap2_mcspi.c +++ b/drivers/spi/omap2_mcspi.c @@ -1014,7 +1014,7 @@ static u8 __initdata spi2_txdma_id[] = { OMAP24XX_DMA_SPI2_TX1, }; -#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX) \ +#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \ || defined(CONFIG_ARCH_OMAP4) static u8 __initdata spi3_rxdma_id[] = { OMAP24XX_DMA_SPI3_RX0, diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 81aac7f4ca59..4f5bb5698f5d 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -61,7 +61,7 @@ config USB_ARCH_HAS_EHCI default y if ARCH_W90X900 default y if ARCH_AT91SAM9G45 default y if ARCH_MXC - default y if ARCH_OMAP34XX + default y if ARCH_OMAP3 default PCI # ARM SA1111 chips have a non-PCI based "OHCI-compatible" USB host interface. diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 1ec3857f22e6..d8d6d3461d32 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1118,7 +1118,7 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver #endif -#ifdef CONFIG_ARCH_OMAP34XX +#ifdef CONFIG_ARCH_OMAP3 #include "ehci-omap.c" #define PLATFORM_DRIVER ehci_hcd_omap_driver #endif diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig index d9db86498022..b4c783c284ba 100644 --- a/drivers/usb/musb/Kconfig +++ b/drivers/usb/musb/Kconfig @@ -37,7 +37,7 @@ config USB_MUSB_SOC depends on USB_MUSB_HDRC default y if ARCH_DAVINCI default y if ARCH_OMAP2430 - default y if ARCH_OMAP34XX + default y if ARCH_OMAP3 default y if (BF54x && !BF544) default y if (BF52x && !BF522 && !BF523) @@ -48,7 +48,7 @@ comment "OMAP 243x high speed USB support" depends on USB_MUSB_HDRC && ARCH_OMAP2430 comment "OMAP 343x high speed USB support" - depends on USB_MUSB_HDRC && ARCH_OMAP34XX + depends on USB_MUSB_HDRC && ARCH_OMAP3 comment "Blackfin high speed USB Support" depends on USB_MUSB_HDRC && ((BF54x && !BF544) || (BF52x && !BF522 && !BF523)) @@ -153,7 +153,7 @@ config MUSB_PIO_ONLY config USB_INVENTRA_DMA bool depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY - default ARCH_OMAP2430 || ARCH_OMAP34XX || BLACKFIN + default ARCH_OMAP2430 || ARCH_OMAP3 || BLACKFIN help Enable DMA transfers using Mentor's engine. diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c index 5eb9318cff77..738efd8063b5 100644 --- a/drivers/usb/musb/musb_core.c +++ b/drivers/usb/musb/musb_core.c @@ -1000,7 +1000,7 @@ static void musb_shutdown(struct platform_device *pdev) * more than selecting one of a bunch of predefined configurations. */ #if defined(CONFIG_USB_TUSB6010) || \ - defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX) + defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) static ushort __initdata fifo_mode = 4; #else static ushort __initdata fifo_mode = 2; diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h index 03d50909b078..5514c7ee85bd 100644 --- a/drivers/usb/musb/musb_core.h +++ b/drivers/usb/musb/musb_core.h @@ -562,7 +562,7 @@ extern void musb_hnp_stop(struct musb *musb); extern int musb_platform_set_mode(struct musb *musb, u8 musb_mode); #if defined(CONFIG_USB_TUSB6010) || defined(CONFIG_BLACKFIN) || \ - defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX) + defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) extern void musb_platform_try_idle(struct musb *musb, unsigned long timeout); #else #define musb_platform_try_idle(x, y) do {} while (0) diff --git a/drivers/w1/masters/Kconfig b/drivers/w1/masters/Kconfig index 3195fb8b7d9a..80b3b123dd7f 100644 --- a/drivers/w1/masters/Kconfig +++ b/drivers/w1/masters/Kconfig @@ -60,7 +60,7 @@ config W1_MASTER_GPIO config HDQ_MASTER_OMAP tristate "OMAP HDQ driver" - depends on ARCH_OMAP2430 || ARCH_OMAP34XX + depends on ARCH_OMAP2430 || ARCH_OMAP3 help Say Y here if you want support for the 1-wire or HDQ Interface on an OMAP processor. diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 050ee147592f..3da3f48720a7 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -194,7 +194,7 @@ config EP93XX_WATCHDOG config OMAP_WATCHDOG tristate "OMAP Watchdog" - depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX + depends on ARCH_OMAP16XX || ARCH_OMAP2 || ARCH_OMAP3 help Support for TI OMAP1610/OMAP1710/OMAP2420/OMAP3430 watchdog. Say 'Y' here to enable the OMAP1610/OMAP1710/OMAP2420/OMAP3430 watchdog timer. diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c index 6bbbd2ab0ee7..c0039b35fb25 100644 --- a/sound/soc/omap/omap-mcbsp.c +++ b/sound/soc/omap/omap-mcbsp.c @@ -82,11 +82,11 @@ static const int omap1_dma_reqs[][2] = {}; static const unsigned long omap1_mcbsp_port[][2] = {}; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) static const int omap24xx_dma_reqs[][2] = { { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX }, { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX }, -#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX }, { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX }, { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX }, @@ -124,7 +124,7 @@ static const unsigned long omap2430_mcbsp_port[][2] = { static const unsigned long omap2430_mcbsp_port[][2] = {}; #endif -#if defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP3) static const unsigned long omap34xx_mcbsp_port[][2] = { { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR, OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR }, diff --git a/sound/soc/omap/omap-mcbsp.h b/sound/soc/omap/omap-mcbsp.h index 647d2f981ab0..1968d03bc532 100644 --- a/sound/soc/omap/omap-mcbsp.h +++ b/sound/soc/omap/omap-mcbsp.h @@ -50,7 +50,7 @@ enum omap_mcbsp_div { #undef NUM_LINKS #define NUM_LINKS 3 #endif -#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) #undef NUM_LINKS #define NUM_LINKS 5 #endif |