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2014-05-30ARM: 8047/1: rwsem: use asm-generic rwsem implementationWill Deacon
asm-generic offers an atomic-add based rwsem implementation, which can avoid the need for heavier, spinlock-based synchronisation on the fast path. This patch makes use of the optimised implementation for ARM CPUs. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30ARM: l2c: trial at enabling some Cortex-A9 optimisationsRussell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30ARM: l2c: remove old .set_debug methodRussell King
We no longer need or require the .set_debug method; we handle everything it used to do via the .write_sec method instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30ARM: l2c: kill L2X0_AUX_CTRL_MASK before anyone else makes use of thisRussell King
L2X0_AUX_CTRL_MASK is not useful for PL310s. It would be better if people thought about their value for this rather than cargo-cult programming. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30ARM: l2c: add platform independent core L2 cache OF initialisationRussell King
Add a hook into the core ARM code to perform L2 cache initialisation in a platform independent manner. Platforms still get to indicate their auxiliary control register values and mask, but the initialisation call will now be made from generic code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30ARM: l2c: fix register namingRussell King
We have a mixture of different devices with different register layouts, but we group all the bits together in an opaque mess. Split them out into those which are L2C-310 specific and ones which refer to earlier devices. Provide full auxiliary control register definitions. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30ARM: l2c: provide generic hook to intercept writes to secure registersRussell King
When Linux is running in the non-secure world, any write to a secure L2C register will generate an abort. Platforms normally have to call firmware to work around this. Provide a hook for them to intercept any L2C secure register write. l2c_write_sec() avoids writes to secure registers which are already set to the appropriate value, thus avoiding the overhead of needlessly calling into the secure monitor. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30ARM: l2c: add and use L2C revision constantsRussell King
The revision namespace is specific to the L2 cache part, so don't name these with generic identifiers, use a part specific identifier. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30ARM: outer cache: add WARN_ON() to outer_disable()Russell King
Add WARN_ON() conditions to outer_disable() to ensure that its requirements aren't violated. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-28ARM: tty: Move HVC DCC assembly to arch/armChristopher Covington
Put architecture-specific assembly code where it belongs, allowing for support of additional architectures such as arm64 in the future. Signed-off-by: Christopher Covington <cov@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-05-27PCI: Turn pcibios_penalize_isa_irq() into a weak functionHanjun Guo
pcibios_penalize_isa_irq() is only implemented by x86 now, and legacy ISA is not used by some architectures. Make pcibios_penalize_isa_irq() a __weak function to simplify the code. This removes the need for new platforms to add stub implementations of pcibios_penalize_isa_irq(). [bhelgaas: changelog, comments] Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-05-27arm: Fix compile warning for psciChristoffer Dall
Commit e71246a23acbc89e9cb4ebf1558d60e65733479f changes psci_init from a function returning a void to an int, but does not change the non CONFIG_ARM_PSCI implementation to return a value, which causes a compile warning. Just return 0. Cc: Ashwin Chaugule <ashwin.chaugule@linaro.org> Cc: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-26Merge tag 'zynq-cleanup-for-3.16' of git://git.xilinx.com/linux-xlnx into ↵Olof Johansson
next/soc Merge "Xilinx Zynq changes for v3.16" from Michal Simek: arm: Xilinx Zynq cleanup patches for v3.16 - Add support for BIG Endian - Add SOC_BUS support - Sort Kconfig options - Fix early console * tag 'zynq-cleanup-for-3.16' of git://git.xilinx.com/linux-xlnx: ARM: zynq: Enable big-endian ARM: zynq: Fix uart0 early console virtual address clocksource: cadence_ttc: Use readl/writel_relaxed instead of __raw ARM: zynq: Sort Kconfig options ARM: zynq: Add support for SOC_BUS Signed-off-by: Olof Johansson <olof@lixom.net>
2014-05-25ARM: 8053/1: kernel: sleep: restore HYP mode configuration in cpu_resumeLorenzo Pieralisi
On CPUs with virtualization extensions the kernel installs HYP mode configuration on both primary and secondary cpus upon cold boot. On platforms where CPUs are shutdown in idle paths (ie CPU core gating), when a CPU resumes from low-power states it currently does not execute code that reinstalls the HYP configuration, which means that the kernel cannot run eg KVM properly on such machines. This patch, mirroring cold-boot behaviour, executes position independent code that reinstalls HYP configuration and drops to SVC mode safely on warmboot, so that deep idle states can be enabled in kernel running as hosts on platforms with power management HW. Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Dave Martin <dave.martin@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Nicolas Pitre <nico@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-25ARM: 8043/1: uprobes need icache flush after xol writeVictor Kamensky
After instruction write into xol area, on ARM V7 architecture code need to flush dcache and icache to sync them up for given set of addresses. Having just 'flush_dcache_page(page)' call is not enough - it is possible to have stale instruction sitting in icache for given xol area slot address. Introduce arch_uprobe_ixol_copy weak function that by default calls uprobes copy_to_page function and than flush_dcache_page function and on ARM define new one that handles xol slot copy in ARM specific way flush_uprobe_xol_access function shares/reuses implementation with/of flush_ptrace_access function and takes care of writing instruction to user land address space on given variety of different cache types on ARM CPUs. Because flush_uprobe_xol_access does not have vma around flush_ptrace_access was split into two parts. First that retrieves set of condition from vma and common that receives those conditions as flags. Note ARM cache flush function need kernel address through which instruction write happened, so instead of using uprobes copy_to_page function changed code to explicitly map page and do memcpy. Note arch_uprobe_copy_ixol function, in similar way as copy_to_user_page function, has preempt_disable/preempt_enable. Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org> Acked-by: Oleg Nesterov <oleg@redhat.com> Reviewed-by: David A. Long <dave.long@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-25ARM: 8029/1: mcpm: Rename the power_down_finish() functions to be less confusingDave Martin
The name "power_down_finish" seems to be causing some confusion, because it suggests that this function is responsible for taking some action to cause the specified CPU to complete its power down. This patch renames the affected functions to "wait_for_powerdown" and similar, since this function's intended purpose is just to wait for the hardware to finish a powerdown initiated by a previous cpu_power_down. Signed-off-by: Dave Martin <Dave.Martin@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-25ARM: 8055/1: cacheflush: use -st dsb option for ensuring completionWill Deacon
dsb st can be used to ensure completion of pending cache maintenance operations, so use it for the v7 cache maintenance operations. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-25ARM: 8046/1: proc: add support for the Cortex-A17 processorWill Deacon
Cortex-A17 has identical initialisation requirements to Cortex-A12, so hook it up in proc-v7.S in the same way. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-25ARM: 8051/1: put_user: fix possible data corruption in put_userAndrey Ryabinin
According to arm procedure call standart r2 register is call-cloberred. So after the result of x expression was put into r2 any following function call in p may overwrite r2. To fix this, the result of p expression must be saved to the temporary variable before the assigment x expression to __r2. Signed-off-by: Andrey Ryabinin <a.ryabinin@samsung.com> Reviewed-by: Nicolas Pitre <nico@linaro.org> Cc: stable@vger.kernel.org Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-26ARM: S3C24XX: move debug-macro.S into the common spaceHeiko Stuebner
Move debug-macro.S from mach/include to include/debug where all other common debug macros are. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-05-23Merge tag 'qcom-soc-for-3.16' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/soc Merge "Qualcomm ARM Based SoC Updates for v3.16" from Kumar Gala: * Enabling building pinctrl and AMBA bus support * Clean up debug UART selection * tag 'qcom-soc-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom: ARM: qcom: Select PINCTRL by default for ARCH_QCOM ARM: debug: qcom: make UART address selection configuration option ARM: qcom: Enable ARM_AMBA option for Qualcomm SOCs. Conflicts: arch/arm/Kconfig.debug arch/arm/mach-qcom/Kconfig Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-05-23ARM: trusted_foundations: fix compile error on non-SMPAlexandre Courbot
The setup_max_cpus variable is only defined if CONFIG_SMP is set. Add a preprocessor condition to avoid the following compilation error if CONFIG_SMP is not set: arch/arm/include/asm/trusted_foundations.h: In function 'register_trusted_foundations': arch/arm/include/asm/trusted_foundations.h:57:2: error: 'setup_max_cpus' undeclared (first use in this function) Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-05-23Merge tag 'dt-dma-properties-for-arm' of ↵Russell King
git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into devel-stable DT support for 'dma-ranges'and 'dma-coherent' properties with ARM updates - The 'dma-ranges' helps to take care of few DMAable system memory restrictions by use of dma_pfn_offset which is maintained per device. Arch code then uses it for dma address translations for such cases. We update the dma_pfn_offset accordingly during DT the device creation process. - The 'dma-coherent' property is used to setup arch's coherent dma_ops.
2014-05-22ARM: debug: qcom: make UART address selection configuration optionIvan T. Ivanov
Separate Qualcomm low-level debugging UART to two options. DEBUG_MSM_UART is used in earlier non-multi platform arches, like MSM7X00A, QSD8X50 and MSM7X30. DEBUG_QCOM_UARTDM is used in multi-plafrom arches and have embedded data mover. Make DEBUG_UART_PHYS and DEBUG_UART_BASE user adjustable by Kconfig menu. Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
2014-05-22ARM: outer cache: add documentation of outer cache functionsRussell King
Add some documentation to cover the outer cache functions so that their requirements can be better understood. Of particular note are the flush_all() and disable() methods which must not be called except in very specific circumstances. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-22ARM: use get_cr() rather than cr_alignmentRussell King
Rather than reading the cr_alignment variable, use get_cr() to read directly from the hardware instead. We have two places where this occurs, neither of them are performance critical. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-22ARM: make get_cr()/set_cr() use unsigned long valuesRussell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-22ARM: l2c: remove outer_inv_all() methodRussell King
No one ever calls this function anywhere in the kernel, so let's completely remove it from the outer cache API and turn it into an internal-only thing. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-21ftrace: Make CALLER_ADDRx macros more genericAKASHI Takahiro
Most archs with HAVE_ARCH_CALLER_ADDR have pretty much the same definitions of CALLER_ADDRx(n). Instead of duplicating the code for all the archs, define a ftrace_return_address0() and ftrace_return_address(n) that can be overwritten by the archs if they need to do something different. Instead of 7 macros in every arch, we now only have at most 2 (and actually only 1 as ftrace_return_address0() should be the same for all archs). The CALLER_ADDRx(n) will now be defined in linux/ftrace.h and use the ftrace_return_address*(n?) macros. This removes a lot of the duplicate code. Link: http://lkml.kernel.org/p/1400585464-30333-1-git-send-email-takahiro.akashi@linaro.org Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
2014-05-20ARM: zynq: Enable big-endianMichal Simek
Enable ARCH_SUPPORTS_BIG_ENDIAN in Kconfig. zynq_secondary_trampoline is the first function that is called on secondary CPU. Reference: "ARM: mcpm: fix big endian issue in mcpm startup code" (sha1: 519ceb9fd10cd7e836d0aa97b2068cc9e97f463b) Fix early printk support. Based on: "ARM: pl01x debug code endian fix" (sha1: 76e3faf156fa95b6465e747d702b94faf67117fc) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20ARM: zynq: Fix uart0 early console virtual addressMichal Simek
Virtual address have to have the same offset within a 2MB aligned section of virtual/phycial address space. Fix uart0 virtual address to be align with physical one. Also remove UART_SIZE which is completely unused. Reported-by: Russ Smith <russells@google.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20arm: dma-iommu: Clean up redundant variableRitesh Harjani
mapping->size can be derived from mapping->bits << PAGE_SHIFT which makes mapping->size as redundant. Clean this up. Signed-off-by: Ritesh Harjani <ritesh.harjani@gmail.com> Reported-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
2014-05-16ARM: imx: add low-level debug support for imx6sxShawn Guo
Enable low-level debug support for i.MX6 SoloX by adding the debug port definitions for the SoC. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-05-15PSCI: Add initial support for PSCIv0.2 functionsAshwin Chaugule
The PSCIv0.2 spec defines standard values of function IDs and introduces a few new functions. Detect version of PSCI and appropriately select the right PSCI functions. Signed-off-by: Ashwin Chaugule <ashwin.chaugule@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
2014-05-13Merge branch 'dt-bus-name' into for-nextRob Herring
2014-05-13Merge tag 'stable/for-linus-3.15-rc5-tag' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip Pull xen bug fixes from David Vrabel: - Fix arm64 crash on boot. - Quiet a noisy arm build warning (virt_to_pfn() redefined). * tag 'stable/for-linus-3.15-rc5-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip: arm64: introduce virt_to_pfn xen/events/fifo: correctly align bitops arm/xen: Remove definiition of virt_to_pfn in asm/xen/page.h
2014-05-12arm,arm64/xen: introduce HYPERVISOR_suspend()Stefano Stabellini
Introduce HYPERVISOR_suspend() and a few additional empty stubs for Xen arch specific functions called by drivers/xen/manage.c. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Signed-off-by: David Vrabel <david.vrabel@citrix.com>
2014-05-07ARM: dma: implement set_arch_dma_coherent_ops()Santosh Shilimkar
Implement the set_arch_dma_coherent_ops() for ARM architecture. Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Olof Johansson <olof@lixom.net> Cc: Grant Likely <grant.likely@linaro.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2014-05-07ARM: dma: Use dma_pfn_offset for dma address translationGrygorii Strashko
In most of cases DMA addresses can be performed using offset value of Bus address space relatively to physical address space as following: PFN->DMA: __pfn_to_phys(pfn + [-]dma_pfn_offset) DMA->PFN: __phys_to_pfn(dma_addr) + [-]dma_pfn_offset Thanks to Russell King for suggesting the optimised macro's for conversion. Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Olof Johansson <olof@lixom.net> Cc: Grant Likely <grant.likely@linaro.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2014-04-30ARM/ARM64: KVM: Make kvm_psci_call() return convention more flexibleAnup Patel
Currently, the kvm_psci_call() returns 'true' or 'false' based on whether the PSCI function call was handled successfully or not. This does not help us emulate system-level PSCI functions where the actual emulation work will be done by user space (QEMU or KVMTOOL). Examples of such system-level PSCI functions are: PSCI v0.2 SYSTEM_OFF and SYSTEM_RESET. This patch updates kvm_psci_call() to return three types of values: 1) > 0 (success) 2) = 0 (success but exit to user space) 3) < 0 (errors) Signed-off-by: Anup Patel <anup.patel@linaro.org> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
2014-04-30ARM/ARM64: KVM: Add base for PSCI v0.2 emulationAnup Patel
Currently, the in-kernel PSCI emulation provides PSCI v0.1 interface to VCPUs. This patch extends current in-kernel PSCI emulation to provide PSCI v0.2 interface to VCPUs. By default, ARM/ARM64 KVM will always provide PSCI v0.1 interface for keeping the ABI backward-compatible. To select PSCI v0.2 interface for VCPUs, the user space (i.e. QEMU or KVMTOOL) will have to set KVM_ARM_VCPU_PSCI_0_2 feature when doing VCPU init using KVM_ARM_VCPU_INIT ioctl. Signed-off-by: Anup Patel <anup.patel@linaro.org> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org> Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
2014-04-30of/fdt: move memreserve and dtb memory reservations into coreRob Herring
Move the /memreserve/ processing and dtb memory reservations into early_init_fdt_scan_reserved_mem. This converts arm, arm64, and powerpc as they are the only users of early_init_fdt_scan_reserved_mem. memblock_reserve is safe to call on the same region twice, so the reservation check for the dtb in powerpc 32-bit reservations is safe to remove. Signed-off-by: Rob Herring <robh@kernel.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Tested-by: Grant Likely <grant.likely@linaro.org> Tested-by: Stephen Chivers <schivers@csc.com>
2014-04-30ARM: vf610: add UART choice for low-level debugStefan Agner
Add choice for low-level debug UART. Similar to i.MX6, there is a numeric configuration, valid choices are 0 to 3. Note that the kernel assumes that the boot loader initialized clock properly. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-04-28arm/xen: Remove definiition of virt_to_pfn in asm/xen/page.hJulien Grall
virt_to_pfn has been defined in asm/memory.h by the commit e26a9e0 "ARM: Better virt_to_page() handling" This will result of a compilation warning when CONFIG_XEN is enabled. arch/arm/include/asm/xen/page.h:80:0: warning: "virt_to_pfn" redefined [enabled by default] #define virt_to_pfn(v) (PFN_DOWN(__pa(v))) ^ In file included from arch/arm/include/asm/page.h:163:0, from arch/arm/include/asm/xen/page.h:4, from include/xen/page.h:4, from arch/arm/xen/grant-table.c:33: The definition in memory.h is nearly the same (it directly expand PFN_DOWN), so we can safely drop virt_to_pfn in xen include. Signed-off-by: Julien Grall <julien.grall@linaro.org> Signed-off-by: David Vrabel <david.vrabel@citrix.com>
2014-04-28Merge commit 'e26a9e0' into stable/for-linus-3.15David Vrabel
2014-04-27Merge branch 'safe-dirty-tlb-flush'Linus Torvalds
This merges the patch to fix possible loss of dirty bit on munmap() or madvice(DONTNEED). If there are concurrent writers on other CPU's that have the unmapped/unneeded page in their TLBs, their writes to the page could possibly get lost if a third CPU raced with the TLB flush and did a page_mkclean() before the page was fully written. Admittedly, if you unmap() or madvice(DONTNEED) an area _while_ another thread is still busy writing to it, you deserve all the lost writes you could get. But we kernel people hold ourselves to higher quality standards than "crazy people deserve to lose", because, well, we've seen people do all kinds of crazy things. So let's get it right, just because we can, and we don't have to worry about it. * safe-dirty-tlb-flush: mm: split 'tlb_flush_mmu()' into tlb flushing and memory freeing parts
2014-04-25mm: split 'tlb_flush_mmu()' into tlb flushing and memory freeing partsLinus Torvalds
The mmu-gather operation 'tlb_flush_mmu()' has done two things: the actual tlb flush operation, and the batched freeing of the pages that the TLB entries pointed at. This splits the operation into separate phases, so that the forced batched flushing done by zap_pte_range() can now do the actual TLB flush while still holding the page table lock, but delay the batched freeing of all the pages to after the lock has been dropped. This in turn allows us to avoid a race condition between set_page_dirty() (as called by zap_pte_range() when it finds a dirty shared memory pte) and page_mkclean(): because we now flush all the dirty page data from the TLB's while holding the pte lock, page_mkclean() will be held up walking the (recently cleaned) page tables until after the TLB entries have been flushed from all CPU's. Reported-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Tested-by: Dave Hansen <dave.hansen@intel.com> Acked-by: Hugh Dickins <hughd@google.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Russell King - ARM Linux <linux@arm.linux.org.uk> Cc: Tony Luck <tony.luck@intel.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2014-04-25ARM: 8041/1: pj4: fix cpu_is_pj4 checkSebastian Hesselbarth
Commit fdb487f5c961b94486a78fa61fa28b8eff1954ab ("ARM: 8015/1: Add cpu_is_pj4 to distinguish PJ4 because it has some differences with V7") introduced a cpuid check for Marvell PJ4 processors to fix a regression caused by adding PJ4 based Marvell Dove into multi_v7. Unfortunately, this check is too narrow to catch PJ4 used on Dove itself and breaks iWMMXt support. This patch therefore relaxes the cpuid mask to match both PJ4 and PJ4B. Also, rework the given comment about PJ4/PJ4B modifications to be a little bit more specific about the differences. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-04-24arm/xen: Remove definiition of virt_to_pfn in asm/xen/page.hJulien Grall
virt_to_pfn has been defined in asm/memory.h by the commit e26a9e0 "ARM: Better virt_to_page() handling" This will result of a compilation warning when CONFIG_XEN is enabled. arch/arm/include/asm/xen/page.h:80:0: warning: "virt_to_pfn" redefined [enabled by default] #define virt_to_pfn(v) (PFN_DOWN(__pa(v))) ^ In file included from arch/arm/include/asm/page.h:163:0, from arch/arm/include/asm/xen/page.h:4, from include/xen/page.h:4, from arch/arm/xen/grant-table.c:33: The definition in memory.h is nearly the same (it directly expand PFN_DOWN), so we can safely drop virt_to_pfn in xen include. Signed-off-by: Julien Grall <julien.grall@linaro.org> Signed-off-by: David Vrabel <david.vrabel@citrix.com>
2014-04-24arm: xen: implement multicall hypercall support.Ian Campbell
As part of this make the usual change to xen_ulong_t in place of unsigned long. This change has no impact on x86. The Linux definition of struct multicall_entry.result differs from the Xen definition, I think for good reasons, and used a long rather than an unsigned long. Therefore introduce a xen_long_t, which is a long on x86 architectures and a signed 64-bit integer on ARM. Use uint32_t nr_calls on x86 for consistency with the ARM definition. Build tested on amd64 and i386 builds. Runtime tested on ARM. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Cc: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com> Signed-off-by: David Vrabel <david.vrabel@citrix.com>
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