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2014-11-19drm/i915: WARN if we receive any rps interrupts on gen>9Imre Deak
This extends commit 132f3f1767dbabfb01f3c9bd63098c65d91eeac9 Author: Imre Deak <imre.deak@intel.com> Date: Mon Nov 10 15:34:33 2014 +0200 drm/i915: WARN if we receive any gen9 rps interrupts to GEN>9 platforms as suggested by Paulo. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-19drm/i915: Don't store panning coordinates as 16.16 fixed pointMatt Roper
When using the universal plane interface, the source rectangle coordinates define the panning offset for the primary plane, which needs to be stored in crtc->{x,y}. The original universal plane code negelected to set these panning offset fields, which was partially remedied in: commit ccc759dc2a0214fd8b65ed4ebe78050874a67f94 Author: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Date: Wed Sep 24 14:20:22 2014 -0300 drm/i915: Merge of visible and !visible paths for primary planes However the plane source coordinates are provided in 16.16 fixed point format and the above commit forgot to convert back to integer coordinates before saving the values. When we replace intel_pipe_set_base() with plane->funcs->update_plane() in a future patch, this bug becomes visible via the set_config entrypoint as well as update_plane. Cc: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Testcase: igt/kms_plane Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-19drm/i915/ddi: set has_infoframe flag on DDI too v2Jesse Barnes
Just like we do in the HDMI code, set the infoframe flag if we detect that infoframes are enabled. v2: check for actual infoframe status as in hdmi code (Daniel) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-19drm/i915: Extend pcode mailbox interfaceTom O'Rourke
In sandybridge_pcode_read and sandybridge_pcode_write, extend the mbox parameter from u8 to u32. On Haswell and Sandybridge, bits 7:0 encode the mailbox command and bits 28:8 are used for address control for specific commands. Based on suggestion from Ville Syrjälä. Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-19drm/i915: Tune down sink crc timeout dmesg outputDaniel Vetter
For whatever reasons this can happen. For real testcases the test will notice the -EIO and fall over, but we also have some testcases that just read all debugfs files. And that shouldn't cause dmesg spam. So tune it down a bit so that we still have the information for debugging. And change the errno so that real testcases can easily differentiate. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84890 Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
2014-11-19drm/i915: Don't continually defer the hangcheckChris Wilson
With multiple rings, we may continue to render on the blitter whilst executing an infinite shader on the render ring. As we currently, rearm the timer with each execbuf, in this scenario the hangcheck will never fire and we will never detect the lockup on the render ring. Instead, only arm the timer once per hangcheck, so that hangcheck runs more frequently. v2: Rearrange code to avoid triggering a BUG_ON in add_timer from softirq context. Testcase: igt/gem_reset_stats/defer-hangcheck* Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86225 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-18drm/i915: Don't print header in error state for non-existing CSDaniel Vetter
This goes back to commit 362b8af7ad1d91266aa4931e62be45c1e5cf753b Author: Ben Widawsky <benjamin.widawsky@intel.com> Date: Thu Jan 30 00:19:38 2014 -0800 drm/i915: Move per ring error state to ring_error Spotted while reading error states. Cc: Ben Widawsky <benjamin.widawsky@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
2014-11-18amdkfd: init aperture once per processAlexey Skidanov
Since the user space may call open() more that once from the same process, the aperture initialization should be moved from kfd_open() Signed-off-by: Alexey Skidanov <Alexey.Skidanov@amd.com> Reviewed-by: Oded Gabbay <oded.gabbay@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>
2014-11-18drm/i915/audio: fix monitor presence indication after disableJani Nikula
Indicate the monitor has been disconnected on disable. The regression has been introduced in commit 5fad84a7530f8e7664cdc6f490cb90653fed1266 Author: Jani Nikula <jani.nikula@intel.com> Date: Tue Nov 4 10:30:23 2014 +0200 drm/i915: rewrite hsw/bdw audio codec enable/disable sequences Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86424 Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-18drm/i915/ddi: add break in DDI mode select switchJesse Barnes
The lack of a break here wasn't for falling through to some other important code, so made me do a double take. Add a break just to make things a little less confusing. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-18drm/i915: Drop return value from lrc_setup_hardware_status_pageDaniel Vetter
kmap never fails. Spotted-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Arun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
2014-11-17drm/i915: Propagate invalid setcrtc cloning errors back to userspaceMatt Roper
When invalid cloning configurations were detected during modeset, we never copied the error code into the return value variable, leading us to return 0 (success) to userspace. This regression has been introduced in commit 50f5275698df4490046cc5b4ed2018abb642a803 Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Fri Nov 7 13:11:00 2014 -0800 drm/i915: use compute_config in set_config v4 Testcase: igt/kms_setmode Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86226 Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-17drm/i915/skl: Use the pipe config DPLL tracking to query the link clockDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-17drm/i915/skl: Set the eDP link rate on DPLL0Damien Lespiau
On SKL DPLL0 is used to derive CDCLK but can also be used to drive an eDP port (as long as we don't want SSC). DPLL0 is special enough to not be handled by the shared DPLL framework (drives CDCLK, not supposed to enable the HDMI mode), So we need to compute the configuration separately from the other DPLLs. Note that we don't need to reprogram DPLL0 (which would mean bringing down CDCLK) to support the various eDP 1.3 link rates as they all share the same VCO (8100). Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-17drm/i915: Add PSR docbookRodrigo Vivi
Let's document PSR a bit. No functional changes. v2: Add actual DocBook entry and accept Daniel's improvements. Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-17drm/i915: Introduce intel_psr.cRodrigo Vivi
No functional changes. Just cleaning and reorganizing it. v2: Rebase it puting it to begin of psr rework. This helps to blame easily at least latest changes. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-17drm/i915: Make dp aux pack/unpack public outside intel_dp.cRodrigo Vivi
No functional change. Just making it public for use outside intel_dp.c Allowing split psr functions. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-17drm/i915: Drop WaRsForcewakeWaitTC0:vlvVille Syrjälä
GEN6_GT_THREAD_STATUS_REG doesn't seem to exist on VLV. Reads just give 0x0 no matter what the state of the render and media wells. There was also some hint in the Gunit HAS that thread status not being needed on VLV, and hence dropped when bringing stuff over from the IVB design. Not really a definite comment about the specific register itself though. Also the w/a itself is no longer listed for VLV in the database. It was there some time ago in the past, but I guess someone figured out the mistake and dropped it. So let's just drop it from the code as well. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Deepak S<deepak.s@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-17drm/i915: Drop the HSW special case from __gen6_gt_wait_for_thread_c0()Ville Syrjälä
Bits [18:16] of GEN6_GT_THREAD_STATUS_REG have always had the same meaning since SNB. So treating them as something special for HSW doesn't make sense to me. Also the bits *seem* to work exactly the same way on IVB, HSW GT2 and HSW GT3. At least intel_reg_read gives the identical results on all platforms with and without forcewake. Also the HSW PM guide rev 0.99 (ww05 2013) doesn't say anything about those bits. It just says to poll for bits [2:0]. As does the more recent BDW PM guide. So just drop the HSW special case and treat all platforms the same way. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Deepak S<deepak.s@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-17drm/i915/skl: Remove spurious warn in get_ddi_pll()Damien Lespiau
When reading out a DDI config that uses a PLL that is not part of the shared_dpll scheme (DPLL0), it's totally normal to end up in the default: case of that switch. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-17drm/i915: Change CHV SKU400 GPU freq divider to 10Ville Syrjälä
According to "Cherryview_GFXclocks_y14w36d1.xlsx" the GPU frequency divider should be 10 in when the CZ clock is 400 MHz. Change the code to agree so that we report the correct frequencies. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Deepak S<deepak.s@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-17drm/i915: Add missing newline to 'DDR speed' debug messagesVille Syrjälä
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Deepak S<deepak.s@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-17drm/i915: Refactor vlv/chv GPU frequency divider setupVille Syrjälä
The divider used in the GPU frequency calculations is compatible between vlv and chv. vlv just wants doubled values compared to chv. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Deepak S<deepak.s@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-17drm/i915: Improve PCBR debug informationVille Syrjälä
Always print the final PCBR register value on both vlv and chv, and also tell us whether the BIOS was a good citizen or not. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Deepak S<deepak.s@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-17drm/i915: Warn if GPLL isn't used on vlv/chvVille Syrjälä
Our freq<->opcode conversions assume that GPLL is always used. Apparently that should be the case always, but let's scream if we ever encounter something different. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Deepak S<deepak.s@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-17drm/i915: Add a name for the Punit GPLLENABLE bitVille Syrjälä
Remove the magic number for the GPLLENABLE bit by adding a name for it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Deepak S<deepak.s@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-17drm/i915: Silence valleyview_set_rps()Ville Syrjälä
Even with the rps debug messages signficantly recuced by commit 67956867aa07c59d6d83628bbc9ee4bd9799a1e1 Author: Ville Syrjälä <ville.syrjala@linux.intel.com> Date: Tue Sep 2 15:12:17 2014 +0300 drm/i915: Don't spam dmesg with rps messages on vlv/chv we still get an inordinate amount of spam from this. Just kill the debug print. If someone wants to observe it they can just use the tracepoint. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Deepak S<deepak.s@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-17drm/i915: Kick fbdev before vgaconDaniel Vetter
It's magic, but it seems to work. This fixes a regression introduced in commit 1bb9e632a0aeee1121e652ee4dc80e5e6f14bcd2 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Tue Jul 8 10:02:43 2014 +0200 drm/i915: Only unbind vgacon, not other console drivers My best guess is that the vga fbdev driver falls over if we rip out parts of vgacon. Hooray. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82439 Cc: stable@vger.kernel.org (v3.16+) Reported-and-tested-by: Lv Zheng <lv.zheng@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2014-11-17drm/i915: drop WaSetupGtModeTdRowDispatch:snbDaniel Vetter
This reverts the regressing commit 6547fbdbfff62c99e4f7b4f985ff8b3454f33b0f Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Fri Dec 14 23:38:29 2012 +0100 drm/i915: Implement WaSetupGtModeTdRowDispatch that causes GPU hangs immediately on boot. Reported-by: Leo Wolf <jclw@ymail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79996 Cc: stable@vger.kernel.org (v3.8+) Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> [Jani: amended the commit message slightly.] Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2014-11-17drm/i915: Reinit display irqs and hpd from chv pipe-a power wellVille Syrjälä
On chv the pipe-a power well is the new disp2d well, and it kills pretty much everything in the display block. So we need to do the the same dance that vlv does wrt. display irqs and hpd when the power well goes up or down. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-17Merge branch 'msm-next' of git://people.freedesktop.org/~robclark/linux into ↵Dave Airlie
drm-next Main pull for 3.19. I may have another pull in a few days with some mdp5 bits (and hopefully mdp5 atomic), but I figured there was no need to hold up what we have already. Main highlights so far: 1) a4xx gpu support (userspace gallium bits on mesa master) 2) mdp4/hdmi/core bits for atomic helpers. Still missing mdp5 conversion, main hold up there is current hard-coded mixer setup isn't clever enough to deal with disabling primary plane while crtc active. 3) various other misc cleanup/fixes/etc.. * 'msm-next' of git://people.freedesktop.org/~robclark/linux: (21 commits) drm/msm: a4xx support for msm-drm drm/msm: Handle register offset differences between a3xx and a4xx drm/msm: small mmap offset cleanups drm/msm/mdp4: atomic drm/msm/hdmi: atomic drm/msm: atomic core bits drm/msm: bit of fb error checking drm/msm: fb prepare/cleanup drm/msm: remove unused compile-test stub drm/msm: small fence cleanup drm/msm/mdp5: drop attached planes table drm/msm/mdp4: drop attached planes table drm/msm/mdp4: don't care about fb in crtc drm/msm/mdp5: drop private primary ptr drm/msm/mdp4: drop private primary ptr drm/msm: Fix fbdev for 16- and 24-bit modes. drm/msm: Allow exported dma-bufs to be mapped drm/msm/hdmi: refactor bind/init drm/msm: update generated headers drm/msm/adreno: slight init order cleanup ...
2014-11-16drm/msm: a4xx support for msm-drmAravind Ganesan
Added a4xx GPU support. Signed-off-by: Aravind Ganesan <aravindg@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm: Handle register offset differences between a3xx and a4xxAravind Ganesan
Register offsets have changed between a3xx and a4xx GPUs. To be able access these registers in common code, we create a lookup table, and set of read-write APIs to access the register through the lookup table. Signed-off-by: Aravind Ganesan <aravindg@codeaurora.org> [robclark: remove REG_ADRENO_UNDEFINED, just use zero, and minor tweaks for latest generated headers] Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm: small mmap offset cleanupsRob Clark
Use pre-computed iova when unmapping, to reduce the places we assume iova and mmap offset are (at the moment) the same. And get rid of an extra drm_gem_free_mmap_offset() call (since it is already called from drm_gem_object_release()) Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm/mdp4: atomicRob Clark
Convert mdp4 display controller backend to atomic helpers. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm/hdmi: atomicRob Clark
Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm: atomic core bitsRob Clark
The core parts for async commit. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm: bit of fb error checkingRob Clark
It's a problem that can't happen yet, since we don't support any multi-planar formats yet. But let's avoid nasty surprises when the time comes. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm: fb prepare/cleanupRob Clark
Atomic wants to split the prepare/pin from where we actually program the scanout address (so that any part that can fail is done synchronously). Add some fb/gem apis to make this easier to use from the kms parts. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm: remove unused compile-test stubRob Clark
Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm: small fence cleanupRob Clark
Give ourselves a way to wait for certain fence #.. makes it easier to wait on a set of bo's, which we'll need for atomic. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm/mdp5: drop attached planes tableRob Clark
Simplify things a bit for atomic, gets rid of some bookkeeping, and makes the code cleaner. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm/mdp4: drop attached planes tableRob Clark
Simplify things a bit for atomic, gets rid of some bookkeeping, and makes the code cleaner. TODO move iterator macro somewhere common. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm/mdp4: don't care about fb in crtcRob Clark
Since we are configuring things via MDP4_PIPE regs in the plane, it seems like setting the dimensions of the primary plane on the OVLP/DMA regs in crtc is unnecessary. This will make life easier when we want to do a nofb modeset. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm/mdp5: drop private primary ptrRob Clark
Since primary-plane support in core, we can just use crtc->primary. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm/mdp4: drop private primary ptrRob Clark
Since primary-plane support in core, we can just use crtc->primary. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm: Fix fbdev for 16- and 24-bit modes.Daniel Thompson
Currently forcing the video mode from the kernel command line (for example video=HDMI-A-1:1280x720-16@60) does not correctly set the number of bits per pixel. This is due to a rather aggressive override in msm_fbdev_create(). This is a particular problem for Android bring up because the software EGL fallbacks don't support 32bpp. Since the overrides are actually the default values anyway then this problem can be trivially fixed by removing the overrides completely. Change was tested by dd'ing a test image to /dev/fb0 with no video= (still 32bpp), video=1920x1080-32@60, video=1920x1080-24@60 and video=1920x1080-16@60 . Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Cc: David Airlie <airlied@linux.ie> Cc: Rob Clark <robdclark@gmail.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm: Allow exported dma-bufs to be mappedDaniel Thompson
Currently msm does not implement gem_prime_mmap. Without this it is not possible to draw onto a dma-buf from userspace (making its very hard to implement the Android rendering model). Fixing this is just a matter of adding a little boilerplate. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm/hdmi: refactor bind/initRob Clark
Split up hdmi_init() into hdmi_init() (done at hdmi sub-device bind/probe time) and hdmi_modeset_init() done from master driver's modeset_init(). Anything that can fail due to dependencies on other drivers which may be missing or not probed yet should go in hdmi_init(), so that devm error/cleanup paths work properly. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm: update generated headersRob Clark
Signed-off-by: Rob Clark <robdclark@gmail.com>
generated by cgit v1.2.3 (git 2.46.0) at 2025-07-24 00:30:24 +0000