From d792b1e94dfad4bce0acd4ac03d361b0038dc8d7 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 26 Sep 2012 18:02:48 +0200 Subject: arm: mvebu: add L2 cache support Signed-off-by: Gregory CLEMENT Tested-and-reviewed-by: Yehuda Yitschak Tested-and-reviewed-by: Lior Amsalem Acked-by: Arnd Bergmann Cc: Jason Cooper Cc: Andrew Lunn Cc: Arnd Bergmann Cc: Olof Johansson Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/Kconfig | 1 + arch/arm/mach-mvebu/irq-armada-370-xp.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index c934e1d4933d..440b13ef1fed 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -22,6 +22,7 @@ config MACH_ARMADA_370_XP bool select ARMADA_370_XP_TIMER select HAVE_SMP + select CACHE_L2X0 select CPU_PJ4B config MACH_ARMADA_370 diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c index 549b6846f940..8e3fb082c3c6 100644 --- a/arch/arm/mach-mvebu/irq-armada-370-xp.c +++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c @@ -25,6 +25,7 @@ #include #include #include +#include /* Interrupt Controller Registers Map */ #define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48) @@ -210,4 +211,7 @@ static const struct of_device_id mpic_of_match[] __initconst = { void __init armada_370_xp_init_irq(void) { of_irq_init(mpic_of_match); +#ifdef CONFIG_CACHE_L2X0 + l2x0_of_init(0, ~0UL); +#endif } -- cgit v1.2.3 From 2f96fbb7d851740d0594a6b74142083d51483ab5 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 26 Sep 2012 18:02:49 +0200 Subject: arm: mvebu: add Aurora L2 Cache Controller to the DT Signed-off-by: Gregory CLEMENT Signed-off-by: Yehuda Yitschak Tested-and-reviewed-by: Yehuda Yitschak Tested-and-reviewed-by: Lior Amsalem Acked-by: Arnd Bergmann Cc: Jason Cooper Cc: Andrew Lunn Cc: Arnd Bergmann Cc: Olof Johansson Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370.dtsi | 6 ++++++ arch/arm/boot/dts/armada-xp.dtsi | 7 +++++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 7fbac28b01f3..636cf7d4009e 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -20,6 +20,12 @@ / { model = "Marvell Armada 370 family SoC"; compatible = "marvell,armada370", "marvell,armada-370-xp"; + L2: l2-cache { + compatible = "marvell,aurora-outer-cache"; + reg = <0xd0008000 0x1000>; + cache-id-part = <0x100>; + wt-override; + }; aliases { gpio0 = &gpio0; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 45a567c2e9ba..367aa3f94912 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -22,6 +22,13 @@ model = "Marvell Armada XP family SoC"; compatible = "marvell,armadaxp", "marvell,armada-370-xp"; + L2: l2-cache { + compatible = "marvell,aurora-system-cache"; + reg = <0xd0008000 0x1000>; + cache-id-part = <0x100>; + wt-override; + }; + mpic: interrupt-controller@d0020000 { reg = <0xd0020a00 0x1d0>, <0xd0021070 0x58>; -- cgit v1.2.3 From 3ee11aef75db51c69cb8cb91dd01afb28036f1b5 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 26 Sep 2012 18:02:50 +0200 Subject: arm: l2x0: add aurora related properties to OF binding Aurora is a L2 Cache Controller designed to be compatible with the L2x0 Cache Controller. L2X0 OF bindings are extended to support some specificity of Aurora (no cache id part number available through hardware, always write through mode, choice between outer cache and system cache). Signed-off-by: Gregory CLEMENT Signed-off-by: Yehuda Yitschak Tested-and-reviewed-by: Lior Amsalem Acked-by: Arnd Bergmann Cc: Grant Likely Cc: Rob Herring Cc: Russell King Cc: Barry Song <21cnbao@gmail.com> Cc: Will Deacon Cc: Arnd Bergmann Cc: Olof Johansson Signed-off-by: Jason Cooper --- Documentation/devicetree/bindings/arm/l2cc.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt index 7ca52161e7ab..76b0ee6ee9a4 100644 --- a/Documentation/devicetree/bindings/arm/l2cc.txt +++ b/Documentation/devicetree/bindings/arm/l2cc.txt @@ -10,6 +10,12 @@ Required properties: "arm,pl310-cache" "arm,l220-cache" "arm,l210-cache" + "marvell,aurora-system-cache": Marvell Controller designed to be + compatible with the ARM one, with system cache mode (meaning + maintenance operations on L1 are broadcasted to the L2 and L2 + performs the same operation). + "marvell,"aurora-outer-cache: Marvell Controller designed to be + compatible with the ARM one with outer cache mode. - cache-unified : Specifies the cache is a unified cache. - cache-level : Should be set to 2 for a level 2 cache. - reg : Physical base address and size of cache controller's memory mapped @@ -29,6 +35,9 @@ Optional properties: filter. Addresses in the filter window are directed to the M1 port. Other addresses will go to the M0 port. - interrupts : 1 combined interrupt. +- cache-id-part: cache id part number to be used if it is not present + on hardware +- wt-override: If present then L2 is forced to Write through mode Example: -- cgit v1.2.3