From 70a2b717d0a32d4702ae45880fc1370d9ce93ec0 Mon Sep 17 00:00:00 2001 From: Antoine Ténart Date: Wed, 30 Jul 2014 20:14:00 +0200 Subject: ARM: dts: berlin: add the AHCI node for the BG2Q MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The BG2Q has an AHCI SATA controller. Add the corresponding nodes (AHCI, PHY) into its device tree. Signed-off-by: Antoine Ténart Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2q.dtsi | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index 891d56b03922..c96a0135f0f8 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -364,6 +364,45 @@ }; }; + ahci: sata@e90000 { + compatible = "marvell,berlin2q-ahci", "generic-ahci"; + reg = <0xe90000 0x1000>; + interrupts = ; + clocks = <&chip CLKID_SATA>; + #address-cells = <1>; + #size-cells = <0>; + + sata0: sata-port@0 { + reg = <0>; + phys = <&sata_phy 0>; + status = "disabled"; + }; + + sata1: sata-port@1 { + reg = <1>; + phys = <&sata_phy 1>; + status = "disabled"; + }; + }; + + sata_phy: phy@e900a0 { + compatible = "marvell,berlin2q-sata-phy"; + reg = <0xe900a0 0x200>; + clocks = <&chip CLKID_SATA>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + status = "disabled"; + + sata-phy@0 { + reg = <0>; + }; + + sata-phy@1 { + reg = <1>; + }; + }; + apb@fc0000 { compatible = "simple-bus"; #address-cells = <1>; -- cgit v1.2.3 From e00ec0bd23ef0eea0c8f8e1b75936a9537ec1c33 Mon Sep 17 00:00:00 2001 From: Antoine Ténart Date: Wed, 30 Jul 2014 20:14:01 +0200 Subject: ARM: dts: berlin: enable the eSATA interface on the BG2Q DMP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The BG2Q has an AHCI SATA controller with an eSATA interface. Enable it. Only enable the first port, the BG2Q DMP does not support the second one. Signed-off-by: Antoine Ténart Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts index ea1f99b8eed6..a403b0a5ba91 100644 --- a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts +++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts @@ -49,3 +49,11 @@ ð0 { status = "okay"; }; + +&sata0 { + status = "okay"; +}; + +&sata_phy { + status = "okay"; +}; -- cgit v1.2.3 From cdaea91019056fad4f21a697038a84606a6187cc Mon Sep 17 00:00:00 2001 From: Antoine Ténart Date: Wed, 3 Sep 2014 09:48:21 +0200 Subject: Documentation: bindings: add reset bindings docs for Marvell Berlin SoCs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the reset binding documentation to the SoC binding documentation as the reset driver in Marvell Berlin SoC is part of the chip/system control registers. This patch adds the required properties to configure the reset controller. Signed-off-by: Antoine Ténart Acked-by: Philipp Zabel Signed-off-by: Sebastian Hesselbarth --- Documentation/devicetree/bindings/arm/marvell,berlin.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt index 904de5781f44..a99eb9eb14c0 100644 --- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt @@ -106,11 +106,21 @@ Required subnode-properties: - groups: a list of strings describing the group names. - function: a string describing the function used to mux the groups. +* Reset controller binding + +A reset controller is part of the chip control registers set. The chip control +node also provides the reset. The register set is not at the same offset between +Berlin SoCs. + +Required property: +- #reset-cells: must be set to 2 + Example: chip: chip-control@ea0000 { compatible = "marvell,berlin2-chip-ctrl"; #clock-cells = <1>; + #reset-cells = <2>; reg = <0xea0000 0x400>; clocks = <&refclk>, <&externaldev 0>; clock-names = "refclk", "video_ext0"; -- cgit v1.2.3 From 1e27a261281c8dd372e839f5a86b5a9656f192e8 Mon Sep 17 00:00:00 2001 From: Antoine Ténart Date: Wed, 3 Sep 2014 09:48:23 +0200 Subject: ARM: dts: berlin: add a required reset property in the chip controller node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The chip controller node now also describes the Marvell Berlin reset controller. Add the required 'reset-cells' property. Signed-off-by: Antoine Ténart Acked-by: Philipp Zabel Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2.dtsi | 1 + arch/arm/boot/dts/berlin2cd.dtsi | 1 + arch/arm/boot/dts/berlin2q.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index 9d7c810ebd0b..d7e81e124de0 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -249,6 +249,7 @@ chip: chip-control@ea0000 { compatible = "marvell,berlin2-chip-ctrl"; #clock-cells = <1>; + #reset-cells = <2>; reg = <0xea0000 0x400>; clocks = <&refclk>; clock-names = "refclk"; diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi index cc1df65da504..68f7032b4686 100644 --- a/arch/arm/boot/dts/berlin2cd.dtsi +++ b/arch/arm/boot/dts/berlin2cd.dtsi @@ -231,6 +231,7 @@ chip: chip-control@ea0000 { compatible = "marvell,berlin2cd-chip-ctrl"; #clock-cells = <1>; + #reset-cells = <2>; reg = <0xea0000 0x400>; clocks = <&refclk>; clock-names = "refclk"; diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index c96a0135f0f8..d38049f90c90 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -349,6 +349,7 @@ chip: chip-control@ea0000 { compatible = "marvell,berlin2q-chip-ctrl"; #clock-cells = <1>; + #reset-cells = <2>; reg = <0xea0000 0x400>, <0xdd0170 0x10>; clocks = <&refclk>; clock-names = "refclk"; -- cgit v1.2.3 From 5a37d07185fbaba3ead2a487f0238eb236f19102 Mon Sep 17 00:00:00 2001 From: Antoine Ténart Date: Tue, 9 Sep 2014 16:47:49 +0200 Subject: ARM: dts: berlin: enable timer 1 for sched_clock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable timer 1 to be the source for the sched_clock, allowing to have a more precise value than 1/HZ. Signed-off-by: Antoine Ténart Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2q.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index d38049f90c90..d4416ae79e62 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -255,7 +255,6 @@ reg = <0x2c14 0x14>; clocks = <&chip CLKID_CFG>; clock-names = "timer"; - status = "disabled"; }; timer2: timer@2c28 { -- cgit v1.2.3 From 297bb063b614b801bd08f3130b780c2ff2776c47 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Tue, 20 May 2014 21:57:45 +0200 Subject: ARM: dts: berlin: Add GPIO leds to Google Chromecast With GPIO support for Marvell Berlin, now add the two gpio-connected LEDs on Google Chromecast. Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2cd-google-chromecast.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts index bcd81ffc495d..0816890a5c0d 100644 --- a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts +++ b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "berlin2cd.dtsi" +#include / { model = "Google Chromecast"; @@ -24,6 +25,22 @@ device_type = "memory"; reg = <0x00000000 0x20000000>; /* 512 MB */ }; + + leds { + compatible = "gpio-leds"; + + white { + label = "white"; + gpios = <&portc 1 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + red { + label = "red"; + gpios = <&portc 2 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; }; &uart0 { status = "okay"; }; -- cgit v1.2.3 From ae01f64baad6299a537a1df4e5d42d94e806a582 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 22 Oct 2014 20:26:49 +0200 Subject: ARM: dts: berlin: Add BG2 ethernet DT nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Marvell BG2 has two fast ethernet controllers with internal PHY, add the corresponding nodes to SoC dtsi. Tested-by: Antoine Ténart Reviewed-by: Florian Fainelli Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index d7e81e124de0..bbdad9510f19 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -79,11 +79,47 @@ clocks = <&chip CLKID_TWD>; }; + eth1: ethernet@b90000 { + compatible = "marvell,pxa168-eth"; + reg = <0xb90000 0x10000>; + clocks = <&chip CLKID_GETH1>; + interrupts = ; + /* set by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + #address-cells = <1>; + #size-cells = <0>; + phy-connection-type = "mii"; + phy-handle = <ðphy1>; + status = "disabled"; + + ethphy1: ethernet-phy@0 { + reg = <0>; + }; + }; + cpu-ctrl@dd0000 { compatible = "marvell,berlin-cpu-ctrl"; reg = <0xdd0000 0x10000>; }; + eth0: ethernet@e50000 { + compatible = "marvell,pxa168-eth"; + reg = <0xe50000 0x10000>; + clocks = <&chip CLKID_GETH0>; + interrupts = ; + /* set by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + #address-cells = <1>; + #size-cells = <0>; + phy-connection-type = "mii"; + phy-handle = <ðphy0>; + status = "disabled"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + }; + apb@e80000 { compatible = "simple-bus"; #address-cells = <1>; -- cgit v1.2.3 From 631338af24b74b6610b5b124ac95053d7585fbe3 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 22 Oct 2014 20:26:50 +0200 Subject: ARM: dts: berlin: Add BG2CD ethernet DT nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Marvell BG2CD has two fast ethernet controllers with internal PHY, add the corresponding nodes to SoC dtsi. Tested-by: Antoine Ténart Reviewed-by: Florian Fainelli Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2cd.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi index 68f7032b4686..fff23aad8205 100644 --- a/arch/arm/boot/dts/berlin2cd.dtsi +++ b/arch/arm/boot/dts/berlin2cd.dtsi @@ -66,6 +66,42 @@ clocks = <&chip CLKID_TWD>; }; + eth1: ethernet@b90000 { + compatible = "marvell,pxa168-eth"; + reg = <0xb90000 0x10000>; + clocks = <&chip CLKID_GETH1>; + interrupts = ; + /* set by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + #address-cells = <1>; + #size-cells = <0>; + phy-connection-type = "mii"; + phy-handle = <ðphy1>; + status = "disabled"; + + ethphy1: ethernet-phy@0 { + reg = <0>; + }; + }; + + eth0: ethernet@e50000 { + compatible = "marvell,pxa168-eth"; + reg = <0xe50000 0x10000>; + clocks = <&chip CLKID_GETH0>; + interrupts = ; + /* set by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + #address-cells = <1>; + #size-cells = <0>; + phy-connection-type = "mii"; + phy-handle = <ðphy0>; + status = "disabled"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + }; + apb@e80000 { compatible = "simple-bus"; #address-cells = <1>; -- cgit v1.2.3 From f5799dcf2c3de418e7d1a2e24728a521d2bd08dc Mon Sep 17 00:00:00 2001 From: Antoine Ténart Date: Wed, 22 Oct 2014 20:26:51 +0200 Subject: ARM: dts: berlin: Add phy-connection-type to BG2Q Ethernet MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Internal FastEthernet PHY on BG2Q is connected via MII, add a corresponding phy-connection-type property to the Ethernet node. Tested-by: Antoine Ténart Reviewed-by: Florian Fainelli Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2q.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index d4416ae79e62..a35deb37ffb5 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -123,6 +123,7 @@ local-mac-address = [00 00 00 00 00 00]; #address-cells = <1>; #size-cells = <0>; + phy-connection-type = "mii"; phy-handle = <ðphy0>; status = "disabled"; -- cgit v1.2.3 From 60daa9f71de148cbfc33187c2ce6d3dd80cf8fa0 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 22 Oct 2014 20:26:52 +0200 Subject: ARM: dts: berlin: Enable ethernet on Sony NSZ-GS7 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Marvell Berlin BG2 based Sony NSZ-GS7 has one ethernet controller connected to rear RJ45 jack. Enable it by default. Tested-by: Antoine Ténart Reviewed-by: Florian Fainelli Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts index c72bfd468d10..27f2f0ad7562 100644 --- a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts +++ b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts @@ -26,4 +26,6 @@ }; }; +ð1 { status = "okay"; }; + &uart0 { status = "okay"; }; -- cgit v1.2.3 From 652538c4d27df714efc4dd092e6defe87c0bbeb9 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Tue, 20 May 2014 16:48:10 +0200 Subject: ARM: dts: berlin: Add SDHCI controller nodes to BG2/BG2CD Marvell Berlin BG2 has three, BG2CD just one pxav3 compatible sdhci controllers, add them to the corresponding DT SoC includes. Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2.dtsi | 34 ++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/berlin2cd.dtsi | 9 +++++++++ 2 files changed, 43 insertions(+) diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index bbdad9510f19..20e7c394a008 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -53,6 +53,35 @@ ranges = <0 0xf7000000 0x1000000>; + sdhci0: sdhci@ab0000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab0000 0x200>; + clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>; + clock-names = "io", "core"; + interrupts = ; + status = "disabled"; + }; + + sdhci1: sdhci@ab0800 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab0800 0x200>; + clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>; + clock-names = "io", "core"; + interrupts = ; + status = "disabled"; + }; + + sdhci2: sdhci@ab1000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab1000 0x200>; + interrupts = ; + clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>; + clock-names = "io", "core"; + pinctrl-0 = <&emmc_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + l2: l2-cache-controller@ac0000 { compatible = "marvell,tauros3-cache", "arm,pl310-cache"; reg = <0xac0000 0x1000>; @@ -289,6 +318,11 @@ reg = <0xea0000 0x400>; clocks = <&refclk>; clock-names = "refclk"; + + emmc_pmux: emmc-pmux { + groups = "G26"; + function = "emmc"; + }; }; apb@fc0000 { diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi index fff23aad8205..9e338ff80fd3 100644 --- a/arch/arm/boot/dts/berlin2cd.dtsi +++ b/arch/arm/boot/dts/berlin2cd.dtsi @@ -45,6 +45,15 @@ ranges = <0 0xf7000000 0x1000000>; + sdhci0: sdhci@ab0000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab0000 0x200>; + clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>; + clock-names = "io", "core"; + interrupts = ; + status = "disabled"; + }; + l2: l2-cache-controller@ac0000 { compatible = "arm,pl310-cache"; reg = <0xac0000 0x1000>; -- cgit v1.2.3 From acbcadc8505a56e7491a9944b4447e5857c6eb15 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Tue, 20 May 2014 20:30:30 +0200 Subject: ARM: dts: berlin: Enable WiFi on Google Chromecast With SDHCI for BG2CD, we can now enable the port and allow to access AzureWave WiFi/BT module on Google Chromecast. Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2cd-google-chromecast.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts index 0816890a5c0d..bdcaff7c321e 100644 --- a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts +++ b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts @@ -43,4 +43,13 @@ }; }; +/* + * AzureWave AW-NH387 (Marvell 88W8787) + * 802.11b/g/n + Bluetooth 2.1 + */ +&sdhci0 { + non-removable; + status = "okay"; +}; + &uart0 { status = "okay"; }; -- cgit v1.2.3 From e4fdc8e5821d852a933963ba56b9b2fa8f68c68f Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Thu, 28 Aug 2014 21:42:39 +0200 Subject: ARM: dts: berlin: Enable eMMC on Sony NSZ-GS7 With SDHCI for BG2, we can now enable the port and allow to access Samsung M8G2FA 8GB eMMC on Sony NSZ-GS7. Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts index 27f2f0ad7562..04f391b5c124 100644 --- a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts +++ b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts @@ -28,4 +28,11 @@ ð1 { status = "okay"; }; +/* Samsung M8G2FA 8GB eMMC */ +&sdhci2 { + non-removable; + bus-width = <8>; + status = "okay"; +}; + &uart0 { status = "okay"; }; -- cgit v1.2.3