diff options
| author | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2010-09-02 19:11:47 +0530 |
|---|---|---|
| committer | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2010-09-06 17:22:12 +0530 |
| commit | 9ab1d784b1dd29199b21c106736395ab26c5c698 (patch) | |
| tree | 117d8cff657a45d20fdc8f03681df60256ceb284 | |
| parent | 90c29472e97a7d7eb2943fb1edb4aab9ab89570c (diff) | |
omap4: pm: Mask Secure interrupt which gate lowpower statesti-2.6.35-omap4-L24.9-p4
This patch masks the Secure interrupt at wakeupgen level. This interrupt
is controlled only from secure SW and non-secure SW should be immune to it.
Additinaly the L3 error interupts are masked since they are gating the
lowpower states. This hack will be removed once the L3 error-handling
is in place
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| -rw-r--r-- | arch/arm/mach-omap2/omap4-wakeupgen.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/omap4-wakeupgen.c b/arch/arm/mach-omap2/omap4-wakeupgen.c index 91f596e5bc3b..1d9a8b09ecad 100644 --- a/arch/arm/mach-omap2/omap4-wakeupgen.c +++ b/arch/arm/mach-omap2/omap4-wakeupgen.c @@ -35,6 +35,7 @@ #define PTMSYNCREQ_EN_OFFSET 0x6D0 #define SAR_BACKUP_STATUS_OFFSET 0x500 #define SAR_BACKUP_STATUS_WAKEUPGEN 0x10 +#define SECURE_L3FW_IRQ_MASK 0xfffff8ff /* Wakeupgen Base addres */ void __iomem *wakeupgen_base; @@ -119,7 +120,7 @@ static int __wakeupgen_irq_all(unsigned int cpu, unsigned int reg) if ((cpu > NR_CPUS) || (omap_rev() == OMAP4430_REV_ES1_0)) return -EPERM; - for (reg_index = 0; reg_index < 4; reg_index++) { + for (reg_index = 1; reg_index < 4; reg_index++) { if (cpu) writel(reg, wakeupgen_base + OMAP4_WKG_ENB_A_1 + (4 * reg_index)); @@ -128,6 +129,16 @@ static int __wakeupgen_irq_all(unsigned int cpu, unsigned int reg) + (4 * reg_index)); } + /* + * Maintain the Secure and L3 interrupt state which can potentialy + * gate low power state + */ + if (cpu) + writel((reg & SECURE_L3FW_IRQ_MASK), + wakeupgen_base + OMAP4_WKG_ENB_A_1); + else + writel((reg & SECURE_L3FW_IRQ_MASK), + wakeupgen_base + OMAP4_WKG_ENB_A_0); return 0; } @@ -147,6 +158,13 @@ static int __init omap4_wakeupgen_init(void) wakeupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K); BUG_ON(!wakeupgen_base); + /* + * Disable Secure and L3 interrupts which can potentialy + * gate low power state + */ + writel(SECURE_L3FW_IRQ_MASK, wakeupgen_base + OMAP4_WKG_ENB_A_0); + writel(SECURE_L3FW_IRQ_MASK, wakeupgen_base + OMAP4_WKG_ENB_A_1); + return 0; } early_initcall(omap4_wakeupgen_init); |