diff options
| author | Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> | 2022-06-30 14:46:18 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-06-30 19:34:36 -0400 |
| commit | 0d8928a94ba18205cc7b41793af333e6731e9d76 (patch) | |
| tree | ab7cf53230014ffb3d7715d769dbff649c260e1e | |
| parent | 3db7f894549a54dd6f8dfb7fe213ede83249bb94 (diff) | |
drm/amd/display: Fix __umoddi3 undefined for 32 bit compilation
While we tried to build amdgpu on i386, we got this error:
ERROR: modpost: "__umoddi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
This commit fixes this issue by replacing the standard module operator
with div_u64_rem.
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Randy Dunlap <rdunlap@infradead.org>
Fixes: d3dfceb58de5 ("drm/amd/display: Add dependant changes for DCN32/321")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Tested-by: Randy Dunlap <rdunlap@infradead.org> # build-tested
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c index a10ec5919194..790aa2b3952c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c @@ -208,12 +208,14 @@ static uint32_t dcn32_cache_lines_for_surface(struct dc *dc, uint32_t surface_si uint32_t num_cached_bytes = 0; uint32_t remaining_size = 0; uint32_t cache_line_size = dc->caps.cache_line_size; + uint32_t remainder = 0; /* 1. Calculate surface size minus the number of bytes stored * in the first cache line (all bytes in first cache line might * not be fully used). */ - num_cached_bytes = cache_line_size - (start_address % cache_line_size); + div_u64_rem(start_address, cache_line_size, &remainder); + num_cached_bytes = cache_line_size - remainder; remaining_size = surface_size - num_cached_bytes; /* 2. Calculate number of cache lines that will be fully used with |