diff options
| author | Thomas Zimmermann <tzimmermann@suse.de> | 2025-01-17 11:29:11 +0100 |
|---|---|---|
| committer | Thomas Zimmermann <tzimmermann@suse.de> | 2025-01-22 13:52:50 +0100 |
| commit | 2eede6f1d2b1d3c36e77555f7b98ab8a45f0527c (patch) | |
| tree | 608b7b1f9ced67b6df95bc5a9386d33ade54e9d6 | |
| parent | 87478ba50a05a1f44508316ae109622e8a85adc9 (diff) | |
drm/ast: Align Gen1 DVO detection to register manual
Align variable names and register constants for TX-chip detection
to the names in the register manual.
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250117103450.28692-7-tzimmermann@suse.de
| -rw-r--r-- | drivers/gpu/drm/ast/ast_main.c | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/ast/ast_reg.h | 1 |
2 files changed, 4 insertions, 3 deletions
diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c index 50b57bc15d53..40d3b7770cf1 100644 --- a/drivers/gpu/drm/ast/ast_main.c +++ b/drivers/gpu/drm/ast/ast_main.c @@ -76,7 +76,7 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post) }; struct drm_device *dev = &ast->base; - u8 jreg, vgacrd1; + u8 vgacra3, vgacrd1; /* * Several of the listed TX chips are not explicitly supported @@ -106,8 +106,8 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post) * SIL164 when there is none. */ if (!need_post) { - jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff); - if (jreg & 0x80) + vgacra3 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff); + if (vgacra3 & AST_IO_VGACRA3_DVO_ENABLED) ast->tx_chip = AST_TX_SIL164; } } else if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) { diff --git a/drivers/gpu/drm/ast/ast_reg.h b/drivers/gpu/drm/ast/ast_reg.h index 2aadf07d135a..0745d58e5b45 100644 --- a/drivers/gpu/drm/ast/ast_reg.h +++ b/drivers/gpu/drm/ast/ast_reg.h @@ -32,6 +32,7 @@ #define AST_IO_VGACR80_PASSWORD (0xa8) #define AST_IO_VGACRA1_VGAIO_DISABLED BIT(1) #define AST_IO_VGACRA1_MMIO_ENABLED BIT(2) +#define AST_IO_VGACRA3_DVO_ENABLED BIT(7) #define AST_IO_VGACRB6_HSYNC_OFF BIT(0) #define AST_IO_VGACRB6_VSYNC_OFF BIT(1) #define AST_IO_VGACRCB_HWC_16BPP BIT(0) /* set: ARGB4444, cleared: 2bpp palette */ |