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authorAlexander Stein <alexander.stein@ew.tq-group.com>2023-12-12 08:52:52 +0100
committerRobert Foss <rfoss@kernel.org>2023-12-15 14:58:36 +0100
commit31094d3d2a5c67a9d47ea64eea38ba27335ff67f (patch)
treeb7acbf3e795d2365e9383ab2edcba08021bd7cd3
parentc3b78577462782e20c18cd30f8fe9b735746467b (diff)
drm/bridge: tc358767: Fix order of register defines
0x0510 is bigger than 0x50c, order them accordingly. No functional change intended. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Robert Foss <rfoss@kernel.org> Signed-off-by: Robert Foss <rfoss@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20231212075257.75084-3-alexander.stein@ew.tq-group.com
-rw-r--r--drivers/gpu/drm/bridge/tc358767.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index b8b29b291b72..637d38ec7628 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -116,13 +116,6 @@
/* System */
#define TC_IDREG 0x0500
#define SYSSTAT 0x0508
-#define SYSCTRL 0x0510
-#define DP0_AUDSRC_NO_INPUT (0 << 3)
-#define DP0_AUDSRC_I2S_RX (1 << 3)
-#define DP0_VIDSRC_NO_INPUT (0 << 0)
-#define DP0_VIDSRC_DSI_RX (1 << 0)
-#define DP0_VIDSRC_DPI_RX (2 << 0)
-#define DP0_VIDSRC_COLOR_BAR (3 << 0)
#define SYSRSTENB 0x050c
#define ENBI2C (1 << 0)
#define ENBLCD0 (1 << 2)
@@ -130,6 +123,13 @@
#define ENBDSIRX (1 << 4)
#define ENBREG (1 << 5)
#define ENBHDCP (1 << 8)
+#define SYSCTRL 0x0510 /* System Control Register */
+#define DP0_AUDSRC_NO_INPUT (0 << 3)
+#define DP0_AUDSRC_I2S_RX (1 << 3)
+#define DP0_VIDSRC_NO_INPUT (0 << 0)
+#define DP0_VIDSRC_DSI_RX (1 << 0)
+#define DP0_VIDSRC_DPI_RX (2 << 0)
+#define DP0_VIDSRC_COLOR_BAR (3 << 0)
#define GPIOM 0x0540
#define GPIOC 0x0544
#define GPIOO 0x0548