diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2024-04-14 13:58:54 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-05-08 15:17:06 -0400 |
| commit | 3345f7ec0d852880b176b07abe8e8c4201a346ca (patch) | |
| tree | 19934f9d30894b0a6e3750e22e2c4eebc811d0ec | |
| parent | ffd3d6e780a525a74b61b6932f440ca5a8fcb4bf (diff) | |
drm/amdgpu: add set_reg_remap callback for NBIO 7.7
This will be used to consolidate the register remap offset
configuration and fix HDP flushes on systems non-4K pages.
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c index 4df1055e640a..fb37e354a9d5 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c @@ -324,6 +324,21 @@ static void nbio_v7_7_get_clockgating_state(struct amdgpu_device *adev, *flags |= AMD_CG_SUPPORT_BIF_LS; } +#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) + +static void nbio_v7_7_set_reg_remap(struct amdgpu_device *adev) +{ + if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) { + adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; + adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; + } else { + adev->rmmio_remap.reg_offset = + SOC15_REG_OFFSET(NBIO, 0, + regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; + adev->rmmio_remap.bus_addr = 0; + } +} + const struct amdgpu_nbio_funcs nbio_v7_7_funcs = { .get_hdp_flush_req_offset = nbio_v7_7_get_hdp_flush_req_offset, .get_hdp_flush_done_offset = nbio_v7_7_get_hdp_flush_done_offset, @@ -345,4 +360,5 @@ const struct amdgpu_nbio_funcs nbio_v7_7_funcs = { .ih_control = nbio_v7_7_ih_control, .init_registers = nbio_v7_7_init_registers, .remap_hdp_registers = nbio_v7_7_remap_hdp_registers, + .set_reg_remap = nbio_v7_7_set_reg_remap, }; |