diff options
| author | José Roberto de Souza <jose.souza@intel.com> | 2021-05-24 14:48:05 -0700 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2021-05-25 10:32:07 -0700 |
| commit | 3cdef2a9f27df8d3b4f356f812732e43597ca293 (patch) | |
| tree | fba9074affd3cfc134b5f5a25744f6f0fb217ebe | |
| parent | 95f7f7d34b057b6d5b167cddd220504fc57a0d3d (diff) | |
drm/i915/display/adl_p: Disable PSR2
We are missing the implementation of some workarounds to enabled PSR2
in Alderlake P, so to avoid any CI report of issues around PSR2
disabling it until all PSR2 workarounds are implemented.
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210524214805.259692-5-jose.souza@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_psr.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index c57210862206..1b27af872ba1 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -765,6 +765,15 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } + /* + * We are missing the implementation of some workarounds to enabled PSR2 + * in Alderlake_P, until ready PSR2 should be kept disabled. + */ + if (IS_ALDERLAKE_P(dev_priv)) { + drm_dbg_kms(&dev_priv->drm, "PSR2 is missing the implementation of workarounds\n"); + return false; + } + if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { drm_dbg_kms(&dev_priv->drm, "PSR2 not supported in transcoder %s\n", |