diff options
| author | Ahmed S. Darwish <darwi@linutronix.de> | 2025-05-08 17:02:35 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2025-05-16 10:49:55 +0200 |
| commit | 4b21e71ad6cc93d39d78176de269a0dc9a318fc6 (patch) | |
| tree | 8de069b6559c3b768c940c17883e13917f28b01f | |
| parent | e7df7289f1481993c9f326aea801323a1d3d0c5f (diff) | |
x86/cacheinfo: Rename CPUID(0x2) descriptors iterator parameter
The CPUID(0x2) descriptors iterator has been renamed from:
for_each_leaf_0x2_entry()
to:
for_each_cpuid_0x2_desc()
since it iterates over CPUID(0x2) cache and TLB "descriptors", not
"entries".
In the macro's x86/cacheinfo call-site, rename the parameter denoting the
parsed descriptor at each iteration from 'entry' to 'desc'.
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: John Ogness <john.ogness@linutronix.de>
Cc: x86-cpuid@lists.linux.dev
Link: https://lore.kernel.org/r/20250508150240.172915-7-darwi@linutronix.de
| -rw-r--r-- | arch/x86/kernel/cpu/cacheinfo.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c index b6349c1792dd..adfa7e8bb865 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -381,7 +381,7 @@ static void intel_cacheinfo_done(struct cpuinfo_x86 *c, unsigned int l3, static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c) { unsigned int l1i = 0, l1d = 0, l2 = 0, l3 = 0; - const struct leaf_0x2_table *entry; + const struct leaf_0x2_table *desc; union leaf_0x2_regs regs; u8 *ptr; @@ -389,12 +389,12 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c) return; cpuid_leaf_0x2(®s); - for_each_cpuid_0x2_desc(regs, ptr, entry) { - switch (entry->c_type) { - case CACHE_L1_INST: l1i += entry->c_size; break; - case CACHE_L1_DATA: l1d += entry->c_size; break; - case CACHE_L2: l2 += entry->c_size; break; - case CACHE_L3: l3 += entry->c_size; break; + for_each_cpuid_0x2_desc(regs, ptr, desc) { + switch (desc->c_type) { + case CACHE_L1_INST: l1i += desc->c_size; break; + case CACHE_L1_DATA: l1d += desc->c_size; break; + case CACHE_L2: l2 += desc->c_size; break; + case CACHE_L3: l3 += desc->c_size; break; } } |