diff options
| author | Gregory CLEMENT <gregory.clement@bootlin.com> | 2025-05-05 14:57:58 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2025-05-20 08:43:24 +0200 |
| commit | 4cc7543eb494daae7d6282e17459e1b06eff82aa (patch) | |
| tree | f1386b59f4274a6982d4e01497c8f9df5617ebc2 | |
| parent | 3b3704261e851e25983860e4c352f1f73786f4ab (diff) | |
MIPS: SMP: Move the AP sync point before the non-parallel aware functions
When CONFIG_HOTPLUG_PARALLEL is enabled, the code executing before
cpuhp_ap_sync_alive() is executed in parallel, while after it is
serialized. The functions set_cpu_sibling_map() and set_cpu_core_map()
were not designed to be executed in parallel, so by moving the
cpuhp_ap_sync_alive() before cpuhp_ap_sync_alive(), we then ensure
they will be called serialized.
The measurement done on EyeQ5 did not show any relevant boot time
increase after applying this patch.
Fixes: 76c43eb507bc ("MIPS: SMP: Implement parallel CPU bring up for EyeQ")
Reported-by: Huacai Chen <chenhuacai@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| -rw-r--r-- | arch/mips/kernel/smp.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 1726744f2b2e..7901b59d8f60 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -374,13 +374,13 @@ asmlinkage void start_secondary(void) calibrate_delay(); cpu_data[cpu].udelay_val = loops_per_jiffy; +#ifdef CONFIG_HOTPLUG_PARALLEL + cpuhp_ap_sync_alive(); +#endif set_cpu_sibling_map(cpu); set_cpu_core_map(cpu); cpumask_set_cpu(cpu, &cpu_coherent_mask); -#ifdef CONFIG_HOTPLUG_PARALLEL - cpuhp_ap_sync_alive(); -#endif notify_cpu_starting(cpu); #ifndef CONFIG_HOTPLUG_PARALLEL |