diff options
| author | Heiko Stuebner <heiko@sntech.de> | 2024-11-13 18:21:12 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2025-01-18 12:33:30 -0800 |
| commit | 66f197785d515d3fe5257ed65e189e4ee0b9b4e3 (patch) | |
| tree | bcc90d00aa738297c18c0f995d73053122bc2eeb | |
| parent | 377be47f90e411c10440650864d72d2ecb639bd7 (diff) | |
RISC-V: define the elements of the VCSR vector CSR
The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0].
Define constants for those to access the elements in a readable way.
Acked-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Tested-by: Yangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-6-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
| -rw-r--r-- | arch/riscv/include/asm/csr.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index fe5d4eb9adea..db1d26dfaef9 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -314,6 +314,10 @@ #define CSR_STIMECMP 0x14D #define CSR_STIMECMPH 0x15D +#define VCSR_VXRM_MASK 3 +#define VCSR_VXRM_SHIFT 1 +#define VCSR_VXSAT_MASK 1 + /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ #define CSR_SISELECT 0x150 #define CSR_SIREG 0x151 |