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authorVijendar Mukunda <Vijendar.Mukunda@amd.com>2025-05-02 21:12:46 +0530
committerMark Brown <broonie@kernel.org>2025-05-03 08:16:43 +0900
commita536f3c51edb63900b3340978d38da3aabc1fb2f (patch)
tree375ffe2a0edee390fd99cc655ae9ce6504fadeba
parent169c5e444bb9cd4ae770f54157a04fdd8569508a (diff)
ASoC: SOF: amd: enable soundwire host wake irq mask
Enable SoundWire host wake interrupt mask during acp init sequence based on wake enable checks for each SoundWire manager instance for ACP7.0 & ACP7.1 platforms. Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com> Link: https://patch.msgid.link/20250502154445.3008598-8-Vijendar.Mukunda@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--sound/soc/sof/amd/acp-dsp-offset.h5
-rw-r--r--sound/soc/sof/amd/acp.c7
2 files changed, 12 insertions, 0 deletions
diff --git a/sound/soc/sof/amd/acp-dsp-offset.h b/sound/soc/sof/amd/acp-dsp-offset.h
index 414151187b44..e77554f74c20 100644
--- a/sound/soc/sof/amd/acp-dsp-offset.h
+++ b/sound/soc/sof/amd/acp-dsp-offset.h
@@ -131,4 +131,9 @@
#define ACP_SW0_EN 0x3000
#define ACP_SW1_EN 0x3C00
#define ACP70_PME_EN 0x1400
+#define ACP70_EXTERNAL_INTR_CNTL1 0x1A08
+#define ACP70_SW0_WAKE_EN 0x1458
+#define ACP70_SW1_WAKE_EN 0x1460
+#define ACP70_SDW_HOST_WAKE_MASK 0x0C00000
+
#endif
diff --git a/sound/soc/sof/amd/acp.c b/sound/soc/sof/amd/acp.c
index 2ad5fbf43c8a..d62ba4f75e4f 100644
--- a/sound/soc/sof/amd/acp.c
+++ b/sound/soc/sof/amd/acp.c
@@ -563,6 +563,7 @@ static int acp_init(struct snd_sof_dev *sdev)
{
const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
struct acp_dev_data *acp_data;
+ unsigned int sdw0_wake_en, sdw1_wake_en;
int ret;
/* power on */
@@ -591,6 +592,12 @@ static int acp_init(struct snd_sof_dev *sdev)
switch (acp_data->pci_rev) {
case ACP70_PCI_ID:
case ACP71_PCI_ID:
+ sdw0_wake_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP70_SW0_WAKE_EN);
+ sdw1_wake_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP70_SW1_WAKE_EN);
+ if (sdw0_wake_en || sdw1_wake_en)
+ snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, ACP70_EXTERNAL_INTR_CNTL1,
+ ACP70_SDW_HOST_WAKE_MASK, ACP70_SDW_HOST_WAKE_MASK);
+
snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_PME_EN, 1);
break;
}