diff options
| author | Divya Koppera <divya.koppera@microchip.com> | 2025-01-15 14:36:32 +0530 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2025-01-16 17:27:56 -0800 |
| commit | bf356a6df7992c7f4e51c51466a419a7148ab1a0 (patch) | |
| tree | 076cb0e798a5cd40b47542fd5c6443d1699cd6a2 | |
| parent | 3030e3d57ba8d0f59bd8162b3b1f3f7ee273f280 (diff) | |
net: phy: microchip_rds_ptp: Header file library changes for PEROUT
This ptp header file library changes will cover PEROUT
macros that are required to generate periodic output
from pin out
Signed-off-by: Divya Koppera <divya.koppera@microchip.com>
Link: https://patch.msgid.link/20250115090634.12941-2-divya.koppera@microchip.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
| -rw-r--r-- | drivers/net/phy/microchip_rds_ptp.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/net/phy/microchip_rds_ptp.h b/drivers/net/phy/microchip_rds_ptp.h index e95c065728b5..25af68337b94 100644 --- a/drivers/net/phy/microchip_rds_ptp.h +++ b/drivers/net/phy/microchip_rds_ptp.h @@ -130,6 +130,23 @@ #define MCHP_RDS_PTP_TSU_HARD_RESET 0xc1 #define MCHP_RDS_PTP_TSU_HARDRESET BIT(0) +#define MCHP_RDS_PTP_CLK_TRGT_SEC_HI 0x15 +#define MCHP_RDS_PTP_CLK_TRGT_SEC_LO 0x16 +#define MCHP_RDS_PTP_CLK_TRGT_NS_HI 0x17 +#define MCHP_RDS_PTP_CLK_TRGT_NS_LO 0x18 + +#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_SEC_HI 0x19 +#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_SEC_LO 0x1a +#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_NS_HI 0x1b +#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_NS_LO 0x1c + +#define MCHP_RDS_PTP_GEN_CFG 0x01 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_MASK GENMASK(11, 8) + +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_SET(value) (((value) & 0xF) << 4) +#define MCHP_RDS_PTP_GEN_CFG_RELOAD_ADD BIT(0) +#define MCHP_RDS_PTP_GEN_CFG_POLARITY BIT(1) + /* Represents 1ppm adjustment in 2^32 format with * each nsec contains 4 clock cycles in 250MHz. * The value is calculated as following: (1/1000000)/((2^-32)/4) @@ -138,6 +155,10 @@ #define MCHP_RDS_PTP_FIFO_SIZE 8 #define MCHP_RDS_PTP_MAX_ADJ 31249999 +#define MCHP_RDS_PTP_BUFFER_TIME 2 +#define MCHP_RDS_PTP_N_PIN 4 +#define MCHP_RDS_PTP_N_PEROUT 1 + #define BASE_CLK(p) ((p)->clk_base_addr) #define BASE_PORT(p) ((p)->port_base_addr) #define PTP_MMD(p) ((p)->mmd) @@ -176,6 +197,9 @@ struct mchp_rds_ptp_clock { /* Lock for phc */ struct mutex ptp_lock; u8 mmd; + int mchp_rds_ptp_event; + int event_pin; + struct ptp_pin_desc *pin_config; }; struct mchp_rds_ptp_rx_ts { |