diff options
| author | Jouni Högander <jouni.hogander@intel.com> | 2023-12-20 12:36:03 +0200 |
|---|---|---|
| committer | Jouni Högander <jouni.hogander@intel.com> | 2023-12-22 08:14:15 +0200 |
| commit | e11300a1d8e38a2311beaebdd2169a15265de103 (patch) | |
| tree | 6a684a4eabacbe32e08433aa79ce3da0f3a9c4c0 | |
| parent | da2d668480c37d43a423ff7822caba2e0c58c4ac (diff) | |
drm/i915/display: Remove intel_crtc_state->psr_vsc
There is no really need to have separate vsc for psr usage. Use
intel_crtc_state->infoframes.vsc instead.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Tested-by: Shawn Lee <shawn.c.lee@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231220103609.1384523-2-jouni.hogander@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_types.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_psr.c | 4 |
2 files changed, 2 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 3fdd8a517983..bbdc2041a990 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1218,7 +1218,6 @@ struct intel_crtc_state { bool wm_level_disabled; u32 dc3co_exitline; u16 su_y_granularity; - struct drm_dp_vsc_sdp psr_vsc; /* * Frequence the dpll for the port should run at. Differs from the diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index b6e2e70e1290..9d5dc3fb6f20 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1380,7 +1380,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state, - &crtc_state->psr_vsc); + &crtc_state->infoframes.vsc); } void intel_psr_get_config(struct intel_encoder *encoder, @@ -1652,7 +1652,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", intel_dp->psr.psr2_enabled ? "2" : "1"); - intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc); + intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->infoframes.vsc); intel_snps_phy_update_psr_power_state(dev_priv, phy, true); intel_psr_enable_sink(intel_dp); intel_psr_enable_source(intel_dp, crtc_state); |