diff options
| author | Vinod Govindapillai <vinod.govindapillai@intel.com> | 2023-03-23 13:44:26 +0200 |
|---|---|---|
| committer | Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> | 2023-03-27 15:58:28 +0300 |
| commit | fd6435ea32d9243d116dbf50e7f1a8b33e01262b (patch) | |
| tree | 6b8aa81fa85b30a2e74face47e22cb030bfbde61 | |
| parent | ff168b37a96736c892007730e703e74d5a23ca48 (diff) | |
drm/i915/reg: use the correct register to access SAGV block time
Wrong register address is used to read the SAG block time. Fix
the register address according to the bspec.
Bspec: 64608
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230323114426.41136-3-vinod.govindapillai@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3abfda4c7a3f..f0f7b578b726 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7740,7 +7740,7 @@ enum skl_power_gate { #define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0) #define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16) -#define MTL_LATENCY_SAGV _MMIO(0x4578b) +#define MTL_LATENCY_SAGV _MMIO(0x4578c) #define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0) #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700) |