diff options
| -rw-r--r-- | drivers/gpu/drm/arc/arcpgu_crtc.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/arc/arcpgu_crtc.c b/drivers/gpu/drm/arc/arcpgu_crtc.c index 1cf29dea931e..15a2f8e074be 100644 --- a/drivers/gpu/drm/arc/arcpgu_crtc.c +++ b/drivers/gpu/drm/arc/arcpgu_crtc.c @@ -74,10 +74,9 @@ static enum drm_mode_status arc_pgu_crtc_mode_valid(struct drm_crtc *crtc, return MODE_NOCLOCK; } -static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc *crtc) +static void arc_pgu_mode_set(struct arcpgu_drm_private *arcpgu) { - struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc); - struct drm_display_mode *m = &crtc->state->adjusted_mode; + struct drm_display_mode *m = &arcpgu->pipe.crtc.state->adjusted_mode; u32 val; arc_pgu_write(arcpgu, ARCPGU_REG_FMT, @@ -111,7 +110,7 @@ static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc *crtc) arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0); arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1); - arc_pgu_set_pxl_fmt(crtc); + arc_pgu_set_pxl_fmt(&arcpgu->pipe.crtc); clk_set_rate(arcpgu->clk, m->crtc_clock * 1000); } @@ -121,6 +120,8 @@ static void arc_pgu_crtc_atomic_enable(struct drm_crtc *crtc, { struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc); + arc_pgu_mode_set(arcpgu); + clk_prepare_enable(arcpgu->clk); arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) | @@ -140,7 +141,6 @@ static void arc_pgu_crtc_atomic_disable(struct drm_crtc *crtc, static const struct drm_crtc_helper_funcs arc_pgu_crtc_helper_funcs = { .mode_valid = arc_pgu_crtc_mode_valid, - .mode_set_nofb = arc_pgu_crtc_mode_set_nofb, .atomic_enable = arc_pgu_crtc_atomic_enable, .atomic_disable = arc_pgu_crtc_atomic_disable, }; |