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path: root/drivers/irqchip/irq-sifive-plic.c
AgeCommit message (Expand)Author
2022-08-06Merge tag 'riscv-for-linus-5.20-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds
2022-07-19riscv: cpu: Add 64bit hartid support on RV64Sunil V L
2022-07-10irqchip/sifive-plic: Separate the enable and mask operationsSamuel Holland
2022-07-10irqchip/sifive-plic: Make better use of the effective affinity maskSamuel Holland
2022-07-01irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handlingSamuel Holland
2022-07-01irqchip/sifive-plic: Add support for Renesas RZ/Five SoCLad Prabhakar
2022-03-14Merge tag 'irqchip-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/maz...Thomas Gleixner
2022-03-02irqchip/sifive-plic: Disable S-mode IRQs if running in M-modeNiklas Cassel
2022-03-02irqchip/sifive-plic: Improve naming scheme for per context offsetsNiklas Cassel
2022-02-02irqchip/sifive-plic: Add missing thead,c900-plic match stringGuo Ren
2021-11-12irqchip/sifive-plic: Fixup EOI failed when maskedGuo Ren
2021-06-10irqchip: Bulk conversion to generic_handle_domain_irq()Marc Zyngier
2021-04-07irqchip/sifive-plic: Mark two global variables __ro_after_initJisheng Zhang
2020-11-01irqchip/sifive-plic: Fix chip_data access within a hierarchyGreentime Hu
2020-10-25irqchip/sifive-plic: Fix broken irq_set_affinity() callbackGreentime Hu
2020-06-09irqchip: RISC-V per-HART local interrupt controller driverAnup Patel
2020-06-09RISC-V: Rename and move plic_find_hart_id() to arch directoryAnup Patel
2020-05-25irqchip/sifive-plic: Improve boot prints for multiple PLIC instancesAnup Patel
2020-05-25irqchip/sifive-plic: Setup cpuhp once after boot CPU handler is presentAnup Patel
2020-05-25irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map()Anup Patel
2020-05-18irqchip/sifive-plic: Remove incorrect requirement about number of irq contextsWesley W. Terpstra
2020-04-17irqchip/sifive-plic: Fix maximum priority threshold valueAtish Patra
2020-03-16irqchip/sifive-plic: Add support for multiple PLICsAtish Patra
2020-03-16irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offlineAtish Patra
2020-01-24Merge tag 'irqchip-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/...irq-core-2020-01-28Thomas Gleixner
2020-01-20irqchip/sifive-plic: Support irq domain hierarchyYash Shah
2020-01-04riscv: prefix IRQ_ macro names with an RV_ namespacePaul Walmsley
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig
2019-10-25Merge tag 'irqchip-fixes-5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/...Thomas Gleixner
2019-10-25irqchip/sifive-plic: Skip contexts except supervisor in plic_init()Alan Mikhak
2019-10-14Merge tag 'irqchip-fixes-5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/...Thomas Gleixner
2019-09-18irqchip/sifive-plic: Switch to fasteoi flowMarc Zyngier
2019-09-05irqchip/sifive-plic: set max threshold for ignored handlersChristoph Hellwig
2019-02-21irqchip/sifive-plic: Implement irq_set_affinity() for SMP hostAnup Patel
2019-02-21irqchip/sifive-plic: Differentiate between PLIC handler and contextAnup Patel
2019-02-21irqchip/sifive-plic: Add warning in plic_init() if handler already presentAnup Patel
2019-02-21irqchip/sifive-plic: Pre-compute context hart base and enable baseAnup Patel
2019-02-14irqchip/irq-sifive-plic: Check and continue in case of an invalid cpuid.Atish Patra
2018-10-22RISC-V: Use Linux logical CPU number instead of hartidAtish Patra
2018-10-22RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartidPalmer Dabbelt
2018-08-13irqchip: add a SiFive PLIC driverChristoph Hellwig
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