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| author | Dave Airlie <airlied@redhat.com> | 2019-06-27 12:33:56 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2019-06-27 12:33:57 +1000 |
| commit | 14808a12bdbdc21143eba70ea07830197b3a04ff (patch) | |
| tree | 41ffee477c66169fd8697b5cf57821813daf4dd8 /drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | |
| parent | b22342ea07e6b9d867c39c84d3d774add88079c1 (diff) | |
| parent | a201b6ac20ff99e1c4b606f54874a20694e3b0c4 (diff) | |
Merge tag 'drm-next-5.3-2019-06-25' of git://people.freedesktop.org/~agd5f/linux into drm-next
drm-next-5.3-2019-06-25:
Merge drm-next
amdgpu:
- SR-IOV L1 policy fixes
- Removed no longer needed vram_page_split module parameter
- Add module parameter to override default ABM level
- Gamma fixes
- No need to check return values for debugfs
- Improve HMM error handling
- Avoid possible OOM situations when lots of thread are submitting with
memory contention
- Improve hw i2c access abritration
- DSC (Display Stream Compression) support in DC
- Initial navi10 support
* DC support
* GFX/Compute support
* SDMA support
* Power Management support
* VCN support
- Static checker fixes
- Misc cleanups
- fix long udelay on arm
amdkfd:
- Implement priority controls for gfx9
- Enable VEGAM
- Rework mqd allocation and init
- Circular locking fix
- Fix SDMA queue allocation race condition
- No need to check return values for debugfs
- Add proc style process information
- Initial navi10 support
radeon:
- No need to check return values for debugfs
UAPI changes:
- GDDR6 added to vram type query
- New Navi10 details added gpu info query
- Navi family added to asic family query
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190625195520.3817-1-alexander.deucher@amd.com
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 15 |
1 files changed, 6 insertions, 9 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c index 31030f86be86..235548c0b41f 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c @@ -451,19 +451,16 @@ void xgpu_ai_mailbox_put_irq(struct amdgpu_device *adev) static void xgpu_ai_init_reg_access_mode(struct amdgpu_device *adev) { - uint32_t rlc_fw_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6); - uint32_t sos_fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); - adev->virt.reg_access_mode = AMDGPU_VIRT_REG_ACCESS_LEGACY; - if (rlc_fw_ver >= 0x5d) - adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_RLC; + /* Enable L1 security reg access mode by defaul, as non-security VF + * will no longer be supported. + */ + adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_RLC; - if (sos_fw_ver >= 0x80455) - adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH; + adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH; - if (sos_fw_ver >= 0x8045b) - adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_SKIP_SEETING; + adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_SKIP_SEETING; } const struct amdgpu_virt_ops xgpu_ai_virt_ops = { |