Merge tag 'drm-next-5.3-2019-06-25' of git://people.freedesktop.org/~agd5f/linux into drm-next

drm-next-5.3-2019-06-25:

Merge drm-next

amdgpu:
- SR-IOV L1 policy fixes
- Removed no longer needed vram_page_split module parameter
- Add module parameter to override default ABM level
- Gamma fixes
- No need to check return values for debugfs
- Improve HMM error handling
- Avoid possible OOM situations when lots of thread are submitting with
  memory contention
- Improve hw i2c access abritration
- DSC (Display Stream Compression) support in DC
- Initial navi10 support
  * DC support
  * GFX/Compute support
  * SDMA support
  * Power Management support
  * VCN support
- Static checker fixes
- Misc cleanups
- fix long udelay on arm

amdkfd:
- Implement priority controls for gfx9
- Enable VEGAM
- Rework mqd allocation and init
- Circular locking fix
- Fix SDMA queue allocation race condition
- No need to check return values for debugfs
- Add proc style process information
- Initial navi10 support

radeon:
- No need to check return values for debugfs

UAPI changes:
- GDDR6 added to vram type query
- New Navi10 details added gpu info query
- Navi family added to asic family query

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190625195520.3817-1-alexander.deucher@amd.com

1 files changed, 6 insertions, 12 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index b769995c3029..87152d8ef0df 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -275,15 +275,6 @@ static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
 	return true;
 }
 
-struct soc15_allowed_register_entry {
-	uint32_t hwip;
-	uint32_t inst;
-	uint32_t seg;
-	uint32_t reg_offset;
-	bool grbm_indexed;
-};
-
-
 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
 	{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 	{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
@@ -388,7 +379,7 @@ void soc15_program_register_sequence(struct amdgpu_device *adev,
 		} else {
 			tmp = RREG32(reg);
 			tmp &= ~(entry->and_mask);
-			tmp |= entry->or_mask;
+			tmp |= (entry->or_mask & entry->and_mask);
 		}
 
 		if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
@@ -722,8 +713,8 @@ static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 	/* This reports 0 on APUs, so return to avoid writing/reading registers
 	 * that may or may not be different from their GPU counterparts
 	 */
-	 if (adev->flags & AMD_IS_APU)
-		 return;
+	if (adev->flags & AMD_IS_APU)
+		return;
 
 	/* Set the 2 events that we wish to watch, defined above */
 	/* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
@@ -1035,6 +1026,8 @@ static int soc15_common_sw_init(void *handle)
 	if (amdgpu_sriov_vf(adev))
 		xgpu_ai_mailbox_add_irq_id(adev);
 
+	adev->df_funcs->sw_init(adev);
+
 	return 0;
 }
 
@@ -1081,6 +1074,7 @@ static int soc15_common_hw_init(void *handle)
 	 */
 	if (adev->nbio_funcs->remap_hdp_registers)
 		adev->nbio_funcs->remap_hdp_registers(adev);
+
 	/* enable the doorbell aperture */
 	soc15_enable_doorbell_aperture(adev, true);
 	/* HW doorbell routing policy: doorbell writing not