diff options
| author | Jithu Joseph <jithu.joseph@intel.com> | 2023-03-21 17:33:55 -0700 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2023-03-27 16:10:20 +0200 |
| commit | d31bbdf42b46cb8dc81deb48c4bf5234dd63d939 (patch) | |
| tree | 0820b32d96501d98d78f0bcbceef3c341dcb6c55 /drivers/platform/x86/intel/ifs/ifs.h | |
| parent | c68e3d473988b9af1f39355be57befb83607d845 (diff) | |
platform/x86/intel/ifs: Introduce Array Scan test to IFS
Array BIST is a new type of core test introduced under the Intel Infield
Scan (IFS) suite of tests.
Emerald Rapids (EMR) is the first CPU to support Array BIST.
Array BIST performs tests on some portions of the core logic such as
caches and register files. These are different portions of the silicon
compared to the parts tested by the first test type
i.e Scan at Field (SAF).
Make changes in the device driver init flow to register this new test
type with the device driver framework. Each test will have its own
sysfs directory (intel_ifs_0 , intel_ifs_1) under misc hierarchy to
accommodate for the differences in test type and how they are initiated.
Upcoming patches will add actual support.
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Link: https://lore.kernel.org/r/20230322003359.213046-6-jithu.joseph@intel.com
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'drivers/platform/x86/intel/ifs/ifs.h')
| -rw-r--r-- | drivers/platform/x86/intel/ifs/ifs.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h index 55bcc70c2966..14789b156299 100644 --- a/drivers/platform/x86/intel/ifs/ifs.h +++ b/drivers/platform/x86/intel/ifs/ifs.h @@ -137,6 +137,9 @@ #define SCAN_TEST_PASS 1 #define SCAN_TEST_FAIL 2 +#define IFS_TYPE_SAF 0 +#define IFS_TYPE_ARRAY_BIST 1 + /* MSR_SCAN_HASHES_STATUS bit fields */ union ifs_scan_hashes_status { u64 data; |