diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2015-05-06 14:28:57 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-05-08 13:03:43 +0200 |
| commit | 22e02c0b4bc87c94895b1f4cb25ee705d5687cb1 (patch) | |
| tree | d48165d237c6afd2e74b6e5c0b585382cfbb9a9f | |
| parent | 813b5e6971cbf1ae7dd0298fe44e39f7f2629f8d (diff) | |
drm/i915: Add missing POSTING_READ()s to BXT dbuf enable sequence
Do a POSTING_READ() between the DBUF_CTL register write and the
udelay() to make sure we really wait after the register write has
happened.
Spotted while reviewing Damien's SKL cdclk patch which had the
POSTING_READ()s.
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8e21e2358c0a..5c2047b6127b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5482,6 +5482,8 @@ void broxton_init_cdclk(struct drm_device *dev) broxton_set_cdclk(dev, 624000); I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); + POSTING_READ(DBUF_CTL); + udelay(10); if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) @@ -5493,6 +5495,8 @@ void broxton_uninit_cdclk(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); + POSTING_READ(DBUF_CTL); + udelay(10); if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) |