diff options
| -rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 48 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dpll_mgr.c | 5 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_drv.h | 1 |
4 files changed, 47 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index edef5e28df7b..36ed636d19bc 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1816,6 +1816,7 @@ struct drm_i915_private { unsigned int fsb_freq, mem_freq, is_ddr3; unsigned int skl_vco_freq; + unsigned int skl_preferred_vco_freq; unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq; unsigned int max_dotclk_freq; unsigned int rawclk_freq; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 9c50b9b808c4..2d8630f96556 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5185,21 +5185,34 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) return max_cdclk_freq*90/100; } +static int skl_calc_cdclk(int max_pixclk, int vco); + static void intel_update_max_cdclk(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; + int max_cdclk, vco; + + vco = dev_priv->skl_preferred_vco_freq; + WARN_ON(vco != 8100 && vco != 8640); + /* + * Use the lower (vco 8640) cdclk values as a + * first guess. skl_calc_cdclk() will correct it + * if the preferred vco is 8100 instead. + */ if (limit == SKL_DFSM_CDCLK_LIMIT_675) - dev_priv->max_cdclk_freq = 675000; + max_cdclk = 617140; else if (limit == SKL_DFSM_CDCLK_LIMIT_540) - dev_priv->max_cdclk_freq = 540000; + max_cdclk = 540000; else if (limit == SKL_DFSM_CDCLK_LIMIT_450) - dev_priv->max_cdclk_freq = 450000; + max_cdclk = 432000; else - dev_priv->max_cdclk_freq = 337500; + max_cdclk = 308570; + + dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); } else if (IS_BROXTON(dev)) { dev_priv->max_cdclk_freq = 624000; } else if (IS_BROADWELL(dev)) { @@ -5256,9 +5269,6 @@ static void intel_update_cdclk(struct drm_device *dev) */ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); - - if (dev_priv->max_cdclk_freq == 0) - intel_update_max_cdclk(dev); } /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ @@ -5507,12 +5517,24 @@ skl_dpll0_update(struct drm_i915_private *dev_priv) } } +void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco) +{ + bool changed = dev_priv->skl_preferred_vco_freq != vco; + + dev_priv->skl_preferred_vco_freq = vco; + + if (changed) + intel_update_max_cdclk(dev_priv->dev); +} + static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) { int min_cdclk = skl_calc_cdclk(0, vco); u32 val; + WARN_ON(vco != 8100 && vco != 8640); + /* select the minimum CDCLK before enabling DPLL 0 */ val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); I915_WRITE(CDCLK_CTL, val); @@ -5548,6 +5570,9 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) DRM_ERROR("DPLL0 not locked\n"); dev_priv->skl_vco_freq = vco; + + /* We'll want to keep using the current vco from now on. */ + skl_set_preferred_cdclk_vco(dev_priv, vco); } static void @@ -5664,7 +5689,9 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv) int cdclk, vco; /* set CDCLK to the lowest frequency, Modeset follows */ - vco = 8100; + vco = dev_priv->skl_preferred_vco_freq; + if (vco == 0) + vco = 8100; cdclk = skl_calc_cdclk(0, vco); skl_set_cdclk(dev_priv, cdclk, vco); @@ -12651,6 +12678,8 @@ static int intel_modeset_checks(struct drm_atomic_state *state) if (dev_priv->display.modeset_calc_cdclk) { if (!intel_state->cdclk_pll_vco) intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq; + if (!intel_state->cdclk_pll_vco) + intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq; ret = dev_priv->display.modeset_calc_cdclk(state); if (ret < 0) @@ -14905,6 +14934,9 @@ void intel_modeset_init(struct drm_device *dev) intel_shared_dpll_init(dev); + if (dev_priv->max_cdclk_freq == 0) + intel_update_max_cdclk(dev); + /* Just disable it once at startup */ i915_disable_vga(dev); intel_setup_outputs(dev); diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index 5391ab66b64d..34ec149fde85 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -1635,6 +1635,11 @@ static void intel_ddi_pll_init(struct drm_device *dev) if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { if (skl_sanitize_cdclk(dev_priv)) DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n"); + + /* We'll want to keep using the current vco from now on */ + if (dev_priv->skl_vco_freq != 0) + skl_set_preferred_cdclk_vco(dev_priv, + dev_priv->skl_vco_freq); } else if (!IS_BROXTON(dev_priv)) { /* * The LCPLL register should be turned on by the BIOS. For now diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 8e8ce9884ce6..2bee217e6ae5 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1143,6 +1143,7 @@ void i915_audio_component_init(struct drm_i915_private *dev_priv); void i915_audio_component_cleanup(struct drm_i915_private *dev_priv); /* intel_display.c */ +void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco); void intel_update_rawclk(struct drm_i915_private *dev_priv); int vlv_get_cck_clock(struct drm_i915_private *dev_priv, const char *name, u32 reg, int ref_freq); |