summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/intel_display.c
AgeCommit message (Collapse)Author
2013-08-11drm/i915: make SDVO TV-out work for multifunction devicesDaniel Vetter
commit 09ede5414f0215461c933032630bf9c3a61a8ba3 upstream. We need to track this correctly. While at it shovel the boolean to track whether the sdvo is in tv mode or not into pipe_config. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36997 Tested-by: Pierre Assal <pierre.assal@verint.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63609 Tested-by: cancan,feng <cancan.feng@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-08-04drm/i915: quirk no PCH_PWM_ENABLE for Dell XPS13 backlightKamal Mostafa
commit e85843bec6c2ea7c10ec61238396891cc2b753a9 upstream. BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=47941 BugLink: https://bugs.launchpad.net/bugs/1163720 BugLink: https://bugs.launchpad.net/bugs/1162026 Some machines suffer from non-functional backlight controls if BLM_PCH_PWM_ENABLE is set, so provide a quirk to avoid doing so. Apply this quirk to Dell XPS 13 models. Tested-by: Eric Griffith <EGriffith92@gmail.com> Tested-by: Kent Baxley <kent.baxley@canonical.com> Signed-off-by: Kamal Mostafa <kamal@canonical.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-08-04drm/i915: Fix dereferencing invalid connectors in is_crtc_connector_off()Chris Wilson
commit 2e57f47d317dd035b18634b0c602272529368fcc upstream. In commit e3de42b68478a8c95dd27520e9adead2af9477a5 Author: Imre Deak <imre.deak@intel.com> Date: Fri May 3 19:44:07 2013 +0200 drm/i915: force full modeset if the connector is in DPMS OFF mode a new function was added that walked over the set of connectors to see if any of the currently associated CRTC was switched off. This function walked an array of connectors, rather than the array of pointers to connectors contained in the drm_mode_set - i.e. it was dereferencing far past the end of the first connector. This only becomes an issue if we attempt to use a clone mode (i.e. more than one connector per CRTC) such that set->num_connectors > 1. Reported-by: Timo Aaltonen <tjaalton@ubuntu.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65927 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Imre Deak <imre.deak@intel.com> Cc: Egbert Eich <eich@suse.de> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-06-03drm/i915: Quirk the pipe A quirk in the modeset state checkerDaniel Vetter
If we always force the pipe A to on we can't use the hw state to decide whether it should be on. Hence quirk the quirk. The problem is that crtc->active tracks the state of the entire display pipe, i.e. including planes, encoders and all. But our hw state readout simply looks at the pipe. But with the pipe A quirk we force-enable that (together with it's pll). To fix that mismatch we have two options: - Quirk the checked state to match what our sw tracking states if the pipe A quirk is in effect. - Improve the hw state readout to not get fooled by the pipe A quirk. Since we already have similar state clamping in e.g. assert_pipe I've opted for the first variant. Also note that we don't really loose any state checking: Individual pieces of the abstract crtc pipe are checked in the enable/disable functions with the various asssert_* checks we have, and the hw state check code doesn't check anything if the pipe is off anyway. v2: Pimp commit message after discussion with Chris and only apply the quirk for the quirk if we're checking pipe A. Otherwise we'll miss state checking for pipe B on i830M ... v3: Make the code comment consistent with the improved commit message, too (Chris). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64764 Cc: stable@vger.kernel.org Cc: Chris Wilson <chris@chris-wilson.co.uk> Reported-and-Tested-by: mlsemon35@gmail.com (v1) Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-05-22drm/i915: force full modeset if the connector is in DPMS OFF modeImre Deak
Currently the driver's assumed behavior for a modeset with an attached FB is that the corresponding connector will be switched to DPMS ON mode if it happened to be in DPMS OFF (or another power save mode). This wasn't enforced though if only the FB changed, everything else (format, connector etc.) remaining the same. In this case we only set the new FB base and left the connector in the old power save mode. Fix this by forcing a full modeset whenever there is an attached FB and any affected connector is in a power save mode. V_2: Run the test for encoders in power save mode outside the the test for fb change: user space may have just disabled the encoders but left everything else in place. Make sure the connector list is not empty before running this test. Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Egbert Eich <eich@suse.de> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61642 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59834 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59339 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64178 Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> [danvet: Apply Jani's s/connector_off/is_crtc_connector_off bikeshed.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-05-21drm/i915: Propagate errors back from fb set-baseChris Wilson
Along the modesetting short cut where we skip trying to do a full modeset and instead simply update the framebuffer base registers, we failed to handle any errors reported. This regression has been introduced in commit 94352cf9a5328bb1a44288e6c2c1276695f8a356 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Thu Jul 5 22:51:56 2012 +0200 drm/i915: push crtc->fb update into pipe_set_base Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-23drm/i915: Make data/link N value power of twoVille Syrjälä
The BIOS uses power of two values for the data/link N value. Follow suit to make the Zotac DP to dual-HDMI dongle work. v2: Clean up the magic numbers and defines Change the N clamping to be a bit easier on the eye Rename intel_reduce_ratio to intel_reduce_m_n_ratio Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49402 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59810 Tested-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: fix bpc vs. bpp confusion in intel_crtc_compute_configDaniel Vetter
Oops. This regression has been introduced in commit 5d2d38ddcac991f71c19d03d95bde8e14abc0352 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Wed Mar 27 00:45:01 2013 +0100 drm/i915: clean up pipe bpp confusion Reported-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: move cpu_transcoder to the pipe configurationDaniel Vetter
For a bunch of reason we need to more accurately track this: - hw pipe state readout for Haswell needs the cpu transcoder. - We need to know the right cpu transcoder in a bunch of places in ->disable and other modeset callbacks. In the future we need to add hw state readout&check support, too. But to avoid ugly merge conflicts do the rote sed job now without any functional changes. v2: Preserve the cpu_transcoder value when overwriting crtc->config. Reported by Paulo. Cc: Paulo Zanoni <przanoni@gmail.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v1) [danvet: Removed rough whitespace that Chris spotted.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: don't intel_crt_init on any ULT machinesPaulo Zanoni
We may have DDI_BUF_CTL(PORT_A) configured with 2 lanes and still not have CRT, so just check for !IS_ULT. This problem happened on a real machine and resulted in a very ugly dmesg. Cc: stable@vger.kernel.org Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: Fixup pfit disabling for gen2/3Daniel Vetter
The recent rework of the pfit handling didn't take into account that the panel fitter is fixed to pipe B: commit 24a1f16de97c4cf0029d9acd04be06db32208726 Author: Mika Kuoppala <mika.kuoppala@linux.intel.com> Date: Fri Feb 8 16:35:37 2013 +0200 drm/i915: disable shared panel fitter for pipe Fix this up by properly computing the pipe the pfit is on. Also extract the logic into its own function, add a debug assert to check that the pipe is off (mostly just documentation) and add some debug output. If pipe A was disabled after pipe B was set up, the panel fitter will be disabled. Now most userspace doesn't do modesets in this order, which is why I couldn't ever reproduce this and why it took me so long to figure out. We really need hw state readout and check support for the pannel fitter ... Reported-by: Hans de Bruin <jmdebruin@xmsnet.nl> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Hans de Bruin <jmdebruin@xmsnet.nl> References: http://permalink.gmane.org/gmane.comp.freedesktop.xorg.drivers.intel/19049 Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: Fixup Oops in the pipe config computationDaniel Vetter
Yet again our current confusion between doing the modeset globally, but only having the new parameters for one crtc at a time. So that intel_set_mode essentially already does a global modeset: intel_modeset_affected_pipes compares the current state with where we want to go to (which is carefully set up by intel_crtc_set_config) and then goes through the modeset sequence for any crtc which needs updating. Now the issue is that the actual interface with the remaining code still only works on one crtc, and so we only pass in one fb and one mode. In intel_set_mode we also only compute one intel_crtc_config (which should be the one for the crtc we're doing a modeset on). The reason for that mismatch is twofold: - We want to eventually do all modeset as global state changes, so it's just infrastructure prep. - But even the old semantics can change more than one crtc when you e.g. move a connector from crtc A to crtc B, then both crtc A and B need to be updated. Usually that means one pipe is disabled and the other enabled. This is also the reason why the hack doesn't touch the disable_pipes mask. Now hilarity ensued in our kms config restore paths when we actually try to do a modeset on all crtcs: If the first crtc should be off and the second should be on, then the call on the first crtc will notice that the 2nd one should be switched on and so tries to compute the pipe_config. But due to a lack of passed-in fb (crtc 1 should be off after all) it only results in tears. This case is ridiculously easy to hit on gen2/3 where the lvds output is restricted to pipe B. Note that before the pipe_config bpp rework gen2/3 didn't care really about the fb->depth, so this is a regression brought to light with commit 4e53c2e010e531b4a014692199e978482d471c7e Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Wed Mar 27 00:44:58 2013 +0100 drm/i915: precompute pipe bpp before touching the hw But apparently Ajax also managed to blow up pch platforms, probably with some randomized configs, and pch platforms trip up over the lack of an fb even in the old code. So this actually goes back to the first introduction of the new modeset restore code in commit 45e2b5f640b3766da3eda48f6c35f088155c06f3 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Fri Nov 23 18:16:34 2012 +0100 drm/i915: force restore on lid open Fix this mess by now by justing shunting all the cool new global modeset logic in intel_modeset_affected_pipes. v2: Improve commit message and clean up all the comments in intel_modeset_affected_pipes - since the introduction of the modeset restore code they've been a bit outdated. Bugzill: https://bugzilla.redhat.com/show_bug.cgi?id=917725 Cc: stable@vger.kernel.org References: http://www.mail-archive.com/stable@vger.kernel.org/msg38084.html Tested-by: Richard Cochran <richardcochran@gmail.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: ensure single initialization and cleanup of backlight deviceJani Nikula
Backlight cleanup in the eDP connector destroy callback caused the backlight device to be removed on some systems that first initialized LVDS and then attempted to initialize eDP. Prevent multiple backlight initializations, and ensure backlight cleanup is only done once by moving it to modeset cleanup. A small wrinkle is the introduced asymmetry in backlight setup/cleanup. This could be solved by adding refcounting, but it seems overkill considering that there should only ever be one backlight device. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=55701 Signed-off-by: Jani Nikula <jani.nikula@intel.com> Tested-by: Peter Verthez <peter.verthez@skynet.be> Cc: stable@vger.kernel.org Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: don't touch the PF regs if the power well is downPaulo Zanoni
This solves some "unclaimed register" messages when booting the machine with eDP attached. V2: Rebase and add the comment requested by Daniel. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: add intel_using_power_wellPaulo Zanoni
It returns true if we've requested to turn the power well on and it's really on. It also returns true for all the previous gens. For now there's just one caller, but I'm going to add more. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: don't check inconsistent modeset state when force-restoringDaniel Vetter
It will be only consistent once we've restored all the crtcs. Since a bunch of other callers also want to just restore a single crtc, add a boolean to disable checking only where it doesn't make sense. Note that intel_modeset_setup_hw_state already has a call to intel_modeset_check_state at the end, so we don't reduce the amount of checking. v2: Try harder not to create a big patch (Chris). v3: Even smaller (still Chris). Also fix a trailing space. References: https://lkml.org/lkml/2013/3/16/60 Cc: Tomas Melin <tomas.melin@iki.fi> Cc: Richard Cochran <richardcochran@gmail.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@vger.kernel.org Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Tested-by: Tomas Melin <tomas.melin@iki.fi> Tested-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: update FDI mPHY setup codeDaniel Vetter
Bspec has been been updated and dropped these two changes for non-sdv LPT PCHs. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: tune down Y tiling scanout warningDaniel Vetter
Userspace can easily hit this and does since Ville added a new evil igt testcase in: commit 069e35e0fc3785faa562adcfd2dd7bbed4cb1dea Author: Ville Syrjälä <ville.syrjala@linux.intel.com> Date: Mon Mar 4 15:34:06 2013 +0200 kms_flip: Add flip-vs-bad-tiling test v2: Fix the spelling in the added comment (Chris). Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63246 Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: set CB tuning also for the reduce clockDaniel Vetter
Since the ratio is different, we also need to pass in the parameters for the reduced clock. Might or might not reduce flicker for the auto-downclocking on lvds/eDP. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: fix FP CB tuning limits for lvdsDaniel Vetter
Only on IBX should we set the limiting factor to 25 unconditionally for dual-channel mode, on CPT/PPT 25 only applies when the lvds refclock is 100MHz. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: fix lost FP_CB_TUNE setting for pch pllsDaniel Vetter
commit de13a2e3f88a4da8e85063b6de37096795079e41 Author: Paulo Zanoni <paulo.r.zanoni@intel.com> Date: Thu Sep 20 18:36:05 2012 -0300 drm/i915: extract compute_dpll from ironlake_crtc_mode_set missed the subtle adjustment of the FP1 register. Fix this up by passing a pointer around instead of the value. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-06drm/i915: Support PCH no displayBen Widawsky
GEN supports a fusing option which subtracts the PCH display (making the CPU display also useless). In this configuration MMIO which gets decoded to a certain range will hang the CPU. For us, this is sort of the equivalent of having no pipes, and we can easily modify some code to not do certain things with no pipes. v2: Moved the num pipes check up in the call chain, and removed extra checks noted by Daniel. For more details, see: http://lists.freedesktop.org/archives/intel-gfx/2013-March/025746.html v3: Drop the intel_setup_overlay check (Daniel) Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-05drm/i915: Set PIPECONF color range bit on ValleyviewVille Syrjälä
VLV has the color range selection bit in the PIPECONF register. Configure it appropriately. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> [danvet: fixup rebase issues due to slightly different baseline.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-05drm/i915: extract i9xx_set_pipeconfDaniel Vetter
Prep-patch to improve the bpc handling in a next patch. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-03drm/i915: create pipe_config->dpll for clock stateDaniel Vetter
Clock computations and handling are highly encoder specific, both in the optimal clock selection and also in which clocks to use and when sharing of clocks is possible. So the best place to do this is somewhere in the encoders, with a generic fallback for those encoders without special needs. To facility this, add a pipe_config->clocks_set boolean. This patch here is only prep work, it simply sets the computed clock values in pipe_config->dpll, and uses that data in the hw clock setting functions. Haswell code isn't touched, simply because Haswell clocks work much different and need their own infrastructure (with probably a Haswell-specific config->ddi_clock substruct). Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-03drm/i915: hw readout support for ->has_pch_encodersDaniel Vetter
Now we can ditch the checks in the Haswell disable code. v2: add support for Haswell Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-03drm/i915: add hw state readout/checking for pipe_configDaniel Vetter
We need to be able to read out the hw state code for a bunch of reasons: - Correctly disabling boot-up/resume state. - Pure paranoia. Since not all of the pipe configuration is e.g. relevant for fastboot (or at least we can allow some wiggle room in some parameters, like the clocks), we need to add a strict_checking parameter to intel_pipe_config_compare for fastboot. For now intel_pipe_config_compare should be fully paranoid and check everything that the hw state readout code supports. Which for this infrastructure code is nothing. I've gone a bit overboard with adding 3 get_pipe_config functions: The ilk version will differ with the next patch, so it's not too onerous. v2: Don't check the hw config if the pipe is off, since an enabled, but dpms off crtc will obviously have tons of difference with the hw state. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-03drm/i915: rip out superflous is_dp&is_cpu_edp trackingDaniel Vetter
The only exception left is is_cpu_edp in the haswell modeset code. We need that to assign the cpu transcoder, but we might want to move that eventually into the encoder, too. \o/-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-03drm/i915: track dp target_clock in pipe_configDaniel Vetter
We need it in the fdi m_n computation, which nicely kills almost all ugly special cases in there. It looks like we also need this to handle 12bpc hdmi correctly. Eventually it might be better to switch things around and put the target clock into adjusted_mode->clock and create a new pipe_config parameter for the port link clock. v2: Add a massive comment in the code to explain this mess. v3: s/dp_target_clock/pixel_target_clock in anticipation of the hdmi use-case. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-03drm/i915: move dp_m_n computation to dp_encoder->compute_configDaniel Vetter
We need a flag to designate dp encoders and the dp link m_n parameters in the pipe config for that. And now that the pipe bpp computations have been moved up and stored in the pipe config, too, we can do this without losing our sanity. v2: Rebased on top of Takashi Iwai's fix to (again) fix the target clock handling for eDP. Luckily the new code is sane enough and just does the right thing! v3: Move ->has_dp_encoder to this patch (Jesse). Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-03drm/i915: clear up the fdi/dp set_m_n confusionDaniel Vetter
There's a rather decent confusion going on around transcoder m_n values. So let's clarify: - All dp encoders need this, either on the pch transcoder if it's a pch port, or on the cpu transcoder/pipe if it's a cpu port. - fdi links need to have the right m_n values for the fdi link set in the cpu transcoder. To handle the pch vs transcoder stuff a bit better, extract transcoder set_m_n helpers. To make them simpler, set intel_crtc->cpu_transcoder als in ironlake_crtc_mode_set, so that gen5+ (where the cpu m_n registers are all at the same offset) can use it. Haswell modeset is decently confused about dp vs. edp vs. fdi. dp vs. edp works exactly the same as dp (since there's no pch dp any more), so use that as a check. And only set up the fdi m_n values if we really have a pch encoder present (which means we have a VGA encoder). On ilk+ we've called ironlake_set_m_n both for cpu_edp and for pch encoders. Now that dp_set_m_n handles all dp links (thanks to the pch encoder check), we can ditch the cpu_edp stuff from the fdi_set_m_n function. Since the dp_m_n values are not readily available, we need to carefully coax the edp values out of the encoder. Hence we can't (yet) kill this superflous complexity. v2: Rebase on top of the ivb fdi B/C check patch - we need to properly clear intel_crtc->fdi_lane, otherwise those checks will misfire. v3: Rebased on top of a s/IS_HASWELL/HAS_DDI/ patch from Paulo Zanoni. v4: Drop the addition of has_dp_encoder, it's in the wrong patch (Jesse). Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-03Merge tag 'v3.9-rc5' into drm-intel-next-queuedDaniel Vetter
Backmerge Linux 3.9-rc5 since I want to merge a few dp clock cleanups for -next, but they will conflict all over the place with commit 9d1a455b0ca1c2c956b4d9ab212864a8695270f1 Author: Takashi Iwai <tiwai@suse.de> Date: Mon Mar 18 11:25:36 2013 +0100 drm/i915: Use the fixed pixel clock for eDP in intel_dp_set_m_n() from -fixes. Conflicts: drivers/gpu/drm/i915/intel_dp.c: Simply adjacent lines changed. drivers/gpu/drm/i915/intel_panel.c: A field rename in -next conflicts with a bugfix in -fixes. Take the version from -fixes and apply the rename. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-02drm/i915: add sprite assertion function for VLVJesse Barnes
Need to make sure sprites are disabled before shutting off a pipe. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-02drm/i915: sprite support for ValleyView v4Jesse Barnes
No constant alpha yet though, that needs a new ioctl and/or property to get/set. v2: use drm_plane_format_cpp (Ville) fix up vlv_disable_plane, remove IVB bits (Ville) remove error path rework (Ville) fix component order confusion (Ville) clean up platform init (Ville) use compute_offset_xtiled (Ville) v3: fix up more format confusion (Ville) update to new page offset function (Ville) v4: remove incorrect formats from framebuffer_init (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-02drm/i915: Skip modifying PCH DREF if not changing clock sourcesChris Wilson
Modifying the clock sources (via the DREF control on the PCH) is a slow multi-stage process as we need to let the clocks stabilise between each stage. If we are not actually changing the clock sources, then we can return early. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jani Nikula <jani.nikula@intel.com> [danvet: Appease checkpatch by deleting a space after a ~] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-03-28drm/i915: fixup fb bpp computation in pipe_config_set_bppDaniel Vetter
Ville pointed out that my assumption that no unsupported pixel format can get past the pipe config computation stage to the platform update_plane callbacks is wrong. The reason is that this function still checks the old fb->depth value instead of the new pixel_format. While checking with all the other places that use this I've noticed that intel_framebuffer_init already has all the platform checks we need, so replace those checks with a WARN_ON. Since fb->depth isn't set for YUV pixel formats and since we already can't create an fb with an rgb layout not support on the running platform I /think/ this patch doesn't fix any bug. But it surely looks better! v2: BGR formats are also only gen4+, so add the corresponding WARN_ON, too (Ville). Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-03-28drm/i915: check fb->pixel_format instead of bits_per_pixelDaniel Vetter
We've mostly switched over to the new more flexible schema, but there's one check left in the modeset code. Motivated by a question from Ville whether there's really no way an unsupported pixel_format can escape into our platform update_plane callbacks. v2: Ville noticed that the fb->depth check is redudant when we already check fb->pixel_format. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-03-28drm/i915: clean up pipe bpp confusionDaniel Vetter
- gen4 and earlier (save for g4x) only really have a 8bpc pipe, with the possibility to dither to 6bpc using the panel fitter - g4x has hdmi, but no 12 bpc pipe ... !? Clamp hdmi accordingly. - TV/SDVO out are the only connectors available on platforms with a pipe bpp != 8, add code to force the pipe to 8bpc unconditionally. <rant> The dither handling on gmch platforms is one giant disaster. I'm hoping somewhat that vlv enabling will fix this up, but given that the 6bpc handling for edp was simply added with another quick hack, I don't have high hopes ... </rant> v2: Neither vlv nor g4x have 12bpc pipes. Still set pipe_bpp to 12*3, but let the crtc code clamp things down to 10bpc on these platforms. v3: Fix a bpc vs. bpp mixup in the gen4 and earlier pipe_bpp limiter code. v4: Drop the hunk in intel_hdmi.c about g4x/vlv 12bpc, it was wrong. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-03-28drm/i915: clean up plane bpp confusionDaniel Vetter
- There is no 16bpc linear color format in our hw. gen4+ has a 16 bpc float layout, but we don't really support it. - 10bpc is a gen4+ feature, fix up the support for it. - Update_plane should never see a wrong fb bpp value, BUG in the corresponding cases. v2: Rebase on top of Ville's plane pixel layout changes. v3: Actually drop the old gen4 check for 10bpc planes, spotted by Ville Syrjälä. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-03-28drm/i915: convert DP autodither code to new infrastructureDaniel Vetter
The old code only handled either 6bpc or 8bpc. Since it's easy to do, reorganize the code to be a bit more generic so that it can also handle 10bpc and 12bpc. Note that we still start with 8bpc, so there's no functional change. Also, since we no don't need to compute the 6BPC flag in the mode_valid callback, we can consolidate things a bit. That requires though that the link bw computation is moved up in the compute_config callback. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-03-28drm/i915: precompute pipe bpp before touching the hwDaniel Vetter
The procedure has now 3 steps: 1. Compute the bpp that the plane will output, this is done in pipe_config_set_bpp and stored into pipe_config->pipe_bpp. Also, this function clamps the pipe_bpp to whatever limit the EDID of any connected output specifies. 2. Adjust the pipe_bpp in the encoder and crtc functions, according to whatever constraints there are. 3. Decide whether to use dither by comparing the stored plane bpp with computed pipe_bpp. There are a few slight functional changes in this patch: - LVDS connector are now also going through the EDID clamping. But in a 2nd change we now unconditionally force the lvds bpc value - this shouldn't matter in reality when the panel setup is consistent, but better safe than sorry. - HDMI now forces the pipe_bpp to the selected value - I think that's what we actually want, since otherwise at least the pixelclock computations are wrong (I'm not sure whether the port would accept e.g. 10 bpc when in 12bpc mode). Contrary to the old code, we pick the next higher bpc value, since otherwise there's no way to make use of the 12 bpc mode (since the next patch will remove the 12bpc plane format, it doesn't exist). Both of these changes are due to the removal of the pipe_bpp = min(display_bpp, plane_bpp); statement. Another slight change is the reworking of the dp bpc code: - For the mode_valid callback it's sufficient to only check whether the mode would fit at the lowest bpc. - The bandwidth computation code is a bit restructured: It now walks all available bpp values in an outer loop and the codeblock that computes derived values (once a good configuration is found) has been moved out of the for loop maze. This is prep work to allow us to successively fall back on bpc values, and also correctly support bpc values != 8 or 6. v2: Rebased on top of Paulo Zanoni's little refactoring to use more drm dp helper functions. v3: Rebased on top of Jani's eDP bpp fix and Ville's limited color range work. v4: Remove the INTEL_MODE_DP_FORCE_6BPC #define, no longer needed. v5: Remove intel_crtc->bpp, too, and fix up the 12bpc check in the hdmi code. Also fixup the bpp check in intel_dp.c, it'll get reworked in a later patch though again. v6: Fix spelling in a comment. v7: Debug output improvements for the bpp computation. v8: Fixup 6bpc lvds check - dual-link and 8bpc mode are different things! v9: Reinstate the fix to properly ignore the firmware edp bpp ... this was lost in a rebase. v10: Both g4x and vlv lack 12bpc pipes, so don't enforce that we have that. Still unsure whether this is the way to go, but at least 6bpc for a 8bpc hdmi output seems to work. v11: And g4x/vlv also lack 12bpc hdmi support, so only support high depth on DP. Adjust the code. v12: Rebased. v13: Split out the introduction of pipe_config->dither|pipe_bpp, as requested from Jesse Barnes. v14: Split out the special 6BPC handling for DP, as requested by Jesse Barnes. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-03-28drm/i915: introduce pipe_config->dither|pipe_bppDaniel Vetter
We want to compute this earlier. To avoid a big complicated patch, this patch here just does the big search&replace and still calls the old functions at the same places. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-03-28drm/i915: add pipe_config->limited_color_rangeDaniel Vetter
Now that we have a useful struct for this, let's use it. Some neat pointer-chasing required, but it's all there already. v2: Rebased on top of the added Haswell limited color range support. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-03-28drm/i915: add pipe_config->has_pch_encoderDaniel Vetter
This is used way too often in the enable/disable paths. And will be even more useful in the future. Note that correct semantics of this change highly depend upon correct updating of intel_crtc->config: Like with all other modeset state, we need to call ->disable with the old config, but ->mode_set and ->enable with the new config. v2: Do not yet use the flag in the ->disable callbacks - atm we don't yet have support for the information stored in the pipe_config in the hw state readout code, so this will be wrong at boot-up/resume. v3: Rebased on top of the hdmi/dp ddi encoder merging. v4: Fixup stupid rebase error which lead to a NULL vfunc deref. v5: On haswell the VGA port is on the PCH! v6: s/IS_HASWELL/HAS_DDI/, spotted by Paulo Zanoni. Also add a missing parameter name in a function declaration. v7: Don't forget to git add ... Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-03-28drm/i915: add pipe_config->pixel_multiplierDaniel Vetter
Used by SDVO (and hopefully, eventually HDMI, if we ever get around to fixing up the low dotclock CEA modes ...). This required adding a new encoder->mode_set callback to be able to pass around the intel_crtc_config. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-03-28drm/i915: add pipe_config->timings_setDaniel Vetter
Only used by the lvds encoder. Note that we shouldn't do the same simple conversion with the FORCE_6BPC flag, since that's much better handled by moving all the pipe_bpc computation around. This requires that we pass the pipe config around to encoders, so that they can set special attributes and set constraints. To do so introduce a new ->compute_config encoder callback, which is called in stead of the drm crtc helper's ->mode_fixup. To avoid massive churn all over the codebase we don't want to convert all existing ->mode_fixup functions. Instead I've opted to convert them on an as-needed basis (mostly to cut down on rebase conflicts and to have more freedom to experiment around while developing the patches). Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-03-28drm/i915: compute pipe_config earlierDaniel Vetter
To make decent modeset state checking possible (e.g. for the check mode with atomic modesetting) we want to have the full pipe configuration and state checks done before we touch the hw. To ensure that all the little bits&pieces that are now moved to the pipe_config handle this correctly, move its computation to the right spot now, before we touch the hw in the disable_pipes step. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-03-28drm/i915: introduce struct intel_crtc_configDaniel Vetter
Currently only containing the requested and the adjusted mode. And only crtc callbacks are converted somewhat to it, encoders will be done on a as-needed basis (simply too much churn in one patch otherwise). Future patches will add tons more useful stuff to this struct, starting with the very simple. v2: Store the pipe_config in the intel_crtc, so that the ->mode-set, ->enable and also ->disable have easy access to it. v3: Store the pipe config in the right crtc ... v4: Rebased. v5: Fixup an OOPS when trying to kfree an ERR_PTR. v6: Used drm_moode_copy and some other small cleanups as suggested by Ville Syrjälä. v7: drm_mode_copy preserves the mode id of the destination, so no need to clear it again (Ville). v8: Break a long line spotted by Paulo. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-03-27drm/i915: Apply alignment restrictions on scanout surfaces for VT-dChris Wilson
From the w/a database: 'To prevent false VT-d type 6 error: The primary display plane must be 256KiB aligned, and require an extra 128 PTEs of padding afterward; The sprites planes must be 128KiB aligned, and require an extra 64 PTEs of padding afterward; The cursors must be 64KiB aligned, and require an extra 2 PTEs of padding afterward.' As we use the same function to pin the primary and sprite planes, we can simply use the more strict requirements for scanouts for both. Instead of using explicit padding PTEs following the scanout objects, we should be able to use the scratch page that is always mapped into the unused PTEs to avoid the VT-d error. References: https://bugs.freedesktop.org/show_bug.cgi?id=59626 References: https://bugs.freedesktop.org/show_bug.cgi?id=59627 References: https://bugs.freedesktop.org/show_bug.cgi?id=59631 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> [danvet: Apply s/vtd_wa/vtd_scanout_wa/ bikeshed since Damien likes it, too.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-03-26drm/i915: restore cursor and sprite state when forcing a config restore v2Jesse Barnes
Needed for VT switchless resume. v2: cursor state is now handled correctly in crtc_enable (Daniel) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>