diff options
| author | Charlie Jenkins <charlie@rivosinc.com> | 2024-11-13 18:21:13 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2025-01-18 12:33:31 -0800 |
| commit | b9a9314424512e536db5e54ff554c2f10759c657 (patch) | |
| tree | 471de169b19650bf0cdc3b4ccbb09d4eb9517396 | |
| parent | 66f197785d515d3fe5257ed65e189e4ee0b9b4e3 (diff) | |
riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT
The VXRM vector csr for xtheadvector has an encoding of 0xa and VXSAT
has an encoding of 0x9.
Co-developed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Tested-by: Yangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-7-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
| -rw-r--r-- | arch/riscv/include/asm/csr.h | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index db1d26dfaef9..2155f5afffd6 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -314,9 +314,14 @@ #define CSR_STIMECMP 0x14D #define CSR_STIMECMPH 0x15D -#define VCSR_VXRM_MASK 3 -#define VCSR_VXRM_SHIFT 1 -#define VCSR_VXSAT_MASK 1 +/* xtheadvector symbolic CSR names */ +#define CSR_VXSAT 0x9 +#define CSR_VXRM 0xa + +/* xtheadvector CSR masks */ +#define CSR_VXRM_MASK 3 +#define CSR_VXRM_SHIFT 1 +#define CSR_VXSAT_MASK 1 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ #define CSR_SISELECT 0x150 |